feat(top): adjust rf control logic, ila for 3rd test

contraint/mm7020_timing.xdc

@@ -13,6 +13,7 @@ set_false_path -through [get_nets u_tdma/tdma_tic_frame_sync_vio*]
 set_false_path -through [get_nets rx_rst]
 set_false_path -through [get_nets rst_sys]
 set_false_path -through [get_nets rst20]
+set_false_path -through [get_nets u_tdma/rx_rst]
 
 set_false_path -through [get_nets u_RecvTop/flag_mgc_done]
 set_false_path -through [get_nets u_RecvTop/flag_frame_sync]

hdl/PAPR.v

@@ -182,13 +182,12 @@ module PAPR #(
     end
 
     ila_frame_sync u_ila_frame_sync (
-        .clk   (clk),              // input wire clk
-        .probe0(vec_mag),          // input wire [21:0]  probe0  
-        .probe1(data_avg),         // input wire [21:0]  probe0  
-        .probe2(cs),               // input wire [2:0]  probe2
-        .probe3(cnt),              // input wire [7:0]  probe2
-        .probe4(frame_sync),       // input wire [0:0]  probe2
-        .probe5(vec_mag_reserved)  // input wire [21:0]  probe2
+        .clk   (clk),        // input wire clk
+        .probe0(vec_mag),    // input wire [21:0]  probe0  
+        .probe1(data_avg),   // input wire [21:0]  probe0  
+        .probe2(cs),         // input wire [2:0]  probe2
+        .probe3(cnt),        // input wire [7:0]  probe2
+        .probe4(frame_sync)  // input wire [0:0]  probe2
     );
 
 

hdl/RecvTop.v

@@ -140,7 +140,7 @@ module RecvTop (
         end
     end
 
-    assign mgc_start = (cnt_mgc_delay == 8'hFE);
+    assign mgc_start         = (cnt_mgc_delay == 8'hFE);
     assign mgc_start_quarter = (cnt_mgc_delay >= 8'hF0) && (cnt_mgc_delay <= 8'hFE);
 
     // * MGC module 
@@ -665,22 +665,15 @@ module RecvTop (
         .clk    (clk_quarter),
         .probe0 (dagc_data_in_i),      // width: 12
         .probe1 (dagc_data_in_q),      // width: 12
-        .probe2 (flag_mgc_done),       // width: 1
-        .probe3 (flag_frame_sync),     // width: 1
-        .probe4 (flag_cfo_done),       // width: 1
-        .probe5 (freqdataout_i),       // width: 10
-        .probe6 (freqdataout_q),       // width: 10
-        .probe7 (IntpARdy),            // width: 1
-        .probe8 (IntpOuti),            // width: 10
-        .probe9 (IntpOutq),            // width: 10
-        .probe10(nd_SC_FDE_dout),      // width: 1
-        .probe11(SC_FDE_douti),        // width: 10
-        .probe12(SC_FDE_doutq),        // width: 10
-        .probe13(phase_adjust_rdy),    // width: 1
-        .probe14(phase_adjust_douti),  // width: 10
-        .probe15(phase_adjust_doutq),  // width: 10
-        .probe16(good_frames),         // width: 9
-        .probe17(bad_frames)           // width: 9
+        .probe2 (flag_frame_sync),     // width: 1
+        .probe3 (phase_adjust_rdy),    // width: 1
+        .probe4 (phase_adjust_douti),  // width: 10
+        .probe5 (phase_adjust_doutq),  // width: 10
+        .probe6 (IntpARdy),            // width: 1
+        .probe7 (IntpOuti),            // width: 10
+        .probe8 (IntpOutq),            // width: 10
+        .probe9 (good_frames),         // width: 9
+        .probe10(bad_frames)           // width: 9
     );
 
 

hdl/SC_FDE_TOP.v

@@ -556,4 +556,13 @@ module SC_FDE_TOP (
         .flagoverflow_FDE_dataout_29to10q(flagoverflow_FDE_dataout_29to10q)   //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
     );
 
+    // ila_scfde u_ila_scfde (
+    //     .clk   (clk),            // input wire clk
+    //     .probe0(flag_ow_left),   // 1
+    //     .probe1(ifft_out_nd),    // 1
+    //     .probe2(ifft_index),     // 8
+    //     .probe3(ifft_out_tdata)  //64
+    // );
+
+
 endmodule

hdl/Transmitter.v

@@ -561,15 +561,15 @@ module Transmitter #(
 
     // ********    Debug    ********
 
-    ila_transmitter u_ila_transmitter (
-        .clk   (clk),                // input wire clk
-        .probe0(cnt_sym_send),       // input wire [15:0]  probe0  
-        .probe1(cs),                 // input wire [3:0]  probe1 
-        .probe2(ns),                 // input wire [3:0]  probe2 
-        .probe3(send_data_ready),    // input wire [0:0]  probe3 
-        .probe4(send_start),         // input wire [0:0]  probe4 
-        .probe5(tx_data_src_tvalid)  // input wire [0:0]  probe5
-    );
+    // ila_transmitter u_ila_transmitter (
+    //     .clk   (clk),                // input wire clk
+    //     .probe0(cnt_sym_send),       // input wire [15:0]  probe0  
+    //     .probe1(cs),                 // input wire [3:0]  probe1 
+    //     .probe2(ns),                 // input wire [3:0]  probe2 
+    //     .probe3(send_data_ready),    // input wire [0:0]  probe3 
+    //     .probe4(send_start),         // input wire [0:0]  probe4 
+    //     .probe5(tx_data_src_tvalid)  // input wire [0:0]  probe5
+    // );
 
 
 endmodule

hdl/ad9361_mgc_pin_ctrl.v

@@ -162,18 +162,18 @@ module ad9361_mgc_pin_ctrl (
     //     .probe_out0(start)  // output wire [0 : 0] probe_out0
     // );
 
-    ila_ad9361_mgc u_ila_ad9361_mgc (
-        .clk   (clk),                                 // input wire clk
-        .probe0(start_posedge),                       // input wire [0:0]  probe0  
-        .probe1(rx_data_i),                           // input wire [11:0]  probe1 
-        .probe2(u_power_measure.cs),                  // input wire [2:0]  probe2 
-        .probe3(u_power_measure.sign_bit_num_i),      // input wire [3:0]  probe3 
-        .probe4(u_power_measure.sign_bit_num_min_i),  // input wire [3:0]  probe4 
-        .probe5(flag_too_high),                       // input wire [0:0]  probe5 
-        .probe6(flag_too_low),                        // input wire [0:0]  probe6
-        .probe7(u_power_measure.cnt_amp_too_high),    // input wire [0:0]  probe6
-        .probe8(u_power_measure.cnt_startup)          // input wire [11:0]  probe6
-    );
+    // ila_ad9361_mgc u_ila_ad9361_mgc (
+    //     .clk   (clk),                                 // input wire clk
+    //     .probe0(start_posedge),                       // input wire [0:0]  probe0  
+    //     .probe1(rx_data_i),                           // input wire [11:0]  probe1 
+    //     .probe2(u_power_measure.cs),                  // input wire [2:0]  probe2 
+    //     .probe3(u_power_measure.sign_bit_num_i),      // input wire [3:0]  probe3 
+    //     .probe4(u_power_measure.sign_bit_num_min_i),  // input wire [3:0]  probe4 
+    //     .probe5(flag_too_high),                       // input wire [0:0]  probe5 
+    //     .probe6(flag_too_low),                        // input wire [0:0]  probe6
+    //     .probe7(u_power_measure.cnt_amp_too_high),    // input wire [0:0]  probe6
+    //     .probe8(u_power_measure.cnt_startup)          // input wire [11:0]  probe6
+    // );
 
 
 endmodule

hdl/phy_control.v

@@ -410,10 +410,10 @@ module phy_control #(
     // frame sync tic
     assign tdma_frame_sync_tic         = tdma_frame_sync_tic_reg;
 
-    vio_phy_param u_vio_phy_param (
-        .clk      (local_clk),
-        .probe_in0(phy_cr_reg)
-    );
+    // vio_phy_param u_vio_phy_param (
+    //     .clk      (local_clk),
+    //     .probe_in0(phy_cr_reg)
+    // );
 
     //--- ADD YOUR OWN LOGIC END
 

hdl/system_top.v

@@ -144,6 +144,12 @@ module system_top (
     // rx
     wire        rx_err_flag_pos;
 
+    wire        rf_io3_d1_12db;
+    wire        rf_io4_d2_6db;
+    wire        rf_io0_d3_18db;
+    wire        rf_io1_d4_12db;
+    wire        rf_io2_trx;  // 1 for tx on, 0 for rx
+
     // vio
     wire        rst_manual;
     wire        rx_rst_vio;
@@ -166,6 +172,19 @@ module system_top (
     assign ad9361_tx_data_q = phy_tx_iq_reverse ? bb_tx_i : bb_tx_q;
     assign bb_rx_i          = phy_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i;
     assign bb_rx_q          = phy_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q;
+    // gpio  rf control
+    assign rf_gpio[0]       = rf_io0_d3_18db;
+    assign rf_gpio[1]       = rf_io1_d4_12db;
+    assign rf_gpio[2]       = rf_io2_trx;
+    assign rf_gpio[3]       = rf_io3_d1_12db;
+    assign rf_gpio[4]       = rf_io4_d2_6db;
+    assign rf_gpio[5]       = 0;
+    // at send slot, rx rst is on, and trx is 1 for tx
+    assign rf_io2_trx       = rx_rst;
+    assign rf_io0_d3_18db   = 0;
+    assign rf_io1_d4_12db   = 0;
+    assign rf_io3_d1_12db   = 0;
+    assign rf_io4_d2_6db    = 0;
 
     // ******** Logic Block ********
 
@@ -383,4 +402,13 @@ module system_top (
     //     .probe1(ad9361_tx_data_q)   // input wire [11:0]  probe1
     // );
 
+    // vio_rf u_vio_rf (
+    //     .clk       (clk_poweron),
+    //     .probe_out0(),
+    //     .probe_out1(rf_io3_d1_12db),
+    //     .probe_out2(rf_io4_d2_6db),
+    //     .probe_out3(rf_io0_d3_18db),
+    //     .probe_out4(rf_io1_d4_12db)
+    // );
+
 endmodule