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tdma module tx_start signal is set high wrongly when slot number = 1 and id !=1 #2

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opened 2024-10-12 16:28:21 +08:00 by ZoroGH · 1 comment
ZoroGH commented 2024-10-12 16:28:21 +08:00
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ZoroGH added the bug label 2024-10-12 16:28:21 +08:00
ZoroGH commented 2024-10-18 19:17:42 +08:00
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update ps logic, intr2ps signal will be trigger at the end of the slot while the next slot is the send slot

update ps logic, `intr2ps` signal will be trigger at the end of the slot while the next slot is the send slot
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Reference: ZoroGH/MM7020#2