418 lines
14 KiB
Verilog
418 lines
14 KiB
Verilog
`timescale 1ns / 1ps
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module net_city (
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// basic
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input clk,
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input rst_initial,
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input rst_manual, //manual
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// tx signal
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output reg tx_start = 1'b0, // pulse
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output reg [63:0] trans_net_data = 64'd0,
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output reg flag_video_send = 1'b0,
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output reg [07:0] recv_id = 8'd0,
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// rx signal
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input frame_sync,
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// input recv_net_data_nd,
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// input [63:0] recv_net_data,
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// net parameter
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input [31:0] frame_sync_time,
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input [07:0] id_num,
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input [07:0] max_slot_num,
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input [07:0] video_id01,
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input [07:0] video_id02,
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input [07:0] video_id03,
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// net state
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output reg is_net = 1'b0,
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output reg flag_to_uc = 1'b0,
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// intr 2 ps
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output wire intr_ps,
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output reg rx_rst,
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input wire tx_done
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);
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//----------parameter----------
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localparam SLOT_TIME = 750000; // 15ms
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//----------rst----------
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wire rst;
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assign rst = rst_initial || rst_manual;
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//----------counter_1s----------
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reg [31:0] cnt_1s = 32'd0;
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always @(posedge clk) begin
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if (rst) begin
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cnt_1s <= 32'd0;
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end
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else begin
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if (cnt_1s == 32'd49999999) begin
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cnt_1s <= 32'd0;
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end
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else begin
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cnt_1s <= cnt_1s + 32'd1;
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end
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end
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end
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//----------flag_tx----------
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//----------state_net----------
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reg [07:0] state_net = 8'd0;
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reg [31:0] cnt_trans_slot = 32'd0;
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reg [31:0] cnt_inter_slot = 32'd0;
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reg [07:0] cur_slot = 8'd0;
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reg [07:0] cnt_video_slot = 8'd0;
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reg [31:0] cnt_other = 32'd0;
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reg [07:0] connect_node = 8'd0;
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reg [63:0] trans_net_data_reg = 64'd0;
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reg [07:0] recv_connect_node = 8'd0;
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reg [07:0] recv_video_id01 = 8'd0;
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reg [07:0] recv_video_id02 = 8'd0;
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reg [07:0] recv_video_id03 = 8'd0;
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// if u dont understand this code blew, plz contact NanzZ 😊
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assign intr_ps = (cnt_trans_slot == SLOT_TIME - 50000) && ((id_num == 1 && (cur_slot == max_slot_num - 1)) || (id_num != 1 && (cur_slot == id_num - 8'd2)));
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always @(posedge clk) begin
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if (rst) begin
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rx_rst <= 0;
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end
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else if (tx_start) begin
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rx_rst <= 1;
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end
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else if (tx_done) begin
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rx_rst <= 0;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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state_net <= 8'd0;
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cnt_trans_slot <= 32'd0;
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cnt_inter_slot <= 32'd0;
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cnt_other <= 32'd0;
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recv_id <= 8'd0;
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recv_connect_node <= 8'd0;
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recv_video_id01 <= 8'd0;
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recv_video_id02 <= 8'd0;
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recv_video_id03 <= 8'd0;
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tx_start <= 1'b0;
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trans_net_data <= 64'd0;
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is_net <= 1'b0;
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flag_video_send <= 1'b0;
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end
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else begin
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case (state_net)
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8'd0: begin
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state_net <= 8'd1;
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cnt_trans_slot <= 32'd0;
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cnt_inter_slot <= 32'd0;
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cnt_other <= 32'd0;
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recv_id <= recv_id;
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recv_connect_node <= 8'd0;
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recv_video_id01 <= recv_video_id01;
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recv_video_id02 <= recv_video_id02;
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recv_video_id03 <= recv_video_id03;
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tx_start <= 1'b0;
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trans_net_data <= 64'd0;
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is_net <= 1'b0;
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flag_video_send <= 1'b0;
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end
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8'd1: begin
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state_net <= 8'd2;
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end
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8'd2: begin
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if (frame_sync) begin
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state_net <= 8'd50;
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cnt_other <= 32'd0;
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cnt_trans_slot <= frame_sync_time;
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cnt_inter_slot <= cnt_trans_slot + 32'd1;
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end
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else if (cnt_other == 32'd49999999) begin
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cnt_other <= 32'd0;
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state_net <= 8'd100;
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is_net <= 1'b1;
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end
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else begin
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cnt_other <= cnt_other + 32'd1;
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end
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end
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8'd100: begin // _tx
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state_net <= 8'd101;
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tx_start <= 1'b1;
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trans_net_data <= trans_net_data_reg;
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cnt_trans_slot <= 32'd0;
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cnt_inter_slot <= 32'd0;
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end
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8'd101: begin
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state_net <= 8'd200;
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tx_start <= 1'b0;
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cnt_trans_slot <= cnt_trans_slot + 32'd1;
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end
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8'd200: begin // wait
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if ((cnt_trans_slot == SLOT_TIME - 2) && (id_num == 1 && (cur_slot == max_slot_num - 1))) begin
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state_net <= 8'd100;
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cnt_trans_slot <= cnt_trans_slot + 32'd1;
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cnt_inter_slot <= 32'd0;
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end
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else if ((cnt_trans_slot == SLOT_TIME - 2) && (id_num != 1 && (cur_slot == id_num - 8'd2))) begin
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state_net <= 8'd100;
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cnt_trans_slot <= cnt_trans_slot + 32'd1;
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cnt_inter_slot <= 32'd0;
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end
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else if (frame_sync) begin
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state_net <= 8'd50;
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cnt_trans_slot <= frame_sync_time;
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cnt_inter_slot <= cnt_trans_slot + 32'd1;
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end
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else begin
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if (cnt_trans_slot == SLOT_TIME - 1) begin
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cnt_trans_slot <= 32'd0;
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end
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else begin
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cnt_trans_slot <= cnt_trans_slot + 32'd1;
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end
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cnt_inter_slot <= 32'd0;
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end
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case (id_num)
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recv_video_id01: begin
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if (cnt_trans_slot == SLOT_TIME - 2 && cnt_video_slot == 8'd0) begin
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flag_video_send <= 1'b1;
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end
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else begin
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flag_video_send <= 1'b0;
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end
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end
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recv_video_id02: begin
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if (cnt_trans_slot == SLOT_TIME - 2 && cnt_video_slot == 8'd1) begin
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flag_video_send <= 1'b1;
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end
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else begin
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flag_video_send <= 1'b0;
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end
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end
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recv_video_id03: begin
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if (cnt_trans_slot == SLOT_TIME - 2 && cnt_video_slot == 8'd2) begin
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flag_video_send <= 1'b1;
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end
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else begin
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flag_video_send <= 1'b0;
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end
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end
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default: begin
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flag_video_send <= 1'b0;
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end
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endcase
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end
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8'd50: begin
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// if (recv_net_data_nd) begin
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// if (recv_net_data[23:00] == 24'h7e5a33) begin
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state_net <= 8'd51;
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is_net <= 1'b1;
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// cnt_trans_slot <= cnt_trans_slot + 32'd1;
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// cnt_inter_slot <= cnt_inter_slot + 32'd1;
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// recv_id <= recv_net_data[63:56];
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// recv_video_id01 <= recv_net_data[55:48];
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// recv_video_id02 <= recv_net_data[47:40];
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// recv_video_id03 <= recv_net_data[39:32];
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// recv_connect_node <= recv_net_data[31:24];
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// end
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// else begin
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// state_net <= 8'd200;
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// is_net <= 1'b0;
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// cnt_trans_slot <= cnt_inter_slot + 32'd1;
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// end
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// end
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// else begin
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// cnt_trans_slot <= cnt_trans_slot + 32'd1;
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// cnt_inter_slot <= cnt_inter_slot + 32'd1;
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// end
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end
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8'd51: begin
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state_net <= 8'd200;
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cnt_trans_slot <= cnt_trans_slot + 32'd1;
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end
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default: begin
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state_net <= 8'd0;
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cnt_trans_slot <= 32'd0;
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cnt_inter_slot <= 32'd0;
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cnt_other <= 32'd0;
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recv_id <= recv_id;
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recv_connect_node <= 8'd0;
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recv_video_id01 <= recv_video_id01;
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recv_video_id02 <= recv_video_id02;
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recv_video_id03 <= recv_video_id03;
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tx_start <= 1'b0;
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trans_net_data <= 64'd0;
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is_net <= 1'b0;
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flag_video_send <= 1'b0;
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end
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endcase
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end
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end
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//----------connect_node----------
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// always @(posedge clk) begin
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// if (rst) begin
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// connect_node <= 8'd0;
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// end else begin
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// if (state_net == 8'd51) begin
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// case (recv_id)
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// 8'd1: begin
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// connect_node[07:06] <= 2'b11;
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// end
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// 8'd2: begin
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// connect_node[05:04] <= 2'b11;
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// end
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// 8'd3: begin
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// connect_node[03:02] <= 2'b11;
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// end
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// 8'd4: begin
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// connect_node[01:00] <= 2'b11;
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// end
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// default: begin
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// connect_node <= 8'd0;
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// end
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// endcase
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// end else if (cnt_trans_slot == SLOT_TIME / 2 && cur_slot == id_num) begin
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// connect_node <= 8'd0;
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// end else begin
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// connect_node <= connect_node;
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// end
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// end
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// end
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//----------trans_net_data_reg----------
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reg [07:0] trans_video_id01;
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reg [07:0] trans_video_id02;
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reg [07:0] trans_video_id03;
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always @(posedge clk) begin
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if (rst) begin
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trans_video_id01 <= 8'd0;
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trans_video_id02 <= 8'd0;
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trans_video_id03 <= 8'd0;
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end
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else begin
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if (id_num == 8'd1) begin //主节点
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trans_video_id01 <= video_id01;
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trans_video_id02 <= video_id02;
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trans_video_id03 <= video_id03;
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end
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else if (recv_id == 8'd1) begin //从节点只听从主节点命令
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trans_video_id01 <= recv_video_id01;
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trans_video_id02 <= recv_video_id02;
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trans_video_id03 <= recv_video_id03;
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end
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else begin
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trans_video_id01 <= trans_video_id01;
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trans_video_id02 <= trans_video_id02;
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trans_video_id03 <= trans_video_id03;
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end
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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trans_net_data_reg <= 64'd0;
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end
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else begin
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if (cnt_trans_slot == SLOT_TIME / 2 && cur_slot == id_num - 8'd1) begin
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trans_net_data_reg[63:56] <= id_num;
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trans_net_data_reg[55:48] <= trans_video_id01;
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trans_net_data_reg[47:40] <= trans_video_id02;
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trans_net_data_reg[39:32] <= trans_video_id03;
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trans_net_data_reg[31:24] <= connect_node;
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trans_net_data_reg[23:00] <= 24'h7e5a33;
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end
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else begin
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trans_net_data_reg <= trans_net_data_reg;
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end
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end
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end
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//----------cur_slot----------
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always @(posedge clk) begin
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if (rst) begin
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cur_slot <= 8'd0;
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end
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else begin
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if (state_net == 8'd51) begin
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if (recv_id <= max_slot_num) begin
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cur_slot <= recv_id - 8'd1;
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end
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else begin
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cur_slot <= cur_slot;
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end
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end
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else if (cnt_trans_slot == SLOT_TIME - 1) begin
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if (cur_slot == max_slot_num - 8'd1) begin
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cur_slot <= 8'd0;
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end
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else begin
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cur_slot <= cur_slot + 8'd1;
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end
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end
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else begin
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cur_slot <= cur_slot;
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end
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end
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end
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//----------cnt_video_slot----------
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always @(posedge clk) begin
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if (rst) begin
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cnt_video_slot <= 8'd0;
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end
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else begin
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if (cnt_trans_slot == SLOT_TIME - 1) begin
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if (cnt_video_slot == 8'd2) begin
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cnt_video_slot <= 8'd0;
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end
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else begin
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cnt_video_slot <= cnt_video_slot + 8'd1;
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end
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end
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else begin
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cnt_video_slot <= cnt_video_slot;
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end
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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flag_to_uc <= 1'b0;
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end
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else begin
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if (cnt_trans_slot == SLOT_TIME / 2 - 1) begin
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flag_to_uc <= 1'b1;
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end
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else begin
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flag_to_uc <= 1'b0;
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end
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end
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end
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ila_MAC ila_MAC (
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.clk (clk),
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.probe0 (tx_start),
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.probe1 (connect_node),
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.probe2 (cnt_trans_slot),
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.probe3 (recv_net_data),
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.probe4 (state_net),
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.probe5 (recv_id),
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.probe6 (cur_slot),
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.probe7 (id_num),
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.probe8 (frame_sync),
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.probe9 (max_slot_num),
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.probe10(recv_net_data_nd),
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.probe11(trans_net_data)
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);
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endmodule
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