54 lines
1.1 KiB
Verilog
54 lines
1.1 KiB
Verilog
`timescale 1ns / 1ns
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module tb_Transmitter ();
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reg clk = 1;
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reg clk_tx = 1;
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reg rst = 1;
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always #1 clk <= ~clk;
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always #2 clk_tx <= ~clk_tx;
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reg intr = 0;
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reg test=0;
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initial begin
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#100 rst <= 0;
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#1000 test <=1;
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#1000 test <=0;
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#1000 test <=1;
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#1000 test <=1;
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end
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Transmitter #(
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.AGC_HEADER_LEN(200),
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.FRAME_HEADER_LEN(512),
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.BLOCK_NUM(3),
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.PHASE1_LEN(2112),
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.PREFIX_LEN(8),
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.CHU_SEQ_LEN(128),
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.GAP_LEN(128)
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) u_Transmitter (
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.clk (clk_tx),
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.rst (rst),
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.speed_mode (0),
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.send_data_ready (),
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.send_start (),
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.send_over (),
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.clk_data_src (),
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.tx_data_src_tdata (),
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.tx_data_src_tready(),
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.tx_data_src_tvalid(),
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.hopping_freq (),
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.ad9361_tx_data_i (),
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.ad9361_tx_data_q (),
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.test (test),
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.hop_wait (2000)
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);
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endmodule
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