102 lines
2.7 KiB
Verilog
102 lines
2.7 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/04/26 17:05:11
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// Design Name:
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// Module Name: tb_tdma
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tb_tdma ();
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reg clk = 1;
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reg rst = 1;
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always #1 clk <= ~clk;
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initial begin
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#10 rst <= 1'b0;
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end
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reg [7:0] local_id = 0;
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initial begin
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#20 local_id <= 1;
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end
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reg flag_frame_sync = 0;
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reg recevied_cur_slot_id_valid = 0;
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reg [7:0] recevied_cur_slot_id = 0;
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tdma u_tdma_master (
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.clk (clk),
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.rst (rst),
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.flag_frame_sync (flag_frame_sync),
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.tdma_slot_len (24'd7500),
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.tdma_tic_2_ps (24'd6000),
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.tdma_slot_num (8'd4),
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.local_id (local_id),
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.recevied_cur_slot_id_valid(recevied_cur_slot_id_valid),
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.recevied_cur_slot_id (recevied_cur_slot_id),
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.intr_2ps (),
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.tx_start (),
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.rx_rst ()
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);
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reg flag_frame_sync_slave = 0;
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reg recevied_cur_slot_id_valid_slave = 0;
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reg [7:0] recevied_cur_slot_id_slave = 7;
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reg [7:0] local_id_slave = 10;
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reg [7:0] cnt = 0;
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always @(posedge clk) begin
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if (cnt < 8'hFF) begin
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cnt <= cnt + 1;
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end
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end
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always @(posedge clk) begin
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if (cnt == 8'hF3) begin
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flag_frame_sync_slave <= 1;
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end
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else begin
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flag_frame_sync_slave <= 0;
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end
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if (cnt == 8'hFE) begin
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recevied_cur_slot_id_valid_slave <= 1;
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end
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else begin
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recevied_cur_slot_id_valid_slave <= 0;
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end
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end
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tdma u_tdma_slave (
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.clk (clk),
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.rst (rst),
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.flag_frame_sync (flag_frame_sync_slave),
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.tdma_slot_len (24'd7500),
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.tdma_tic_2_ps (24'd6000),
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.tdma_slot_num (8'd10),
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.local_id (local_id_slave),
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.recevied_cur_slot_id_valid(recevied_cur_slot_id_valid_slave),
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.recevied_cur_slot_id (recevied_cur_slot_id_slave),
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.intr_2ps (),
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.tx_start (),
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.rx_rst ()
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);
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endmodule
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