386 lines
13 KiB
Verilog
386 lines
13 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/11/18 23:18:07
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// Design Name:
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// Module Name: Message_Store
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module Message_Store #(
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parameter WIDTH = 4'd8
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) (
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input clk,
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input rst_MS,
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input framesync_MS, //帧同步标志，高脉冲
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input nd_MS, //译码输入数据有效标志，高有效
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input [WIDTH-1:0] din_MS, //译码输入软信息
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input [ 0:0] oe_MS, //使能输出信号，高脉冲
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output deal_end_MS, //转换完成标志
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output syncout_MS, //高脉冲
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output rdy_MS, //高有效的连续信号
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output reg [WIDTH-1:0] dout01_MS = 8'd0, // 输出数据
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output reg [WIDTH-1:0] dout02_MS = 8'd0,
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output reg [WIDTH-1:0] dout03_MS = 8'd0,
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output reg [WIDTH-1:0] dout04_MS = 8'd0
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);
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reg [10:0] cnt_MS = 11'd0;
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reg flag_end = 1'd0;
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always @(posedge clk) begin
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if (rst_MS) begin
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flag_end <= 11'd0;
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end
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else begin
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if (framesync_MS) flag_end <= 1'd1;
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else if (nd_MS && cnt_MS == 11'd2047) flag_end <= 1'd0;
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else flag_end <= flag_end;
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end
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end
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// 产生基准计数
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always @(posedge clk) begin
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if (rst_MS) begin
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cnt_MS <= 11'd0;
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end
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else begin
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if (flag_end) begin
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if (nd_MS) cnt_MS <= cnt_MS + 11'd1;
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else begin
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cnt_MS <= cnt_MS;
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end
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end
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else begin
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cnt_MS <= cnt_MS;
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end
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end
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end
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reg wea1_01 = 1'd0, wea1_02 = 1'd0, wea1_03 = 1'd0, wea1_04 = 1'd0, wea2_01 = 1'd0, wea2_02 = 1'd0, wea2_03 = 1'd0, wea2_04 = 1'd0;
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reg [8:0] addr_wr1_01 = 9'd511, addr_wr1_02 = 9'd511, addr_wr1_03 = 9'd511, addr_wr1_04 = 9'd511, addr_wr2_01 = 9'd511, addr_wr2_02 = 9'd511, addr_wr2_03 = 9'd511, addr_wr2_04 = 9'd511;
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reg [WIDTH-1:0] din1_01 = 8'd0, din1_02 = 8'd0, din1_03 = 8'd0, din1_04 = 8'd0, din2_01 = 8'd0, din2_02 = 8'd0, din2_03 = 8'd0, din2_04 = 8'd0;
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reg [8:0] addr_rd1_01 = 9'd511, addr_rd1_02 = 9'd511, addr_rd1_03 = 9'd511, addr_rd1_04 = 9'd511, addr_rd2_01 = 9'd511, addr_rd2_02 = 9'd511, addr_rd2_03 = 9'd511, addr_rd2_04 = 9'd511;
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wire [WIDTH-1:0] dout1_01, dout1_02, dout1_03, dout1_04, dout2_01, dout2_02, dout2_03, dout2_04;
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RAM_512_8 Lp1_01 (
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.clka (clk),
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.wea (wea1_01),
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.addra(addr_wr1_01),
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.dina (din1_01),
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.clkb (clk),
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.addrb(addr_rd1_01),
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.doutb(dout1_01)
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);
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RAM_512_8 Lp1_02 (
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.clka (clk),
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.wea (wea1_02),
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.addra(addr_wr1_02),
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.dina (din1_02),
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.clkb (clk),
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.addrb(addr_rd1_02),
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.doutb(dout1_02)
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);
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RAM_512_8 Lp1_03 (
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.clka (clk),
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.wea (wea1_03),
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.addra(addr_wr1_03),
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.dina (din1_03),
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.clkb (clk),
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.addrb(addr_rd1_03),
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.doutb(dout1_03)
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);
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RAM_512_8 Lp1_04 (
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.clka (clk),
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.wea (wea1_04),
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.addra(addr_wr1_04),
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.dina (din1_04),
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.clkb (clk),
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.addrb(addr_rd1_04),
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.doutb(dout1_04)
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);
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RAM_512_8 Lp2_01 (
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.clka (clk),
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.wea (wea2_01),
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.addra(addr_wr2_01),
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.dina (din2_01),
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.clkb (clk),
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.addrb(addr_rd2_01),
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.doutb(dout2_01)
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);
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RAM_512_8 Lp2_02 (
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.clka (clk),
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.wea (wea2_02),
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.addra(addr_wr2_02),
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.dina (din2_02),
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.clkb (clk),
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.addrb(addr_rd2_02),
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.doutb(dout2_02)
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);
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RAM_512_8 Lp2_03 (
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.clka (clk),
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.wea (wea2_03),
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.addra(addr_wr2_03),
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.dina (din2_03),
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.clkb (clk),
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.addrb(addr_rd2_03),
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.doutb(dout2_03)
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);
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RAM_512_8 Lp2_04 (
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.clka (clk),
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.wea (wea2_04),
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.addra(addr_wr2_04),
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.dina (din2_04),
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.clkb (clk),
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.addrb(addr_rd2_04),
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.doutb(dout2_04)
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);
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reg flag_switch_MS = 1'd0;
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always @(posedge clk) begin
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if (rst_MS) flag_switch_MS <= 1'd0;
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else begin
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if (nd_MS && cnt_MS == 11'd2047) flag_switch_MS <= ~flag_switch_MS;
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else flag_switch_MS <= flag_switch_MS;
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end
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end
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// 乒乓写缓存过程
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always @(posedge clk) begin
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if (rst_MS) begin
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wea1_01 <= 1'd0;
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wea1_02 <= 1'd0;
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wea1_03 <= 1'd0;
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wea1_04 <= 1'd0;
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wea2_01 <= 1'd0;
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wea2_02 <= 1'd0;
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wea2_03 <= 1'd0;
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wea2_04 <= 1'd0;
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addr_wr1_01 <= 9'd511;
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addr_wr1_02 <= 9'd511;
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addr_wr1_03 <= 9'd511;
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addr_wr1_04 <= 9'd511;
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addr_wr2_01 <= 9'd511;
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addr_wr2_02 <= 9'd511;
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addr_wr2_03 <= 9'd511;
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addr_wr2_04 <= 9'd511;
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din1_01 <= 8'd0;
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din1_02 <= 8'd0;
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din1_03 <= 8'd0;
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din1_04 <= 8'd0;
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din2_01 <= 8'd0;
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din2_02 <= 8'd0;
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din2_03 <= 8'd0;
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din2_04 <= 8'd0;
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end
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else begin
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if (nd_MS) //所有的写操作均在nd_MS有效时进行
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if (flag_switch_MS == 1'd0) begin //写第一个缓存区
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if (cnt_MS >= 11'd0 && cnt_MS < 11'd512) begin
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wea1_01 <= 1'd1;
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addr_wr1_01 <= addr_wr1_01 + 9'd1;
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din1_01 <= din_MS;
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end
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else if (cnt_MS >= 11'd512 && cnt_MS < 11'd1024) begin
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wea1_02 <= 1'd1;
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addr_wr1_02 <= addr_wr1_02 + 9'd1;
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din1_02 <= din_MS;
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wea1_01 <= 1'd0;
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end
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else if (cnt_MS >= 11'd1024 && cnt_MS < 11'd1536) begin
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wea1_03 <= 1'd1;
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addr_wr1_03 <= addr_wr1_03 + 9'd1;
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din1_03 <= din_MS;
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wea1_02 <= 1'd0;
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end
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else if (cnt_MS >= 11'd1536 && cnt_MS <= 11'd2047) begin
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wea1_04 <= 1'd1;
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addr_wr1_04 <= addr_wr1_04 + 9'd1;
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din1_04 <= din_MS;
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wea1_03 <= 1'd0;
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end
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end
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else begin
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if (cnt_MS >= 11'd0 && cnt_MS < 11'd512) begin
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wea2_01 <= 1'd1;
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addr_wr2_01 <= addr_wr2_01 + 9'd1;
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din2_01 <= din_MS;
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end
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else if (cnt_MS >= 11'd512 && cnt_MS < 11'd1024) begin
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wea2_02 <= 1'd1;
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addr_wr2_02 <= addr_wr2_02 + 9'd1;
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din2_02 <= din_MS;
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wea2_01 <= 1'd0;
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end
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else if (cnt_MS >= 11'd1024 && cnt_MS < 11'd1536) begin
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wea2_03 <= 1'd1;
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addr_wr2_03 <= addr_wr2_03 + 9'd1;
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din2_03 <= din_MS;
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wea2_02 <= 1'd0;
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end
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else if (cnt_MS >= 11'd1536 && cnt_MS <= 11'd2047) begin
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wea2_04 <= 1'd1;
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addr_wr2_04 <= addr_wr2_04 + 9'd1;
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din2_04 <= din_MS;
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wea2_03 <= 1'd0;
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end
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end
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else begin
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wea1_01 <= 1'd0;
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wea1_02 <= 1'd0;
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wea1_03 <= 1'd0;
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wea1_04 <= 1'd0;
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wea2_01 <= 1'd0;
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wea2_02 <= 1'd0;
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wea2_03 <= 1'd0;
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wea2_04 <= 1'd0;
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din1_01 <= 8'd0;
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din1_02 <= 8'd0;
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din1_03 <= 8'd0;
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din1_04 <= 8'd0;
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din2_01 <= 8'd0;
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din2_02 <= 8'd0;
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din2_03 <= 8'd0;
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din2_04 <= 8'd0;
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addr_wr1_01 <= addr_wr1_01;
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addr_wr1_02 <= addr_wr1_02;
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addr_wr1_03 <= addr_wr1_03;
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addr_wr1_04 <= addr_wr1_04;
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addr_wr2_01 <= addr_wr2_01;
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addr_wr2_02 <= addr_wr2_02;
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addr_wr2_03 <= addr_wr2_03;
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addr_wr2_04 <= addr_wr2_04;
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end
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end
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end
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reg flag_out = 1'd0;
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reg [10:0] cnt_out_MS = 11'd0;
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// 产生输出计数器
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always @(posedge clk) begin
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if (rst_MS) begin
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flag_out <= 1'd0;
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cnt_out_MS <= 11'd0;
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end
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else begin
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if (oe_MS) begin
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flag_out <= 1'd1;
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cnt_out_MS <= 11'd0;
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end
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else begin
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if (flag_out && cnt_out_MS < 11'd540) begin
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cnt_out_MS <= cnt_out_MS + 11'd1;
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end
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else begin
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flag_out <= 1'd0;
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cnt_out_MS <= cnt_out_MS;
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end
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end
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end
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end
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// 控制输出缓存地址
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always @(posedge clk) begin
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if (rst_MS) begin
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addr_rd1_01 <= 9'd511;
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addr_rd1_02 <= 9'd511;
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addr_rd1_03 <= 9'd511;
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addr_rd1_04 <= 9'd511;
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addr_rd2_01 <= 9'd511;
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addr_rd2_02 <= 9'd511;
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addr_rd2_03 <= 9'd511;
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addr_rd2_04 <= 9'd511;
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end
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else begin
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if (flag_switch_MS) begin // 输出缓存１中的数据
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if (cnt_out_MS >= 11'd1 && cnt_out_MS <= 11'd512) begin
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addr_rd1_01 <= addr_rd1_01 + 9'd1;
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addr_rd1_02 <= addr_rd1_02 + 9'd1;
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addr_rd1_03 <= addr_rd1_03 + 9'd1;
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addr_rd1_04 <= addr_rd1_04 + 9'd1;
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end
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else begin
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addr_rd1_01 <= 9'd511;
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addr_rd1_02 <= 9'd511;
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addr_rd1_03 <= 9'd511;
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addr_rd1_04 <= 9'd511;
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end
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end
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else begin // 输出缓存2中的数据
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if (cnt_out_MS >= 11'd1 && cnt_out_MS <= 11'd512) begin
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addr_rd2_01 <= addr_rd2_01 + 9'd1;
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addr_rd2_02 <= addr_rd2_02 + 9'd1;
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addr_rd2_03 <= addr_rd2_03 + 9'd1;
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addr_rd2_04 <= addr_rd2_04 + 9'd1;
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end
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else begin
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addr_rd2_01 <= 9'd511;
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addr_rd2_02 <= 9'd511;
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addr_rd2_03 <= 9'd511;
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addr_rd2_04 <= 9'd511;
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end
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end
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end
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end
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// 输出缓存数据到译码器
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always @(posedge clk) begin
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if (rst_MS) begin
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dout01_MS <= 8'd0;
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dout02_MS <= 8'd0;
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dout03_MS <= 8'd0;
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dout04_MS <= 8'd0;
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end
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else begin
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if (flag_switch_MS) begin
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if (cnt_out_MS >= 11'd5 && cnt_out_MS <= 11'd516) begin
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dout01_MS <= dout1_01;
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dout02_MS <= dout1_02;
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dout03_MS <= dout1_03;
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dout04_MS <= dout1_04;
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end
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else begin
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dout01_MS <= 8'd0;
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dout02_MS <= 8'd0;
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dout03_MS <= 8'd0;
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dout04_MS <= 8'd0;
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end
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end
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else begin
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if (cnt_out_MS >= 11'd5 && cnt_out_MS <= 11'd516) begin
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dout01_MS <= dout2_01;
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dout02_MS <= dout2_02;
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dout03_MS <= dout2_03;
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dout04_MS <= dout2_04;
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end
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else begin
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dout01_MS <= 8'd0;
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dout02_MS <= 8'd0;
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dout03_MS <= 8'd0;
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dout04_MS <= 8'd0;
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end
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end
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end
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end
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// 输出处理完成、同步脉冲和使能标志
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assign deal_end_MS = (cnt_MS == 11'd2047 && nd_MS) ? 1'd1 : 1'd0;
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assign syncout_MS = (cnt_out_MS == 11'd5) ? 1'd1 : 1'd0;
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assign rdy_MS = (cnt_out_MS >= 11'd6 && cnt_out_MS <= 11'd517) ? 1'd1 : 1'd0;
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endmodule
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