72 lines
1.6 KiB
Verilog
72 lines
1.6 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/11/18 21:06:38
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// Design Name:
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// Module Name: Interp_half
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module Interp_half(
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input clk,
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input [9:0] din_p1,
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input [9:0] din_t0,
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input [9:0] din_n1,
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input [9:0] din_n2,
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output reg [9:0] dout
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);
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wire [13:0] multquartert0;
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wire [13:0] multquartern1;
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CN1_half CT0_half (.CLK(clk), .A(din_t0), .P(multquartert0));
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CN1_half CN1_half (.CLK(clk), .A(din_n1), .P(multquartern1));
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reg [9:0] multquarterp1 = 10'd0;
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reg [9:0] multquartern2 = 10'd0;
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always @(posedge clk)begin
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multquarterp1 <= din_p1;
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multquartern2 <= din_n2;
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end
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reg [14:0] sumquarter1 = 15'd0;
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reg [14:0] sumquarter2 = 15'd0;
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always @(posedge clk)begin
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sumquarter1 <= {multquartert0[13],multquartert0}-{{5{multquarterp1[9]}},multquarterp1};
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sumquarter2 <= {multquartern1[13],multquartern1}-{{5{multquartern2[9]}},multquartern2};
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end
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reg [15:0] sumquarter3 = 16'd0;
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always @(posedge clk)begin
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sumquarter3 <= {sumquarter2[14],sumquarter2}+{sumquarter1[14],sumquarter1};
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end
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always @(posedge clk)begin
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if(sumquarter3[15:13]==3'b111||sumquarter3[15:13]==3'b000)begin
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dout <= sumquarter3[13:4];
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end else begin
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dout <= (sumquarter3[15]==1'b1) ? 10'b10_0000_0000 : 10'b01_1111_1111;
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end
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end
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endmodule
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