197 lines
5.6 KiB
Verilog
197 lines
5.6 KiB
Verilog
`timescale 1ns / 1ns
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// +------------------------------+
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// | |
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// | |
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// +---------+------------> shift_ram(depth=1024) +-------------------+
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// | | | |
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// | | | |
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// | +------------------------------+ |
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// | |
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// | |
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// | |
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// | +------------+ |
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// | + | | - |
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// | | sliding | |
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// | | window | |
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// +---------------------> <----------------------------+
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// | |
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// +-----+------+
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// |
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// | average_out
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// |
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// v
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module PAPR #(
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parameter MAG_WIDTH = 22,
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parameter WINDOW_DEPTH = 1023
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// parameter GATE = 8
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) (
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input clk,
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input rst,
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input [MAG_WIDTH-1:0] vec_mag,
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input mag_valid,
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output reg frame_sync,
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output reg frame_sync_pulse
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);
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localparam SUM_WIDTH = 32;
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localparam CNT_START = 16; // 32*4 / 8 * mag_valid signal is active high per 8 clk
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localparam CNT_END = 44; // 88*4 / 8
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localparam PULSE_PERIOD = 50;
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reg [MAG_WIDTH-1:0] vec_mag_d1;
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reg [MAG_WIDTH-1:0] vec_mag_d2;
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reg [MAG_WIDTH-1:0] vec_mag_d3;
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reg [MAG_WIDTH-1:0] vec_mag_reserved;
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// accumulate ==> average ==> papr
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wire [MAG_WIDTH-1:0] vec_mag_1024;
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reg [ 7:0] cnt;
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wire [MAG_WIDTH-1:0] data_avg;
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reg [SUM_WIDTH-1:0] data_sum;
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assign data_avg = data_sum[SUM_WIDTH-1:10];
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always @(posedge clk) begin
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if (rst) begin
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vec_mag_d1 <= 0;
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vec_mag_d2 <= 0;
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vec_mag_d3 <= 0;
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end
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else if (mag_valid) begin
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vec_mag_d1 <= vec_mag;
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vec_mag_d2 <= vec_mag_d1;
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vec_mag_d3 <= vec_mag_d2;
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end
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else begin
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vec_mag_d1 <= vec_mag_d1;
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vec_mag_d2 <= vec_mag_d2;
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vec_mag_d3 <= vec_mag_d3;
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end
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end
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shift_reg #(
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.DATA_WIDTH(MAG_WIDTH),
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.DEPTH (WINDOW_DEPTH)
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) u_shift_reg (
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.clk (clk),
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.rst (rst),
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.we (mag_valid),
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.din (vec_mag),
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.dout(vec_mag_1024)
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);
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always @(posedge clk) begin
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if (rst) begin
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data_sum <= 0;
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end
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else begin
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if (mag_valid) begin
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data_sum <= data_sum + vec_mag - vec_mag_1024;
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end
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else begin
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data_sum <= data_sum;
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end
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end
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end
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// FSM
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reg [2:0] cs = 0;
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reg [2:0] ns = 0;
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always @(posedge clk) begin
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cs <= ns;
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end
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always @(*) begin
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ns = cs;
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case (cs)
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0: begin
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if (mag_valid && vec_mag_1024 != 'd0 && data_avg != 'd0 && ({3'd0, vec_mag_d2[MAG_WIDTH-1:3]} >= data_avg) && (vec_mag_d2 >= vec_mag_d1) && (vec_mag_d2 >= vec_mag_d3) && (vec_mag_d2 >= 22'h5000)) begin
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ns = 1;
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end
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end
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1: begin
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if (cnt == CNT_START - 1) begin
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ns = 2;
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end
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end
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2: begin
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if (vec_mag_reserved < {vec_mag[MAG_WIDTH-3:0], 2'b0}) begin
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ns = 0;
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end
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else if (cnt == CNT_END - 1) begin
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ns = 3;
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end
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end
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3: begin
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// generate pulse
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ns = 4;
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end
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4: begin
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if (cnt == PULSE_PERIOD - 1) begin
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ns = 0;
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end
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end
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endcase
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end
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always @(posedge clk) begin
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if (cs == 0 && ns == 1) begin
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vec_mag_reserved <= vec_mag_d2;
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end
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else if (cs == 0) begin
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vec_mag_reserved <= 0;
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end
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end
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always @(posedge clk) begin
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if (cs == 1 || cs == 2) begin
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if (mag_valid) begin
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cnt <= cnt + 1;
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end
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end
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else if (cs == 4) begin
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cnt <= cnt + 1;
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end
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else if (cs == 0) begin
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cnt <= 0;
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end
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end
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always @(posedge clk) begin
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frame_sync_pulse <= (cs == 3);
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if (cs == 4) begin
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frame_sync <= 1;
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end
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else begin
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frame_sync <= 0;
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end
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end
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ila_frame_sync u_ila_frame_sync (
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.clk (clk), // input wire clk
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.probe0(vec_mag), // input wire [21:0] probe0
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.probe1(data_avg), // input wire [21:0] probe0
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.probe2(cs), // input wire [2:0] probe2
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.probe3(cnt), // input wire [7:0] probe2
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.probe4(frame_sync), // input wire [0:0] probe2
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.probe5(vec_mag_reserved) // input wire [21:0] probe2
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);
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endmodule
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