83 lines
2.0 KiB
Verilog
83 lines
2.0 KiB
Verilog
module extract_mac_frame (
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input clk,
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input rst,
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// ldpc out
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input ldpc_dec_out_start,
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input ldpc_dec_out_valid,
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input ldpc_dec_out_data,
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// axis
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output wire m_axis_mac_frame_tvalid,
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output wire [31:0] m_axis_mac_frame_tdata,
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input m_axis_mac_frame_tready,
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output reg m_axis_mac_frame_tlast
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);
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// NOTE: module 1bit --> 32bit
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// transfer 1bit serial to 32bit and sent to axis fifo
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//
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localparam MAC_FRAME_LEN_BIT = 107520;
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localparam MAC_FRAME_LEN_BYTE = 13440;
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localparam MAC_FRAME_LEN_QUAD_BYTE = 3360;
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// ******** Wire & Reg ********
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reg [15:0] cnt_axis_out;
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wire flag_handshake;
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// serial input
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wire ser;
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wire ser_valid;
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wire [31:0] par;
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wire par_valid;
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// ******** Assingment ********
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assign ser = ldpc_dec_out_data;
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assign ser_valid = ldpc_dec_out_valid;
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assign m_axis_mac_frame_tvalid = par_valid;
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assign m_axis_mac_frame_tdata = par;
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assign flag_handshake = m_axis_mac_frame_tvalid & m_axis_mac_frame_tready;
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// ******** Logic Block ********
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always @(posedge clk) begin
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if (rst) begin
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cnt_axis_out <= 0;
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end
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else if (flag_handshake) begin
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cnt_axis_out <= cnt_axis_out + 1;
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end
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end
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always @(*) begin
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if (cnt_axis_out == MAC_FRAME_LEN_QUAD_BYTE - 1 && flag_handshake) begin
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m_axis_mac_frame_tlast = 1;
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end
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else begin
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m_axis_mac_frame_tlast = 0;
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end
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end
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// ******** Inst ********
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// serial 1bit --> 32bit
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ser2par u_ser2par (
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.clk (clk),
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.rst (rst),
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.ser (ser),
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.ser_valid(ser_valid),
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.par (par),
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.par_valid(par_valid)
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);
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// ******** Debug ********
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endmodule
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