410 lines
13 KiB
Verilog
410 lines
13 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/12/20 21:52:37
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// Design Name:
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// Module Name: SCFDE_recv_FrameSync
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module SCFDE_recv_FrameSync (
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input clk,
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input rst,
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input rst_ready,
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input [9:0] datain_i,
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input [9:0] datain_q,
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input debug_loss,
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output reg [9:0] Sync_i = 10'd0,
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output reg [9:0] Sync_q = 10'd0,
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output reg Sync_rdy = 1'b0, //判断出峰的标志位，出峰后拉高1clk
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output reg Pilot_rdy = 1'b0, //出峰后88个clk后拉高1clk，对齐导频头
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output reg flag_sync = 1'b0,
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output reg Pilot_rdy_hide1_d1 = 1'b0
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//debug
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);
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//----------卷积与流水累加替代模块----------//
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//wire [19:0] add_regi_2048;
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//wire [19:0] add_regq_2048;
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wire [18:0] add_regi_19bit;
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wire [18:0] add_regq_19bit;
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/*conv_add conv_add(
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.clk(clk),
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.rst(rst),
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.data_i(datain_i),
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.data_q(datain_q),
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.add_regi_2048(add_regi_2048),
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.add_regq_2048(add_regq_2048)
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);*/
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wire [ 9:0] dataout_i;
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wire dout_valid_i;
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DMF DMF_i (
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.clk (clk),
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.rst (rst),
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.din_data (datain_i),
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.din_valid (1'b1),
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.dout_dmf (add_regi_19bit),
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.dout_data (dataout_i),
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.dout_valid(dout_valid_i)
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);
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wire [9:0] dataout_q;
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wire dout_valid_q;
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DMF DMF_q (
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.clk (clk),
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.rst (rst),
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.din_data (datain_q),
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.din_valid (1'b1),
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.dout_dmf (add_regq_19bit),
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.dout_data (dataout_q),
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.dout_valid(dout_valid_q)
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);
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//----------将实部和虚部的相关结果求近似模值----------//
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//----------6 delay----------//
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wire [19:0] reg_add11;
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wire [18:0] add_regi;
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wire [18:0] add_regq;
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wire ApproxAbs_rdy;
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assign add_regi = (add_regi_19bit[18] == 1'd1) ? -add_regi_19bit : add_regi_19bit;
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assign add_regq = (add_regq_19bit[18] == 1'd1) ? -add_regq_19bit : add_regq_19bit;
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ApproxAbs_v2_20bit ApproxAbs_v2_tsync4 (
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.clk (clk),
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.ND (dout_valid_i),
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.Din_I(add_regi),
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.Din_Q(add_regq),
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.Dout (reg_add11),
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.Rdy (ApproxAbs_rdy)
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);
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//----------将1024个相关结果流水累加----------//
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reg rst_1 = 1'b0;
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reg [7:0] rst_1_cnt = 8'b0;
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always @(posedge clk) begin
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if (!ApproxAbs_rdy) begin
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rst_1_cnt = 8'b0;
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end
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else begin
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rst_1_cnt <= rst_1_cnt > 8'd128 ? 8'd129 : rst_1_cnt + 8'd1;
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end
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rst_1 <= (rst_1_cnt < 8'd128);
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end
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wire [19:0] average_add10;
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average_1024 average_1024 (
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.clk (clk),
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.rst (rst_1),
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.nd (ApproxAbs_rdy),
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.din (reg_add11),
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.average(average_add10)
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);
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//----------将和求平均值，从而得到门限----------//
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reg [19:0] reg_save1024 = 20'd0;
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reg [19:0] reg_save1024_d1 = 20'd0;
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reg [19:0] reg_save1024_d2 = 20'd0;
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reg [19:0] reg_save1024_d2_x2 = 20'd0;
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reg [19:0] reg_save_pilot;
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reg [19:0] Threshold;
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reg [ 3:0] th_control = 4'd8;
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always @(posedge clk) begin
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if (rst) begin
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reg_save1024 <= 20'd0;
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reg_save1024_d1 <= 20'd0;
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reg_save1024_d2 <= 20'd0;
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reg_save1024_d2_x2 <= 20'd0;
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Threshold <= 20'd0;
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end
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else begin
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reg_save1024 <= reg_add11;
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reg_save1024_d1 <= reg_save1024;
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reg_save1024_d2 <= reg_save1024_d1;
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case (th_control)
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4'd1: begin
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Threshold <= average_add10;
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reg_save1024_d2_x2 <= reg_save1024_d1;
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end
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4'd2: begin
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Threshold <= {average_add10[18:0], 1'b0};
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reg_save1024_d2_x2 <= reg_save1024_d1;
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end
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4'd3: begin
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Threshold <= average_add10 + {average_add10[18:0], 1'b0};
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reg_save1024_d2_x2 <= reg_save1024_d1;
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end
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4'd4: begin
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Threshold <= {average_add10[17:0], 2'b00};
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reg_save1024_d2_x2 <= {reg_save1024_d1[18:0], 1'b0};
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end
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4'd5: begin
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Threshold <= average_add10 + {average_add10[17:0], 2'b00};
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reg_save1024_d2_x2 <= {reg_save1024_d1[18:0], 1'b0};
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end
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4'd6: begin
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Threshold <= {average_add10[18:0], 1'b0} + {average_add10[17:0], 2'b00};
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reg_save1024_d2_x2 <= reg_save1024_d1 + {reg_save1024_d1[18:0], 1'b0};
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end
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4'd7: begin
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Threshold <= average_add10 + {average_add10[18:0], 1'b0} + {average_add10[17:0], 2'b0};
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reg_save1024_d2_x2 <= reg_save1024_d1 + {reg_save1024_d1[18:0], 1'b0};
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end
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4'd8: begin
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Threshold <= {average_add10[16:0], 3'b000};
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reg_save1024_d2_x2 <= {reg_save1024_d1[17:0], 2'b00};
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end
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4'd9: begin
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Threshold <= average_add10 + {average_add10[16:0], 3'b000};
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reg_save1024_d2_x2 <= {reg_save1024_d1[17:0], 2'b00};
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end
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default: begin
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Threshold <= {average_add10[17:0], 2'b00};
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reg_save1024_d2_x2 <= {reg_save1024_d1[18:0], 1'b0};
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end
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endcase
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end
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end
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//----------将相关求和后的近似模值与门限比较；若高于门限，再与相邻近似模值比较----------//
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reg [ 6:0] counter88 = 7'd0;
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//rst之后500个clk之内不允许拉高Pilot_rdy_hide1
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reg [11:0] count_rst500 = 12'd0;
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reg [ 3:0] state_framesync;
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always @(posedge clk) begin
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if (rst) begin
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count_rst500 <= 15'd0;
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state_framesync <= 4'd0;
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counter88 <= 7'd0;
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reg_save_pilot <= 20'd0;
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Pilot_rdy_hide1_d1 <= 1'b0;
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flag_sync <= 1'b0;
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Sync_rdy <= 1'b0;
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end
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else begin
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case (state_framesync)
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4'd0: begin
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if (count_rst500 == 12'd32) begin //等待32个clk的rst
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count_rst500 <= 12'd0;
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state_framesync <= 4'd1;
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end
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else begin
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count_rst500 <= count_rst500 + 12'd1;
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state_framesync <= state_framesync;
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end
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end
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4'd1: begin
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if (Threshold != 20'd0) begin
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state_framesync <= 4'd2;
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end
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else begin
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state_framesync <= state_framesync;
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end
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end
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4'd2: begin
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if (count_rst500 == 12'd2048) begin //等待计数过2048个clk
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count_rst500 <= 12'd0;
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state_framesync <= 4'd3;
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end
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else begin
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count_rst500 <= count_rst500 + 12'd1;
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state_framesync <= state_framesync;
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end
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end
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4'd3: begin
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if ((reg_save1024_d1 > Threshold)) begin //检测到过门限值
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if ((reg_save1024_d1 >= reg_save1024) && (reg_save1024_d1 >= reg_save1024_d2)) begin
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if (reg_save1024_d1 >= 20'd128) begin
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Sync_rdy <= 1'b1;
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state_framesync <= 4'd4;
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reg_save_pilot <= reg_save1024_d1;
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end
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else begin
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Sync_rdy <= 1'b0;
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state_framesync <= state_framesync;
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end
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end
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else begin
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Sync_rdy <= 1'b0;
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end
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end
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else begin
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Sync_rdy <= 1'b0;
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end
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end
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4'd4: begin
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if (counter88 == 7'd86) begin
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Sync_rdy <= 1'b0;
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flag_sync <= 1'b1;
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Pilot_rdy_hide1_d1 <= 1'b1;
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state_framesync <= 4'd5;
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end
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else if (counter88 >= 7'd32) begin
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if (reg_save_pilot >= reg_save1024_d2_x2) begin // ? reg_save_pilot是DMF滤波器输出峰值
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counter88 <= counter88 + 7'd1;
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end
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else begin
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counter88 <= 7'd0;
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state_framesync <= 4'd3;
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Sync_rdy <= 1'b0;
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end
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flag_sync <= 1'b0;
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end
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else begin
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counter88 <= counter88 + 7'd1;
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flag_sync <= 1'b0;
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end
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end
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4'd5: begin
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flag_sync <= 1'b1;
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Pilot_rdy_hide1_d1 <= 1'b0;
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state_framesync <= state_framesync;
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end
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default: begin
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if (count_rst500 == 12'd32) begin
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count_rst500 <= 12'd0;
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state_framesync <= 4'd1;
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end
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else begin
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count_rst500 <= count_rst500 + 12'd1;
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state_framesync <= state_framesync;
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end
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end
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endcase
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end
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end
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//----------将输入数据打延迟，与Sync_rdy拉高的时刻同步输出----------//
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reg [9:0] datain_i_d1;
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reg [9:0] datain_q_d1;
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reg [9:0] datain_i_d2;
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reg [9:0] datain_q_d2;
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reg [9:0] datain_i_d3;
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reg [9:0] datain_q_d3;
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reg [9:0] datain_i_d4;
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reg [9:0] datain_q_d4;
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reg [9:0] datain_i_d5;
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reg [9:0] datain_q_d5;
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reg [9:0] datain_i_d6;
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reg [9:0] datain_q_d6;
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reg [9:0] datain_i_d7;
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reg [9:0] datain_q_d7;
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reg [9:0] datain_i_d8;
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reg [9:0] datain_q_d8;
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reg [9:0] datain_i_d9;
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reg [9:0] datain_q_d9;
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/*shift_ram_x shift_ram_i1 (
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.D(datain_i),
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.CLK(clk),
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.Q(datain_i_d3)
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);
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wire [9:0] datain_q_d3;
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shift_ram_x shift_ram_q1 (
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.D(datain_q),
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.CLK(clk),
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.Q(datain_q_d3)
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);*/
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always @(posedge clk) begin
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if (rst) begin
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Sync_i <= 10'd0;
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Sync_q <= 10'd0;
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datain_i_d1 <= 10'd0;
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datain_q_d1 <= 10'd0;
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datain_i_d2 <= 10'd0;
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datain_q_d2 <= 10'd0;
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datain_i_d3 <= 10'd0;
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datain_q_d3 <= 10'd0;
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datain_i_d4 <= 10'd0;
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datain_q_d4 <= 10'd0;
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datain_i_d5 <= 10'd0;
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datain_q_d5 <= 10'd0;
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datain_i_d6 <= 10'd0;
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datain_q_d6 <= 10'd0;
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datain_i_d7 <= 10'd0;
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datain_q_d7 <= 10'd0;
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datain_i_d8 <= 10'd0;
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datain_q_d8 <= 10'd0;
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datain_i_d9 <= 10'd0;
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datain_q_d9 <= 10'd0;
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end
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else begin
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datain_i_d1 <= datain_i;
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datain_q_d1 <= datain_q;
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datain_i_d2 <= datain_i_d1;
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datain_q_d2 <= datain_q_d1;
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datain_i_d3 <= datain_i_d2;
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datain_q_d3 <= datain_q_d2;
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datain_i_d4 <= datain_i_d3;
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datain_q_d4 <= datain_q_d3;
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datain_i_d5 <= datain_i_d4;
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datain_q_d5 <= datain_q_d4;
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datain_i_d6 <= datain_i_d5;
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datain_q_d6 <= datain_q_d5;
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datain_i_d7 <= datain_i_d6;
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datain_q_d7 <= datain_q_d6;
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datain_i_d8 <= datain_i_d7;
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datain_q_d8 <= datain_q_d7;
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datain_i_d9 <= datain_i_d8;
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datain_q_d9 <= datain_q_d8;
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Sync_i <= datain_i_d9;
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Sync_q <= datain_q_d9;
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end
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end
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// `ifdef FrameSync_debug
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/* ila_FS_inst ila_FS_inst(
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.clk(clk),
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.probe0(datain_i),//10
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.probe1(datain_q),//10
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.probe2(rst),//1
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.probe3(Pilot_rdy_hide1_d1),//1
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.probe4(reg_save1024_d2_x2),//20
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.probe5(average_add10),//20
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.probe6(Threshold),//20
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.probe7(reg_save1024_d1),//20
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.probe8(debug_loss),//1
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.probe9(flag_sync),//1
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.probe10(state_framesync),//4
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.probe11(counter88),//7
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.probe12(Sync_rdy),//1
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.probe13(th_control)//4
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);*/
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// ILA LARGE
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/*ila_large ila_MF_large_inst(
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.clk(clk),
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.probe0(datain_i[9:0]),
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.probe1({rst_ready,rst,Pilot_rdy_hide1})
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);*/
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// `endif
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endmodule
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