83 lines
1.9 KiB
Verilog
83 lines
1.9 KiB
Verilog
`timescale 1ns / 1ns
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module tb_extract_mac_frame ();
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reg clk = 0;
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always #1 clk <= ~clk;
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reg [ 3:0] cnt_startup = 0;
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reg rst;
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reg ldpc_in;
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reg [31:0] cnt_in = 0;
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reg [ 4:0] cnt_sleep = 0;
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reg sleep = 0;
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reg cnt_in_valid = 0;
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wire m_axis_mac_frame_tvalid;
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wire [31:0] m_axis_mac_frame_tdata;
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wire m_axis_mac_frame_tlast;
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always @(posedge clk) begin
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if (m_axis_mac_frame_tlast == 1) begin
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cnt_startup <= 0;
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end
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else if (cnt_startup < 4'hF) begin
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cnt_startup <= cnt_startup + 1;
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end
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rst <= cnt_startup <= 4'hC;
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end
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always @(posedge clk) begin
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if (rst) begin
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cnt_in <= 0;
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end
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ldpc_in <= $random();
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if (cnt_startup == 4'hF) begin
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if (sleep) begin
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cnt_in <= 0;
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cnt_in_valid <= 0;
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cnt_sleep <= cnt_sleep + 1;
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if (cnt_sleep == 5'b11111) begin
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sleep <= 0;
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end
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end
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else begin
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cnt_sleep <= 0;
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if (cnt_in < 1024) begin
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cnt_in <= cnt_in + 1;
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end
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if (cnt_in == 1023) begin
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sleep <= 1;
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end
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cnt_in_valid <= 1;
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end
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end
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end
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extract_mac_frame u_extract_mac_frame (
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.clk (clk),
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.rst (rst),
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.ldpc_dec_out_start (cnt_startup == 4'hD),
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.ldpc_dec_out_valid (cnt_in_valid),
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.ldpc_dec_out_data (ldpc_in),
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.m_axis_mac_frame_tvalid(m_axis_mac_frame_tvalid),
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.m_axis_mac_frame_tdata (m_axis_mac_frame_tdata),
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.m_axis_mac_frame_tready(1),
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.m_axis_mac_frame_tlast (m_axis_mac_frame_tlast)
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);
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endmodule
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