342 lines
13 KiB
Verilog
342 lines
13 KiB
Verilog
`timescale 1ns / 1ns
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// *******************************************************
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// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ *
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// * ╚══███╔╝██╔═══██╗██╔══██╗██╔═══██╗██╔════╝ ██║ ██║ *
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// * ███╔╝ ██║ ██║██████╔╝██║ ██║██║ ███╗███████║ *
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// * ███╔╝ ██║ ██║██╔══██╗██║ ██║██║ ██║██╔══██║ *
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// * ███████╗╚██████╔╝██║ ██║╚██████╔╝╚██████╔╝██║ ██║ *
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// * ╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ *
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// *******************************************************
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// * this module get data from the ps ( a axis-fifo in fact)
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// * and then use the ldpc algorithm to encode the data, which
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// * is 16 bit parallel, then it dose a width convert to
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// * 2 bit (i and q) , add a prefix which is 8 sym len. finally,
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// * send the data with prefix to a fifo (2 bit width, ditributed ram),
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// * waiting the transmitter to fetch
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// *
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// * later update (2024/5/14):
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// * we find the 16bit parallel cost too much resource, so we change it
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// * to 1bit serial module,
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// * 该模块首先将输入的数据32bit数据进行位宽转换为1bit数据，输入到ldpc模块中进行编码
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// * 然后将ldpc模块通过fifo进行位宽转换成2bit数据（Q，I），然后添加循环前缀（8个符号）
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// * 送入到fifo_enc_out中，并结束。
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// *
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// * Q : 何时开始编码？
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// * A : 前端有数据下发，且该模块是输出fifo模块中数据不足（<200syms)才进行编码。
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module enc_control #(
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parameter ENC_IN_LEN = 1024,
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parameter ENC_OUT_LEN = 2048,
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parameter INPUT_DATA_WIDTH = 32
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) (
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input clk,
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input rst,
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//from ps axis-fifo
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input s_axis_fifo_tvalid,
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output reg s_axis_fifo_tready,
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input [INPUT_DATA_WIDTH - 1:0] s_axis_fifo_tdata,
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input [ 31:0] data_src_count,
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// fifo signal
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input wire fifo_enc_out_rd_clk,
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input wire fifo_enc_out_rd_en,
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output wire [ 31:0] fifo_enc_out_dout_map,
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output wire fifo_enc_out_empty
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);
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// ******** Wire & Reg ********
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localparam CNT_IN_MAX = ENC_IN_LEN / INPUT_DATA_WIDTH;
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localparam CNT_IN_WIDTH = $clog2(CNT_IN_MAX);
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localparam CNT_OUT_MAX = ENC_OUT_LEN;
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localparam CNT_OUT_WIDTH = $clog2(CNT_OUT_MAX); // 多留1bit
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// status
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localparam [3:0] S_IDLE = 4'd0;
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localparam [3:0] S_START = 4'd1;
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localparam [3:0] S_WAIT_LDPC_OUT = 4'd2;
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localparam [3:0] S_WAIT_ADD_PREFIX_DONE = 4'd3;
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reg [ 3:0] cs;
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reg [ 3:0] ns;
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// input data width convert
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reg wc_data_in_valid;
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wire wc_data_in_ready;
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wire [ 31:0] wc_data_in;
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wire wc_data_out_valid;
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wire wc_data_out;
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// ldpc io signal
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reg ldpc_in_start;
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reg ldpc_in_valid;
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wire ldpc_out_start;
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wire ldpc_out_valid;
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wire ldpc_dout;
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// ldpc io cnt
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reg [ CNT_IN_WIDTH : 0] cnt_in; // 多留1bit
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reg [CNT_OUT_WIDTH : 0] cnt_out; // 多留1bit
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// map
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wire [ 1:0] fifo_enc_out_dout;
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wire [ 15:0] fifo_enc_out_dout_i;
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wire [ 15:0] fifo_enc_out_dout_q;
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wire fifo_enc_out_almost_empty;
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wire fifo_enc_out_prog_empty_1x; // 20 sym
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wire fifo_enc_out_prog_empty; // 20 sym
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// control the fifo width convert read channel
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wire fifo_wc_prog_full;
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reg fifo_wc_prog_full_d1;
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wire fifo_wc_empty;
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reg add_prefix_start;
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// signal for add_prefix
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reg [ 2:0] cnt_add_prefix_in;
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wire add_prefix_in_ready;
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wire [ 1:0] data_add_prefix_in;
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wire data_add_prefix_in_ready;
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wire [ 1:0] data_add_prefix_out;
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wire data_add_prefix_out_valid;
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// ******** Assingment ********
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assign fifo_enc_out_dout_i = (fifo_enc_out_dout[0] == 1'b0) ? 16'h7FFF : 16'h8001;
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assign fifo_enc_out_dout_q = (fifo_enc_out_dout[1] == 1'b0) ? 16'h7FFF : 16'h8001;
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assign fifo_enc_out_dout_map = {fifo_enc_out_dout_q, fifo_enc_out_dout_i};
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assign wc_data_in = s_axis_fifo_tdata;
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// ******** Logic Block ********
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always @(posedge clk) begin
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if (rst == 1'b1) begin
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cs <= S_IDLE;
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end
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else begin
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cs <= ns;
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end
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end
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// fsm
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always @(*) begin
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// NOTE: S_IDLE --> START (width convert --> encoding module) --> wait output done --> IDLE
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case (cs)
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S_IDLE: begin
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// ! attention
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// if source is valid which means there are data waiting for encoding
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// and the pre-stage fifo counts not equal 0
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// and the width convert fifo is empty
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// and the finally stage fifo is almost empty
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// TODO:check the conditions, done 2024年5月27日
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if (s_axis_fifo_tvalid && data_src_count >= 32 && fifo_enc_out_prog_empty && ~data_add_prefix_in_ready && ~data_add_prefix_out_valid) begin
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ns = S_START;
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end
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else begin
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ns = S_IDLE;
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end
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end
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S_START: begin
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ns = S_WAIT_LDPC_OUT;
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end
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S_WAIT_LDPC_OUT: begin
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if (cnt_out == CNT_OUT_MAX) begin
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ns = S_WAIT_ADD_PREFIX_DONE;
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end
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else begin
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ns = S_WAIT_LDPC_OUT;
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end
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end
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S_WAIT_ADD_PREFIX_DONE: begin
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if (fifo_wc_empty && add_prefix_in_ready) begin
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ns = S_IDLE;
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end
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else begin
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ns = S_WAIT_ADD_PREFIX_DONE;
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end
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end
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default: begin
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ns = S_IDLE;
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end
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endcase
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end
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always @(posedge clk) begin
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if (rst) begin
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wc_data_in_valid <= 0;
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end
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else if (ns == S_START || cnt_in < CNT_IN_MAX && cs != S_IDLE) begin
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wc_data_in_valid <= s_axis_fifo_tvalid;
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end
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else begin
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wc_data_in_valid <= 0;
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end
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end
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always @(*) begin
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if (rst) begin
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s_axis_fifo_tready = 0;
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end
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else begin
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if (cs != S_IDLE && cnt_in < CNT_IN_MAX) begin
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s_axis_fifo_tready = wc_data_in_ready;
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end
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else begin
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s_axis_fifo_tready = 0;
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end
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end
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end
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always @(*) begin
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ldpc_in_start = (cs == S_START);
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ldpc_in_valid = wc_data_out_valid;
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end
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always @(posedge clk) begin
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if (cs == S_IDLE) begin
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cnt_in <= 0;
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end
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else if (wc_data_in_ready && wc_data_in_valid) begin
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cnt_in <= cnt_in + 1;
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end
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end
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always @(posedge clk) begin
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if (ldpc_out_start || cnt_out > 0 && cnt_out <= CNT_OUT_MAX) begin
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cnt_out <= cnt_out + 1;
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end
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else begin
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cnt_out <= 0;
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end
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end
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// get the rising edge
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always @(posedge clk) begin
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fifo_wc_prog_full_d1 <= fifo_wc_prog_full;
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end
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// shit code, no modify timing is in a mess
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always @(posedge clk) begin
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if (rst) begin
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cnt_add_prefix_in <= 0;
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end
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else if (fifo_wc_prog_full & ~fifo_wc_prog_full_d1) begin
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cnt_add_prefix_in <= cnt_add_prefix_in + 1;
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end
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else if (add_prefix_start) begin
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if (cnt_add_prefix_in < 4) begin
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cnt_add_prefix_in <= cnt_add_prefix_in + 1;
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end
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else begin
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cnt_add_prefix_in <= 0;
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end
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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add_prefix_start <= 0;
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end
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else if (fifo_wc_prog_full & ~fifo_wc_prog_full_d1 || cnt_add_prefix_in > 0 && add_prefix_in_ready && ~add_prefix_start) begin
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add_prefix_start <= 1'b1;
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end
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else begin
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add_prefix_start <= 1'b0;
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end
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end
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// ******** Inst ********
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width_convert #(
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.INPUT_WIDTH (32),
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.OUTPUT_WIDTH(1)
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) u_width_convert (
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.clk (clk),
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.rst (rst),
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.data_in_valid (wc_data_in_valid),
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.data_in_ready (wc_data_in_ready),
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.data_in (wc_data_in),
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.data_out_valid(wc_data_out_valid),
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.data_out (wc_data_out)
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);
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// encoding module
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CCSDS_LDPC_ENC_R12 u_CCSDS_LDPC_ENC_R12 (
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.clk (clk),
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.rst (rst),
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.Encoder_SyncIn (ldpc_in_start),
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.Encoder_Nd (ldpc_in_valid),
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.Encoder_Din (wc_data_out),
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.Encode_Dout (ldpc_dout),
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.Encode_Sync_Dout(ldpc_out_start),
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.Encode_Rdy (ldpc_out_valid)
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);
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fifo_width_convert_1_2 u_fifo_width_convert_1_2 (
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.clk (clk), // input wire clk
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.srst (rst), // input wire srst
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.din (ldpc_dout), // input wire [0 : 0] din
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.wr_en (ldpc_out_valid), // input wire wr_en
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.rd_en (data_add_prefix_in_ready), // input wire rd_en
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.dout (data_add_prefix_in), // output wire [1 : 0] dout
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.full (), // output wire full
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.empty (fifo_wc_empty), // output wire empty
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.prog_full(fifo_wc_prog_full)
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);
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add_prefix #(
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.WIDTH (2), // ! if this parameter is changed, make sure the shift IP inside is also changed
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.DATA_LEN (256), //! if the WIDTH or DATA_LEN parameter is changed, make sure the shift IP inside is also changed
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.PREFIX_LEN(32)
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) u_add_prefix (
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.clk (clk),
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.start (add_prefix_start),
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.ready (add_prefix_in_ready),
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.data_in ({data_add_prefix_in[0], data_add_prefix_in[1]}), // NOTE : reverse to adjust to IQmerge module
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.data_in_ready (data_add_prefix_in_ready),
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.data_out (data_add_prefix_out),
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.data_out_valid(data_add_prefix_out_valid)
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);
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fifo_enc_out u_fifo_enc_out (
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.rst (rst), // input wire rst
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.wr_clk (clk), // input wire wr_clk
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.rd_clk (fifo_enc_out_rd_clk), // input wire rd_clk
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.din (data_add_prefix_out), // input wire [1 : 0] din
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.wr_en (data_add_prefix_out_valid), // input wire wr_en
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.rd_en (fifo_enc_out_rd_en), // input wire rd_en
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.dout (fifo_enc_out_dout), // output wire [1 : 0] dout
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.full (), // output wire full
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.empty (fifo_enc_out_empty), // output wire empty
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.almost_empty(fifo_enc_out_almost_empty), // output wire almost_empty
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.prog_empty (fifo_enc_out_prog_empty_1x) // output wire prog_empty
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);
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xpm_cdc_single #(
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.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
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.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
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.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
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.SRC_INPUT_REG (1) // DECIMAL; 0=do not register input, 1=register input
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) xpm_cdc_single_inst (
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.dest_out(fifo_enc_out_prog_empty), // 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
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.dest_clk(clk), // 1-bit input: Clock signal for the destination clock domain.
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.src_clk (fifo_enc_out_rd_clk), // 1-bit input: optional; required when SRC_INPUT_REG = 1
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.src_in (fifo_enc_out_prog_empty_1x) // 1-bit input: Input signal to be synchronized to dest_clk domain.
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);
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// ******** Debug ********
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endmodule
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