83 lines
3.0 KiB
Verilog
83 lines
3.0 KiB
Verilog
`timescale 1ns / 1ns
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// * Engineer:
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// * *************************************************** *
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// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ *
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// * ╚══███╔╝██╔═══██╗██╔══██╗██╔═══██╗██╔════╝ ██║ ██║ *
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// * ███╔╝ ██║ ██║██████╔╝██║ ██║██║ ███╗███████║ *
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// * ███╔╝ ██║ ██║██╔══██╗██║ ██║██║ ██║██╔══██║ *
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// * ███████╗╚██████╔╝██║ ██║╚██████╔╝╚██████╔╝██║ ██║ *
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// * ╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ *
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// * *************************************************** *
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// * Create Date: 2024/04/08
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// * Update Date: 2024/05/17
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// ! PLEASE MAKE SURE THE PARAMETER ARE VALID
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// ! WHEN U INSTANTIATE THIS MODULE
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module tdma #(
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parameter SLOT_LEN = 1250000,
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parameter TIC_TO_PS_LEN = 1200000,
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parameter TIC_FRAME_SYNC = 42272
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) (
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input clk,
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input rst,
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input flag_is_master, // TODO: refactor it to parameters
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input flag_frame_sync,
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output intr_2ps,
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(* KEEP = "TRUE" *) output tx_start,
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(* KEEP = "TRUE" *) output rx_rst
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);
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// TODO: 需要检查综合后电路是否会被优化
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// BUG: 需要修复bug，重构代码，把主从分开写，通过参数进行优化
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// ******** Wire & Reg ********
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reg flag_is_tx_slot;
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// ******** Assingment ********
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// ******** Logic Block ********
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reg [23:0] cnt;
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always @(posedge clk) begin
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if (rst) begin
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cnt <= 0;
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end
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else begin
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if (!flag_is_master && flag_frame_sync) begin
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// slave update cnt
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cnt <= TIC_FRAME_SYNC;
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end
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else begin
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// master
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if (cnt < SLOT_LEN) begin
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cnt <= cnt + 1;
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end
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else begin
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cnt <= 0;
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end
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end
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end
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end
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assign tx_start = flag_is_tx_slot & (cnt == 16'd10);
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assign rx_rst = flag_is_tx_slot | (~flag_is_tx_slot & (cnt <= 16'd10));
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assign intr_2ps = ~flag_is_tx_slot & (cnt == TIC_TO_PS_LEN);
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always @(posedge clk) begin
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if (rst) begin
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flag_is_tx_slot <= 0;
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end
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else if (!flag_is_master && flag_frame_sync) begin
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flag_is_tx_slot <= 0;
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end
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else if (cnt == 16'd1) begin
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flag_is_tx_slot <= ~flag_is_tx_slot;
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end
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end
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// ******** Inst ********
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// ******** Debug ********
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endmodule
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