MM7020/sim/TB_sys.v

`timescale 10ns / 10ns
module TB_sys ();


    reg clk;
    reg req;
    always #1 clk <= ~clk;




    // ******** Wire & Reg  ********

    // power on clock domain
    wire        clk_poweron;
    (*max_fanout = 256 *)
    wire        rst_sys;
    wire        poweron_locked;

    // ad9361 clock domain
    wire        locked;
    wire        clk_1x;
    wire        clk_2x;
    wire        clk_4x;

    // emio
    wire [31:0] gpio_i;
    wire [31:0] gpio_o;
    wire [31:0] gpio_t;

    // enc signal
    wire        enc_fifo_rd_en;
    wire [31:0] enc_fifo_dout_map;
    wire        enc_fifo_empty;

    // tx bus
    wire        clk_tx_data_src;
    wire [31:0] tx_data_src_count;
    wire [15:0] tx_data_src_tdata;
    wire        tx_data_src_tready;
    wire        tx_data_src_tvalid;

    // baseband signal
    wire [11:0] ad9361_rx_data_i;
    wire [11:0] ad9361_rx_data_q;
    wire        ad9361_rx_frame_i;
    wire        ad9361_rx_frame_q;
    wire [11:0] ad9361_tx_data_i;
    wire [11:0] ad9361_tx_data_q;

    // test
    wire        flag_transmitter_test;


    reg         pl2ps_intr2;
    reg  [31:0] cnt;


    // ******** Assingment  ********

    assign ad9361_tx_clk  = clk_1x;
    assign rst_sys        = ~poweron_locked;
    // ad9361 control
    assign ad9361_enable  = gpio_o[0];  // ad9361 enable state machine control
    assign ad9361_en_agc  = gpio_o[1];  // ad9361 agc control
    assign ad9361_reset_b = gpio_o[2];  // ad9361 reset
    assign ad9361_txnrx   = gpio_o[3];  // ad9361 txnrx


    // ******** Logic Block ********

    always @(posedge clk) begin
        if (rst_sys) begin
            pl2ps_intr2 <= 0;
            cnt         <= 0;
        end
        else begin
            cnt <= cnt + 1;
            if (cnt == 1000 || cnt == 1500 || cnt == 2000) begin
                pl2ps_intr2 <= 1;
            end
            else begin
                pl2ps_intr2 <= 0;
            end
        end
    end

    // ********    Inst     ********

    clk_wiz_poweron u_clk_wiz_poweron (
        // Clock out ports
        .clk_poweron(clk_poweron),     // output clk_poweron
        // Status and control signals
        .locked     (poweron_locked),  // output locked
        // Clock in ports
        .clk_crystal(clk_crystal)      // input clk_crystal
    );

    // clock domain - ad9361 rx & tx 
    clk_wiz_baseband u_clk_wiz_baseband (
        // Clock out ports
        .clk_1x (clk_1x),        // output clk_1x
        .clk_2x (clk_2x),        // output clk_2x
        .clk_4x (clk_4x),        // output clk_4x
        // Status and control signals
        .locked (locked),        // output locked
        // Clock in ports
        .clk_src(ad9361_rx_clk)  // input clk_src
    );

    MM7020_BD_wrapper u_MM7020_BD_wrapper (
        .ad9361_spi_clk    (ad9361_spi_clk),
        .ad9361_spi_csn    (ad9361_spi_csn),
        .ad9361_spi_miso   (ad9361_spi_miso),
        .ad9361_spi_mosi   (ad9361_spi_mosi),
        .clk_ps            (clk_poweron),
        .rst_ps            (rst_sys),
        // ddr
        .ddr_addr          (ddr_addr),
        .ddr_ba            (ddr_ba),
        .ddr_cas_n         (ddr_cas_n),
        .ddr_ck_n          (ddr_ck_n),
        .ddr_ck_p          (ddr_ck_p),
        .ddr_cke           (ddr_cke),
        .ddr_cs_n          (ddr_cs_n),
        .ddr_dm            (ddr_dm),
        .ddr_dq            (ddr_dq),
        .ddr_dqs_n         (ddr_dqs_n),
        .ddr_dqs_p         (ddr_dqs_p),
        .ddr_odt           (ddr_odt),
        .ddr_ras_n         (ddr_ras_n),
        .ddr_reset_n       (ddr_reset_n),
        .ddr_we_n          (ddr_we_n),
        // fixed io
        .fixed_io_ddr_vrn  (fixed_io_ddr_vrn),
        .fixed_io_ddr_vrp  (fixed_io_ddr_vrp),
        .fixed_io_mio      (fixed_io_mio),
        .fixed_io_ps_clk   (fixed_io_ps_clk),
        .fixed_io_ps_porb  (fixed_io_ps_porb),
        .fixed_io_ps_srstb (fixed_io_ps_srstb),
        // gpio ps
        .gpio_i            (gpio_i),
        .gpio_o            (gpio_o),
        .gpio_t            (gpio_t),
        // intr  pl to ps
        .pl2ps_intr2       (pl2ps_intr2),
        .pl2ps_intr3       (pl2ps_intr3),
        // tx fifo
        .tx_data_src_count (tx_data_src_count),
        .tx_data_src_tdata (tx_data_src_tdata),
        .tx_data_src_tready(tx_data_src_tready),
        .tx_data_src_tvalid(tx_data_src_tvalid),
        // uart 
        .uart_rx           (uart_rx),
        .uart_tx           (uart_tx)
    );




    // ---- PHY layer logic start

    // enc_control u_enc_control (
    //     .clk               (clk_poweron),
    //     .rst               (rst_sys),
    //     .s_axis_fifo_tvalid(tx_data_src_tvalid),
    //     .s_axis_fifo_tready(tx_data_src_tready),
    //     .s_axis_fifo_tdata (tx_data_src_tdata),
    //     .data_src_count    (tx_data_src_count),
    //     .fifo_rd_clk       (clk_1x),
    //     .fifo_rd_en        (enc_fifo_rd_en),
    //     .fifo_dout_map     (enc_fifo_dout_map),
    //     .fifo_empty        (enc_fifo_empty)
    // );

    // Transmitter u_Transmitter (
    //     .clk               (clk_1x),
    //     .rst               (rst_sys),
    //     .speed_mode        (0),
    //     .send_data_ready   (send_data_ready),
    //     .send_start        (send_start),
    //     .send_over         (send_over),
    //     .clk_data_src      (clk_data_src),
    //     .tx_data_src_tdata (enc_fifo_dout_map),
    //     .tx_data_src_tready(enc_fifo_rd_en),
    //     .tx_data_src_tvalid(~enc_fifo_empty),
    //     .hopping_freq      (),
    //     .ad9361_tx_data_i  (ad9361_tx_data_i),
    //     .ad9361_tx_data_q  (ad9361_tx_data_q),
    //     .test              (flag_transmitter_test),
    //     .hop_wait          (2000)
    // );





endmodule