169 lines
5.2 KiB
Verilog
169 lines
5.2 KiB
Verilog
`timescale 1ns / 1ps
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// +------------------------------+
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// | |
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// | |
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// +---------+------------> shift_ram(depth=1024) +-------------------+
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// | | | |
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// | | | |
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// | +------------------------------+ |
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// | |
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// | |
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// | |
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// | +------------+ |
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// | + | | - |
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// | | sliding | |
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// | | window | |
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// +---------------------> <----------------------------+
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// | |
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// +-----+------+
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// |
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// | average_out
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// |
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// v
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module PAPR #(
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parameter MAG_WIDTH = 22,
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parameter WINDOW_DEPTH = 1023
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// parameter GATE = 8
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) (
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input clk,
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input rst,
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input [MAG_WIDTH-1:0] vec_mag,
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input mag_valid,
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output reg frame_sync,
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output reg frame_sync_pulse
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);
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localparam SUM_WIDTH = 32;
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reg mag_valid_d1;
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reg [MAG_WIDTH-1:0] vec_mag_d1;
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reg [MAG_WIDTH-1:0] vec_mag_d2;
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reg [MAG_WIDTH-1:0] vec_mag_d3;
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reg frame_sync_d1;
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always @(posedge clk) begin
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mag_valid_d1 <= mag_valid;
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if (rst) begin
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vec_mag_d1 <= 'd0;
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vec_mag_d2 <= 'd0;
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vec_mag_d3 <= 'd0;
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end
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else if (mag_valid) begin
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vec_mag_d1 <= vec_mag;
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vec_mag_d2 <= vec_mag_d1;
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vec_mag_d3 <= vec_mag_d2;
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end
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else begin
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vec_mag_d1 <= vec_mag_d1;
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vec_mag_d2 <= vec_mag_d2;
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vec_mag_d3 <= vec_mag_d3;
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end
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end
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// accumulate ==> average ==> papr
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wire [MAG_WIDTH-1:0] vec_mag_1024;
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reg [ 5:0] cnt;
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// shift_1024 shift_1024 (
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// .D (vec_mag), // input wire [21 : 0] D
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// .CLK(clk), // input wire CLK
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// .Q (vec_mag_1024) // output wire [21 : 0] Q
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// );
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shift_reg #(
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.DATA_WIDTH(MAG_WIDTH),
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.DEPTH (WINDOW_DEPTH)
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) u_shift_reg (
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.clk (clk),
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.rst (rst),
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.we (mag_valid),
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.din (vec_mag),
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.dout(vec_mag_1024)
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);
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reg [SUM_WIDTH-1:0] data_sum;
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always @(posedge clk) begin
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if (rst) begin
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data_sum <= 'd0;
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end
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else begin
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if (mag_valid) begin
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data_sum <= data_sum + vec_mag - vec_mag_1024;
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end
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else begin
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data_sum <= data_sum;
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end
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end
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end
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wire [MAG_WIDTH-1:0] data_avg;
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assign data_avg = data_sum[SUM_WIDTH-1:10];
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always @(posedge clk) begin
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if (rst) begin
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frame_sync <= 1'd0;
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end
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else if (vec_mag_1024 != 'd0 && data_avg != 'd0) begin
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// NOTE: 防止0均值的情况，比如，一开始信号很小，刚好接收到有信号，那么均值为0，峰值有值，那么一定会过门限。
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if (mag_valid_d1 && ({3'd0, vec_mag_d2[MAG_WIDTH-1:3]} >= data_avg) && (vec_mag_d2 >= vec_mag_d1) && (vec_mag_d2 >= vec_mag_d3) && (vec_mag_d2 >= 22'h5000)) begin
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frame_sync <= 1'd1;
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end
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else if (cnt == 6'b111111) begin
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frame_sync <= 1'd0;
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end
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else begin
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frame_sync <= frame_sync;
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end
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end
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else begin
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frame_sync <= frame_sync;
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end
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end
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always @(posedge clk) begin
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frame_sync_d1 <= frame_sync;
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if (frame_sync && ~frame_sync_d1) begin
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frame_sync_pulse <= 1'd1;
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end
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else begin
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frame_sync_pulse <= 1'd0;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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cnt <= 6'd0;
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end
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else if (frame_sync && mag_valid_d1) begin
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cnt <= cnt + 6'd1;
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end
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else if (cnt == 6'b111111) begin
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cnt <= 6'd0;
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end
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end
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// ******** Wire & Reg ********
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// ******** Assingment ********
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// ******** Logic Block ********
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// ******** Inst ********
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// ******** Debug ********
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// NOTE: comment
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ila_frame_sync u_ila_frame_sync (
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.clk (clk), // input wire clk
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.probe0(vec_mag), // input wire [21:0] probe0
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.probe1(mag_valid), // input wire [0:0] probe1
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.probe2(frame_sync) // input wire [0:0] probe2
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);
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endmodule
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