644 lines
23 KiB
Verilog
644 lines
23 KiB
Verilog
`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/12/23 17:06:52
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// Design Name:
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// Module Name: freqestm
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module freqestm (
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input clk,
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input rst,
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input framesync,
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input mgc_rdy,
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input [9:0] datain_i,
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input [9:0] datain_q,
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output reg [9:0] dataout_i,
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output reg [9:0] dataout_q,
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output reg framesync_delay,
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output reg data_save,
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output reg rst_freq
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);
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wire [19:0] datain_01;
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wire [19:0] datain_02;
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wire [19:0] datain_03;
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wire framesync_d2;
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wire framesync_d3;
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wire [19:0] dataout_16;
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assign datain_01 = {datain_q, datain_i};
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shiftram_freq shiftram_freq_01 (
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.CLK(clk),
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.D (datain_01),
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.Q (datain_02)
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);
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shiftram_freq shiftram_freq_02 (
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.CLK(clk),
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.D (datain_02),
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.Q (datain_03)
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);
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wire empty;
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wire full;
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reg rd_en;
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reg wr_en;
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fifo_freq fifo_freq (
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.clk (clk),
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.srst (rst),
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.din (datain_03),
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.wr_en(wr_en),
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.full (full),
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.rd_en(rd_en),
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.empty(empty),
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.dout (dataout_16)
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);
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reg [15:0] cnt_fifo;
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reg [ 2:0] state_fifo;
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always @(posedge clk) begin
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if (rst) begin
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cnt_fifo <= 16'd0;
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wr_en <= 1'b0;
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rd_en <= 1'b0;
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state_fifo <= 3'd0;
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end
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else begin
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case (state_fifo)
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3'd0: begin
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if (mgc_rdy) begin
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state_fifo <= 3'd1;
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end
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else begin
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state_fifo <= state_fifo;
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end
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end
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3'd1: begin
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if (cnt_fifo == 16'd2175) begin
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wr_en <= 1'b1;
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cnt_fifo <= cnt_fifo + 16'd1;
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end
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else if (cnt_fifo == 16'd18065) begin
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rd_en <= 1'b1;
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cnt_fifo <= cnt_fifo;
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end
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else begin
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cnt_fifo <= cnt_fifo + 16'd1;
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wr_en <= wr_en;
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rd_en <= rd_en;
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end
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state_fifo <= state_fifo;
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end
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endcase
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end
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end
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reg [11:0] cnt_pilot;
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reg [14:0] cnt_frame;
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reg [ 7:0] cnt_bag;
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reg [11:0] cnt_cp;
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reg [11:0] cnt_process;
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reg [11:0] addra_pilot01;
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reg [11:0] addrb_pilot01;
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reg [11:0] addra_pilot02;
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reg [11:0] addrb_pilot02;
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reg [ 4:0] state_freq;
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reg [19:0] din_pilot01;
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reg [19:0] din_pilot02;
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wire [19:0] dout_pilot01;
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wire [19:0] dout_pilot02;
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reg framesync_delay_d1 = 1'b0;
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reg framesync_delay_d2 = 1'b0;
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reg framesync_delay_d3 = 1'b0;
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reg framesync_delay_d4 = 1'b0;
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reg framesync_delay_d5 = 1'b0;
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reg framesync_delay_d6 = 1'b0;
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reg framesync_delay_d7 = 1'b0;
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reg framesync_delay_d8 = 1'b0;
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reg framesync_delay_d9 = 1'b0;
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reg wea_01;
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reg wea_02;
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ram_pilot ram_pilota (
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.clka (clk),
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.clkb (clk),
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.addra(addra_pilot01),
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.addrb(addrb_pilot01),
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.dina (din_pilot01),
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.doutb(dout_pilot01),
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.wea (wea_01)
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);
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ram_pilot ram_pilotb (
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.clka (clk),
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.clkb (clk),
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.addra(addra_pilot02),
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.addrb(addrb_pilot02),
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.dina (din_pilot02),
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.doutb(dout_pilot02),
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.wea (wea_02)
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);
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wire [ 2:0] Multouti01_head;
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wire [ 2:0] Multoutq01_head;
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wire [20:0] Multouti01;
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wire [20:0] Multoutq01;
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reg acc_rdy;
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com_freq com_freq (
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.aclk (clk),
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.s_axis_a_tvalid (1'd1),
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.s_axis_a_tdata ({6'd0, dout_pilot01[19:10], 6'd0, dout_pilot01[9:0]}),
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.s_axis_b_tvalid (1'd1),
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.s_axis_b_tdata ({6'd0, dout_pilot02[19:10], 6'd0, dout_pilot02[9:0]}),
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.m_axis_dout_tvalid(m_axis_dout_tvalid01),
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.m_axis_dout_tdata ({Multoutq01_head, Multoutq01, Multouti01_head, Multouti01})
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);
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reg dfreq_word_nd_DDS;
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reg [31:0] acc_com_i;
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reg [31:0] acc_com_q;
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reg [ 9:0] phase_reg;
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reg [13:0] freq_out;
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wire [ 9:0] phase_out;
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wire [ 5:0] phase_out_head;
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wire phaserdy;
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reg [ 3:0] cnt_6;
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always @(posedge clk) begin
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if (rst) begin
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//dataout_i <= 12'd0;
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//dataout_q <= 12'd0;
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framesync_delay_d2 <= 1'b0;
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framesync_delay_d3 <= 1'b0;
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framesync_delay_d4 <= 1'b0;
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framesync_delay_d5 <= 1'b0;
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framesync_delay_d6 <= 1'b0;
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framesync_delay_d7 <= 1'b0;
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framesync_delay_d8 <= 1'b0;
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framesync_delay <= 1'b0;
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state_freq <= 5'd0;
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framesync_delay_d1 <= 1'b0;
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cnt_bag <= 8'd0;
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acc_com_i <= 32'd0;
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acc_com_q <= 32'd0;
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phase_reg <= 10'd0;
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freq_out <= 14'd0;
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cnt_pilot <= 12'd0;
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cnt_frame <= 15'd0;
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cnt_process <= 12'd0;
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addra_pilot01 <= 12'd0;
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addra_pilot02 <= 12'd0;
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addrb_pilot01 <= 12'd0;
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addrb_pilot02 <= 12'd0;
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din_pilot01 <= 20'd0;
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din_pilot02 <= 20'd0;
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cnt_cp <= 12'd0;
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wea_01 <= 1'b0;
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wea_02 <= 1'b0;
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acc_rdy <= 1'b0;
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data_save <= 1'b0;
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dfreq_word_nd_DDS <= 1'b0;
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cnt_6 <= 4'd0;
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end
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else begin
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framesync_delay_d2 <= data_save;
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framesync_delay_d3 <= framesync_delay_d2;
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framesync_delay_d4 <= framesync_delay_d3;
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framesync_delay_d5 <= framesync_delay_d4;
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framesync_delay_d6 <= framesync_delay_d5;
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framesync_delay_d7 <= framesync_delay_d6;
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framesync_delay_d8 <= framesync_delay_d7;
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framesync_delay <= framesync_delay_d8;
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case (state_freq)
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5'd0: begin
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if (framesync) begin
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state_freq <= 5'd1;
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wea_01 <= 1'b1;
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if (datain_q == 10'd512) din_pilot01[19:10] <= 10'd511;
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else din_pilot01[19:10] <= -datain_q;
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din_pilot01[9:0] <= datain_i[9:0];
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end
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else begin
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state_freq <= 5'd0;
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end
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//dataout_i <= 12'd0;
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//dataout_q <= 12'd0;
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framesync_delay_d1 <= 1'b0;
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cnt_bag <= 8'd0;
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acc_com_i <= 32'd0;
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acc_com_q <= 32'd0;
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phase_reg <= 10'd0;
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freq_out <= 14'd0;
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cnt_pilot <= 12'd0;
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cnt_frame <= 15'd0;
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cnt_process <= 12'd0;
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addra_pilot01 <= 12'd0;
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addra_pilot02 <= 12'd0;
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addrb_pilot01 <= 12'd0;
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addrb_pilot02 <= 12'd0;
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din_pilot01 <= 20'd0;
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din_pilot02 <= 20'd0;
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cnt_cp <= 12'd0;
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wea_01 <= 1'b0;
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wea_02 <= 1'b0;
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acc_rdy <= 1'b0;
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dfreq_word_nd_DDS <= 1'b0;
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end
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5'd1: begin
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if (cnt_pilot == 12'd1023) begin
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addra_pilot01 <= addra_pilot01;
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cnt_pilot <= 12'd0;
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state_freq <= 5'd11;
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cnt_frame <= cnt_frame + 15'd1;
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cnt_bag <= cnt_bag;
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wea_01 <= 1'b0;
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end
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else begin
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if (datain_q == 10'd512) din_pilot01[19:10] <= 10'd511;
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else din_pilot01[19:10] <= -datain_q;
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din_pilot01[9:0] <= datain_i[9:0];
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addra_pilot01 <= addra_pilot01 + 12'd1;
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cnt_pilot <= cnt_pilot + 12'd1;
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cnt_frame <= cnt_frame + 15'd1;
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cnt_bag <= cnt_bag;
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wea_01 <= 1'b1;
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end
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end
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5'd2: begin
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if (cnt_frame == 15'd13823) begin
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state_freq <= 5'd3;
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cnt_frame <= 15'd0;
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wea_02 <= 1'b1;
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din_pilot02 <= {datain_q, datain_i};
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end
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else begin
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cnt_frame <= cnt_frame + 15'd1;
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end
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end
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5'd3: begin
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if (cnt_pilot == 12'd1023) begin
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addra_pilot02 <= addra_pilot02;
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cnt_pilot <= 12'd0;
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state_freq <= 5'd13;
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cnt_frame <= cnt_frame + 15'd1;
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cnt_bag <= cnt_bag + 8'd1;
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wea_02 <= 1'b0;
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end
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else begin
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din_pilot02 <= {datain_q, datain_i};
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addra_pilot02 <= addra_pilot02 + 12'd1;
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cnt_pilot <= cnt_pilot + 12'd1;
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cnt_frame <= cnt_frame + 15'd1;
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cnt_bag <= cnt_bag;
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wea_02 <= 1'b1;
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end
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end
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5'd4: begin
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state_freq <= 5'd5;
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cnt_frame <= cnt_frame + 15'd1;
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acc_com_i <= 32'd0;
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acc_com_q <= 32'd0;
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end
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5'd5: begin
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if (cnt_6 == 4'd6) begin
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if (Multouti01[20] == 1'b1) acc_com_i <= acc_com_i + {11'b11111111111, Multouti01};
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else acc_com_i <= acc_com_i + {11'b00000000000, Multouti01};
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if (Multoutq01[20] == 1'b1) acc_com_q <= acc_com_q + {11'b11111111111, Multoutq01};
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else acc_com_q <= acc_com_q + {11'b00000000000, Multoutq01};
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cnt_6 <= cnt_6;
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end
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else begin
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acc_com_q <= acc_com_q;
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acc_com_i <= acc_com_i;
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cnt_6 <= cnt_6 + 4'd1;
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end
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if (cnt_pilot >= 12'd2047) begin
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addrb_pilot01 <= 12'd0;
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addrb_pilot02 <= 12'd0;
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cnt_frame <= cnt_frame + 15'd1;
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if (cnt_pilot == 12'd2053) begin
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acc_rdy <= 1'b1;
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cnt_pilot <= 12'd0;
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state_freq <= 5'd6;
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cnt_6 <= 4'd0;
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end
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else begin
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cnt_pilot <= cnt_pilot + 12'd1;
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end
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end
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else begin
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cnt_pilot <= cnt_pilot + 12'd1;
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addrb_pilot01 <= addrb_pilot01 + 12'd1;
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addrb_pilot02 <= addrb_pilot02 + 12'd1;
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acc_rdy <= 1'b0;
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cnt_frame <= cnt_frame + 15'd1;
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end
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end
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5'd6: begin
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acc_rdy <= 1'b0;
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if (phaserdy) begin
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phase_reg <= phase_out;
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state_freq <= 5'd7;
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cnt_frame <= cnt_frame + 15'd1;
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wea_01 <= 1'b1;
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if (dout_pilot02[19:10] == 10'd512) din_pilot01[19:10] <= 10'd511;
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else din_pilot01[19:10] <= -dout_pilot02[19:10];
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din_pilot01[9:0] <= dout_pilot02[9:0];
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addrb_pilot02 <= addrb_pilot02 + 12'd1;
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end
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else begin
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phase_reg <= phase_reg;
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cnt_frame <= cnt_frame + 15'd1;
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end
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end
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5'd7: begin
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state_freq <= 5'd8;
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data_save <= 1'b1;
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if (phase_reg[9] == 1'b1) freq_out <= {3'b111, phase_reg, 1'b0} + {4'b1111, phase_reg};
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else freq_out <= {3'b000, phase_reg, 1'b0} + {4'b0000, phase_reg};
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cnt_frame <= cnt_frame + 15'd1;
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dfreq_word_nd_DDS <= 1'b1;
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if (cnt_bag == 8'd1) framesync_delay_d1 <= 1'b1;
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else framesync_delay_d1 <= 1'b0;
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wea_01 <= 1'b1;
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if (dout_pilot02[19:10] == 10'd512) din_pilot01[19:10] <= 10'd511;
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else din_pilot01[19:10] <= -dout_pilot02[19:10];
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din_pilot01[9:0] <= dout_pilot02[9:0];
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addrb_pilot02 <= addrb_pilot02 + 12'd1;
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end
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5'd8: begin
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dfreq_word_nd_DDS <= 1'b0;
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framesync_delay_d1 <= 1'b0;
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if (cnt_pilot >= 12'd2045) begin
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addrb_pilot02 <= 12'd0;
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if (cnt_pilot == 12'd2047) begin
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addra_pilot01 <= 12'd0;
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addrb_pilot02 <= 12'd0;
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cnt_pilot <= 12'd0;
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state_freq <= 5'd9;
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cnt_frame <= cnt_frame + 15'd1;
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wea_01 <= 1'b0;
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end
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else begin
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if (dout_pilot02[19:10] == 10'd512) din_pilot01[19:10] <= 10'd511;
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else din_pilot01[19:10] <= -dout_pilot02[19:10];
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din_pilot01[9:0] <= dout_pilot02[9:0];
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addra_pilot01 <= addra_pilot01 + 12'd1;
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cnt_pilot <= cnt_pilot + 12'd1;
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cnt_frame <= cnt_frame + 15'd1;
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wea_01 <= 1'b1;
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end
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end
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else begin
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if (dout_pilot02[19:10] == 10'd512) din_pilot01[19:10] <= 10'd511;
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else din_pilot01[19:10] <= -dout_pilot02[19:10];
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din_pilot01[9:0] <= dout_pilot02[9:0];
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addra_pilot01 <= addra_pilot01 + 12'd1;
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addrb_pilot02 <= addrb_pilot02 + 12'd1;
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cnt_pilot <= cnt_pilot + 12'd1;
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cnt_frame <= cnt_frame + 15'd1;
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wea_01 <= 1'b1;
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end
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end
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5'd9: begin
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if (cnt_frame == 15'd13823) begin
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if (cnt_bag == 8'd40) begin
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state_freq <= 5'd10;
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cnt_bag <= cnt_bag + 8'd1;
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end
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else begin
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state_freq <= 5'd3;
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wea_02 <= 1'b1;
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din_pilot02 <= {datain_q, datain_i};
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end
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cnt_frame <= 15'd0;
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end
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else begin
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cnt_frame <= cnt_frame + 15'd1;
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end
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end
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5'd10: begin
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if (cnt_frame == 15'd13695) begin
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cnt_frame <= 15'd0;
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state_freq <= 5'd0;
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end
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else begin
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cnt_frame <= cnt_frame + 15'd1;
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end
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end
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5'd11: begin
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if (cnt_cp == 12'd127) begin
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state_freq <= 5'd12;
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cnt_cp <= 12'd0;
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wea_01 <= 1'b1;
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addra_pilot01 <= addra_pilot01 + 12'd1;
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cnt_frame <= cnt_frame + 15'd1;
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if (datain_q == 10'd512) din_pilot01[19:10] <= 10'd511;
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else din_pilot01[19:10] <= -datain_q;
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din_pilot01[9:0] <= datain_i[9:0];
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end
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else begin
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cnt_cp <= cnt_cp + 12'd1;
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state_freq <= state_freq;
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cnt_frame <= cnt_frame + 15'd1;
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|
end
|
|
|
|
end
|
|
|
|
|
|
5'd12: begin
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|
if (cnt_pilot == 12'd1023) begin
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|
addra_pilot01 <= 12'd0;
|
|
cnt_pilot <= 12'd0;
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|
state_freq <= 12'd2;
|
|
cnt_frame <= cnt_frame + 15'd1;
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|
cnt_bag <= cnt_bag;
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|
wea_01 <= 1'b0;
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|
end
|
|
else begin
|
|
if (datain_q == 10'd512) din_pilot01[19:10] <= 10'd511;
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|
else din_pilot01[19:10] <= -datain_q;
|
|
|
|
din_pilot01[9:0] <= datain_i[9:0];
|
|
addra_pilot01 <= addra_pilot01 + 12'd1;
|
|
cnt_pilot <= cnt_pilot + 12'd1;
|
|
cnt_frame <= cnt_frame + 15'd1;
|
|
cnt_bag <= cnt_bag;
|
|
wea_01 <= 1'b1;
|
|
end
|
|
end
|
|
|
|
5'd13: begin
|
|
if (cnt_cp == 12'd127) begin
|
|
state_freq <= 5'd14;
|
|
cnt_cp <= 12'd0;
|
|
cnt_frame <= cnt_frame + 15'd1;
|
|
din_pilot02 <= {datain_q, datain_i};
|
|
addra_pilot02 <= addra_pilot02 + 12'd1;
|
|
wea_02 <= 1'b1;
|
|
end
|
|
else begin
|
|
cnt_cp <= cnt_cp + 12'd1;
|
|
state_freq <= state_freq;
|
|
cnt_frame <= cnt_frame + 15'd1;
|
|
end
|
|
|
|
end
|
|
|
|
|
|
5'd14: begin
|
|
if (cnt_pilot == 12'd1023) begin
|
|
addra_pilot02 <= 12'd0;
|
|
cnt_pilot <= 12'd0;
|
|
state_freq <= 5'd4;
|
|
cnt_frame <= cnt_frame + 15'd1;
|
|
cnt_bag <= cnt_bag;
|
|
wea_02 <= 1'b0;
|
|
end
|
|
else begin
|
|
din_pilot02 <= {datain_q, datain_i};
|
|
addra_pilot02 <= addra_pilot02 + 12'd1;
|
|
cnt_pilot <= cnt_pilot + 12'd1;
|
|
cnt_frame <= cnt_frame + 15'd1;
|
|
cnt_bag <= cnt_bag;
|
|
wea_02 <= 1'b1;
|
|
end
|
|
end
|
|
|
|
endcase
|
|
end
|
|
|
|
end
|
|
|
|
|
|
atan2_freq atan2_freq (
|
|
.aclk (clk), // input wire aclk
|
|
.s_axis_cartesian_tvalid(acc_rdy), // input wire s_axis_cartesian_tvalid
|
|
.s_axis_cartesian_tdata ({acc_com_q, acc_com_i}), // input wire [47 : 0] s_axis_cartesian_tdata
|
|
.m_axis_dout_tvalid (phaserdy), // output wire m_axis_dout_tvalid
|
|
.m_axis_dout_tdata ({phase_out_head, phase_out}) // output wire [15 : 0] m_axis_dout_tdata
|
|
);
|
|
|
|
wire [11:0] DDS_trunc_i;
|
|
wire [11:0] DDS_trunc_q;
|
|
wire DDS_trunc_nd;
|
|
wire Demod_ovrflw;
|
|
|
|
|
|
|
|
reg [11:0] DDSin_i;
|
|
reg [11:0] DDSin_q;
|
|
|
|
always @(posedge clk) begin
|
|
if (dataout_16[19] == 1'b1) DDSin_q <= {2'b11, dataout_16[19:10]};
|
|
else DDSin_q <= {2'b00, dataout_16[19:10]};
|
|
if (dataout_16[9] == 1'b1) DDSin_i <= {2'b11, dataout_16[9:0]};
|
|
else DDSin_i <= {2'b00, dataout_16[9:0]};
|
|
end
|
|
|
|
|
|
DDS_compensate DDS_compensate_mx (
|
|
.clk (clk),
|
|
.rst (rst), //捕获模块复位受到发端影响，测试捕获情冿
|
|
.din_nd (1'd1),
|
|
.din_i (DDSin_i),
|
|
.din_q (DDSin_q),
|
|
.acq_nd (1'b0), // 捕获信息 //捕获到了复位丿欿
|
|
.dfreq_word_nd (dfreq_word_nd_DDS), // 频偏NCO信息
|
|
.dfreq_word (freq_out),
|
|
.framesync_success(framesync), // 帧同步标志，用于切码
|
|
.demod_trunc_i (DDS_trunc_i),
|
|
.demod_trunc_q (DDS_trunc_q),
|
|
.demod_trunc_nd (DDS_trunc_nd),
|
|
.Demod_ovrflw (Demod_ovrflw)
|
|
);
|
|
|
|
always @(posedge clk) begin
|
|
if (DDS_trunc_i[11:9] == 3'b000 || DDS_trunc_i[11:9] == 3'b111) begin
|
|
dataout_i <= DDS_trunc_i[9:0];
|
|
end
|
|
else begin
|
|
dataout_i <= (DDS_trunc_i[11] == 1'b1) ? 10'b10_0000_0000 : 10'b01_1111_1111;
|
|
end
|
|
if (DDS_trunc_q[11:9] == 3'b000 || DDS_trunc_q[11:9] == 3'b111) begin
|
|
dataout_q <= DDS_trunc_q[9:0];
|
|
end
|
|
else begin
|
|
dataout_q <= (DDS_trunc_q[11] == 1'b1) ? 10'b10_0000_0000 : 10'b01_1111_1111;
|
|
end
|
|
end
|
|
|
|
reg [19:0] cnt_rst = 20'd0;
|
|
always @(posedge clk) begin
|
|
if (framesync_delay_d8 && !framesync_delay) begin
|
|
cnt_rst <= 20'd0;
|
|
rst_freq <= 1'b0;
|
|
end
|
|
else begin
|
|
if (cnt_rst == 20'd580620) begin
|
|
rst_freq <= 1'b1;
|
|
cnt_rst <= cnt_rst + 20'd1;
|
|
end
|
|
else if (cnt_rst == 20'd580621) begin
|
|
rst_freq <= 1'b0;
|
|
cnt_rst <= cnt_rst;
|
|
end
|
|
else begin
|
|
cnt_rst <= cnt_rst + 20'd1;
|
|
rst_freq <= 1'b0;
|
|
end
|
|
end
|
|
end
|
|
|
|
endmodule
|