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ThirdTestRelease
MM7020/hdl
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ZoroGH 9d566f6b74 feat(top): add abnormal logic to pass 3rd test
2024-10-18 14:05:04 +08:00
..
abs_min_4din.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
ad9361_dp_fdd_1r1t.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
ad9361_mgc_pin_ctrl.v
fix(top): reverse iq in recv
2024-08-02 20:51:37 +08:00
ad9361_spi_interface.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
add_prefix.v
fix(system): adjust cp len, frame sync pos, IQ map
2024-07-25 23:32:28 +08:00
ApproxAbs_18bit.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
ApproxAbs_v2.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
CCSDS_LDPC_DEC_K1024_R12_TOPP.v
feat(top): add mac layer control, half tested
2024-07-29 19:04:48 +08:00
CCSDS_LDPC_DEC_K1024_R12.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
CCSDS_LDPC_ENC_R12.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
Chn_Estimate.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
CK_PRO.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
CN_PRO.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
CNU_3din.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
CNU_6din.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
DAGC_v2.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
data_equalizer.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
data_ow.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
DDS_compensate.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
enc_control.v
feat(top): new (de)scrambler, crc16
2024-08-13 22:07:58 +08:00
extract_mac_frame.v
feat(top): new (de)scrambler, crc16
2024-08-13 22:07:58 +08:00
frame_sync.v
Init repo
2024-07-19 14:09:20 +08:00
FrameMerge.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
freqestm.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
Interp_half.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
Interp_quarter.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
Interpolation.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
IQmerge.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
LDPC_DEC_PRO.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
LDPC_TopManage_2.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
MagnitudeEstimator.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
Message_Store.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
MF_Top.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
net_city.v
feat(tdma): update tdma logic
2024-10-09 20:13:52 +08:00
Noise_Estimate.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
Normalization_Factor_0_8125.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
OUT_PRO.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
Out_Process_R12.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
PAPR.v
feat(tdma): update tdma logic
2024-10-09 20:13:52 +08:00
phase_adjust.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
phy_control.v
merge(sys): merge tdma update
2024-10-12 11:02:35 +08:00
power_measure.v
fix(top): reverse iq in recv
2024-08-02 20:51:37 +08:00
Receiver.v
stash pop
2024-07-22 15:09:15 +08:00
RecvTop.v
feat(tdma): update tdma logic
2024-10-09 20:13:52 +08:00
SC_FDE_TOP.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
SCFDE_recv_FrameSync.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
scrambler.v
feat(top): new (de)scrambler, crc16
2024-08-13 22:07:58 +08:00
ser2par.v
feat(top): new (de)scrambler, crc16
2024-08-13 22:07:58 +08:00
shift_reg.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
system_top.v
feat(top): add abnormal logic to pass 3rd test
2024-10-18 14:05:04 +08:00
tdma.v
merge(sys): merge tdma update
2024-10-12 11:02:35 +08:00
TimeSync_top.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
Transmitter.v
fix(system): adjust cp len, frame sync pos, IQ map
2024-07-25 23:32:28 +08:00
trunc_25to12_2dly.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
TSync_Abs_new4.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
TSync_Abs_new16.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
up_axi.v
Init repo
2024-07-19 14:09:20 +08:00
VN_PRO.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
VNU_1din.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
VNU_2din.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
VNU_3din.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
VNU_6din.v
refactor(recviver): simulation pass for ila data
2024-07-24 21:32:28 +08:00
width_convert.v
feat(top): new (de)scrambler, crc16
2024-08-13 22:07:58 +08:00