162 lines
4.9 KiB
Verilog
162 lines
4.9 KiB
Verilog
// * Engineer:
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// * *************************************************** *
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// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ *
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// * ╚══███╔╝██╔═══██╗██╔══██╗██╔═══██╗██╔════╝ ██║ ██║ *
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// * ███╔╝ ██║ ██║██████╔╝██║ ██║██║ ███╗███████║ *
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// * ███╔╝ ██║ ██║██╔══██╗██║ ██║██║ ██║██╔══██║ *
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// * ███████╗╚██████╔╝██║ ██║╚██████╔╝╚██████╔╝██║ ██║ *
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// * ╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ *
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// * *************************************************** *
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// * Update Date:
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// * NOTE :
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module scrambler #(
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parameter ILA_ON = 0
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) (
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input clk,
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input rst_n,
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// s_axis_stream
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input [31:0] s_axis_tdata,
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input s_axis_tvalid,
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output reg s_axis_tready,
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input s_axis_tlast,
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input [31:0] s_axis_rd_data_count,
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// m_axis_stream
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output reg [31:0] m_axis_tdata,
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output reg m_axis_tvalid,
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input m_axis_tready,
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output reg m_axis_tlast
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);
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// ******** Wire & Reg ********
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wire rst;
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reg [ 2:0] addr_scramble = 0;
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reg [ 2:0] addr_scramble_d1 = 0;
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reg [ 2:0] addr_scramble_d2 = 0;
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wire [31:0] data_scramble_mask;
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reg [ 3:0] cnt_in;
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reg [31:0] s_axis_tdata_d1;
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reg [31:0] s_axis_tdata_d2;
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reg s_axis_tready_d1;
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reg s_axis_tlast_d1;
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// fsm
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reg [ 1:0] cs = 0;
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reg [ 1:0] ns = 0;
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localparam S_IDLE = 0;
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localparam S_WORKING = 1;
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// ******** Assingment ********
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assign rst = ~rst_n;
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// ******** Logic Block ********
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always @(posedge clk) begin
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cs <= ns;
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end
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always @(*) begin
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ns = cs;
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case (cs)
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S_IDLE: begin
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if (s_axis_tvalid && m_axis_tready && s_axis_rd_data_count >= 8) begin
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ns = S_WORKING;
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end
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end
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S_WORKING: begin
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if (addr_scramble_d2 == 3'h7) begin
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ns = S_IDLE;
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end
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end
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default: begin
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ns = S_IDLE;
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end
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endcase
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end
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always @(posedge clk) begin
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if (cs == S_IDLE) begin
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addr_scramble <= 0;
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end
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else begin
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addr_scramble <= addr_scramble + 1;
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end
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addr_scramble_d1 <= addr_scramble;
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addr_scramble_d2 <= addr_scramble_d1;
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end
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always @(posedge clk) begin
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if (cs == S_WORKING) begin
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m_axis_tdata <= s_axis_tdata_d1 ^ data_scramble_mask;
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end
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else begin
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m_axis_tdata <= 0;
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end
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end
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always @(posedge clk) begin
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if (cs == S_WORKING && s_axis_tvalid && cnt_in < 4'd8) begin
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s_axis_tready <= 1;
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end
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else begin
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s_axis_tready <= 0;
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end
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end
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always @(posedge clk) begin
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s_axis_tdata_d1 <= s_axis_tdata;
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s_axis_tready_d1 <= s_axis_tready;
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m_axis_tvalid <= s_axis_tready_d1;
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s_axis_tlast_d1 <= s_axis_tlast;
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m_axis_tlast <= s_axis_tlast_d1;
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end
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always @(posedge clk) begin
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if (cs == S_IDLE) begin
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cnt_in <= 0;
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end
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else if (cs == S_WORKING && cnt_in < 4'd8) begin
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cnt_in <= cnt_in + 1;
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end
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end
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// ******** Inst ********
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bram_scramble u_bram_scramble (
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.clka (clk), // input wire clka
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.addra(addr_scramble), // input wire [2 : 0] addra
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.douta(data_scramble_mask) // output wire [31 : 0] douta
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);
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// ******** Debug ********
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generate
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if (ILA_ON)
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ila_scrambler u_ila_scrambler (
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.clk (clk), // input wire clk
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.probe0(s_axis_tvalid), // input wire [0:0] probe0
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.probe1(s_axis_tready), // input wire [0:0] probe1
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.probe2(s_axis_tdata), // input wire [31:0] probe2
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.probe3(s_axis_tlast), // input wire [0:0] probe3
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.probe4(m_axis_tvalid), // input wire [0:0] probe4
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.probe5(m_axis_tready), // input wire [0:0] probe5
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.probe6(m_axis_tdata), // input wire [31:0] probe6
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.probe7(m_axis_tlast), // input wire [0:0] probe7
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.probe8(data_scramble_mask) // input wire [31:0] probe8
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);
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endgenerate
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endmodule
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