132 lines
5.1 KiB
C
132 lines
5.1 KiB
C
/**
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* \file common.h
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* \brief Contains type definitions and prototype declarations for common.c
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*/
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/**
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* \page Disclaimer Legal Disclaimer
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* Copyright 2015-2017 Analog Devices Inc.
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* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
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*
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*/
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#ifndef _COMMON_H_
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#define _COMMON_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* build project settings include the path to the desired platform folder for correct includes */
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#include "stdint.h"
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#define THROW_ERROR()
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#define SPIARRAYSIZE 1024
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/* assuming 3 byte SPI message - integer math enforces floor() */
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#define SPIARRAYTRIPSIZE ((SPIARRAYSIZE / 3) * 3)
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/*========================================
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* Enums and structures
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*=======================================*/
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/* proposed to increase number of error return values to make unique for each return */
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typedef enum
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{
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ADIERR_OK=0,
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ADIERR_INV_PARM,
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ADIERR_FAILED
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} ADI_ERR;
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/*!< \brief COMMON layer error reporting enumerated types */
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typedef enum
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{
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COMMONERR_OK=0,
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COMMONERR_FAILED
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} commonErr_t;
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/* bit 0 is MESSAGE, bit 1 is WARNING, bit 2 is ERROR */
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typedef enum
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{
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ADIHAL_LOG_NONE = 0x0,
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ADIHAL_LOG_MESSAGE = 0x1,
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ADIHAL_LOG_WARNING = 0x2,
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ADIHAL_LOG_ERROR = 0x4,
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ADIHAL_LOG_SPI = 0x8,
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ADIHAL_LOG_AXI_REG = 0x10,
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ADIHAL_LOG_AXI_MEM = 0x20,
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ADIHAL_LOG_ALL = 0x3F
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} ADI_LOGLEVEL;
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/**
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* \brief Data structure to hold SPI settings for all system device types
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*/
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typedef struct
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{
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uint8_t chipSelectIndex; ///< valid 1~8
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uint8_t writeBitPolarity; ///< the level of the write bit of a SPI write instruction word, value is inverted for SPI read operation
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uint8_t longInstructionWord; ///< 1 = 16bit instruction word, 0 = 8bit instruction word
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uint8_t MSBFirst; ///< 1 = MSBFirst, 0 = LSBFirst
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uint8_t CPHA; ///< clock phase, sets which clock edge the data updates (valid 0 or 1)
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uint8_t CPOL; ///< clock polarity 0 = clock starts low, 1 = clock starts high
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uint8_t enSpiStreaming; ///< Not implemented. SW feature to improve SPI throughput.
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uint8_t autoIncAddrUp; ///< Not implemented. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr = addr-1
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uint8_t fourWireMode; ///< 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode.
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uint32_t spiClkFreq_Hz; ///< SPI Clk frequency in Hz (default 25000000), platform will use next lowest frequency that it's baud rate generator can create */
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} spiSettings_t;
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/* global variable so application layer can set the log level */
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extern ADI_LOGLEVEL CMB_LOGLEVEL;
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extern struct spi_desc *spi_ad_desc;
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extern struct gpio_desc *gpio_ad9371_resetb;
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extern struct gpio_desc *gpio_ad9528_resetb;
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extern struct gpio_desc *gpio_ad9528_sysref_req;
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/* initialize hardware platform */
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commonErr_t CMB_initPlatform(void);
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/* close hardware pointers */
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commonErr_t CMB_closeHardware(void);
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/* GPIO function */
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commonErr_t CMB_setGPIO(uint32_t GPIO);
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/* hardware reset function */
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commonErr_t CMB_hardReset(uint8_t spiChipSelectIndex);
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/* SPI read/write functions */
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commonErr_t CMB_setSPIOptions(spiSettings_t *spiSettings); /* allows the platform HAL to work with devices with various SPI settings */
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commonErr_t CMB_setSPIChannel(uint16_t chipSelectIndex ); /* value of 0 deasserts all chip selects */
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commonErr_t CMB_SPIWriteByte(spiSettings_t *spiSettings, uint16_t addr, uint8_t data); /* single SPI byte write function */
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commonErr_t CMB_SPIWriteBytes(spiSettings_t *spiSettings, uint16_t *addr, uint8_t *data, uint32_t count);
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commonErr_t CMB_SPIReadByte (spiSettings_t *spiSettings, uint16_t addr, uint8_t *readdata); /* single SPI byte read function */
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commonErr_t CMB_SPIWriteField(spiSettings_t *spiSettings, uint16_t addr, uint8_t field_val, uint8_t mask, uint8_t start_bit); /* write a field in a single register */
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commonErr_t CMB_SPIReadField (spiSettings_t *spiSettings, uint16_t addr, uint8_t *field_val, uint8_t mask, uint8_t start_bit); /* read a field in a single register */
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/* platform timer functions */
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commonErr_t CMB_wait_ms(uint32_t time_ms);
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commonErr_t CMB_wait_us(uint32_t time_us);
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commonErr_t CMB_setTimeout_ms(uint32_t timeOut_ms);
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commonErr_t CMB_setTimeout_us(uint32_t timeOut_us);
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commonErr_t CMB_hasTimeoutExpired();
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/* platform logging functions */
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commonErr_t CMB_openLog(const char *filename);
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commonErr_t CMB_closeLog(void);
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commonErr_t CMB_writeToLog(ADI_LOGLEVEL level, uint8_t deviceIndex, uint32_t errorCode, const char *comment);
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commonErr_t CMB_flushLog(void);
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/* platform FPGA AXI register read/write functions */
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commonErr_t CMB_regRead(uint32_t offset, uint32_t *data);
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commonErr_t CMB_regWrite(uint32_t offset, uint32_t data);
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/* platform DDR3 memory read/write functions */
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commonErr_t CMB_memRead(uint32_t offset, uint32_t *data, uint32_t len);
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commonErr_t CMB_memWrite(uint32_t offset, uint32_t *data, uint32_t len);
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#ifdef __cplusplus
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}
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#endif
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#endif
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