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cleanup

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Gatsby Van
2024-03-16 13:18:16 +08:00
parent f6c2568a75
commit 0c6d861620
3 changed files with 10 additions and 9 deletions
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df_datalink_sp/src/networking/link_layer/link_layer.c
+1 -1
View File
@@ -991,7 +991,7 @@ int32_t Linklayer_EventHandler(L2_INST *instPtr, const L2_EVENT *l2Event)
else
{
DBG_WARNING("Unsupported routine state [%" PRId8 "], "
"Continue with previous routine table.\n", instPtr->nextState);
"Continue with previous routine table.\n", instPtr->nextState);
}
break;
}
df_datalink_sp/src/networking/phy_layer/phy_layer.c
+6 -3
View File
@@ -488,7 +488,7 @@ int32_t Phy_InstInit(PHY_INST **instPtr, PHY_CONFIG *phyConfig)
uint32_t phyMainCtrl = PhyRead(*instPtr, PHY_MAIN_CTRL);
phyMainCtrl &= ~PHY_MAIN_CTRL_NSCAN_MASK;
phyMainCtrl |= PHY_MAIN_CTRL_NSCAN_MASK &
(L1_NUM_ANT_NRRW_PATTERN << PHY_MAIN_CTRL_NSCAN_SHIFT);
(L1_NUM_ANT_NRRW_PATTERN << PHY_MAIN_CTRL_NSCAN_SHIFT);
PhyWrite(*instPtr, PHY_MAIN_CTRL, phyMainCtrl);
}
else
@@ -1271,7 +1271,9 @@ void Phy_RefreshHwSate(PHY_INST *instPtr)
instPtr->hwSate.spFpgaTemp = (evalData > TEMPERATURE_MAX)
? INT8_MAX
: ((evalData < TEMPERATURE_MIN) ? INT8_MIN : (int8_t)round(evalData / TEMPERATURE_LSB));
instPtr->hwSate.isSpOk = (instPtr->hwSate.spFpgaVolt == (VOLT_PS_OK | VOLT_PSAUX_OK | VOLT_DDR_OK | VOLT_PL_OK | VOLT_PLAUX_OK | VOLT_BRAM_OK)) && (instPtr->hwSate.spClkState == (CLK_SP_PLL0_LOCK | CLK_SP_PLL1_LOCK)) && (instPtr->hwSate.spAdLockState == (CLK_AD0_BBPLL_LOCK | CLK_AD0_RFPLL_LOCK | CLK_AD1_BBPLL_LOCK | CLK_AD1_RFPLL_LOCK));
instPtr->hwSate.isSpOk = (instPtr->hwSate.spFpgaVolt == (VOLT_PS_OK | VOLT_PSAUX_OK | VOLT_DDR_OK | VOLT_PL_OK | VOLT_PLAUX_OK | VOLT_BRAM_OK))
&& (instPtr->hwSate.spClkState == (CLK_SP_PLL0_LOCK | CLK_SP_PLL1_LOCK))
&& (instPtr->hwSate.spAdLockState == (CLK_AD0_BBPLL_LOCK | CLK_AD0_RFPLL_LOCK | CLK_AD1_BBPLL_LOCK | CLK_AD1_RFPLL_LOCK));
#else
instPtr->hwSate.isSpOk = true;
#endif
@@ -1312,7 +1314,8 @@ void Phy_RefreshHwSate(PHY_INST *instPtr)
instPtr->hwSate.antMgc1 |= (rawData & ANT_RF_MGC_CH4_MASK) >> 24;
// Determin if antenna is ok.
instPtr->hwSate.isAntOk = (instPtr->hwSate.antVolt == (VOLT_ANT_PROC_OK | VOLT_ANT_RF_OK | VOLT_ANT_NIL_OK | ANT_STATE_OK)) && (instPtr->hwSate.antPll == (CLK_ANT_BBPLL_LOCK | CLK_ANT_RFPLL0_LOCK | CLK_ANT_RFPLL1_LOCK));
instPtr->hwSate.isAntOk = (instPtr->hwSate.antVolt == (VOLT_ANT_PROC_OK | VOLT_ANT_RF_OK | VOLT_ANT_NIL_OK | ANT_STATE_OK))
&& (instPtr->hwSate.antPll == (CLK_ANT_BBPLL_LOCK | CLK_ANT_RFPLL0_LOCK | CLK_ANT_RFPLL1_LOCK));
memset(instPtr->hwSate.reserve, 0x00, sizeof(instPtr->hwSate.reserve));
df_datalink_sp/src/systembus/systembus.c
+3 -5
View File
@@ -237,8 +237,7 @@ inline bool SystemBus_IsRxBusy(SYSBUS *instPtr)
static int32_t SystemBus_GenSelfTestRsp(SYSBUS *instPtr)
{
ASSERT(instPtr != NULL);
SYSBUS_UART_FRAME *sysbusRsp;
sysbusRsp = malloc(sizeof(SYSBUS_UART_FRAME));
SYSBUS_UART_FRAME *sysbusRsp = malloc(sizeof(SYSBUS_UART_FRAME));
if (sysbusRsp == NULL) {
DBG_ERROR("Failed to allocate memory for SELF TEST Response!\n");
return ENOMEM;
@@ -728,10 +727,9 @@ int32_t SystemBus_TxIntrHandler(SYSBUS *instPtr)
int32_t SystemBus_RxIntrHandler(SYSBUS *instPtr)
{
ASSERT(instPtr != NULL);
int32_t Status;
SYSBUS_UART_FRAME *sysbusReq;
instPtr->isRxDone = true; // whether reception successes or not, receiving procedure ended.
sysbusReq = malloc(sizeof(SYSBUS_UART_FRAME));
int32_t Status;
SYSBUS_UART_FRAME *sysbusReq = malloc(sizeof(SYSBUS_UART_FRAME));
if (sysbusReq == NULL)
{
return ENOMEM;