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*bugfix: correct hardware status determination

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Gatsby Van
2024-02-22 16:25:32 +08:00
parent 5cabf2ab65
commit 95041a8395
2 changed files with 9 additions and 9 deletions
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df_datalink_sp/src/networking/phy_layer/phy_layer.c
+5 -5
View File
@@ -1222,9 +1222,9 @@ void Phy_RefreshHwSate(PHY_INST *instPtr)
instPtr->hwSate.spFpgaTemp = (evalData > TEMPERATURE_MAX)
? INT8_MAX
: ((evalData < TEMPERATURE_MIN) ? INT8_MIN : (int8_t) round(evalData/TEMPERATURE_LSB));
instPtr->hwSate.isSpOk = (instPtr->hwSate.spFpgaVolt == (VOLT_PS_OK & VOLT_PSAUX_OK & VOLT_DDR_OK & VOLT_PL_OK & VOLT_PLAUX_OK & VOLT_BRAM_OK))
&& (instPtr->hwSate.spClkState == (CLK_SP_PLL0_LOCK & CLK_SP_PLL1_LOCK))
&& (instPtr->hwSate.spAdLockState == (CLK_AD0_BBPLL_LOCK && CLK_AD0_RFPLL_LOCK & CLK_AD1_BBPLL_LOCK & CLK_AD1_RFPLL_LOCK));
instPtr->hwSate.isSpOk = (instPtr->hwSate.spFpgaVolt == (VOLT_PS_OK | VOLT_PSAUX_OK | VOLT_DDR_OK | VOLT_PL_OK | VOLT_PLAUX_OK | VOLT_BRAM_OK))
&& (instPtr->hwSate.spClkState == (CLK_SP_PLL0_LOCK | CLK_SP_PLL1_LOCK))
&& (instPtr->hwSate.spAdLockState == (CLK_AD0_BBPLL_LOCK | CLK_AD0_RFPLL_LOCK | CLK_AD1_BBPLL_LOCK | CLK_AD1_RFPLL_LOCK));
#else
instPtr->hwSate.isSpOk = true;
#endif
@@ -1265,8 +1265,8 @@ void Phy_RefreshHwSate(PHY_INST *instPtr)
instPtr->hwSate.antMgc1 |= (rawData & ANT_RF_MGC_CH4_MASK) >> 24;
// Determin if antenna is ok.
instPtr->hwSate.isAntOk = (instPtr->hwSate.antVolt == (VOLT_ANT_PROC_OK & VOLT_ANT_RF_OK & VOLT_ANT_NIL_OK & ANT_STATE_OK))
&& (instPtr->hwSate.antPll == (CLK_ANT_BBPLL_LOCK & CLK_ANT_RFPLL0_LOCK & CLK_ANT_RFPLL1_LOCK));
instPtr->hwSate.isAntOk = (instPtr->hwSate.antVolt == (VOLT_ANT_PROC_OK | VOLT_ANT_RF_OK | VOLT_ANT_NIL_OK | ANT_STATE_OK))
&& (instPtr->hwSate.antPll == (CLK_ANT_BBPLL_LOCK | CLK_ANT_RFPLL0_LOCK | CLK_ANT_RFPLL1_LOCK));
memset(instPtr->hwSate.reserve, 0x00, sizeof(instPtr->hwSate.reserve));
df_datalink_sp/src/system_monitor.h
+4 -4
View File
@@ -36,12 +36,12 @@
#define VOLT_ANT_NIL_OK BIT(4)
#define ANT_STATE_OK BIT(6)
#define IS_PS_VALID(x) (x <= 0.95 && x >= 1.05)
#define IS_PS_VALID(x) (x <= 1.05 && x >= 0.95)
#define IS_PSAUX_VALID(x) (x <= 1.89 && x >= 1.71)
#define IS_DDR_VALID(x) (x <= 1.14 && x >= 1.89)
#define IS_PL_VALID(x) (x <= 0.97 && x >= 1.03)
#define IS_DDR_VALID(x) (x <= 1.89 && x >= 1.14)
#define IS_PL_VALID(x) (x <= 1.03 && x >= 0.97)
#define IS_PLAUX_VALID(x) (x <= 1.89 && x >= 1.71)
#define IS_BRAM_VALID(x) (x <= 0.97 && x >= 1.03)
#define IS_BRAM_VALID(x) (x <= 1.03 && x >= 0.97)
#define CLK_SP_PLL0_LOCK BIT(0)
#define CLK_SP_PLL1_LOCK BIT(2)