BSP update: trim unnecessary memory

df_datalink_ge/src/main.c

@@ -140,8 +140,8 @@ uint8_t testDataLj[] =
 	0xB5, 0xA3, 0x38, 0x47, 0x1D, 0x1D, 0xFA, 0x3F,
 	0x39, 0xB4, 0xC8, 0x76, 0xBE, 0xAB, 0x8E, 0x40,
 	0xC9, 0xE8, 0x80, 0x24, 0xEC, 0xCB, 0x13, 0x40,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4E, 0x0B,
+	0x37, 0x38, 0x7F, 0x22, 0x72, 0x06, 0xF0, 0x01,
-	0x04, 0x00, 0xB8, 0xAA, 0x08, 0x47, 0x1E, 0xC6,
+	0x00, 0x00, 0xB8, 0xAA, 0x08, 0x47, 0x1E, 0xC6,
 	0xB0, 0x47, 0x54, 0xFD, 0xEB, 0x45, 0xA1, 0x8A,
 	0x86, 0x44, 0x43, 0xB6, 0xC8, 0x44, 0x4E, 0x19,
 	0xA8, 0x42
@@ -149,27 +149,27 @@ uint8_t testDataLj[] =
 
 uint8_t testDataFlj[] =
 {
-	0x1E, 0x8C, 0x16, 0x12, 0x0F, 0x03, 0xC1, 0x01,
+	0xFD, 0x1E, 0xA5, 0x22, 0x72, 0x02, 0x5A, 0x02,
 	0x00, 0x00, 0x81, 0x97, 0x39, 0x3F, 0xF1, 0xF4,
 	0xC0, 0x3F, 0x27, 0xF1, 0x65, 0x44, 0x53, 0x5C,
-	0xD3, 0x3F, 0xEE, 0x8D, 0x17, 0x12, 0x0F, 0x03,
+	0xD3, 0x3F, 0xB5, 0x24, 0xA6, 0x22, 0x72, 0x02,
-	0xE8, 0x02, 0x00, 0x00, 0xFC, 0xE0, 0x44, 0x47,
+	0x83, 0x01, 0x00, 0x00, 0xFC, 0xE0, 0x44, 0x47,
 	0xB7, 0x83, 0x35, 0x47, 0xA4, 0xBF, 0xE5, 0xC4,
 	0xE8, 0xDC, 0xD1, 0x44, 0x5D, 0x5D, 0xE7, 0x44,
 	0x7D, 0x1B, 0xE8, 0xC1, 0x60, 0x97, 0x57, 0x42,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x7E, 0xF3, 0x17, 0x12, 0x0F, 0x03, 0x22, 0x00,
+	0x5D, 0x86, 0xA6, 0x22, 0x72, 0x02, 0xA5, 0x02,
 	0x00, 0x00, 0x97, 0x4E, 0xB5, 0x47, 0xC4, 0x2A,
 	0xB0, 0x47, 0x2D, 0x00, 0x21, 0xC5, 0x8A, 0x85,
 	0xD1, 0x44, 0x23, 0xFD, 0xC8, 0x44, 0xA1, 0xC4,
 	0xEA, 0xC1, 0x91, 0x4E, 0x71, 0xC2, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8E, 0x1A,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6D, 0xAD,
-	0x18, 0x12, 0x0F, 0x03, 0x22, 0x00, 0x00, 0x00,
+	0xA6, 0x22, 0x72, 0x02, 0xA5, 0x02, 0x00, 0x00,
 	0xCD, 0x07, 0xD6, 0x47, 0x1D, 0xA4, 0xCE, 0x47,
 	0x6E, 0x61, 0x33, 0xC5, 0x85, 0x55, 0xD1, 0x44,
 	0x9C, 0x16, 0xBD, 0x44, 0x36, 0xC0, 0xEB, 0xC1,
 	0xF0, 0xFF, 0x5B, 0x42, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0xCB, 0x82, 0x02, 0x00
+	0x00, 0x00, 0x00, 0x00, 0x78, 0x25, 0x03, 0x00
 };
 #endif
 
@@ -416,6 +416,10 @@ void ScuTimer_IntrHandler(void *context)
 	{
 		// Refresh log
 		Phy_RefreshHwSate(phyInstPtr);
+		if (TimeCtrl_GetIntCnt(tmcInstPtr) - phyInstPtr->lastLogTime >= PHY_LOG_EXPIRE)
+		{
+			Phy_UpdateLogging(phyInstPtr);
+		}
 
 		if (Mpc_IsEnable(mpcDescPtr))
 		{
@@ -494,7 +498,7 @@ int main(void)
 	}
 
 	/* Physical Layer Initialize */
-	Status = Phy_InstInit(&phyInstPtr, &phyConfig);
+	Status = Phy_Init(&phyInstPtr, &phyConfig);
 	if (Status == SUCCESS)
 	{
 		DBG_PRINT("Physical layer Init SUCCESS! \n");

df_datalink_sp/bsp/ps7_cortexa9_0/include/xparameters.h

@@ -24,7 +24,7 @@
 
 /* Definitions for interface TMC */
 #define XPAR_TMC_BASEADDR 0x43C30000
-#define XPAR_TMC_HIGHADDR 0x43C3FFFF
+#define XPAR_TMC_HIGHADDR 0x43C30FFF
 
 #include "xparameters_ps.h"
 
@@ -57,7 +57,7 @@
 #define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
 #define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_WRITE_ACCESS 0U
 #define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_BASEADDR 0x42000000U
-#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_HIGHADDR 0x42000FFFU
+#define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_HIGHADDR 0x42001FFFU
 #define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU  
 #define XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU  
 
@@ -75,7 +75,7 @@
 #define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
 #define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_WRITE_ACCESS 0U
 #define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_S_AXI_BASEADDR 0x40004000U
-#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_S_AXI_HIGHADDR 0x40005FFFU
+#define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_S_AXI_HIGHADDR 0x40004FFFU
 #define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU  
 #define XPAR_PHY_DATA_INTERFACE_ANT_INFO_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU  
 
@@ -93,7 +93,7 @@
 #define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
 #define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_WRITE_ACCESS 0U
 #define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_S_AXI_BASEADDR 0x40000000U
-#define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_S_AXI_HIGHADDR 0x40001FFFU
+#define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_S_AXI_HIGHADDR 0x40000FFFU
 #define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU  
 #define XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU  
 
@@ -111,7 +111,7 @@
 #define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 0U
 #define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_WRITE_ACCESS 0U
 #define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_S_AXI_BASEADDR 0x40002000U
-#define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_S_AXI_HIGHADDR 0x40003FFFU
+#define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_S_AXI_HIGHADDR 0x40002FFFU
 #define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU  
 #define XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU  
 
@@ -131,7 +131,7 @@
 #define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 0U
 #define XPAR_BRAM_0_WRITE_ACCESS 0U
 #define XPAR_BRAM_0_BASEADDR 0x42000000U
-#define XPAR_BRAM_0_HIGHADDR 0x42000FFFU
+#define XPAR_BRAM_0_HIGHADDR 0x42001FFFU
 #define XPAR_BRAM_0_CTRL_BASEADDR 0xFFFFFFFFU  
 #define XPAR_BRAM_0_CTRL_HIGHADDR 0xFFFFFFFEU  
 
@@ -148,7 +148,7 @@
 #define XPAR_BRAM_1_ECC_ONOFF_RESET_VALUE 0U
 #define XPAR_BRAM_1_WRITE_ACCESS 0U
 #define XPAR_BRAM_1_BASEADDR 0x40004000U
-#define XPAR_BRAM_1_HIGHADDR 0x40005FFFU
+#define XPAR_BRAM_1_HIGHADDR 0x40004FFFU
 #define XPAR_BRAM_1_CTRL_BASEADDR 0xFFFFFFFFU  
 #define XPAR_BRAM_1_CTRL_HIGHADDR 0xFFFFFFFEU  
 
@@ -165,7 +165,7 @@
 #define XPAR_BRAM_2_ECC_ONOFF_RESET_VALUE 0U
 #define XPAR_BRAM_2_WRITE_ACCESS 0U
 #define XPAR_BRAM_2_BASEADDR 0x40000000U
-#define XPAR_BRAM_2_HIGHADDR 0x40001FFFU
+#define XPAR_BRAM_2_HIGHADDR 0x40000FFFU
 #define XPAR_BRAM_2_CTRL_BASEADDR 0xFFFFFFFFU  
 #define XPAR_BRAM_2_CTRL_HIGHADDR 0xFFFFFFFEU  
 
@@ -182,7 +182,7 @@
 #define XPAR_BRAM_3_ECC_ONOFF_RESET_VALUE 0U
 #define XPAR_BRAM_3_WRITE_ACCESS 0U
 #define XPAR_BRAM_3_BASEADDR 0x40002000U
-#define XPAR_BRAM_3_HIGHADDR 0x40003FFFU
+#define XPAR_BRAM_3_HIGHADDR 0x40002FFFU
 #define XPAR_BRAM_3_CTRL_BASEADDR 0xFFFFFFFFU  
 #define XPAR_BRAM_3_CTRL_HIGHADDR 0xFFFFFFFEU  
 
@@ -346,7 +346,7 @@
 
 /* Definitions for peripheral SYSTEMBUS */
 #define XPAR_SYSTEMBUS_BASEADDR 0x43C10000
-#define XPAR_SYSTEMBUS_HIGHADDR 0x43C11FFF
+#define XPAR_SYSTEMBUS_HIGHADDR 0x43C10FFF
 
 
 /******************************************************************/

df_datalink_sp/src/main.c

@@ -360,6 +360,11 @@ void ScuTimer_IntrHandler(void *context)
 	{
 		// Refresh log
 		Phy_RefreshHwSate(phyInstPtr);
+		if (TimeCtrl_GetIntCnt(tmcInstPtr) - phyInstPtr->lastLogTime >= PHY_LOG_EXPIRE)
+		{
+			Phy_UpdateLogging(phyInstPtr);
+		}
+
 		XScuTimer_ClearInterruptStatus((XScuTimer *)xdesc->instance);
 	}
 	else
@@ -420,7 +425,7 @@ int main(void)
 	}
 
 	/* Physical Layer Initialize */
-	Status = Phy_InstInit(&phyInstPtr, &phyConfig);
+	Status = Phy_Init(&phyInstPtr, &phyConfig);
 	if (Status == SUCCESS)
 	{
 		DBG_PRINT("Physical layer Init SUCCESS! \n");

df_datalink_sp/src/networking/phy_layer/phy_layer.c

@@ -35,6 +35,9 @@
 #endif
 
 /************************** Constant Definitions *****************************/
+#define PHY_TIME_WORD_H_MAX UINT32_MAX
+#define PHY_TIME_WORD_L_MAX 0x0007A120 // 5ms/10ns
+
 #define L1_FRAME_LEN_MAX (8192 / 8)			// byte
 #define L1_FRAME_2KBPS_20MS_LEN 0			// byte
 #define L1_FRAME_2KBPS_100MS_LEN (312 / 8)	// byte
@@ -318,7 +321,22 @@ void Phy_UpdateState(PHY_INST *instPtr)
 	{
 		instPtr->isValid = false;
 	}
+	Phy_UpdateLogging(instPtr);
+}
 
+/*****************************************************************************/
+/**
+ * @brief	Update physical layer logging.
+ *
+ * @param   instPtr A pointer to physical layer control instance.
+ *
+ * @return	NONE.
+ *
+ ******************************************************************************/
+void Phy_UpdateLogging(PHY_INST *instPtr)
+{
+	ASSERT(instPtr != NULL);
+	uint64_t peak, avg;
 	// Logging
 	instPtr->recvSlotTime.int_part = PhyRead(instPtr, TM_TARGET_H);
 	instPtr->recvSlotTime.frac_part = PhyRead(instPtr, TM_TARGET_L);
@@ -330,7 +348,6 @@ void Phy_UpdateState(PHY_INST *instPtr)
 	instPtr->phyLog.crcCnt = PhyRead(instPtr, PHY_CRC_OK_CNT);
 	instPtr->phyLog.doppler = Phy_GetFreqEst(instPtr);
 	instPtr->phyLog.recvStamp = (uint64_t)instPtr->recvFsTime.int_part * TIME_FRAC_MAX + instPtr->recvFsTime.frac_part;
-	uint64_t peak, avg;
 	peak = PhyRead(instPtr, PHY_ACQ_PEAK_L);
 	peak |= ((uint64_t)PhyRead(instPtr, PHY_ACQ_PEAK_H)) << 32;
 	avg = PhyRead(instPtr, PHY_ACQ_MEAN_L);
@@ -348,6 +365,7 @@ void Phy_UpdateState(PHY_INST *instPtr)
 	memset(instPtr->phyLog.reserve, 0x00, sizeof(instPtr->phyLog.reserve));
 	// Sync logs to system monitor
 	SysMonitor_UpdatePhysicalLayerLog(&(instPtr->phyLog));
+	instPtr->lastLogTime = PhyRead(instPtr, TM_TARGET_H);
 }
 
 /*****************************************************************************/
@@ -361,7 +379,7 @@ void Phy_UpdateState(PHY_INST *instPtr)
  * @return  SUCCESS
  *
  ******************************************************************************/
-int32_t Phy_InstInit(PHY_INST **instPtr, PHY_CONFIG *phyConfig)
+int32_t Phy_Init(PHY_INST **instPtr, PHY_CONFIG *phyConfig)
 {
 	ASSERT(instPtr != NULL);
 	ASSERT(phyConfig != NULL);
@@ -387,6 +405,7 @@ int32_t Phy_InstInit(PHY_INST **instPtr, PHY_CONFIG *phyConfig)
 	(*instPtr)->recvSlotTime.frac_part = UINT32_MAX;
 	(*instPtr)->antConfigOffset = 0;
 	(*instPtr)->sendDataOffset = 0;
+	(*instPtr)->lastLogTime = 0;
 	Phy_AntConfigInit(&((*instPtr)->antConfig));
 
 	memset(&((*instPtr))->tor, PHY_TOR_SUSPEND, sizeof(PHY_RCD));

df_datalink_sp/src/networking/phy_layer/phy_layer.h

@@ -53,8 +53,7 @@
 #define L1_FRAME_200KBPS_5MS_HOPS 20
 #define L1_FRAME_1M2BPS_5MS_HOPS 20
 
-#define PHY_TIME_WORD_H_MAX UINT32_MAX
+#define PHY_LOG_EXPIRE	40 // 50*5ms
-#define PHY_TIME_WORD_L_MAX 0x0007A120 // 5ms/10ns
 /***************** Macros (Inline Functions) Definitions *********************/
 /**************************** Type Definitions *******************************/
 typedef enum
@@ -227,6 +226,7 @@ typedef struct
 	PHY_ANT_ANGLE antNrrwPattern[L1_NUM_ANT_NRRW_PATTERN];
 	HWSTATE hwSate;
 	PHYLOG phyLog;
+	uint32_t lastLogTime;
 } PHY_INST;
 
 /************************** Variable Definitions *****************************/
@@ -242,10 +242,11 @@ extern uint16_t hopPattern_200KBPS_5MS[L1_FRAME_200KBPS_5MS_HOPS];
 extern uint16_t hopPattern_1M2BPS_5MS[L1_FRAME_1M2BPS_5MS_HOPS];
 
 /************************** Function Prototypes ******************************/
-int32_t Phy_InstInit(PHY_INST **instPtr, PHY_CONFIG *phyConfig);
+int32_t Phy_Init(PHY_INST **instPtr, PHY_CONFIG *phyConfig);
 void Phy_Destroy(PHY_INST *instPtr);
 
 void Phy_UpdateState(PHY_INST *instPtr);
+void Phy_UpdateLogging(PHY_INST *instPtr);
 void Phy_RefreshHwSate(PHY_INST *instPtr);
 
 void Phy_Start(PHY_INST *instPtr);

df_datalink_sp/unit_test/linklayer_emulate_unit_test.c

@@ -25,7 +25,7 @@ L2_INST *linkInstPtr = NULL;
 uint32_t tmcReg[32] = {0};
 uint32_t phycReg[512] = {0};
 
-L2_CONFIG l2Config = 
+L2_CONFIG l2Config =
 {
 	.myType = L2_NODE_HEAD,
 	.isInterHead = false,
@@ -38,7 +38,7 @@ L2_CONFIG l2Config =
 	.tmcInstPtr = NULL
 };
 
-PHY_CONFIG l1Config = 
+PHY_CONFIG l1Config =
 {
 	.devId = 0,
 	.txBramId = 0,
@@ -48,7 +48,7 @@ PHY_CONFIG l1Config =
 	.baseAddr = (uintptr_t)phycReg
 };
 
-TMC_CONFIG tmcConfig = 
+TMC_CONFIG tmcConfig =
 {
 	.baseAddr = (uintptr_t)tmcReg,
 	.reset = 10
@@ -68,7 +68,7 @@ void linklayer_setup(void)
 	ASSERT_EQUAL(SUCCESS, Status);
 	Status = TimeCtrl_Init(&tmcInstPtr, &tmcConfig);
 	ASSERT_EQUAL(SUCCESS, Status);
-	Status = Phy_InstInit(&phyInstPtr, &l1Config);
+	Status = Phy_Init(&phyInstPtr, &l1Config);
 	ASSERT_EQUAL(SUCCESS, Status);
 
 	// Update l2 config
@@ -87,7 +87,7 @@ void linklayer_teardown(void)
 	SysMonitor_Destroy();
 }
 
-void forge_adv_frame(uint8_t *buff, uint8_t srcId, uint8_t destId, 
+void forge_adv_frame(uint8_t *buff, uint8_t srcId, uint8_t destId,
 	uint32_t frameNum, uint32_t slotNum, uint32_t netStartTime)
 {
 	uint8_t type = L2_ADV_FRAME;
@@ -188,13 +188,13 @@ TEST(linklayer_master_routine)
 
 			if (L2_GetCurrentFrameType(linkInstPtr) == L2_CFM_FRAME && slotNum % 4 == 1)
 			{
-				forge_cfm_frame((uint8_t *)phyInstPtr->recvDataAddr, 2, 1, 
+				forge_cfm_frame((uint8_t *)phyInstPtr->recvDataAddr, 2, 1,
 				L2_GetCurrentFrameNum(linkInstPtr), L2_GetCurrentSlotNum(linkInstPtr) - 4);
 				PhyWrite(phyInstPtr, TXRX_STATE, 0x01010101);
 				PhyWrite(phyInstPtr, RECVDATA_STATE, L2_CMF_PACK_LEN);
 				PhyWrite(phyInstPtr, COASE_FREQEST, COASE_TYPE_40KBPS_20MS);
 			}
-			
+
 			if (L2_GetCurrentFrameType(linkInstPtr) == L2_SVC_FRAME && slotNum % 4 == 1)
 			{
 				forge_svc_frame((uint8_t *)phyInstPtr->recvDataAddr, 2, 1,
@@ -283,13 +283,13 @@ TEST(linklayer_slave_netsetup)
 				PhyWrite(phyInstPtr, FSTIME_H, frameSyncSlot);
 				PhyWrite(phyInstPtr, FSTIME_L, Phy_GetTimeComp(L1_10KBPS_20MS_FRAME));
 			}
-			
+
 			if (L2_GetCurrentFrameType(linkInstPtr) == L2_CFM_FRAME && slotNum % 4 == 1)
 			{
-				frameSyncSlot = L2_GetCurrentFrameNum(linkInstPtr) * L2_SLOTS_PER_FRAME 
+				frameSyncSlot = L2_GetCurrentFrameNum(linkInstPtr) * L2_SLOTS_PER_FRAME
 								+ L2_GetCurrentSlotNum(linkInstPtr) - 4;
-				
+
-				forge_cfm_frame((uint8_t *)phyInstPtr->recvDataAddr, 1, 2, 
+				forge_cfm_frame((uint8_t *)phyInstPtr->recvDataAddr, 1, 2,
 				frameSyncSlot/L2_SLOTS_PER_FRAME, frameSyncSlot%L2_SLOTS_PER_FRAME);
 
 				PhyWrite(phyInstPtr, TXRX_STATE, 0x01010101);
@@ -301,10 +301,10 @@ TEST(linklayer_slave_netsetup)
 
 			if (L2_GetCurrentFrameType(linkInstPtr) == L2_SVC_FRAME && slotNum % 4 == 1)
 			{
-				frameSyncSlot = L2_GetCurrentFrameNum(linkInstPtr) * L2_SLOTS_PER_FRAME 
+				frameSyncSlot = L2_GetCurrentFrameNum(linkInstPtr) * L2_SLOTS_PER_FRAME
 								+ L2_GetCurrentSlotNum(linkInstPtr) - 4;
 
-				forge_svc_frame((uint8_t *)phyInstPtr->recvDataAddr, 1, 2, 
+				forge_svc_frame((uint8_t *)phyInstPtr->recvDataAddr, 1, 2,
 				frameSyncSlot/L2_SLOTS_PER_FRAME, frameSyncSlot%L2_SLOTS_PER_FRAME);
 
 				PhyWrite(phyInstPtr, TXRX_STATE, 0x01010101);
@@ -327,7 +327,7 @@ TEST(linklayer_slave_netsetup)
 
 		// 2ms interrupt
 		if (tmcReg[TIME_FRAC_REG] == 200000)
-		{ 
+		{
 			Status = Linklayer_Proc(linkInstPtr);
 			if ((tmcReg[TIME_INT_REG] + 1) / 200 < linkInstPtr->netStartTime)
 			{