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add multirate qpsk transmitter, modify frequency hopping procedure

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josh
2024-11-02 01:00:01 +08:00
parent 197ee19bef
commit 5a7731b846
53 changed files with 15638 additions and 27959 deletions
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.gitignore
+20
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@@ -0,0 +1,20 @@
# System generated files
# -- macOS
.DS_Store
.AppleDouble
.LSOverride
._*
# -- Windows
Thumbs.db
ehthumbs.db
Desktop.ini
# -- Linux
*~
# IDEs and editors' files
*.idea
*.vscode
*.sublime-workspace
*.sublime-project
zc706_cx9261a_demo/system_top.xsa
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zc706_cx9261a_demo/vitis_classic_autobuild/config.json
+2 -2
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@@ -1,8 +1,8 @@
{
"project_name": "zc706_cx9261a",
"version": "0.0.1",
"version": "0.0.2",
"hw_design": "../system_top.xsa",
"hw_version": "zc706_cx9261a_demo-HW-0.0.1",
"hw_version": "zc706_cx9261a_demo-HW-0.0.2",
"apps": {
"zc706_cx9261a_app": {
"sources": ["source_zc706_cx9261a/"],
zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/config/app_config.h
+12 -11
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@@ -48,7 +48,8 @@
#else // Zynq-7000
#define CPU_CLK_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
#define APP_TIMER_CLK_HZ (CPU_CLK_HZ / 2)
#define FCLK_CLK0_HZ 100000000
#define FCLK_CLK0_HZ 50000000
#define FCLK_CLK1_HZ 200000000
#endif
/********* Zynq Platform Configs **********/
// APP Timer (for logging)
@@ -121,7 +122,7 @@
// #define HAVE_DEBUG_MESSAGES /* For Debug purposes only */
// -- AD9361 SPI Engine Configuration
#define AD9361_SPI_DEVICE_ID 0
#define AD9361_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
#define AD9361_SPI_ENGINE_REF_CLK FCLK_CLK1_HZ
#define AD9361_SPI_ENGINE_MAX_SPEED 5000000
#define AD9361_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
#define AD9361_SPI_ENGINE_DATA_WIDTH 8
@@ -209,8 +210,8 @@ typedef enum
#define CX9261A_HOP_FLAG (CX9261A_GPIO_OFFSET+15)
// -- CX9261A SPI Engine Configuration
#define CX9261A_SPI_DEVICE_ID 0
#define CX9261A_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
#define CX9261A_SPI_ENGINE_MAX_SPEED 5000000
#define CX9261A_SPI_ENGINE_REF_CLK FCLK_CLK1_HZ
#define CX9261A_SPI_ENGINE_MAX_SPEED 50000000
#define CX9261A_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
#define CX9261A_SPI_ENGINE_DATA_WIDTH 8
#define CX9261A_SPI_ENGINE_CS_DELAY 3
@@ -227,7 +228,7 @@ typedef enum
#define HMC7044_GPIO_3 (HMC7044_GPIO_OFFSET + 5)
// -- HMC7044 SPI Engine Configuration
#define HMC7044_SPI_DEVICE_ID 0
#define HMC7044_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
#define HMC7044_SPI_ENGINE_REF_CLK FCLK_CLK1_HZ
#define HMC7044_SPI_ENGINE_MAX_SPEED 5000000
#define HMC7044_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
#define HMC7044_SPI_ENGINE_DATA_WIDTH 8
@@ -243,7 +244,7 @@ typedef enum
#define AD9528_STATUS_1 (AD9528_GPIO_OFFSET+3)
// -- AD9528 SPI Engine Configuration
#define AD9528_SPI_DEVICE_ID 0
#define AD9528_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
#define AD9528_SPI_ENGINE_REF_CLK FCLK_CLK1_HZ
#define AD9528_SPI_ENGINE_MAX_SPEED 5000000
#define AD9528_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
#define AD9528_SPI_ENGINE_DATA_WIDTH 8
@@ -255,7 +256,7 @@ typedef enum
#define LMK04828_GPIO_OFFSET 54
// -- LMK04828 SPI Engine Configuration
#define LMK04828_SPI_DEVICE_ID 0
#define LMK04828_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
#define LMK04828_SPI_ENGINE_REF_CLK FCLK_CLK1_HZ
#define LMK04828_SPI_ENGINE_MAX_SPEED 5000000
#define LMK04828_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
#define LMK04828_SPI_ENGINE_DATA_WIDTH 8
@@ -267,7 +268,7 @@ typedef enum
#define LMX2594_ADC_GPIO_OFFSET 54
// -- LMX2594_ADC SPI Engine Configuration
#define LMX2594_ADC_SPI_DEVICE_ID 0
#define LMX2594_ADC_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
#define LMX2594_ADC_SPI_ENGINE_REF_CLK FCLK_CLK1_HZ
#define LMX2594_ADC_SPI_ENGINE_MAX_SPEED 5000000
#define LMX2594_ADC_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
#define LMX2594_ADC_SPI_ENGINE_DATA_WIDTH 8
@@ -279,7 +280,7 @@ typedef enum
#define LMX2594_DAC_GPIO_OFFSET 54
// -- LMX2594_DAC SPI Engine Configuration
#define LMX2594_DAC_SPI_DEVICE_ID 0
#define LMX2594_DAC_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
#define LMX2594_DAC_SPI_ENGINE_REF_CLK FCLK_CLK1_HZ
#define LMX2594_DAC_SPI_ENGINE_MAX_SPEED 5000000
#define LMX2594_DAC_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
#define LMX2594_DAC_SPI_ENGINE_DATA_WIDTH 8
@@ -292,7 +293,7 @@ typedef enum
#define AD9653_POWR_DOWN (AD9653_GPIO_OFFSET+0)
// -- AD9653 SPI Engine Configuration
#define AD9653_SPI_DEVICE_ID 0
#define AD9653_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
#define AD9653_SPI_ENGINE_REF_CLK FCLK_CLK1_HZ
#define AD9653_SPI_ENGINE_MAX_SPEED 5000000
#define AD9653_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
#define AD9653_SPI_ENGINE_DATA_WIDTH 8
@@ -304,7 +305,7 @@ typedef enum
#define AD9694_GPIO_OFFSET 54
// -- AD9694 SPI Engine Configuration
#define AD9694_SPI_DEVICE_ID 0
#define AD9694_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
#define AD9694_SPI_ENGINE_REF_CLK FCLK_CLK1_HZ
#define AD9694_SPI_ENGINE_MAX_SPEED 5000000
#define AD9694_SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
#define AD9694_SPI_ENGINE_DATA_WIDTH 8
zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/dev_profile/cx9261a_profile.c
+2 -2
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@@ -180,7 +180,7 @@ CX9261A_CX9261AConfiguration cx9261a_configuration = {
.tx1Source = CX9261A_LOSRC_Pll1,
.tx2Source = CX9261A_LOSRC_Pll2},
// 本振频率 注意：使用的所有PLL，频率必须设为正数
.pllFreq = {.pll1Freq = 121.88,
.pllFreq = {.pll1Freq = 500,
.pll2Freq = 5000,
.pll3Freq = 800,
.pll4Freq = 900,
@@ -215,7 +215,7 @@ CX9261A_CX9261AConfiguration cx9261a_configuration = {
.rx3CalibPll = CX9261A_LOSRC_Pll5,
.tx1CalibPll = 0,
.tx2CalibPll = 0,
.rxMethod = CX9261A_CALM_Tracking,
.rxMethod = CX9261A_CALM_TST,
.txMethod = CX9261A_CALM_Bisec,
.f0 = 4,
// .rxMultiPoints = {2200, 2400, 2600, 2800, 3000, 3200, 3400,
zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/drivers/rf-transceiver/cx9261a/cx9261a_riscv_bin.c
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zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/hwconfig.c
+187 -72
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@@ -21,6 +21,7 @@
// Xilinx
#include "xgpiops.h"
#include "drivers/axi_core/spi_engine/spi_engine.h"
#include "sleep.h"
// App
#include "common.h"
#include "error.h"
@@ -53,6 +54,10 @@ XGpioPs Gpio;
XRFdc RFdc;
#endif
#define MIN_FREQ 121.88
#define MAX_FREQ 5000
#define FREQ_SEP 200
/*****************************************************************************/
/**
* @brief Hardware_SwitchFreq
@@ -330,10 +335,16 @@ int CX9261A_spiRead(int address)
return reg;
}
void CX9261A_udelay(double us)
{
usleep((uint32_t)us);
}
void CX9261A_mdelay(double ms)
{
mdelay((uint32_t)(ms));
usleep((uint32_t)(ms*1000));
}
void CX9261A_setPin(int pin, int value)
{
switch(pin){
@@ -389,19 +400,45 @@ void CX9261A_setPin(int pin, int value)
return;
}
void cx9261a_trx_ch_pll_config(u8 pll_index)
void replaceBits(uint8_t *reg, unsigned int start, unsigned int end, uint8_t after) {
// 生成掩码，用于清除目标位区间
uint8_t mask = ((1 << (start - end + 1)) - 1) << end;
// 清除 reg 中的指定位
*reg &= ~mask;
// 插入 after 的对应位到目标区间
*reg |= (after << end) & mask;
}
int CX9261A_afcPll1_pause(double delay_us)
{
u8 rx_data;
u8 recv_buf[3]={0};
u32 trx_ch_pll_data;
CX9261A_Log("PLL1 AFC PAUSE");
uint8_t r61D = (uint8_t)CX9261A_spiRead(0x61D);
int saved = r61D;
replaceBits(&r61D, 5, 4, 0b10);
CX9261A_spiWrite(0x61D, r61D);
CX9261A_spiWrite(0x617, 0x00);
CX9261A_spiWrite(0x617, 0x13);
// CX9261A_udelay(delay_us);
CX9261A_spiWrite(0x61D, saved);
int lock = CX9261A_spiRead(0x635);
return 0x10 & lock;
}
if(pll_index==1){
trx_ch_pll_data = 0x00077DCF;
}else if(pll_index==2){
trx_ch_pll_data = 0x00077D0C;
}
cx9261a_write(cx9261a_inst,trx_ch_pll_data >> 8, trx_ch_pll_data);
int CX9261A_afcPll2_pause(double delay_us)
{
CX9261A_Log("PLL2 AFC PAUSE");
uint8_t r63F = (uint8_t)CX9261A_spiRead(0x63F);
int saved = r63F;
replaceBits(&r63F, 5, 4, 0b10);
CX9261A_spiWrite(0x63F, r63F);
CX9261A_spiWrite(0x639, 0x00);
CX9261A_spiWrite(0x639, 0x13);
// CX9261A_udelay(delay_us);
CX9261A_spiWrite(0x63F, saved);
int lock = CX9261A_spiRead(0x657);
return 0x10 & lock;
}
/*****************************************************************************/
@@ -762,6 +799,20 @@ int32_t Hardware_Init(void)
/**********************************************************/
cx9261a_init(&cx9261a_inst, &cx9261a_default_init_param);
double min_freq = 3000.0;
double max_freq = 5000.0;
int cal_freq_num = 21;
double freq_sep = (max_freq-min_freq)/(cal_freq_num-1);
for (int ii = 0; ii < cal_freq_num; ii++)
{
cx9261a_configuration.calib.rxMultiPoints[ii] = min_freq + ii*freq_sep;
cx9261a_configuration.calib.txMultiPoints[ii] = min_freq + ii*freq_sep;
}
cx9261a_configuration.calib.numRxPoint = cal_freq_num;
cx9261a_configuration.calib.numTxPoint = cal_freq_num;
// 绑定函数
CX9261A_setLoggingFunc(CX9261A_Log);
CX9261A_setWriteSpiFunc(CX9261A_spiWrite);
@@ -771,8 +822,6 @@ int32_t Hardware_Init(void)
// 开始配置芯片
CX9261A_initialChip(); // 最开始需要调用此函数
int reg;
reg = CX9261A_spiRead(0x000);
CX9261A_initialPowerConfig(&cx9261a_configuration);
// 配置温补
CX9261A_configTemperatureCompensation(cx9261a_configuration.tempComp);
@@ -825,77 +874,143 @@ int32_t Hardware_Init(void)
CX9261A_configADCCalib(cx9261a_configuration.clock.adc);
CX9261A_configFlashCalib();
CX9261A_configDcCalib(&(cx9261a_configuration.calib));
// CX9261A_configQecCalib(&cx9261a_configuration);
CX9261A_configQecCalib(&cx9261a_configuration);
// CX9261A_loadRxCalibPredis(0, CX9261A_RXCH_Rx1, CX9261A_LOSRC_Pll1);
// CX9261A_loadRxCalibPredis(0, CX9261A_RXCH_Rx2, CX9261A_LOSRC_Pll1);
// 切换到工作模式
CX9261A_configPowerMode(cx9261a_configuration.powerManagement.powerMode);
int reg;
CX9261A_spiWrite(0x02E,0x03);
reg = CX9261A_spiRead(0x0AB);
CX9261A_spiWrite(0x02E,0x06);
// 跳频
uint8_t hop_flag = 0;
uint8_t hop_flag_new = 0;
double hop_freq;
// while (true)
// int hop_freq_num = 3*floor((cal_freq_num-1)/2); // 切换顺序为 0, 1, 2, 0, 3, 4, 0, 5, 6 ...
// double hop_freq[hop_freq_num];
// int next_pll_index = 1;
// double curr_freq;
// int freq_index = 0;
//
// for (int ii = 0; ii < hop_freq_num/3; ii++)
// {
// gpio_get_value(cx9261a_inst->gpio_desc_hop_flag, &hop_flag_new);
// if (hop_flag != hop_flag_new)
// {
// hop_flag = hop_flag_new;
//
// double hop_freq;
// double hop_freq1 = 800.25;
// int pll_index=1;
// int unlock_pll1_cnt=0,unlock_pll2_cnt=0;
//
// hop_freq = (rand()%(800-30))+30+(rand()%(101))/(double)100;
//
// if(hop_freq == hop_freq1){
// if(pll_index == 2){
// pll_index = 4;
// }
// else if(pll_index == 1){
// pll_index = 3;
// }
// }
//
// if(hop_flag_new == 1)
// {
// if(pll_index == 1 || pll_index == 3)
// {
// //切换至pll2来源
// cx9261a_trx_ch_pll_config(2);
// //配置pll1参数
// CX9261A_configPll1(hop_freq,&(cx9261a_configuration.clock));
// // unlock_pll1_cnt=PLL_config(1,hop_freq,ref)-1;
// while (!CX9261A_afcPll1()) {
// unlock_pll1_cnt++;
// }
// pll_index = 2;
// }
// else if(pll_index == 2 || pll_index == 4)
// {
// //切换至pll1来源
// cx9261a_trx_ch_pll_config(1);
// //配置pll2参数
// CX9261A_configPll2(hop_freq,&(cx9261a_configuration.clock));
// // unlock_pll2_cnt=PLL_config(2,hop_freq,ref)-1;
// while (!CX9261A_afcPll2()) {
// unlock_pll2_cnt++;
// }
// pll_index = 1;
// }
// }
// hop_freq1 = hop_freq;
// if(unlock_pll2_cnt!=0 || unlock_pll1_cnt !=0){
// DBG_ERROR("pll1 unlock num: %d; pll2 unlock num: %d;.\n", unlock_pll1_cnt, unlock_pll2_cnt);
// }
// }
// hop_freq[3*ii] = cx9261a_configuration.calib.rxMultiPoints[0];
// hop_freq[3*ii+1] = cx9261a_configuration.calib.rxMultiPoints[2*ii+1];
// hop_freq[3*ii+2] = cx9261a_configuration.calib.rxMultiPoints[2*ii+2];
// }
//
// if (hop_freq[freq_index] != cx9261a_configuration.pllFreq.pll1Freq)
// {
// curr_freq = hop_freq[freq_index];
//
// CX9261A_configPllSource(&(cx9261a_configuration.pllSource));
// CX9261A_configPll1(hop_freq[freq_index], &(cx9261a_configuration.clock));
// CX9261A_afcPll1_pause(25);
// // set pll1 as default
// cx9261a_configuration.pllSource.rx1Source = CX9261A_LOSRC_Pll1;
// cx9261a_configuration.pllSource.tx1Source = CX9261A_LOSRC_Pll1;
// // // prepare next pll
// CX9261A_configPll2(hop_freq[freq_index+1], &(cx9261a_configuration.clock));
// CX9261A_afcPll2_pause(25);
// // index update
// next_pll_index = 2;
// }
static int hop_cnt = 0;
static int next_pll_index = 2;
static double curr_freq;
static double next_freq = MIN_FREQ;
while (true)
{
gpio_get_value(cx9261a_inst->gpio_desc_hop_flag, &hop_flag_new);
if (hop_flag != hop_flag_new)
{
hop_flag = hop_flag_new;
// 1st demo of frequency hopping
int unlock_pll1_cnt = 0, unlock_pll2_cnt = 0;
curr_freq = next_freq;
hop_cnt++;
if (hop_cnt % 3 == 2)
{
next_freq = MIN_FREQ;
}
else
{
next_freq = (curr_freq + FREQ_SEP > MAX_FREQ) ? MIN_FREQ : curr_freq + FREQ_SEP;
}
if (next_pll_index == 2)
{
// switch pll
CX9261A_spiWrite(0x77D,0x0C);
// prepare next pll
CX9261A_configPll1(next_freq, &(cx9261a_configuration.clock));
while (!CX9261A_afcPll1_pause(20))
{
unlock_pll1_cnt++;
}
// index update
next_pll_index = 1;
}
else
{
// switch pll
CX9261A_spiWrite(0x77D,0xCF);
// prepare next pll
CX9261A_configPll2(next_freq, &(cx9261a_configuration.clock));
while (!CX9261A_afcPll2_pause(20))
{
unlock_pll2_cnt++;
}
// index update
next_pll_index = 2;
}
if(unlock_pll2_cnt!=0 || unlock_pll1_cnt !=0){
xil_printf("pll1 unlock num: %d; pll2 unlock num: %d;.\n", unlock_pll1_cnt, unlock_pll2_cnt);
}
// 2nd demo of frequency hopping
// curr_freq = hop_freq[freq_index];
// hop_flag = hop_flag_new;
// freq_index = (freq_index == hop_freq_num - 1) ? 0 : freq_index + 1;
//
// if (next_pll_index == 2)
// {
// // switch pll
//// cx9261a_configuration.pllSource.rx1Source = CX9261A_LOSRC_Pll2;
//// cx9261a_configuration.pllSource.tx1Source = CX9261A_LOSRC_Pll2;
//// CX9261A_configPllSource(&(cx9261a_configuration.pllSource));
// CX9261A_spiWrite(0x77D,0x0C);
// // prepare next pll
// CX9261A_configPll1(hop_freq[freq_index], &(cx9261a_configuration.clock));
// CX9261A_afcPll1_pause(25);
// // index update
// next_pll_index = 1;
// }
// else if (next_pll_index == 1)
// {
// // switch pll
//// cx9261a_configuration.pllSource.rx1Source = CX9261A_LOSRC_Pll1;
//// cx9261a_configuration.pllSource.tx1Source = CX9261A_LOSRC_Pll1;
//// CX9261A_configPllSource(&(cx9261a_configuration.pllSource));
// CX9261A_spiWrite(0x77D,0xCF);
// // prepare next pll
// CX9261A_configPll2(hop_freq[freq_index], &(cx9261a_configuration.clock));
// CX9261A_afcPll2_pause(25);
// // index update
// next_pll_index = 2;
// }
}
}
#endif
DBG_INFO("HDWR: configuration Done.\n");
return SUCCESS;
}
zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/debug_nets.ltx
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zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/system_top.bit
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zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/system_top.ltx
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zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/sim/system_bd_axi_spi_engine_0_0.v
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@@ -1,245 +0,0 @@
// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: analog.com:user:axi_spi_engine:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* IP_DEFINITION_SOURCE = "package_project" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_bd_axi_spi_engine_0_0 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_awprot,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_arprot,
s_axi_rvalid,
s_axi_rready,
s_axi_rresp,
s_axi_rdata,
irq,
spi_clk,
spi_resetn,
cmd_ready,
cmd_valid,
cmd_data,
sdo_data_ready,
sdo_data_valid,
sdo_data,
sdi_data_ready,
sdi_data_valid,
sdi_data,
sync_ready,
sync_valid,
sync_data
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_clock, ASSOCIATED_BUSIF spi_engine_offload_ctrl0:s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK, xilinx.com:signal:clock:1.0 spi_engine_offload_ctrl0_s_axi_signal_clock CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST, xilinx.com:signal:reset:1.0 spi_engine_offload_ctrl0_s_axi_signal_reset RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *)
input wire [15 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *)
input wire [15 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
S 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *)
output wire [31 : 0] s_axi_rdata;
output wire irq;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_clock, ASSOCIATED_BUSIF spi_engine_ctrl, ASSOCIATED_RESET spi_resetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 spi_engine_ctrl_signal_clock CLK" *)
input wire spi_clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 spi_engine_ctrl_signal_reset RST" *)
output wire spi_resetn;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_READY" *)
input wire cmd_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_VALID" *)
output wire cmd_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_DATA" *)
output wire [15 : 0] cmd_data;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_READY" *)
input wire sdo_data_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_VALID" *)
output wire sdo_data_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_DATA" *)
output wire [7 : 0] sdo_data;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_READY" *)
output wire sdi_data_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_VALID" *)
input wire sdi_data_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_DATA" *)
input wire [7 : 0] sdi_data;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_READY" *)
output wire sync_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_VALID" *)
input wire sync_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_DATA" *)
input wire [7 : 0] sync_data;
axi_spi_engine #(
.CMD_FIFO_ADDRESS_WIDTH(4),
.SYNC_FIFO_ADDRESS_WIDTH(4),
.SDO_FIFO_ADDRESS_WIDTH(5),
.SDI_FIFO_ADDRESS_WIDTH(5),
.MM_IF_TYPE(0),
.ASYNC_SPI_CLK(1'B0),
.NUM_OFFLOAD(0),
.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH(4),
.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH(4),
.ID(0),
.DATA_WIDTH(8),
.NUM_OF_SDI(1)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awprot(s_axi_awprot),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wready(s_axi_wready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bresp(s_axi_bresp),
.s_axi_bready(s_axi_bready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arready(s_axi_arready),
.s_axi_arprot(s_axi_arprot),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rdata(s_axi_rdata),
.up_clk(1'B0),
.up_rstn(1'B0),
.up_wreq(1'B0),
.up_waddr(14'B0),
.up_wdata(32'B0),
.up_wack(),
.up_rreq(1'B0),
.up_raddr(14'B0),
.up_rdata(),
.up_rack(),
.irq(irq),
.spi_clk(spi_clk),
.spi_resetn(spi_resetn),
.cmd_ready(cmd_ready),
.cmd_valid(cmd_valid),
.cmd_data(cmd_data),
.sdo_data_ready(sdo_data_ready),
.sdo_data_valid(sdo_data_valid),
.sdo_data(sdo_data),
.sdi_data_ready(sdi_data_ready),
.sdi_data_valid(sdi_data_valid),
.sdi_data(sdi_data),
.sync_ready(sync_ready),
.sync_valid(sync_valid),
.sync_data(sync_data),
.offload0_cmd_wr_en(),
.offload0_cmd_wr_data(),
.offload0_sdo_wr_en(),
.offload0_sdo_wr_data(),
.offload0_mem_reset(),
.offload0_enable(),
.offload0_enabled(1'B0),
.offload_sync_ready(),
.offload_sync_valid(1'B0),
.offload_sync_data(8'B0)
);
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/synth/system_bd_axi_spi_engine_0_0.v
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// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: analog.com:user:axi_spi_engine:1.0
// IP Revision: 1
(* X_CORE_INFO = "axi_spi_engine,Vivado 2019.1.3" *)
(* CHECK_LICENSE_TYPE = "system_bd_axi_spi_engine_0_0,axi_spi_engine,{}" *)
(* IP_DEFINITION_SOURCE = "package_project" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_bd_axi_spi_engine_0_0 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_awprot,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_arprot,
s_axi_rvalid,
s_axi_rready,
s_axi_rresp,
s_axi_rdata,
irq,
spi_clk,
spi_resetn,
cmd_ready,
cmd_valid,
cmd_data,
sdo_data_ready,
sdo_data_valid,
sdo_data,
sdi_data_ready,
sdi_data_valid,
sdi_data,
sync_ready,
sync_valid,
sync_data
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_clock, ASSOCIATED_BUSIF spi_engine_offload_ctrl0:s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK, xilinx.com:signal:clock:1.0 spi_engine_offload_ctrl0_s_axi_signal_clock CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST, xilinx.com:signal:reset:1.0 spi_engine_offload_ctrl0_s_axi_signal_reset RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *)
input wire [15 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *)
input wire [15 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
S 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *)
output wire [31 : 0] s_axi_rdata;
output wire irq;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_clock, ASSOCIATED_BUSIF spi_engine_ctrl, ASSOCIATED_RESET spi_resetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 spi_engine_ctrl_signal_clock CLK" *)
input wire spi_clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 spi_engine_ctrl_signal_reset RST" *)
output wire spi_resetn;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_READY" *)
input wire cmd_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_VALID" *)
output wire cmd_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_DATA" *)
output wire [15 : 0] cmd_data;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_READY" *)
input wire sdo_data_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_VALID" *)
output wire sdo_data_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_DATA" *)
output wire [7 : 0] sdo_data;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_READY" *)
output wire sdi_data_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_VALID" *)
input wire sdi_data_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_DATA" *)
input wire [7 : 0] sdi_data;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_READY" *)
output wire sync_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_VALID" *)
input wire sync_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_DATA" *)
input wire [7 : 0] sync_data;
axi_spi_engine #(
.CMD_FIFO_ADDRESS_WIDTH(4),
.SYNC_FIFO_ADDRESS_WIDTH(4),
.SDO_FIFO_ADDRESS_WIDTH(5),
.SDI_FIFO_ADDRESS_WIDTH(5),
.MM_IF_TYPE(0),
.ASYNC_SPI_CLK(1'B0),
.NUM_OFFLOAD(0),
.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH(4),
.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH(4),
.ID(0),
.DATA_WIDTH(8),
.NUM_OF_SDI(1)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awprot(s_axi_awprot),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wready(s_axi_wready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bresp(s_axi_bresp),
.s_axi_bready(s_axi_bready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arready(s_axi_arready),
.s_axi_arprot(s_axi_arprot),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rdata(s_axi_rdata),
.up_clk(1'B0),
.up_rstn(1'B0),
.up_wreq(1'B0),
.up_waddr(14'B0),
.up_wdata(32'B0),
.up_wack(),
.up_rreq(1'B0),
.up_raddr(14'B0),
.up_rdata(),
.up_rack(),
.irq(irq),
.spi_clk(spi_clk),
.spi_resetn(spi_resetn),
.cmd_ready(cmd_ready),
.cmd_valid(cmd_valid),
.cmd_data(cmd_data),
.sdo_data_ready(sdo_data_ready),
.sdo_data_valid(sdo_data_valid),
.sdo_data(sdo_data),
.sdi_data_ready(sdi_data_ready),
.sdi_data_valid(sdi_data_valid),
.sdi_data(sdi_data),
.sync_ready(sync_ready),
.sync_valid(sync_valid),
.sync_data(sync_data),
.offload0_cmd_wr_en(),
.offload0_cmd_wr_data(),
.offload0_sdo_wr_en(),
.offload0_sdo_wr_data(),
.offload0_mem_reset(),
.offload0_enable(),
.offload0_enabled(1'B0),
.offload_sync_ready(),
.offload_sync_valid(1'B0),
.offload_sync_data(8'B0)
);
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.dcp
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zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci
+86 -79
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@@ -2,10 +2,10 @@
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "system_bd_axi_spi_engine_0_0",
"cell_name": "axi_spi_engine/axi_spi_engine",
"cell_name": "axi_spi_engine",
"component_reference": "analog.com:user:axi_spi_engine:1.0",
"ip_revision": "1",
"gen_directory": ".",
"gen_directory": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0",
"parameters": {
"component_parameters": {
"CMD_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -20,6 +20,10 @@
"ID": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
"NUM_OF_SDI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"CFG_INFO_0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"CFG_INFO_1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"CFG_INFO_2": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"CFG_INFO_3": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Component_Name": [ { "value": "system_bd_axi_spi_engine_0_0", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
@@ -34,7 +38,11 @@
"OFFLOAD0_SDO_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
"NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"CFG_INFO_0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"CFG_INFO_1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"CFG_INFO_2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"CFG_INFO_3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynq" } ],
@@ -53,12 +61,11 @@
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "1" } ],
"LOCKEDBYUSER": [ { "value": "TRUE" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "." } ],
"OUTPUTDIR": [ { "value": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2019.1.3" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
@@ -108,37 +115,37 @@
"mode": "slave",
"memory_map_ref": "s_axi",
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
@@ -167,14 +174,14 @@
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
"ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "s_axi_aclk" } ]
@@ -185,8 +192,8 @@
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "s_axi_aresetn" } ]
@@ -197,18 +204,18 @@
"abstraction_type": "analog.com:interface:spi_engine_ctrl_rtl:1.0",
"mode": "master",
"port_maps": {
"CMD_READY": [ { "physical_name": "cmd_ready" } ],
"CMD_VALID": [ { "physical_name": "cmd_valid" } ],
"CMD_DATA": [ { "physical_name": "cmd_data" } ],
"SDO_READY": [ { "physical_name": "sdo_data_ready" } ],
"SDO_VALID": [ { "physical_name": "sdo_data_valid" } ],
"SDO_DATA": [ { "physical_name": "sdo_data" } ],
"SDI_READY": [ { "physical_name": "sdi_data_ready" } ],
"SDI_VALID": [ { "physical_name": "sdi_data_valid" } ],
"SDI_DATA": [ { "physical_name": "sdi_data" } ],
"SYNC_READY": [ { "physical_name": "sync_ready" } ],
"SYNC_VALID": [ { "physical_name": "sync_valid" } ],
"SYNC_DATA": [ { "physical_name": "sync_data" } ]
"cmd_ready": [ { "physical_name": "cmd_ready" } ],
"cmd_valid": [ { "physical_name": "cmd_valid" } ],
"cmd_data": [ { "physical_name": "cmd_data" } ],
"sdo_ready": [ { "physical_name": "sdo_data_ready" } ],
"sdo_valid": [ { "physical_name": "sdo_data_valid" } ],
"sdo_data": [ { "physical_name": "sdo_data" } ],
"sdi_ready": [ { "physical_name": "sdi_data_ready" } ],
"sdi_valid": [ { "physical_name": "sdi_data_valid" } ],
"sdi_data": [ { "physical_name": "sdi_data" } ],
"sync_ready": [ { "physical_name": "sync_ready" } ],
"sync_valid": [ { "physical_name": "sync_valid" } ],
"sync_data": [ { "physical_name": "sync_data" } ]
}
},
"spi_engine_ctrl_signal_clock": {
@@ -216,14 +223,14 @@
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "spi_engine_ctrl", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "spi_resetn", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
"ASSOCIATED_BUSIF": [ { "value": "spi_engine_ctrl", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "spi_resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "2e+08", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK1", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "spi_clk" } ]
@@ -234,8 +241,8 @@
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "master",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "spi_resetn" } ]
@@ -246,14 +253,14 @@
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "spi_engine_offload_ctrl0:s_axi", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
"ASSOCIATED_BUSIF": [ { "value": "spi_engine_offload_ctrl0:s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "s_axi_aclk" } ]
@@ -264,8 +271,8 @@
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "s_axi_aresetn" } ]
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xml
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zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_constr.xdc
-1
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@@ -1 +0,0 @@
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_sim_netlist.v
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zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_sim_netlist.vhdl
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zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_stub.v
-60
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@@ -1,60 +0,0 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Sun Sep 29 16:31:49 2024
// Host : gatsby-dev running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa)
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/CX9261A/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_stub.v
// Design : system_bd_axi_spi_engine_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z045ffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_spi_engine,Vivado 2019.1.3" *)
module system_bd_axi_spi_engine_0_0(s_axi_aclk, s_axi_aresetn, s_axi_awvalid,
s_axi_awaddr, s_axi_awready, s_axi_awprot, s_axi_wvalid, s_axi_wdata, s_axi_wstrb,
s_axi_wready, s_axi_bvalid, s_axi_bresp, s_axi_bready, s_axi_arvalid, s_axi_araddr,
s_axi_arready, s_axi_arprot, s_axi_rvalid, s_axi_rready, s_axi_rresp, s_axi_rdata, irq,
spi_clk, spi_resetn, cmd_ready, cmd_valid, cmd_data, sdo_data_ready, sdo_data_valid, sdo_data,
sdi_data_ready, sdi_data_valid, sdi_data, sync_ready, sync_valid, sync_data)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awvalid,s_axi_awaddr[15:0],s_axi_awready,s_axi_awprot[2:0],s_axi_wvalid,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wready,s_axi_bvalid,s_axi_bresp[1:0],s_axi_bready,s_axi_arvalid,s_axi_araddr[15:0],s_axi_arready,s_axi_arprot[2:0],s_axi_rvalid,s_axi_rready,s_axi_rresp[1:0],s_axi_rdata[31:0],irq,spi_clk,spi_resetn,cmd_ready,cmd_valid,cmd_data[15:0],sdo_data_ready,sdo_data_valid,sdo_data[7:0],sdi_data_ready,sdi_data_valid,sdi_data[7:0],sync_ready,sync_valid,sync_data[7:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [15:0]s_axi_awaddr;
output s_axi_awready;
input [2:0]s_axi_awprot;
input s_axi_wvalid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [1:0]s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [15:0]s_axi_araddr;
output s_axi_arready;
input [2:0]s_axi_arprot;
output s_axi_rvalid;
input s_axi_rready;
output [1:0]s_axi_rresp;
output [31:0]s_axi_rdata;
output irq;
input spi_clk;
output spi_resetn;
input cmd_ready;
output cmd_valid;
output [15:0]cmd_data;
input sdo_data_ready;
output sdo_data_valid;
output [7:0]sdo_data;
output sdi_data_ready;
input sdi_data_valid;
input [7:0]sdi_data;
output sync_ready;
input sync_valid;
input [7:0]sync_data;
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_stub.vhdl
-65
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@@ -1,65 +0,0 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Sun Sep 29 16:31:49 2024
-- Host : gatsby-dev running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa)
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/CX9261A/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0_stub.vhdl
-- Design : system_bd_axi_spi_engine_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z045ffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_bd_axi_spi_engine_0_0 is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awready : out STD_LOGIC;
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arready : out STD_LOGIC;
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
irq : out STD_LOGIC;
spi_clk : in STD_LOGIC;
spi_resetn : out STD_LOGIC;
cmd_ready : in STD_LOGIC;
cmd_valid : out STD_LOGIC;
cmd_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
sdo_data_ready : in STD_LOGIC;
sdo_data_valid : out STD_LOGIC;
sdo_data : out STD_LOGIC_VECTOR ( 7 downto 0 );
sdi_data_ready : out STD_LOGIC;
sdi_data_valid : in STD_LOGIC;
sdi_data : in STD_LOGIC_VECTOR ( 7 downto 0 );
sync_ready : out STD_LOGIC;
sync_valid : in STD_LOGIC;
sync_data : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end system_bd_axi_spi_engine_0_0;
architecture stub of system_bd_axi_spi_engine_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awvalid,s_axi_awaddr[15:0],s_axi_awready,s_axi_awprot[2:0],s_axi_wvalid,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wready,s_axi_bvalid,s_axi_bresp[1:0],s_axi_bready,s_axi_arvalid,s_axi_araddr[15:0],s_axi_arready,s_axi_arprot[2:0],s_axi_rvalid,s_axi_rready,s_axi_rresp[1:0],s_axi_rdata[31:0],irq,spi_clk,spi_resetn,cmd_ready,cmd_valid,cmd_data[15:0],sdo_data_ready,sdo_data_valid,sdo_data[7:0],sdi_data_ready,sdi_data_valid,sdi_data[7:0],sync_ready,sync_valid,sync_data[7:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_spi_engine,Vivado 2019.1.3";
begin
end;
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_1/system_bd_spi_engine_execution_0_1.xci
+3 -3
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@@ -2,7 +2,7 @@
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "system_bd_spi_engine_execution_0_1",
"cell_name": "spi_engine_execution",
"cell_name": "axi_spi_engine/spi_engine_execution",
"component_reference": "analog.com:user:spi_engine_execution:1.0",
"ip_revision": "1",
"gen_directory": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_1",
@@ -147,10 +147,10 @@
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "spi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "2e+08", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK1", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_system_ila_0_0/system_bd_system_ila_0_0.xci
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zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xadc_wiz_0_0/system_bd_xadc_wiz_0_0.xci
+16 -16
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@@ -311,25 +311,25 @@
"mode": "slave",
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "11", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.xci
+2 -2
View File
@@ -2,7 +2,7 @@
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "system_bd_xbar_0",
"cell_name": "axi_interconnect_0_upgraded_ipi/xbar",
"cell_name": "axi_interconnect_0/xbar",
"component_reference": "xilinx.com:ip:axi_crossbar:2.1",
"ip_revision": "32",
"gen_directory": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_xbar_0",
@@ -1316,7 +1316,7 @@
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
"TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
"TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/1cb1/axi_spi_engine.v
-625
View File
@@ -1,625 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_spi_engine #(
parameter CMD_FIFO_ADDRESS_WIDTH = 4,
parameter SYNC_FIFO_ADDRESS_WIDTH = 4,
parameter SDO_FIFO_ADDRESS_WIDTH = 5,
parameter SDI_FIFO_ADDRESS_WIDTH = 5,
parameter MM_IF_TYPE = 0,
parameter ASYNC_SPI_CLK = 0,
parameter NUM_OFFLOAD = 0,
parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = 4,
parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4,
parameter ID = 0,
parameter [15:0] DATA_WIDTH = 8,
parameter [ 7:0] NUM_OF_SDI = 1 ) (
// Slave AXI interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [15:0] s_axi_awaddr,
output s_axi_awready,
input [2:0] s_axi_awprot,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [15:0] s_axi_araddr,
output s_axi_arready,
input [2:0] s_axi_arprot,
output s_axi_rvalid,
input s_axi_rready,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
// up interface
input up_clk,
input up_rstn,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack,
output reg irq,
// SPI signals
input spi_clk,
output spi_resetn,
input cmd_ready,
output cmd_valid,
output [15:0] cmd_data,
input sdo_data_ready,
output sdo_data_valid,
output [(DATA_WIDTH-1):0] sdo_data,
output sdi_data_ready,
input sdi_data_valid,
input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
output sync_ready,
input sync_valid,
input [7:0] sync_data,
// Offload ctrl signals
output offload0_cmd_wr_en,
output [15:0] offload0_cmd_wr_data,
output offload0_sdo_wr_en,
output [(DATA_WIDTH-1):0] offload0_sdo_wr_data,
output offload0_mem_reset,
output offload0_enable,
input offload0_enabled,
output offload_sync_ready,
input offload_sync_valid,
input [7:0] offload_sync_data);
localparam PCORE_VERSION = 'h010071;
localparam S_AXI = 0;
localparam UP_FIFO = 1;
wire clk;
wire rstn;
wire [CMD_FIFO_ADDRESS_WIDTH:0] cmd_fifo_room;
wire cmd_fifo_almost_empty;
wire [15:0] cmd_fifo_in_data;
wire cmd_fifo_in_ready;
wire cmd_fifo_in_valid;
wire [SDO_FIFO_ADDRESS_WIDTH:0] sdo_fifo_room;
wire sdo_fifo_almost_empty;
wire [(DATA_WIDTH-1):0] sdo_fifo_in_data;
wire sdo_fifo_in_ready;
wire sdo_fifo_in_valid;
wire sdi_fifo_out_data_msb_s;
wire [SDI_FIFO_ADDRESS_WIDTH:0] sdi_fifo_level;
wire sdi_fifo_almost_full;
wire [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_fifo_out_data;
wire sdi_fifo_out_ready;
wire sdi_fifo_out_valid;
wire [7:0] sync_fifo_data;
wire sync_fifo_valid;
wire [7:0] offload_sync_fifo_data;
wire offload_sync_fifo_valid;
reg up_sw_reset = 1'b1;
wire up_sw_resetn = ~up_sw_reset;
reg [31:0] up_rdata_ff = 'd0;
reg up_wack_ff = 1'b0;
reg up_rack_ff = 1'b0;
wire up_wreq_s;
wire up_rreq_s;
wire [31:0] up_wdata_s;
wire [13:0] up_waddr_s;
wire [13:0] up_raddr_s;
// Scratch register
reg [31:0] up_scratch = 'h00;
reg [7:0] sync_id = 'h00;
reg sync_id_pending = 1'b0;
reg [7:0] offload_sync_id = 'h00;
reg offload_sync_id_pending = 1'b0;
generate if (MM_IF_TYPE == S_AXI) begin
// assign clock and reset
assign clk = s_axi_aclk;
assign rstn = s_axi_aresetn;
// interface wrapper
up_axi #(
.AXI_ADDRESS_WIDTH (16)
) i_up_axi (
.up_rstn(rstn),
.up_clk(clk),
.up_axi_awvalid(s_axi_awvalid),
.up_axi_awaddr(s_axi_awaddr),
.up_axi_awready(s_axi_awready),
.up_axi_wvalid(s_axi_wvalid),
.up_axi_wdata(s_axi_wdata),
.up_axi_wstrb(s_axi_wstrb),
.up_axi_wready(s_axi_wready),
.up_axi_bvalid(s_axi_bvalid),
.up_axi_bresp(s_axi_bresp),
.up_axi_bready(s_axi_bready),
.up_axi_arvalid(s_axi_arvalid),
.up_axi_araddr(s_axi_araddr),
.up_axi_arready(s_axi_arready),
.up_axi_rvalid(s_axi_rvalid),
.up_axi_rresp(s_axi_rresp),
.up_axi_rdata(s_axi_rdata),
.up_axi_rready(s_axi_rready),
.up_wreq(up_wreq_s),
.up_waddr(up_waddr_s),
.up_wdata(up_wdata_s),
.up_wack(up_wack_ff),
.up_rreq(up_rreq_s),
.up_raddr(up_raddr_s),
.up_rdata(up_rdata_ff),
.up_rack(up_rack_ff)
);
assign up_rdata = 32'b0;
assign up_rack = 1'b0;
assign up_wack = 1'b0;
end
endgenerate
generate if (MM_IF_TYPE == UP_FIFO) begin
// assign clock and reset
assign clk = up_clk;
assign rstn = up_rstn;
assign up_wreq_s = up_wreq;
assign up_waddr_s = up_waddr;
assign up_wdata_s = up_wdata;
assign up_wack = up_wack_ff;
assign up_rreq_s = up_rreq;
assign up_raddr_s = up_raddr;
assign up_rdata = up_rdata_ff;
assign up_rack = up_rack_ff;
end
endgenerate
// IRQ handling
reg [3:0] up_irq_mask = 'h0;
wire [3:0] up_irq_source;
wire [3:0] up_irq_pending;
assign up_irq_source = {
offload_sync_id_pending,
sync_id_pending,
sdi_fifo_almost_full,
sdo_fifo_almost_empty,
cmd_fifo_almost_empty
};
assign up_irq_pending = up_irq_mask & up_irq_source;
always @(posedge clk) begin
if (rstn == 1'b0)
irq <= 1'b0;
else
irq <= |up_irq_pending;
end
always @(posedge clk) begin
if (rstn == 1'b0) begin
up_wack_ff <= 1'b0;
up_scratch <= 'h00;
up_sw_reset <= 1'b1;
end else begin
up_wack_ff <= up_wreq_s;
if (up_wreq_s) begin
case (up_waddr_s)
8'h02: up_scratch <= up_wdata_s;
8'h10: up_sw_reset <= up_wdata_s;
endcase
end
end
end
reg offload0_enable_reg;
reg offload0_mem_reset_reg;
wire offload0_enabled_s;
// the software reset should reset all the registers
always @(posedge clk) begin
if (up_sw_resetn == 1'b0) begin
up_irq_mask <= 'h00;
offload0_enable_reg <= 1'b0;
offload0_mem_reset_reg <= 1'b0;
end else begin
if (up_wreq_s) begin
case (up_waddr_s)
8'h20: up_irq_mask <= up_wdata_s;
8'h40: offload0_enable_reg <= up_wdata_s[0];
8'h42: offload0_mem_reset_reg <= up_wdata_s[0];
endcase
end
end
end
always @(posedge clk) begin
if (rstn == 1'b0) begin
up_rack_ff <= 'd0;
end else begin
up_rack_ff <= up_rreq_s;
end
end
generate
if (NUM_OF_SDI > 1) begin
// Only the first two SDI data can be recovered through AXI regmap
assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data[DATA_WIDTH+:DATA_WIDTH];
end else begin
assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data;
end
endgenerate
always @(posedge clk) begin
case (up_raddr_s)
8'h00: up_rdata_ff <= PCORE_VERSION;
8'h01: up_rdata_ff <= ID;
8'h02: up_rdata_ff <= up_scratch;
8'h03: up_rdata_ff <= {8'b0, NUM_OF_SDI, DATA_WIDTH};
8'h10: up_rdata_ff <= up_sw_reset;
8'h20: up_rdata_ff <= up_irq_mask;
8'h21: up_rdata_ff <= up_irq_pending;
8'h22: up_rdata_ff <= up_irq_source;
8'h30: up_rdata_ff <= sync_id;
8'h31: up_rdata_ff <= offload_sync_id;
8'h34: up_rdata_ff <= cmd_fifo_room;
8'h35: up_rdata_ff <= sdo_fifo_room;
8'h36: up_rdata_ff <= sdi_fifo_level;
8'h3a: up_rdata_ff <= sdi_fifo_out_data[DATA_WIDTH-1:0];
8'h3b: up_rdata_ff <= sdi_fifo_out_data_msb_s; /* store SDI's 32 bits MSB, if exists */
8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */
8'h40: up_rdata_ff <= {offload0_enable_reg};
8'h41: up_rdata_ff <= {offload0_enabled_s};
default: up_rdata_ff <= 'h00;
endcase
end
always @(posedge clk) begin
if (up_sw_resetn == 1'b0) begin
sync_id <= 'h00;
sync_id_pending <= 1'b0;
end else begin
if (sync_fifo_valid == 1'b1) begin
sync_id <= sync_fifo_data;
sync_id_pending <= 1'b1;
end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[3] == 1'b1) begin
sync_id_pending <= 1'b0;
end
end
end
always @(posedge clk) begin
if (up_sw_resetn == 1'b0) begin
offload_sync_id <= 'h00;
offload_sync_id_pending <= 1'b0;
end else begin
if (offload_sync_fifo_valid == 1'b1) begin
offload_sync_id <= offload_sync_fifo_data;
offload_sync_id_pending <= 1'b1;
end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[3] == 1'b1) begin
offload_sync_id_pending <= 1'b0;
end
end
end
generate if (ASYNC_SPI_CLK) begin
wire spi_reset;
ad_rst i_spi_resetn (
.rst_async(up_sw_reset),
.clk(spi_clk),
.rst(spi_reset),
.rstn()
);
assign spi_resetn = ~spi_reset;
end else begin
assign spi_resetn = ~up_sw_reset;
end
endgenerate
/* Evaluates to true if FIFO level/room is 3/4 or above */
`define axi_spi_engine_check_watermark(x, n) \
(x[n] == 1'b1 || x[n-1:n-2] == 2'b11)
assign cmd_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h38;
assign cmd_fifo_in_data = up_wdata_s[15:0];
assign cmd_fifo_almost_empty =
`axi_spi_engine_check_watermark(cmd_fifo_room, CMD_FIFO_ADDRESS_WIDTH);
util_axis_fifo #(
.DATA_WIDTH(16),
.ASYNC_CLK(ASYNC_SPI_CLK),
.ADDRESS_WIDTH(CMD_FIFO_ADDRESS_WIDTH),
.S_AXIS_REGISTERED(0)
) i_cmd_fifo (
.s_axis_aclk(clk),
.s_axis_aresetn(up_sw_resetn),
.s_axis_ready(cmd_fifo_in_ready),
.s_axis_valid(cmd_fifo_in_valid),
.s_axis_data(cmd_fifo_in_data),
.s_axis_room(cmd_fifo_room),
.s_axis_empty(),
.m_axis_aclk(spi_clk),
.m_axis_aresetn(spi_resetn),
.m_axis_ready(cmd_ready),
.m_axis_valid(cmd_valid),
.m_axis_data(cmd_data),
.m_axis_level()
);
assign sdo_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h39;
assign sdo_fifo_in_data = up_wdata_s[(DATA_WIDTH-1):0];
assign sdo_fifo_almost_empty =
`axi_spi_engine_check_watermark(sdo_fifo_room, SDO_FIFO_ADDRESS_WIDTH);
util_axis_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.ASYNC_CLK(ASYNC_SPI_CLK),
.ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH),
.S_AXIS_REGISTERED(0)
) i_sdo_fifo (
.s_axis_aclk(clk),
.s_axis_aresetn(up_sw_resetn),
.s_axis_ready(sdo_fifo_in_ready),
.s_axis_valid(sdo_fifo_in_valid),
.s_axis_data(sdo_fifo_in_data),
.s_axis_room(sdo_fifo_room),
.s_axis_empty(),
.m_axis_aclk(spi_clk),
.m_axis_aresetn(spi_resetn),
.m_axis_ready(sdo_data_ready),
.m_axis_valid(sdo_data_valid),
.m_axis_data(sdo_data),
.m_axis_level()
);
assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a;
assign sdi_fifo_almost_full =
`axi_spi_engine_check_watermark(sdi_fifo_level, SDI_FIFO_ADDRESS_WIDTH);
util_axis_fifo #(
.DATA_WIDTH(NUM_OF_SDI * DATA_WIDTH),
.ASYNC_CLK(ASYNC_SPI_CLK),
.ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH),
.S_AXIS_REGISTERED(0)
) i_sdi_fifo (
.s_axis_aclk(spi_clk),
.s_axis_aresetn(spi_resetn),
.s_axis_ready(sdi_data_ready),
.s_axis_valid(sdi_data_valid),
.s_axis_data(sdi_data),
.s_axis_room(),
.s_axis_empty(),
.m_axis_aclk(clk),
.m_axis_aresetn(up_sw_resetn),
.m_axis_ready(sdi_fifo_out_ready),
.m_axis_valid(sdi_fifo_out_valid),
.m_axis_data(sdi_fifo_out_data),
.m_axis_level(sdi_fifo_level)
);
generate if (ASYNC_SPI_CLK) begin
// synchronization FIFO for the SYNC interface
util_axis_fifo #(
.DATA_WIDTH(8),
.ASYNC_CLK(ASYNC_SPI_CLK),
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
.S_AXIS_REGISTERED(0)
) i_sync_fifo (
.s_axis_aclk(spi_clk),
.s_axis_aresetn(spi_resetn),
.s_axis_ready(sync_ready),
.s_axis_valid(sync_valid),
.s_axis_data(sync_data),
.s_axis_room(),
.s_axis_empty(),
.m_axis_aclk(clk),
.m_axis_aresetn(up_sw_resetn),
.m_axis_ready(1'b1),
.m_axis_valid(sync_fifo_valid),
.m_axis_data(sync_fifo_data),
.m_axis_level()
);
// synchronization FIFO for the offload command interface
wire up_offload0_cmd_wr_en_s;
wire [15:0] up_offload0_cmd_wr_data_s;
util_axis_fifo #(
.DATA_WIDTH(16),
.ASYNC_CLK(ASYNC_SPI_CLK),
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
.S_AXIS_REGISTERED(0)
) i_offload_cmd_fifo (
.s_axis_aclk(clk),
.s_axis_aresetn(up_sw_resetn),
.s_axis_ready(),
.s_axis_valid(up_offload0_cmd_wr_en_s),
.s_axis_data(up_offload0_cmd_wr_data_s),
.s_axis_room(),
.s_axis_empty(),
.m_axis_aclk(spi_clk),
.m_axis_aresetn(spi_resetn),
.m_axis_ready(1'b1),
.m_axis_valid(offload0_cmd_wr_en),
.m_axis_data(offload0_cmd_wr_data),
.m_axis_level()
);
assign up_offload0_cmd_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h44;
assign up_offload0_cmd_wr_data_s = up_wdata_s[15:0];
// synchronization FIFO for the offload SDO interface
wire up_offload0_sdo_wr_en_s;
wire [DATA_WIDTH-1:0] up_offload0_sdo_wr_data_s;
util_axis_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.ASYNC_CLK(ASYNC_SPI_CLK),
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
.S_AXIS_REGISTERED(0)
) i_offload_sdo_fifo (
.s_axis_aclk(clk),
.s_axis_aresetn(up_sw_resetn),
.s_axis_ready(),
.s_axis_valid(up_offload0_sdo_wr_en_s),
.s_axis_data(up_offload0_sdo_wr_data_s),
.s_axis_room(),
.s_axis_empty(),
.m_axis_aclk(spi_clk),
.m_axis_aresetn(spi_resetn),
.m_axis_ready(1'b1),
.m_axis_valid(offload0_sdo_wr_en),
.m_axis_data(offload0_sdo_wr_data),
.m_axis_level()
);
assign up_offload0_sdo_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h45;
assign up_offload0_sdo_wr_data_s = up_wdata_s[DATA_WIDTH-1:0];
// synchronization FIFO for the Offload SYNC interface
util_axis_fifo #(
.DATA_WIDTH(8),
.ASYNC_CLK(ASYNC_SPI_CLK),
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
.S_AXIS_REGISTERED(0)
) i_offload_sync_fifo (
.s_axis_aclk(spi_clk),
.s_axis_aresetn(spi_resetn),
.s_axis_ready(offload_sync_ready),
.s_axis_valid(offload_sync_valid),
.s_axis_data(offload_sync_data),
.s_axis_room(),
.s_axis_empty(),
.m_axis_aclk(clk),
.m_axis_aresetn(up_sw_resetn),
.m_axis_ready(1'b1),
.m_axis_valid(offload_sync_fifo_valid),
.m_axis_data(offload_sync_fifo_data),
.m_axis_level()
);
end else begin /* ASYNC_SPI_CLK == 0 */
assign sync_fifo_valid = sync_valid;
assign sync_fifo_data = sync_data;
assign sync_ready = 1'b1;
assign offload0_cmd_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h44;
assign offload0_cmd_wr_data = up_wdata_s[15:0];
assign offload0_sdo_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h45;
assign offload0_sdo_wr_data = up_wdata_s[DATA_WIDTH-1:0];
assign offload_sync_fifo_valid = offload_sync_valid;
assign offload_sync_fifo_data = offload_sync_data;
assign offload_sync_ready = 1'b1;
end
endgenerate
sync_bits #(
.NUM_OF_BITS (1),
.ASYNC_CLK (ASYNC_SPI_CLK)
) i_offload_enable_sync (
.in_bits (offload0_enable_reg),
.out_resetn (spi_resetn),
.out_clk (spi_clk),
.out_bits (offload0_enable));
sync_bits #(
.NUM_OF_BITS (1),
.ASYNC_CLK (ASYNC_SPI_CLK)
) i_offload_enabled_sync (
.in_bits (offload0_enabled),
.out_resetn (up_sw_resetn),
.out_clk (clk),
.out_bits (offload0_enabled_s));
sync_bits #(
.NUM_OF_BITS (1),
.ASYNC_CLK (ASYNC_SPI_CLK)
) i_offload_mem_reset_sync (
.in_bits (offload0_mem_reset_reg),
.out_resetn (spi_resetn),
.out_clk (spi_clk),
.out_bits (offload0_mem_reset));
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cb53/sync_bits.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
/*
* Helper module for synchronizing bit signals from one clock domain to another.
* It uses the standard approach of 2 FF in series.
* Note, that while the module allows to synchronize multiple bits at once it is
* only able to synchronize multi-bit signals where at max one bit changes per
* clock cycle (e.g. a gray counter).
*/
`timescale 1ns/100ps
module sync_bits #(
// Number of bits to synchronize
parameter NUM_OF_BITS = 1,
// Whether input and output clocks are asynchronous, if 0 the synchronizer will
// be bypassed and the output signal equals the input signal.
parameter ASYNC_CLK = 1)(
input [NUM_OF_BITS-1:0] in_bits,
input out_resetn,
input out_clk,
output [NUM_OF_BITS-1:0] out_bits);
generate if (ASYNC_CLK == 1) begin
reg [NUM_OF_BITS-1:0] cdc_sync_stage1 = 'h0;
reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0;
always @(posedge out_clk)
begin
if (out_resetn == 1'b0) begin
cdc_sync_stage1 <= 'b0;
cdc_sync_stage2 <= 'b0;
end else begin
cdc_sync_stage1 <= in_bits;
cdc_sync_stage2 <= cdc_sync_stage1;
end
end
assign out_bits = cdc_sync_stage2;
end else begin
assign out_bits = in_bits;
end endgenerate
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cb53/sync_data.v
-97
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module sync_data #(
parameter NUM_OF_BITS = 1,
parameter ASYNC_CLK = 1
) (
input in_clk,
input [NUM_OF_BITS-1:0] in_data,
input out_clk,
output reg [NUM_OF_BITS-1:0] out_data
);
generate
if (ASYNC_CLK == 1) begin
wire out_toggle;
wire in_toggle;
reg out_toggle_d1 = 1'b0;
reg in_toggle_d1 = 1'b0;
reg [NUM_OF_BITS-1:0] cdc_hold;
sync_bits i_sync_out (
.in_bits(in_toggle_d1),
.out_clk(out_clk),
.out_resetn(1'b1),
.out_bits(out_toggle)
);
sync_bits i_sync_in (
.in_bits(out_toggle_d1),
.out_clk(in_clk),
.out_resetn(1'b1),
.out_bits(in_toggle)
);
wire in_load = in_toggle == in_toggle_d1;
wire out_load = out_toggle ^ out_toggle_d1;
always @(posedge in_clk) begin
if (in_load == 1'b1) begin
cdc_hold <= in_data;
in_toggle_d1 <= ~in_toggle_d1;
end
end
always @(posedge out_clk) begin
if (out_load == 1'b1) begin
out_data <= cdc_hold;
end
out_toggle_d1 <= out_toggle;
end
end else begin
always @(*) begin
out_data <= in_data;
end
end
endgenerate
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cb53/sync_event.v
-120
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module sync_event #(
parameter NUM_OF_EVENTS = 1,
parameter ASYNC_CLK = 1
) (
input in_clk,
input [NUM_OF_EVENTS-1:0] in_event,
input out_clk,
output reg [NUM_OF_EVENTS-1:0] out_event
);
generate
if (ASYNC_CLK == 1) begin
wire out_toggle;
wire in_toggle;
reg out_toggle_d1 = 1'b0;
reg in_toggle_d1 = 1'b0;
sync_bits i_sync_out (
.in_bits(in_toggle_d1),
.out_clk(out_clk),
.out_resetn(1'b1),
.out_bits(out_toggle)
);
sync_bits i_sync_in (
.in_bits(out_toggle_d1),
.out_clk(in_clk),
.out_resetn(1'b1),
.out_bits(in_toggle)
);
wire in_ready = in_toggle == in_toggle_d1;
wire load_out = out_toggle ^ out_toggle_d1;
reg [NUM_OF_EVENTS-1:0] in_event_sticky = 'h00;
wire [NUM_OF_EVENTS-1:0] pending_events = in_event_sticky | in_event;
wire [NUM_OF_EVENTS-1:0] out_event_s;
always @(posedge in_clk) begin
if (in_ready == 1'b1) begin
in_event_sticky <= {NUM_OF_EVENTS{1'b0}};
if (|pending_events == 1'b1) begin
in_toggle_d1 <= ~in_toggle_d1;
end
end else begin
in_event_sticky <= pending_events;
end
end
if (NUM_OF_EVENTS > 1) begin
reg [NUM_OF_EVENTS-1:0] cdc_hold = 'h00;
always @(posedge in_clk) begin
if (in_ready == 1'b1) begin
cdc_hold <= pending_events;
end
end
assign out_event_s = cdc_hold;
end else begin
// When there is only one event, we know that it is set.
assign out_event_s = 1'b1;
end
always @(posedge out_clk) begin
if (load_out == 1'b1) begin
out_event <= out_event_s;
end else begin
out_event <= {NUM_OF_EVENTS{1'b0}};
end
out_toggle_d1 <= out_toggle;
end
end else begin
always @(*) begin
out_event <= in_event;
end
end
endgenerate
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cb53/sync_gray.v
-115
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@@ -1,115 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
/*
* Helper module for synchronizing a counter from one clock domain to another
* using gray code. To work correctly the counter must not change its value by
* more than one in one clock cycle in the source domain. I.e. the value may
* change by either -1, 0 or +1.
*/
`timescale 1ns/100ps
module sync_gray #(
// Bit-width of the counter
parameter DATA_WIDTH = 1,
// Whether the input and output clock are asynchronous, if set to 0 the
// synchronizer will be bypassed and out_count will be in_count.
parameter ASYNC_CLK = 1)(
input in_clk,
input in_resetn,
input [DATA_WIDTH-1:0] in_count,
input out_resetn,
input out_clk,
output [DATA_WIDTH-1:0] out_count);
generate if (ASYNC_CLK == 1) begin
reg [DATA_WIDTH-1:0] cdc_sync_stage0 = 'h0;
reg [DATA_WIDTH-1:0] cdc_sync_stage1 = 'h0;
reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0;
reg [DATA_WIDTH-1:0] out_count_m = 'h0;
function [DATA_WIDTH-1:0] g2b;
input [DATA_WIDTH-1:0] g;
reg [DATA_WIDTH-1:0] b;
integer i;
begin
b[DATA_WIDTH-1] = g[DATA_WIDTH-1];
for (i = DATA_WIDTH - 2; i >= 0; i = i - 1)
b[i] = b[i + 1] ^ g[i];
g2b = b;
end
endfunction
function [DATA_WIDTH-1:0] b2g;
input [DATA_WIDTH-1:0] b;
reg [DATA_WIDTH-1:0] g;
integer i;
begin
g[DATA_WIDTH-1] = b[DATA_WIDTH-1];
for (i = DATA_WIDTH - 2; i >= 0; i = i -1)
g[i] = b[i + 1] ^ b[i];
b2g = g;
end
endfunction
always @(posedge in_clk) begin
if (in_resetn == 1'b0) begin
cdc_sync_stage0 <= 'h00;
end else begin
cdc_sync_stage0 <= b2g(in_count);
end
end
always @(posedge out_clk) begin
if (out_resetn == 1'b0) begin
cdc_sync_stage1 <= 'h00;
cdc_sync_stage2 <= 'h00;
out_count_m <= 'h00;
end else begin
cdc_sync_stage1 <= cdc_sync_stage0;
cdc_sync_stage2 <= cdc_sync_stage1;
out_count_m <= g2b(cdc_sync_stage2);
end
end
assign out_count = out_count_m;
end else begin
assign out_count = in_count;
end endgenerate
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cf62/address_gray_pipelined.v
-152
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module fifo_address_gray_pipelined #(
parameter ADDRESS_WIDTH = 4
) (
input m_axis_aclk,
input m_axis_aresetn,
input m_axis_ready,
output reg m_axis_valid,
output [ADDRESS_WIDTH-1:0] m_axis_raddr,
output reg [ADDRESS_WIDTH:0] m_axis_level,
input s_axis_aclk,
input s_axis_aresetn,
output reg s_axis_ready,
input s_axis_valid,
output reg s_axis_empty,
output [ADDRESS_WIDTH-1:0] s_axis_waddr,
output reg [ADDRESS_WIDTH:0] s_axis_room
);
localparam MAX_ROOM = {1'b1,{ADDRESS_WIDTH{1'b0}}};
reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
reg [ADDRESS_WIDTH:0] _s_axis_waddr_next;
wire [ADDRESS_WIDTH:0] _s_axis_raddr;
reg [ADDRESS_WIDTH:0] _m_axis_raddr = 'h00;
reg [ADDRESS_WIDTH:0] _m_axis_raddr_next;
wire [ADDRESS_WIDTH:0] _m_axis_waddr;
assign s_axis_waddr = _s_axis_waddr[ADDRESS_WIDTH-1:0];
assign m_axis_raddr = _m_axis_raddr[ADDRESS_WIDTH-1:0];
always @(*)
begin
if (s_axis_ready && s_axis_valid)
_s_axis_waddr_next <= _s_axis_waddr + 1'b1;
else
_s_axis_waddr_next <= _s_axis_waddr;
end
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
_s_axis_waddr <= 'h00;
end else begin
_s_axis_waddr <= _s_axis_waddr_next;
end
end
always @(*)
begin
if (m_axis_ready && m_axis_valid)
_m_axis_raddr_next <= _m_axis_raddr + 1'b1;
else
_m_axis_raddr_next <= _m_axis_raddr;
end
always @(posedge m_axis_aclk)
begin
if (m_axis_aresetn == 1'b0) begin
_m_axis_raddr <= 'h00;
end else begin
_m_axis_raddr <= _m_axis_raddr_next;
end
end
sync_gray #(
.DATA_WIDTH(ADDRESS_WIDTH + 1)
) i_waddr_sync (
.in_clk(s_axis_aclk),
.in_resetn(s_axis_aresetn),
.out_clk(m_axis_aclk),
.out_resetn(m_axis_aresetn),
.in_count(_s_axis_waddr),
.out_count(_m_axis_waddr)
);
sync_gray #(
.DATA_WIDTH(ADDRESS_WIDTH + 1)
) i_raddr_sync (
.in_clk(m_axis_aclk),
.in_resetn(m_axis_aresetn),
.out_clk(s_axis_aclk),
.out_resetn(s_axis_aresetn),
.in_count(_m_axis_raddr),
.out_count(_s_axis_raddr)
);
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
s_axis_ready <= 1'b1;
s_axis_empty <= 1'b1;
s_axis_room <= MAX_ROOM;
end else begin
s_axis_ready <= (_s_axis_raddr[ADDRESS_WIDTH] == _s_axis_waddr_next[ADDRESS_WIDTH] ||
_s_axis_raddr[ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[ADDRESS_WIDTH-1:0]);
s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next;
s_axis_room <= _s_axis_raddr - _s_axis_waddr_next + MAX_ROOM;
end
end
always @(posedge m_axis_aclk)
begin
if (m_axis_aresetn == 1'b0) begin
m_axis_valid <= 1'b0;
m_axis_level <= 'h00;
end else begin
m_axis_valid <= _m_axis_waddr != _m_axis_raddr_next;
m_axis_level <= _m_axis_waddr - _m_axis_raddr_next;
end
end
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cf62/address_sync.v
-109
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@@ -1,109 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module fifo_address_sync #(
parameter ADDRESS_WIDTH = 4
) (
input clk,
input resetn,
input m_axis_ready,
output reg m_axis_valid,
output reg [ADDRESS_WIDTH-1:0] m_axis_raddr,
output [ADDRESS_WIDTH:0] m_axis_level,
output reg s_axis_ready,
input s_axis_valid,
output reg s_axis_empty,
output reg [ADDRESS_WIDTH-1:0] s_axis_waddr,
output [ADDRESS_WIDTH:0] s_axis_room
);
localparam MAX_ROOM = {1'b1,{ADDRESS_WIDTH{1'b0}}};
reg [ADDRESS_WIDTH:0] room = MAX_ROOM;
reg [ADDRESS_WIDTH:0] level = 'h00;
reg [ADDRESS_WIDTH:0] level_next;
assign s_axis_room = room;
assign m_axis_level = level;
wire read = m_axis_ready & m_axis_valid;
wire write = s_axis_ready & s_axis_valid;
always @(posedge clk)
begin
if (resetn == 1'b0) begin
s_axis_waddr <= 'h00;
m_axis_raddr <= 'h00;
end else begin
if (write)
s_axis_waddr <= s_axis_waddr + 1'b1;
if (read)
m_axis_raddr <= m_axis_raddr + 1'b1;
end
end
always @(*)
begin
if (read & ~write)
level_next <= level - 1'b1;
else if (~read & write)
level_next <= level + 1'b1;
else
level_next <= level;
end
always @(posedge clk)
begin
if (resetn == 1'b0) begin
m_axis_valid <= 1'b0;
s_axis_ready <= 1'b0;
level <= 'h00;
room <= MAX_ROOM;
s_axis_empty <= 'h00;
end else begin
level <= level_next;
room <= MAX_ROOM - level_next;
m_axis_valid <= level_next != 0;
s_axis_ready <= level_next != MAX_ROOM;
s_axis_empty <= level_next == 0;
end
end
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/cf62/util_axis_fifo.v
-248
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@@ -1,248 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_axis_fifo #(
parameter DATA_WIDTH = 64,
parameter ASYNC_CLK = 1,
parameter ADDRESS_WIDTH = 4,
parameter S_AXIS_REGISTERED = 1
) (
input m_axis_aclk,
input m_axis_aresetn,
input m_axis_ready,
output m_axis_valid,
output [DATA_WIDTH-1:0] m_axis_data,
output [ADDRESS_WIDTH:0] m_axis_level,
input s_axis_aclk,
input s_axis_aresetn,
output s_axis_ready,
input s_axis_valid,
input [DATA_WIDTH-1:0] s_axis_data,
output s_axis_empty,
output [ADDRESS_WIDTH:0] s_axis_room
);
generate if (ADDRESS_WIDTH == 0) begin
reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram;
reg s_axis_waddr = 1'b0;
reg m_axis_raddr = 1'b0;
wire m_axis_waddr;
wire s_axis_raddr;
sync_bits #(
.NUM_OF_BITS(1),
.ASYNC_CLK(ASYNC_CLK)
) i_waddr_sync (
.out_clk(m_axis_aclk),
.out_resetn(m_axis_aresetn),
.in_bits(s_axis_waddr),
.out_bits(m_axis_waddr)
);
sync_bits #(
.NUM_OF_BITS(1),
.ASYNC_CLK(ASYNC_CLK)
) i_raddr_sync (
.out_clk(s_axis_aclk),
.out_resetn(s_axis_aresetn),
.in_bits(m_axis_raddr),
.out_bits(s_axis_raddr)
);
assign m_axis_valid = m_axis_raddr != m_axis_waddr;
assign m_axis_level = m_axis_valid;
assign s_axis_ready = s_axis_raddr == s_axis_waddr;
assign s_axis_empty = s_axis_ready;
assign s_axis_room = s_axis_ready;
always @(posedge s_axis_aclk) begin
if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1)
cdc_sync_fifo_ram <= s_axis_data;
end
always @(posedge s_axis_aclk) begin
if (s_axis_aresetn == 1'b0) begin
s_axis_waddr <= 1'b0;
end else begin
if (s_axis_ready & s_axis_valid) begin
s_axis_waddr <= s_axis_waddr + 1'b1;
end
end
end
always @(posedge m_axis_aclk) begin
if (m_axis_aresetn == 1'b0) begin
m_axis_raddr <= 1'b0;
end else begin
if (m_axis_valid & m_axis_ready)
m_axis_raddr <= m_axis_raddr + 1'b1;
end
end
assign m_axis_data = cdc_sync_fifo_ram;
end else begin
reg [DATA_WIDTH-1:0] ram[0:2**ADDRESS_WIDTH-1];
wire [ADDRESS_WIDTH-1:0] s_axis_waddr;
wire [ADDRESS_WIDTH-1:0] m_axis_raddr;
wire _m_axis_ready;
wire _m_axis_valid;
wire [ADDRESS_WIDTH:0] _m_axis_level;
wire s_mem_write;
wire m_mem_read;
reg valid;
always @(posedge m_axis_aclk) begin
if (m_axis_aresetn == 1'b0) begin
valid <= 1'b0;
end else begin
if (_m_axis_valid)
valid <= 1'b1;
else if (m_axis_ready)
valid <= 1'b0;
end
end
assign s_mem_write = s_axis_ready & s_axis_valid;
assign m_mem_read = (~valid || m_axis_ready) && _m_axis_valid;
if (ASYNC_CLK == 1) begin
// The assumption is that in this mode the S_AXIS_REGISTERED is 1
fifo_address_gray_pipelined #(
.ADDRESS_WIDTH(ADDRESS_WIDTH)
) i_address_gray (
.m_axis_aclk(m_axis_aclk),
.m_axis_aresetn(m_axis_aresetn),
.m_axis_ready(_m_axis_ready),
.m_axis_valid(_m_axis_valid),
.m_axis_raddr(m_axis_raddr),
.m_axis_level(_m_axis_level),
.s_axis_aclk(s_axis_aclk),
.s_axis_aresetn(s_axis_aresetn),
.s_axis_ready(s_axis_ready),
.s_axis_valid(s_axis_valid),
.s_axis_empty(s_axis_empty),
.s_axis_waddr(s_axis_waddr),
.s_axis_room(s_axis_room)
);
// When the clocks are asynchronous instantiate a block RAM
// regardless of the requested size to make sure we threat the
// clock crossing correctly
ad_mem #(
.DATA_WIDTH (DATA_WIDTH),
.ADDRESS_WIDTH (ADDRESS_WIDTH))
i_mem (
.clka(s_axis_aclk),
.wea(s_mem_write),
.addra(s_axis_waddr),
.dina(s_axis_data),
.clkb(m_axis_aclk),
.reb(m_mem_read),
.addrb(m_axis_raddr),
.doutb(m_axis_data)
);
assign _m_axis_ready = ~valid || m_axis_ready;
assign m_axis_valid = valid;
// the util_axis_fifo is functioning in 'first write fall through' mode,
// which means that we need to assure that the value of the level reflects
// the actual FIFO level plus the available data, which sits on the bus
assign m_axis_level = (m_axis_valid) ? _m_axis_level + 1'b1 : _m_axis_level;
end else begin
fifo_address_sync #(
.ADDRESS_WIDTH(ADDRESS_WIDTH)
) i_address_sync (
.clk(m_axis_aclk),
.resetn(m_axis_aresetn),
.m_axis_ready(_m_axis_ready),
.m_axis_valid(_m_axis_valid),
.m_axis_raddr(m_axis_raddr),
.m_axis_level(m_axis_level),
.s_axis_ready(s_axis_ready),
.s_axis_valid(s_axis_valid),
.s_axis_empty(s_axis_empty),
.s_axis_waddr(s_axis_waddr),
.s_axis_room(s_axis_room)
);
// When the clocks are synchronous use behavioral modeling for the SDP RAM
// Let the synthesizer decide what to infer (distributed or block RAM)
always @(posedge s_axis_aclk) begin
if (s_mem_write)
ram[s_axis_waddr] <= s_axis_data;
end
if (S_AXIS_REGISTERED == 1) begin
reg [DATA_WIDTH-1:0] data;
always @(posedge m_axis_aclk) begin
if (m_mem_read)
data <= ram[m_axis_raddr];
end
assign _m_axis_ready = ~valid || m_axis_ready;
assign m_axis_data = data;
assign m_axis_valid = valid;
end else begin
assign _m_axis_ready = m_axis_ready;
assign m_axis_valid = _m_axis_valid;
assign m_axis_data = ram[m_axis_raddr];
end
end
end endgenerate
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ipshared/common/ad_mem.v
-71
View File
@@ -1,71 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_mem #(
parameter DATA_WIDTH = 16,
parameter ADDRESS_WIDTH = 5) (
input clka,
input wea,
input [(ADDRESS_WIDTH-1):0] addra,
input [(DATA_WIDTH-1):0] dina,
input clkb,
input reb,
input [(ADDRESS_WIDTH-1):0] addrb,
output reg [(DATA_WIDTH-1):0] doutb);
(* ram_style = "block" *)
reg [(DATA_WIDTH-1):0] m_ram[0:((2**ADDRESS_WIDTH)-1)];
always @(posedge clka) begin
if (wea == 1'b1) begin
m_ram[addra] <= dina;
end
end
always @(posedge clkb) begin
if (reb == 1'b1) begin
doutb <= m_ram[addrb];
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/system_bd.bd
+76 -12
View File
@@ -1,7 +1,7 @@
{
"design": {
"design_info": {
"boundary_crc": "0xFFC3C3D2DEE0B4A1",
"boundary_crc": "0xFFC3C3D2D3E28C10",
"device": "xc7z045ffg900-2",
"gen_directory": "../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd",
"name": "system_bd",
@@ -26,7 +26,8 @@
"m01_couplers": {}
},
"xlconcat_irq": "",
"system_management": ""
"system_management": "",
"system_ila_spi": ""
},
"interface_ports": {
"ddr": {
@@ -1385,7 +1386,12 @@
"interface_ports": [
"spi_engine_execution/spi",
"spi"
]
],
"hdl_attributes": {
"DEBUG": {
"value": "true"
}
}
},
"axi_spi_engine_spi_engine_ctrl": {
"interface_ports": [
@@ -1422,15 +1428,20 @@
"spi_clk_0_1": {
"ports": [
"spi_clk",
"axi_spi_engine/spi_clk",
"spi_engine_execution/clk"
"spi_engine_execution/clk",
"axi_spi_engine/spi_clk"
]
},
"spi_engine_execution_active": {
"ports": [
"spi_engine_execution/active",
"active"
]
],
"hdl_attributes": {
"DEBUG": {
"value": "true"
}
}
}
}
},
@@ -1887,6 +1898,40 @@
"value": "false"
}
}
},
"system_ila_spi": {
"vlnv": "xilinx.com:ip:system_ila:1.1",
"ip_revision": "17",
"xci_name": "system_bd_system_ila_0_0",
"xci_path": "ip/system_bd_system_ila_0_0/system_bd_system_ila_0_0.xci",
"inst_hier_path": "system_ila_spi",
"parameters": {
"C_MON_TYPE": {
"value": "MIX"
},
"C_NUM_MONITOR_SLOTS": {
"value": "1"
},
"C_NUM_OF_PROBES": {
"value": "1"
},
"C_PROBE0_TYPE": {
"value": "0"
},
"C_SLOT_0_INTF_TYPE": {
"value": "analog.com:interface:spi_engine_rtl:1.0"
},
"C_SLOT_0_TYPE": {
"value": "0"
}
},
"interface_ports": {
"SLOT_0_SPI_ENGINE": {
"mode": "Monitor",
"vlnv_bus_definition": "analog.com:interface:spi_engine:1.0",
"vlnv": "analog.com:interface:spi_engine_rtl:1.0"
}
}
}
},
"interface_nets": {
@@ -1911,8 +1956,17 @@
"axi_spi_engine_spi": {
"interface_ports": [
"spi",
"axi_spi_engine/spi"
]
"axi_spi_engine/spi",
"system_ila_spi/SLOT_0_SPI_ENGINE"
],
"hdl_attributes": {
"DEBUG": {
"value": "true"
},
"MARK_DEBUG": {
"value": "true"
}
}
},
"processing_system7_DDR": {
"interface_ports": [
@@ -1943,8 +1997,17 @@
"axi_spi_engine_active": {
"ports": [
"axi_spi_engine/active",
"spi_active"
]
"spi_active",
"system_ila_spi/probe0"
],
"hdl_attributes": {
"DEBUG": {
"value": "true"
},
"MARK_DEBUG": {
"value": "true"
}
}
},
"axi_spi_engine_irq": {
"ports": [
@@ -1957,7 +2020,6 @@
"processing_system7/FCLK_CLK0",
"processing_system7/M_AXI_GP0_ACLK",
"axi_spi_engine/s_axi_aclk",
"axi_spi_engine/spi_clk",
"axi_interconnect_0/ACLK",
"axi_interconnect_0/S00_ACLK",
"axi_interconnect_0/M00_ACLK",
@@ -1969,7 +2031,9 @@
"processing_system7_FCLK_CLK1": {
"ports": [
"processing_system7/FCLK_CLK1",
"ps_clk_200M"
"ps_clk_200M",
"axi_spi_engine/spi_clk",
"system_ila_spi/clk"
]
},
"processing_system7_FCLK_RESET0_N": {
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui
+32 -31
View File
@@ -1,45 +1,46 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"0.798638",
"Default View_TopLeft":"-533,0",
"Default View_TopLeft":"-601,1",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
# -string -flagsOSRD
preplace port ddr -pg 1 -lvl 3 -x 930 -y 150 -defaultsOSRD
preplace port fixed_io -pg 1 -lvl 3 -x 930 -y 170 -defaultsOSRD
preplace port Vp_Vn -pg 1 -lvl 0 -x 0 -y 590 -defaultsOSRD
preplace port port-id_spi_active -pg 1 -lvl 3 -x 930 -y 70 -defaultsOSRD
preplace port port-id_ps_clk_200M -pg 1 -lvl 3 -x 930 -y 190 -defaultsOSRD
preplace port spi -pg 1 -lvl 3 -x 930 -y 930 -defaultsOSRD
preplace portBus gpio_i -pg 1 -lvl 3 -x 930 -y 90 -defaultsOSRD -right
preplace portBus gpio_o -pg 1 -lvl 3 -x 930 -y 110 -defaultsOSRD
preplace portBus gpio_t -pg 1 -lvl 3 -x 930 -y 130 -defaultsOSRD
preplace port ddr -pg 1 -lvl 3 -x 1040 -y 150 -defaultsOSRD
preplace port fixed_io -pg 1 -lvl 3 -x 1040 -y 170 -defaultsOSRD
preplace port Vp_Vn -pg 1 -lvl 0 -x -10 -y 590 -defaultsOSRD
preplace port spi -pg 1 -lvl 3 -x 1040 -y 930 -defaultsOSRD
preplace port port-id_spi_active -pg 1 -lvl 3 -x 1040 -y 70 -defaultsOSRD
preplace port port-id_ps_clk_200M -pg 1 -lvl 3 -x 1040 -y 190 -defaultsOSRD
preplace portBus gpio_i -pg 1 -lvl 3 -x 1040 -y 90 -defaultsOSRD -right
preplace portBus gpio_o -pg 1 -lvl 3 -x 1040 -y 110 -defaultsOSRD
preplace portBus gpio_t -pg 1 -lvl 3 -x 1040 -y 130 -defaultsOSRD
preplace inst processing_system7 -pg 1 -lvl 1 -x 260 -y 200 -defaultsOSRD
preplace inst axi_spi_engine -pg 1 -lvl 1 -x 260 -y 950 -defaultsOSRD
preplace inst rst_ps7_50M -pg 1 -lvl 2 -x 710 -y 270 -defaultsOSRD
preplace inst rst_ps7_50M -pg 1 -lvl 2 -x 740 -y 270 -defaultsOSRD
preplace inst axi_interconnect_0 -pg 1 -lvl 1 -x 260 -y 740 -defaultsOSRD
preplace inst xlconcat_irq -pg 1 -lvl 2 -x 710 -y 420 -defaultsOSRD -orient R180
preplace inst system_management -pg 1 -lvl 2 -x 710 -y 600 -defaultsOSRD
preplace netloc processing_system7_FCLK_CLK0 1 0 2 20 10 510
preplace netloc processing_system7_FCLK_RESET0_N 1 1 1 500 250n
preplace netloc rst_ps7_50M_peripheral_aresetn 1 0 3 40 580 530J 490 910
preplace inst xlconcat_irq -pg 1 -lvl 2 -x 740 -y 420 -defaultsOSRD -orient R180
preplace inst system_management -pg 1 -lvl 2 -x 740 -y 600 -defaultsOSRD
preplace inst system_ila_spi -pg 1 -lvl 2 -x 740 -y 90 -defaultsOSRD
preplace netloc GPIO_I_0_1 1 1 2 530 490 950
preplace netloc axi_spi_engine_active 1 1 2 560J 750 970
preplace netloc axi_spi_engine_irq 1 1 2 N 970 930
preplace netloc processing_system7_FCLK_CLK0 1 0 2 10 10 480
preplace netloc processing_system7_FCLK_CLK1 1 0 3 20 570 540J 710 1000J
preplace netloc processing_system7_FCLK_RESET0_N 1 1 1 550 250n
preplace netloc processing_system7_GPIO_O 1 1 2 510J 730 980J
preplace netloc processing_system7_GPIO_T 1 1 2 500J 720 990J
preplace netloc rst_ps7_50M_peripheral_aresetn 1 0 3 40 580 490J 740 940
preplace netloc system_management_ip2intc_irpt 1 2 1 920 410n
preplace netloc xlconcat_irq_dout 1 0 2 50 420 N
preplace netloc processing_system7_FCLK_CLK1 1 1 2 480J 140 910J
preplace netloc GPIO_I_0_1 1 1 2 N 90 N
preplace netloc processing_system7_GPIO_O 1 1 2 NJ 110 NJ
preplace netloc processing_system7_GPIO_T 1 1 2 NJ 130 NJ
preplace netloc system_management_ip2intc_irpt 1 2 1 900 410n
preplace netloc axi_spi_engine_active 1 1 2 490J 70 N
preplace netloc axi_spi_engine_irq 1 1 2 N 970 890
preplace netloc processing_system7_DDR 1 1 2 NJ 150 N
preplace netloc processing_system7_M_AXI_GP0 1 0 2 30 390 470
preplace netloc axi_interconnect_0_M00_AXI 1 0 2 50 600 470
preplace netloc processing_system7_FIXED_IO 1 1 2 NJ 170 N
preplace netloc axi_interconnect_0_M01_AXI 1 1 1 520 570n
preplace netloc Vp_Vn_0_1 1 0 2 NJ 590 NJ
preplace netloc axi_spi_engine_spi 1 1 2 NJ 930 NJ
levelinfo -pg 1 0 260 710 930
pagesize -pg 1 -db -bbox -sgen -100 0 1070 1030
preplace netloc axi_interconnect_0_M00_AXI 1 0 2 50 600 470
preplace netloc axi_interconnect_0_M01_AXI 1 1 1 550 570n
preplace netloc axi_spi_engine_spi 1 1 2 520J 930 NJ
preplace netloc processing_system7_DDR 1 1 2 490J 10 960
preplace netloc processing_system7_FIXED_IO 1 1 2 NJ 170 N
preplace netloc processing_system7_M_AXI_GP0 1 0 2 30 390 470
levelinfo -pg 1 -10 260 740 1040
pagesize -pg 1 -db -bbox -sgen -110 0 1180 1030
"
}
{
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui
+12 -6
View File
@@ -1,23 +1,29 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"1.0",
"Default View_TopLeft":"-438,-327",
"Default View_TopLeft":"-423,-321",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
# -string -flagsOSRD
preplace port s_axi -pg 1 -lvl 0 -x -10 -y 60 -defaultsOSRD
preplace port spi_0 -pg 1 -lvl 3 -x 1040 -y 90 -defaultsOSRD
preplace port spi -pg 1 -lvl 3 -x 1040 -y 80 -defaultsOSRD
preplace port port-id_s_axi_aclk -pg 1 -lvl 0 -x -10 -y 80 -defaultsOSRD
preplace port port-id_s_axi_aresetn -pg 1 -lvl 0 -x -10 -y 100 -defaultsOSRD
preplace port port-id_spi_clk -pg 1 -lvl 0 -x -10 -y 120 -defaultsOSRD
preplace port port-id_active -pg 1 -lvl 3 -x 1040 -y 100 -defaultsOSRD
preplace port port-id_irq -pg 1 -lvl 3 -x 1040 -y 170 -defaultsOSRD
preplace inst axi_spi_engine -pg 1 -lvl 1 -x 640 -y 90 -defaultsOSRD
preplace inst spi_engine_execution_0 -pg 1 -lvl 2 -x 890 -y 100 -defaultsOSRD
preplace inst spi_engine_execution -pg 1 -lvl 2 -x 900 -y 90 -defaultsOSRD
preplace netloc axi_spi_engine_irq 1 1 2 780J 170 NJ
preplace netloc axi_spi_engine_spi_resetn 1 1 1 N 110
preplace netloc s_axi_aclk_0_1 1 0 1 N 80
preplace netloc s_axi_aresetn_0_1 1 0 1 N 100
preplace netloc spi_clk_0_1 1 0 1 N 120
preplace netloc spi_clk_0_1 1 0 2 500 180 790
preplace netloc spi_engine_execution_active 1 2 1 NJ 100
preplace netloc Conn1 1 0 1 N 60
preplace netloc Conn2 1 2 1 N 90
levelinfo -pg 1 -10 640 890 1040
preplace netloc Conn2 1 2 1 N 80
preplace netloc axi_spi_engine_spi_engine_ctrl 1 1 1 N 70
levelinfo -pg 1 -10 640 900 1040
pagesize -pg 1 -db -bbox -sgen -160 -480 1140 330
"
}
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/CreatePN40_LocalTemp_256points.m
+75
View File
@@ -0,0 +1,75 @@
%% PN56
clc;clear;close all;
addpath(genpath(pwd));
%% 参数设置
load("PN40_reverse.mat");
% GMSK 调制的参数
BT = 0.3;
Rc = 1.5e6; % 码片速率 1.4Mcps
fs_clk = 48e6; % ADC 的采样速率
fs_acq = 4.8e6; % 捕获模块采样速率为3.2M, 与 Rc并不是整数倍关系
SampRate = fs_clk/Rc; % 对于码片的过采样率
% PN 码,帧结构参数
PNLen = 40; % 一组PN码的长度
% 捕获时参数
FFT_Len = 256;
Acq_Sample = fs_acq/Rc; %捕获时,采用的过采样率
FreSearchIdx = 0;
%% 发送端
frameSend = repmat(PN40,1,40);
[GMSKSendWave] = gmsk_base_modfpga_fuc(frameSend,BT,SampRate,4);
%变采样率,获取本地模板
% h = LPF_Fpass1p8_Fstop2p2_Fs48_40dB;
% hLen = floor(length(h)/2);
%
% GMSKSendWave2 = conv(GMSKSendWave,h);
% GMSKSendWave2 = GMSKSendWave2(hLen+1:end-hLen);
% 对抗混叠滤波后的数据,进行抽取
% Acq_Din = downsample(GMSKSendWave2,fs_clk/fs_acq);
Acq_Din = downsample(GMSKSendWave,fs_clk/fs_acq);
% 取本地模板
PNWave = Acq_Din(1:FFT_Len);
PNWaveLocalTemp = PNWave(1:FFT_Len);
PNWaveLocalTemp_Norm = PNWaveLocalTemp/max(PNWaveLocalTemp);
Acq_FFTLocalTemp = fft(PNWave,FFT_Len);
Acq_FFTLocalTemp_Norm = Acq_FFTLocalTemp/max(abs(Acq_FFTLocalTemp));
%save("GMSKSendWave.mat","GMSKSendWave");
%归一化并量化
q = quantizer([16, 15], 'fixed', 'convergent', 'saturate');
Acq_FFTLocalTemp_Norm = quantize(q,Acq_FFTLocalTemp_Norm);
% 转换为 16进制
Acq_FFTLocalTemp_I_FPGA = num2hex(q,real(Acq_FFTLocalTemp_Norm));
Acq_FFTLocalTemp_Q_FPGA = num2hex(q,imag(Acq_FFTLocalTemp_Norm));
Acq_FFTLocalTemp_FPGA = [Acq_FFTLocalTemp_Q_FPGA,Acq_FFTLocalTemp_I_FPGA];
%% 写入到 coe 文件中
data = Acq_FFTLocalTemp_FPGA;
fid = fopen("New_AcqPN40_FFTLocalTemp_256points.coe",'w');
fprintf(fid,'memory_initialization_radix=16;\n');
fprintf(fid,'memory_initialization_vector=\n');
for i = 1:length(data)
fprintf(fid,'%s\n',data(i,:));
end
fclose(fid);
% %% 保存Maltab 变量
% save("Acq_FFTLocalTemp.mat","Acq_FFTLocalTemp_Norm","Acq_FFTLocalTemp_FPGA");
%
save("New_AcqPN40_FFTLocalTemp_256points.mat","Acq_FFTLocalTemp_Norm","PNWaveLocalTemp_Norm");
%%
rmpath(genpath(pwd));
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/coe_gen.m
+90
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@@ -0,0 +1,90 @@
function coe_gen(data,file_name,varargin)%varargin : type radix [bit_width]
%coe_gen - Xilinx coe文件生成，根据官网语法说明编写
%
% coe_gen(data, file_nanme)
% coe_gen(data,file_name,type)
% coe_gen(data,file_name,type, 'd')
% coe_gen(data,file_name,type, radix, bit_width)
%
% data - integer double 需要写入的数据,整数或定点小数一维向量
% 为定点数时，只能使用十进制保存
% file_name - char 文件名或完成存放路径
% type - char coe文件类型 'memory' 'filter' 'correlator' 'interleaver'
% radix - char 数据保存进制 'b' 'd' 'h'
% 'b' 二进制
% 'd' 十进制
% 'h' 十六进制
% 二进制与十六进制时候需要指明位宽
% bit_width - integer 数据位宽
%
% Author: Fan Hao.
% References: https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgn_r_coe_file_syntax.htm
% Copyright Beijing Institute of Technology.
radix_dic_str = ['b','o','d','h'];
radix_dic_num = [2 8 10 16];
narginchk(2,5);
%input check
if isempty(varargin) %default properties
radix = 10; type = 'memory';
else %type check
if length(varargin)>=1 &&ismember(varargin{1},{'memory','filter','correlator','interleaver'})
type = varargin{1};
else
error('ERROR: wrong coe file type!');
end%radix and bit_width check
if length(varargin)>=2 && ismember(varargin{2},['b','d','h'])
radix = radix_dic_num(radix_dic_str==varargin{2});
if varargin{2} ~= 'd'
if length(varargin)==3 && ~mod(varargin{3},1)
bit_width = varargin{3};
else
error('ERROR: bit width must be specified as a integer.');
end
else
if length(varargin)==3
error('ERROR: too many argument.');
end
end
else
if length(varargin)==1
radix = 10;
else
error("ERROR: radix must be 'b' or 'd' or 'h'.");
end
end
end
%create file
file_p = fopen(file_name, 'w+', 'n', 'UTF-8');
if type == 'memory'
fprintf(file_p,['MEMORY_INITIALIZATION_RADIX = ' num2str(radix) ';\n']);
else
fprintf(file_p,['RADIX = ' num2str(radix) ';\n']);
end
switch type
case 'memory'
fprintf(file_p,['MEMORY_INITIALIZATION_VECTOR = ' '\n']);
case 'filter'
fprintf(file_p,['COEFDATA = ' '\n']);
case 'correlator'
fprintf(file_p,['PATTERN = ' '\n']);
case 'interleaver'
fprintf(file_p,['BRANCH_LENGTH_VECTOR = ' '\n']);
end
for i = 1:length(data)
switch radix
case 2
temp = dec2bin(data(i),bit_width);
case 10
temp = num2str(data(i));
case 16
temp = dec2hex(data(i),ceil(bit_width/4));
end
if i == length(data)
fprintf(file_p,[temp ';\n']);
else
fprintf(file_p,[temp ',\n']);
end
end
fclose(file_p);
end
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/generate_baseband_coe.m
+29
View File
@@ -0,0 +1,29 @@
% clear all
% clc
% % pnSequence=comn.PNSequence('Polynomial','x^10+x^7+1','InitialConditions',[zeros(1,9),1],'SamplesPerFrame',2^10-1);
% % PRBS10=pnSequence();
% % PRB10_polar=1-2*[ PRBS10;0];
% % coe_gen(PRBS10,'prbs10.coe','memory');
% hrc=rcosdesign(0.35,6,8,'sqrt');
% %hrc=rcosdesign(0.25,12,64);
% hrc_16b=round(hrc/max(hrc)*(2^15-1));
% %coe_gen(hrc_16b,'hrc_64_12_025.coe','memory');
% coe_gen(hrc_16b,'hrc_8_6_035.coe','memory');
clear all
clc
fs = 64e6;
Rs = 48e6;
alpha = 0.3;
hrc_48 = rcosdesign(alpha,12,4,'sqrt');%span=6,sps=4
hrc_48_16b=round(hrc_48/max(hrc_48)*(2^15-1));
coe_gen(hrc_48_16b,'hrc_4_12_03.coe','memory');
hrc_12 = rcosdesign(alpha,12,16,'sqrt');
hrc_12_16b=round(hrc_12/max(hrc_12)*(2^15-1));
coe_gen(hrc_12_16b,'hrc_16_12_03.coe','memory');
hrc_1p5 = rcosdesign(alpha,12,128,'sqrt');
hrc_1p5_16b=round(hrc_1p5/max(hrc_1p5)*(2^15-1));
coe_gen(hrc_1p5_16b,'hrc_128_12_03.coe','memory');
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/hrc_128_12_03.coe
+1539
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File diff suppressed because it is too large Load Diff
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/hrc_16_12_03.coe
+195
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@@ -0,0 +1,195 @@
RADIX = 10;
COEFDATA =
-203,
-163,
-111,
-50,
17,
85,
152,
212,
261,
296,
315,
315,
295,
257,
203,
134,
55,
-29,
-113,
-191,
-258,
-309,
-340,
-348,
-331,
-290,
-226,
-142,
-43,
64,
172,
273,
360,
426,
462,
465,
432,
360,
252,
112,
-55,
-238,
-428,
-612,
-778,
-911,
-1000,
-1033,
-1003,
-903,
-732,
-492,
-190,
163,
553,
960,
1363,
1738,
2060,
2305,
2451,
2476,
2368,
2114,
1714,
1171,
497,
-288,
-1154,
-2067,
-2986,
-3864,
-4652,
-5298,
-5752,
-5968,
-5902,
-5521,
-4797,
-3715,
-2271,
-476,
1651,
4073,
6744,
9606,
12592,
15628,
18635,
21533,
24239,
26679,
28782,
30486,
31740,
32508,
32767,
32508,
31740,
30486,
28782,
26679,
24239,
21533,
18635,
15628,
12592,
9606,
6744,
4073,
1651,
-476,
-2271,
-3715,
-4797,
-5521,
-5902,
-5968,
-5752,
-5298,
-4652,
-3864,
-2986,
-2067,
-1154,
-288,
497,
1171,
1714,
2114,
2368,
2476,
2451,
2305,
2060,
1738,
1363,
960,
553,
163,
-190,
-492,
-732,
-903,
-1003,
-1033,
-1000,
-911,
-778,
-612,
-428,
-238,
-55,
112,
252,
360,
432,
465,
462,
426,
360,
273,
172,
64,
-43,
-142,
-226,
-290,
-331,
-348,
-340,
-309,
-258,
-191,
-113,
-29,
55,
134,
203,
257,
295,
315,
315,
296,
261,
212,
152,
85,
17,
-50,
-111,
-163,
-203;
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/coe/hrc_4_12_03.coe
+51
View File
@@ -0,0 +1,51 @@
RADIX = 10;
COEFDATA =
-203,
17,
261,
295,
55,
-258,
-331,
-43,
360,
432,
-55,
-778,
-1003,
-190,
1363,
2451,
1714,
-1154,
-4652,
-5902,
-2271,
6744,
18635,
28782,
32767,
28782,
18635,
6744,
-2271,
-5902,
-4652,
-1154,
1714,
2451,
1363,
-190,
-1003,
-778,
-55,
432,
360,
-43,
-331,
-258,
55,
295,
261,
17,
-203;
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/cx9261a_fifo/cx9261a_fifo.xci
+479
View File
@@ -0,0 +1,479 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "cx9261a_fifo",
"component_reference": "xilinx.com:ip:fifo_generator:13.2",
"ip_revision": "10",
"gen_directory": "../../../../zc706_cx9261a_demo.gen/sources_1/ip/cx9261a_fifo",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "cx9261a_fifo", "resolve_type": "user", "usage": "all" } ],
"Fifo_Implementation": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
"Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
"asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Input_Data_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Input_Depth": [ { "value": "64", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Output_Data_Width": [ { "value": "32", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Output_Depth": [ { "value": "64", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Use_Embedded_Registers": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Reset_Pin": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Reset_Type": [ { "value": "Asynchronous_Reset", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Full_Flags_Reset_Value": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Use_Dout_Reset": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Underflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Overflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Data_Count_Width": [ { "value": "6", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Write_Data_Count_Width": [ { "value": "6", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Read_Data_Count_Width": [ { "value": "6", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Programmable_Full_Type": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
"Full_Threshold_Assert_Value": [ { "value": "61", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Full_Threshold_Negate_Value": [ { "value": "60", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
"Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Empty_Threshold_Negate_Value": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Clock_Type_AXI": [ { "value": "Common_Clock", "resolve_type": "user", "usage": "all" } ],
"HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
"ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"ADDRESS_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
"FIFO_Implementation_wach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
"FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
"Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
"FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
"FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
"Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
"FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
"FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/hrc_128_12_03/hrc_128_12_03.xci
+350
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zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/hrc_16_12_03/hrc_16_12_03.xci
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zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/hrc_4_12_03/hrc_4_12_03.xci
+350
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@@ -0,0 +1,350 @@
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zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/ila_trx/ila_trx.xci
+8 -8
View File
@@ -2047,14 +2047,14 @@
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@@ -3135,7 +3135,7 @@
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zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/ila_trx_fb/ila_trx_fb.xci
-6301
View File
File diff suppressed because it is too large Load Diff
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/sys_clk_gen/sys_clk_gen.xci
+676
View File
@@ -0,0 +1,676 @@
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"REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
"PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
"CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
"USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
"PRIM_IN_FREQ": [ { "value": "128", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
"PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
"IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
"RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
"USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
"SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
"JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
"CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
"SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKIN1_JITTER_PS": [ { "value": "78.12", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"NUM_OUT_CLKS": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
"CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
"CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
"CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
"CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
"CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
"CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
"CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
"DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
"DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
"DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
"DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
"DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
"DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
"DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
"PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
"PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
"PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
"PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "48", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
"CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
"CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
"CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
"CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
"CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
"CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
"CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
"FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
"CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
"CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
"CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
"CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
"CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
"CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
"CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
"PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
"SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
"USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
"USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
"LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
"POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
"CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
"STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
"CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
"INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
"CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
"SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
"SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
"SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
"OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
"MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
"MMCM_CLKFBOUT_MULT_F": [ { "value": "7.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_CLKIN1_PERIOD": [ { "value": "7.812", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ],
"MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "15.750", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_CLKOUT1_DIVIDE": [ { "value": "21", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
"PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
"PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
"PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
"PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
"BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ]
},
"port_maps": {
"CLK_IN1": [ { "physical_name": "clk_in1" } ]
}
},
"clock_CLK_OUT1": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "master",
"parameters": {
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK_OUT1": [ { "physical_name": "clk_out1" } ]
}
},
"clock_CLK_OUT2": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "master",
"parameters": {
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK_OUT2": [ { "physical_name": "clk_out2" } ]
}
}
}
}
}
}
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/new/system_top.v
+163 -131
View File
@@ -197,24 +197,24 @@ system_bd_wrapper system_bd
////////////////////////////////////////////////////////////////////////////////
////////////////////////////// CX9261A Interface ///////////////////////////////
////////////////////////////////////////////////////////////////////////////////
wire data_clk;
wire data_valid;
wire data_clk2;
wire data_valid2;
wire data_clk3;
wire data_valid3;
wire [15:0] rx1_data_i;
wire [15:0] rx1_data_q;
wire [15:0] rx2_data_i;
wire [15:0] rx2_data_q;
wire [15:0] rx3_data_i;
wire [15:0] rx3_data_q;
wire [15:0] tx1_data_i;
wire [15:0] tx1_data_q;
wire [15:0] tx2_data_i;
wire [15:0] tx2_data_q;
wire tx_data_ready;
wire tx_data_ready2;
wire cx9261a_data_clk;
wire cx9261a_data_valid;
wire cx9261a_data_clk2;
wire cx9261a_data_valid2;
wire cx9261a_data_clk3;
wire cx9261a_data_valid3;
wire [15:0] cx9261a_rx1_data_i;
wire [15:0] cx9261a_rx1_data_q;
wire [15:0] cx9261a_rx2_data_i;
wire [15:0] cx9261a_rx2_data_q;
wire [15:0] cx9261a_rx3_data_i;
wire [15:0] cx9261a_rx3_data_q;
wire [15:0] cx9261a_tx1_data_i;
wire [15:0] cx9261a_tx1_data_q;
wire [15:0] cx9261a_tx2_data_i;
wire [15:0] cx9261a_tx2_data_q;
wire cx9261a_tx_data_ready;
wire cx9261a_tx_data_ready2;
wire cx9261a_mclk1;
wire cx9261a_mclk2;
@@ -251,24 +251,24 @@ cx9261a_if cx9261a_if_cmos
.tdd_fdd_sel (cx9261a_tdd_fdd_sel ), // PS GPIO控制 tdd:1; fdd:0 保持芯片接口模式配置一致;
.r1t1_r2t2_sel (cx9261a_r1t1_r2t2_sel ), // PS GPIO控制 r2t2:1; r1t1:0 保持芯片接口模式配置一致;
//基带数据接口
.data_clk (data_clk ), // f(data_clk) = f(RX1_MCLK_IN_N);
.data_valid (data_valid ), // 任一接口模式下，data_valid可使rx1_i/q_data数据速率和ADC1采样率（无抽取）保持一致
.data_clk2 (data_clk2 ), // f(data_clk2) = f(RX2_MCLK_IN_P);
.data_valid2 (data_valid2 ), // 任一接口模式下，data_valid2可使rx2_i/q_data数据速率和ADC2采样率（无抽取）保持一致
.data_clk3 (data_clk3 ), // f(data_clk3) = f(RXFB_MCLK_IN);
.data_valid3 (data_valid3 ), // 任一接口模式下，data_valid3可使rx3_i/q_data数据速率和ADC3采样率（无抽取）保持一致
.rx1_i_data (rx1_data_i ), // \----------------------------------------------------------------------------------------
.rx1_q_data (rx1_data_q ), // \eg.：fadc = 64MSPS,fdac = 256MSPS,dac采样率固定是dac采样率的4倍。
.rx2_i_data (rx2_data_i ), // \发射数字插值倍数保持是接收数字抽取倍数4倍,则基带接收数据速率等于发射数据速率。
.rx2_q_data (rx2_data_q ), // \在FDD/singleport/r1t1、TDD/singleport/r2t2、FDD/dualport/r2t2三种数据接口模式下，
.rx3_i_data (rx3_data_i ), // \数据随路时钟MCLK fmclk = 2 * fadc，其余接口模式 fmclk = 2 * fadc。
.rx3_q_data (rx3_data_q ), // \rx1/2/3_i/q_data数据 和 tx1/2_i/q_data数据 对应处于 data_clk/2/3（速率等于MCLK）时钟域
.tx1_i_data (tx1_data_i ), // \为了保证基带接收数据速率等于发射数据速率,在上述三种三种数据接口模式下
.tx1_q_data (tx1_data_q ), // \data_valid/2/3实际是data_clk/2的两分频，其余接口模式 tx_data_ready常高;
.tx2_i_data (tx2_data_i ), // \tx_data_ready实际是data_clk/2的两分频，其余接口模式 tx_data_ready常高。
.tx2_q_data (tx2_data_q ), // \----------------------------------------------------------------------------------------
.tx_data_ready (tx_data_ready ), // 任一接口模式下，tx_data_ready可使tx1_i/q_data数据速率（4倍插值后）和DAC1采样率保持一致
.tx_data_ready2 (tx_data_ready2 ), // 任一接口模式下，tx_data_ready2可使tx2_i/q_data数据速率（4倍插值后）和DAC2采样率保持一致
.data_clk (cx9261a_data_clk ), // f(data_clk) = f(RX1_MCLK_IN_N);
.data_valid (cx9261a_data_valid ), // 任一接口模式下，data_valid可使rx1_i/q_data数据速率和ADC1采样率（无抽取）保持一致
.data_clk2 (cx9261a_data_clk2 ), // f(data_clk2) = f(RX2_MCLK_IN_P);
.data_valid2 (cx9261a_data_valid2 ), // 任一接口模式下，data_valid2可使rx2_i/q_data数据速率和ADC2采样率（无抽取）保持一致
.data_clk3 (cx9261a_data_clk3 ), // f(data_clk3) = f(RXFB_MCLK_IN);
.data_valid3 (cx9261a_data_valid3 ), // 任一接口模式下，data_valid3可使rx3_i/q_data数据速率和ADC3采样率（无抽取）保持一致
.rx1_i_data (cx9261a_rx1_data_i ), // \----------------------------------------------------------------------------------------
.rx1_q_data (cx9261a_rx1_data_q ), // \eg.：fadc = 64MSPS,fdac = 256MSPS,dac采样率固定是dac采样率的4倍。
.rx2_i_data (cx9261a_rx2_data_i ), // \发射数字插值倍数保持是接收数字抽取倍数4倍,则基带接收数据速率等于发射数据速率。
.rx2_q_data (cx9261a_rx2_data_q ), // \在FDD/singleport/r1t1、TDD/singleport/r2t2、FDD/dualport/r2t2三种数据接口模式下，
.rx3_i_data (cx9261a_rx3_data_i ), // \数据随路时钟MCLK fmclk = 2 * fadc，其余接口模式 fmclk = 2 * fadc。
.rx3_q_data (cx9261a_rx3_data_q ), // \rx1/2/3_i/q_data数据 和 tx1/2_i/q_data数据 对应处于 data_clk/2/3（速率等于MCLK）时钟域
.tx1_i_data (cx9261a_tx1_data_i ), // \为了保证基带接收数据速率等于发射数据速率,在上述三种三种数据接口模式下
.tx1_q_data (cx9261a_tx1_data_q ), // \data_valid/2/3实际是data_clk/2的两分频，其余接口模式 tx_data_ready常高;
.tx2_i_data (cx9261a_tx2_data_i ), // \tx_data_ready实际是data_clk/2的两分频，其余接口模式 tx_data_ready常高。
.tx2_q_data (cx9261a_tx2_data_q ), // \----------------------------------------------------------------------------------------
.tx_data_ready (cx9261a_tx_data_ready ), // 任一接口模式下，tx_data_ready可使tx1_i/q_data数据速率（4倍插值后）和DAC1采样率保持一致
.tx_data_ready2 (cx9261a_tx_data_ready2 ), // 任一接口模式下，tx_data_ready2可使tx2_i/q_data数据速率（4倍插值后）和DAC2采样率保持一致
//芯片数据接口 \----------------------------------------------------------------------------------------
.RX1_FRAME_N (cx9261a_rx1_frame ), // \争对客户板上数据时序异常情况，可通过IDELAYE2原语对RX1_MCLK_IN_N进行延时调节，其输出为MCLK1；
.RX1_MCLK_IN_N (cx9261a_mclk1 ), // \RX2_MCLK_IN_P延时调节，其输出为MCLK2；RXFB_MCLK_IN延时调节，其输出为MCLK3。
@@ -293,56 +293,110 @@ cx9261a_if cx9261a_if_cmos
// <--------------------------------------------------------------------------->
// <--------------------- insert transmitter logic below ---------------------->
// <--------------------------------------------------------------------------->
wire [ 1:0] waveform_sel_1;
wire sweep_on_1 ;
wire [31:0] freq_set_1 ;
wire [ 1:0] iq_sel_1 ;
wire [ 3:0] bb_rshift_1 ;
wire sys_clk_64M;
wire sys_clk_48M;
wire sys_rstn;
tx_qpsk #(
.BIT_DATA (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001),
.BIT_DATA_LEN (1024),
sys_clk_gen u_sys_clk_gen
(
// Clock out ports
.clk_out1 (sys_clk_64M ), // output clk_out1
.clk_out2 (sys_clk_48M ), // output clk_out2
// Status and control signals
.locked (sys_rstn ), // output locked
// Clock in ports
.clk_in1 (cx9261a_data_clk ) // input clk_in1
);
wire [15:0] tx_data_i, tx_data_q;
wire [1:0] waveform_sel;
wire sweep_on;
wire [31:0] freq_set;
wire [1:0] iq_sel;
wire [3:0] bb_rshift;
tx_qpsk_v1 #(
.BIT_DATA (1023'b000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001),
.BIT_DATA_LEN (1023),
.CLK_FREQ (48000000),
.DATA_WIDTH (16)
) u_tx1_qpsk
(
.clk (data_clk ), // input clk
.rst (1'b0 ), // input rst
.tx_data_i (tx1_data_i ), // output [11:0] tx_data_i
.tx_data_q (tx1_data_q ), // output [11:0] tx_data_q
.clk (sys_clk_64M ), // input clk
.rst (~sys_rstn ), // input rst
.tx_data_i (tx_data_i ), // output [11:0] tx_data_i
.tx_data_q (tx_data_q ), // output [11:0] tx_data_q
// debug ports
.waveform_sel (waveform_sel_1[1:0]), // input [ 1:0] waveform_sel
.sweep_on (sweep_on_1 ), // input sweep_on
.freq_set (freq_set_1 ), // input [31:0] freq_set
.iq_sel (iq_sel_1 ), // input [ 1:0] iq_sel
.bb_rshift (bb_rshift_1 ) // input [ 3:0] bb_rshift
.waveform_sel (waveform_sel ), // input [ 1:0] waveform_sel
.sweep_on (sweep_on ), // input sweep_on
.freq_set (freq_set ), // input [31:0] freq_set
.iq_sel (iq_sel ), // input [ 1:0] iq_sel
.bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift
);
wire [ 1:0] waveform_sel_2;
wire sweep_on_2 ;
wire [31:0] freq_set_2 ;
wire [ 1:0] iq_sel_2 ;
wire [ 3:0] bb_rshift_2 ;
tx_qpsk #(
.BIT_DATA (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001),
.BIT_DATA_LEN (1024),
.CLK_FREQ (48000000),
.DATA_WIDTH (16)
) u_tx2_qpsk
cx9261a_fifo cx9261a_fifo_tx1
(
.clk (data_clk2 ), // input clk
.rst (1'b0 ), // input rst
.tx_data_i (tx2_data_i ), // output [11:0] tx_data_i
.tx_data_q (tx2_data_q ), // output [11:0] tx_data_q
// debug ports
.waveform_sel (waveform_sel_2[1:0]), // input [ 1:0] waveform_sel
.sweep_on (sweep_on_2 ), // input sweep_on
.freq_set (freq_set_2 ), // input [31:0] freq_set
.iq_sel (iq_sel_2 ), // input [ 1:0] iq_sel
.bb_rshift (bb_rshift_2 ) // input [ 3:0] bb_rshift
.wr_clk (sys_clk_64M ), // input wire wr_clk
.rd_clk (cx9261a_data_clk ), // input wire rd_clk
.din ({tx_data_q,tx_data_i} ), // input wire [15 : 0] din
.wr_en (1'b1 ), // input wire wr_en
.rd_en (cx9261a_tx_data_ready ), // input wire rd_en
.dout ({cx9261a_tx1_data_q,cx9261a_tx1_data_i}), // output wire [15 : 0] dout
.full ( ), // output wire full
.empty ( ) // output wire empty
);
cx9261a_fifo cx9261a_fifo_tx2
(
.wr_clk (sys_clk_64M ), // input wire wr_clk
.rd_clk (cx9261a_data_clk2 ), // input wire rd_clk
.din ({tx_data_q,tx_data_i} ), // input wire [15 : 0] din
.wr_en (1'b1 ), // input wire wr_en
.rd_en (cx9261a_tx_data_ready2 ), // input wire rd_en
.dout ({cx9261a_tx2_data_q,cx9261a_tx2_data_i}), // output wire [15 : 0] dout
.full ( ), // output wire full
.empty ( ) // output wire empty
);
wire [15:0] rx1_data_i, rx1_data_q;
wire [15:0] rx2_data_i, rx2_data_q;
wire [15:0] rx3_data_i, rx3_data_q;
cx9261a_fifo cx9261a_fifo_rx1
(
.wr_clk (cx9261a_data_clk ), // input wire wr_clk
.rd_clk (sys_clk_64M ) , // input wire rd_clk
.din ({cx9261a_rx1_data_q,cx9261a_rx1_data_i}), // input wire [15 : 0] din
.wr_en (cx9261a_data_valid ), // input wire wr_en
.rd_en (1'b1 ), // input wire rd_en
.dout ({rx1_data_q,rx1_data_i} ), // output wire [15 : 0] dout
.full ( ), // output wire full
.empty ( ) // output wire empty
);
cx9261a_fifo cx9261a_fifo_rx2
(
.wr_clk (cx9261a_data_clk2 ), // input wire wr_clk
.rd_clk (sys_clk_64M ) , // input wire rd_clk
.din ({cx9261a_rx2_data_q,cx9261a_rx2_data_i}), // input wire [15 : 0] din
.wr_en (cx9261a_data_valid2 ), // input wire wr_en
.rd_en (1'b1 ), // input wire rd_en
.dout ({rx2_data_q,rx2_data_i} ), // output wire [15 : 0] dout
.full ( ), // output wire full
.empty ( ) // output wire empty
);
cx9261a_fifo cx9261a_fifo_rx3
(
.wr_clk (cx9261a_data_clk3 ), // input wire wr_clk
.rd_clk (sys_clk_64M ) , // input wire rd_clk
.din ({cx9261a_rx3_data_q,cx9261a_rx3_data_i}), // input wire [15 : 0] din
.wr_en (cx9261a_data_valid3 ), // input wire wr_en
.rd_en (1'b1 ), // input wire rd_en
.dout ({rx3_data_q,rx3_data_i} ), // output wire [15 : 0] dout
.full ( ), // output wire full
.empty ( ) // output wire empty
);
////////////////////////////////////////////////////////////////////////////////
////////////////////////////// Simple Hop Control //////////////////////////////
@@ -357,79 +411,57 @@ reg hop_trig_d = 'b0;
assign hop_flag = hop_flag_buf;
always @(posedge data_clk) begin
hop_trig_d <= hop_trig;
if (hop_en) begin
hop_cnt <= (hop_cnt == hop_inter) ? 'b0 : hop_cnt + 1'b1;
hop_flag_buf <= (hop_cnt == hop_inter) ? ~hop_flag_buf : hop_flag_buf;
always @(posedge sys_clk_64M or negedge sys_rstn) begin
if (!sys_rstn) begin
hop_cnt <= 'b0;
hop_flag_buf <= 'b0;
hop_trig_d <= 'b0;
end
else begin
hop_cnt <= 'b0;
hop_flag_buf <= (hop_trig_d & ~hop_trig) ? ~hop_flag_buf : hop_flag_buf;
hop_trig_d <= hop_trig;
if (hop_en) begin
hop_cnt <= (hop_cnt >= hop_inter - 1) ? 'b0 : hop_cnt + 1'b1;
hop_flag_buf <= (hop_cnt == hop_inter - 1) ? ~hop_flag_buf : hop_flag_buf;
end
else begin
hop_cnt <= 'b0;
hop_flag_buf <= (hop_trig_d & ~hop_trig) ? ~hop_flag_buf : hop_flag_buf;
end
end
end
////////////////////////////////////////////////////////////////////////////////
//////////////////////////////// ILAs and VIOs /////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
vio_hop u_vio_hop (
.clk (data_clk ), // input wire clk
vio_hop u_vio_hop
(
.clk (sys_clk_64M), // input wire clk
.probe_out0 (hop_inter ), // output wire [31 : 0] probe_out0
.probe_out1 (hop_en ), // output wire [0 : 0] probe_out1
.probe_out2 (hop_trig ) // output wire [0 : 0] probe_out2
);
ila_trx u_ila_trx1
ila_trx u_ila_trx
(
.clk (data_clk ), // input wire clk
.probe0 (data_valid ), // input wire [0:0] probe0
.probe1 (rx1_data_i ), // input wire [11:0] probe1
.probe2 (rx1_data_q ), // input wire [11:0] probe2
.probe3 (tx_data_ready ), // input wire [0:0] probe3
.probe4 (tx1_data_i ), // input wire [11:0] probe4
.probe5 (tx1_data_q ), // input wire [11:0] probe5
.probe6 (hop_flag ) // input wire [0:0] probe6
.clk (sys_clk_64M), // input wire clk
.probe0 (hop_flag ), // input wire [15:0] probe0
.probe1 (tx_data_i ), // input wire [15:0] probe1
.probe2 (tx_data_q ), // input wire [15:0] probe2
.probe3 (rx1_data_i ), // input wire [15:0] probe3
.probe4 (rx1_data_q ), // input wire [15:0] probe4
.probe5 (rx2_data_i ), // input wire [15:0] probe5
.probe6 (rx2_data_q ) // input wire [15:0] probe6
);
ila_trx u_ila_trx2
vio_manual_ctrl u_vio_manual_ctrl
(
.clk (data_clk2 ), // input wire clk
.probe0 (data_valid2 ), // input wire [0:0] probe0
.probe1 (rx2_data_i ), // input wire [11:0] probe1
.probe2 (rx2_data_q ), // input wire [11:0] probe2
.probe3 (tx_data_ready2 ), // input wire [0:0] probe3
.probe4 (tx2_data_i ), // input wire [11:0] probe4
.probe5 (tx2_data_q ), // input wire [11:0] probe5
.probe6 (hop_flag ) // input wire [0:0] probe6
);
ila_trx_fb u_ila_rx_fb
(
.clk (data_clk3 ), // input wire clk
.probe0 (data_valid3), // input wire [0:0] probe0
.probe1 (rx3_data_i ), // input wire [11:0] probe1
.probe2 (rx3_data_q ) // input wire [11:0] probe2
);
vio_manual_ctrl u_vio_manual_ctrl_1
(
.clk (data_clk ), // input wire clk
.probe_out0 (waveform_sel_1 ), // output wire [1 : 0] probe_out0
.probe_out1 (sweep_on_1 ), // output wire [0 : 0] probe_out1
.probe_out2 (freq_set_1 ), // output wire [31 : 0] probe_out2
.probe_out3 (iq_sel_1 ), // output wire [1 : 0] probe_out3
.probe_out4 (bb_rshift_1 ) // output wire [3 : 0] probe_out4
);
vio_manual_ctrl u_vio_manual_ctrl_2
(
.clk (data_clk2 ), // input wire clk
.probe_out0 (waveform_sel_2 ), // output wire [1 : 0] probe_out0
.probe_out1 (sweep_on_2 ), // output wire [0 : 0] probe_out1
.probe_out2 (freq_set_2 ), // output wire [31 : 0] probe_out2
.probe_out3 (iq_sel_2 ), // output wire [1 : 0] probe_out3
.probe_out4 (bb_rshift_2 ) // output wire [3 : 0] probe_out4
.clk (sys_clk_64M ), // input wire clk
.probe_out0 (waveform_sel ), // output wire [1 : 0] probe_out0
.probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1
.probe_out2 (freq_set ), // output wire [31 : 0] probe_out2
.probe_out3 (iq_sel ), // output wire [1 : 0] probe_out3
.probe_out4 (bb_rshift ) // output wire [3 : 0] probe_out4
);
endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/new/tx_qpsk_v1.v
+523
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@@ -0,0 +1,523 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// _ _ ____
// | | ___ ___| |__ / ___| __ _ ___
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
// \___/ \___/|___/_| |_| \____|\__,_|\___/
//
// Create Date: 2022/03/23 20:17:56
// Last Modified Date: 2023/03/10 15:41
// Design Name:
// Module Name: tx_qpsk
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// 20230228-1541 - 修改不扫频、无基带频偏时 [baseband_i/q] 的数据输出，原来从
// 乘法器引出，会导致频率为 0 时输出数据错误，现在直接从基带数据引出。
// 20230310-1542 - 增加输入参数，发送数据更改为直接由参数输入，发送方波改为 8
// 倍过采样，发送双音信号中 1MHz 信号的频率控制字可以根据参数中的时钟频率计
// 算得出。
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tx_qpsk_v1
#(
parameter DATA_WIDTH = 12, // need to be <= 16
parameter BIT_DATA = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)]
parameter BIT_DATA_LEN = 128,
parameter SQUARE_INTERP = 1,
parameter CLK_FREQ = 245760000 // in Hertz
)
(
input clk ,
input rst ,
output [DATA_WIDTH-1:0] tx_data_i ,
output [DATA_WIDTH-1:0] tx_data_q ,
// debug ports
input [ 1:0] waveform_sel ,
input sweep_on ,
input [31:0] freq_set ,
input [ 1:0] iq_sel ,
input [ 3:0] bb_rshift
);
localparam RCOS_INTERP = 1;
localparam INTERP = (RCOS_INTERP > SQUARE_INTERP) ? RCOS_INTERP : SQUARE_INTERP;
localparam FREQ_WORD_1M = 64'd2**64'd32*64'd1000000/CLK_FREQ;
////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// Data Counter /////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// symbol & interpolation counter
reg [$clog2(INTERP*BIT_DATA_LEN)-1 : 0] cnt = 'b0;
always @(posedge clk) begin
if (rst) begin
cnt <= 'b0;
end
else begin
cnt <= (cnt == INTERP*BIT_DATA_LEN - 1) ? 'b0 : cnt + 16'b1;
end
end
////////////////////////////////////////////////////////////////////////////////
////////////////////// Root-Rasied Cosine Shaping Filter ///////////////////////
////////////////////////////////////////////////////////////////////////////////
// address
reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_i = 'b0;
reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_q = 'b1;
always @(posedge clk) begin
if (rst) begin
hrc_data_addr_i <= 'b0;
hrc_data_addr_q <= 'b1;
end
else begin
hrc_data_addr_i <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b0};
hrc_data_addr_q <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b1};
end
end
// bit data
reg hrc_data_i = 'b0;
reg hrc_data_q = 'b0;
always @(posedge clk) begin
if (rst) begin
hrc_data_i <= 'b0;
hrc_data_q <= 'b0;
end
else begin
hrc_data_i <= BIT_DATA[hrc_data_addr_i];
hrc_data_q <= BIT_DATA[hrc_data_addr_q];
end
end
// polarization
wire [ 7:0] hrc_data_polar_i;
wire [ 7:0] hrc_data_polar_q;
assign hrc_data_polar_i = {{7{hrc_data_i}},1'b1};
assign hrc_data_polar_q = {{7{hrc_data_q}},1'b1};
/* // root raised cosine shaping-filter
wire [23:0] hrc_wave_i;
wire [23:0] hrc_wave_q;
hrc_64_12_025 u_hrc_i (
.aclk (clk ), // input wire aclk
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
.s_axis_data_tready ( ), // output wire s_axis_data_tready
.s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (hrc_wave_i ) // output wire [23 : 0] m_axis_data_tdata
);
hrc_64_12_025 u_hrc_q (
.aclk (clk ), // input wire aclk
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
.s_axis_data_tready ( ), // output wire s_axis_data_tready
.s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (hrc_wave_q ) // output wire [23 : 0] m_axis_data_tdata
); */
wire [23:0] hrc_wave_i_48;
wire [23:0] hrc_wave_q_48;
hrc_4_12_03 i_hrc_4_12_03 (
.aclk (clk ), // input wire aclk
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
.s_axis_data_tready ( ), // output wire s_axis_data_tready
.s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (hrc_wave_i_48 ) // output wire [23 : 0] m_axis_data_tdata
);
hrc_4_12_03 q_hrc_4_12_03 (
.aclk (clk ), // input wire aclk
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
.s_axis_data_tready ( ), // output wire s_axis_data_tready
.s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (hrc_wave_q_48 ) // output wire [23 : 0] m_axis_data_tdata
);
wire [23:0] hrc_wave_i_12;
wire [23:0] hrc_wave_q_12;
hrc_16_12_03 i_hrc_16_12_03 (
.aclk (clk ), // input wire aclk
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
.s_axis_data_tready ( ), // output wire s_axis_data_tready
.s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (hrc_wave_i_12 ) // output wire [23 : 0] m_axis_data_tdata
);
hrc_16_12_03 q_hrc_16_12_03 (
.aclk (clk ), // input wire aclk
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
.s_axis_data_tready ( ), // output wire s_axis_data_tready
.s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (hrc_wave_q_12 ) // output wire [23 : 0] m_axis_data_tdata
);
wire [23:0] hrc_wave_i_1p5;
wire [23:0] hrc_wave_q_1p5;
hrc_128_12_03 i_hrc_128_12_03 (
.aclk (clk ), // input wire aclk
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
.s_axis_data_tready ( ), // output wire s_axis_data_tready
.s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (hrc_wave_i_1p5 ) // output wire [23 : 0] m_axis_data_tdata
);
hrc_128_12_03 q_hrc_128_12_03 (
.aclk (clk ), // input wire aclk
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
.s_axis_data_tready ( ), // output wire s_axis_data_tready
.s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (hrc_wave_q_1p5 ) // output wire [23 : 0] m_axis_data_tdata
);
////////////////////////////////////////////////////////////////////////////////
///////////////////// Waveform Selection & Hopping Control /////////////////////
////////////////////////////////////////////////////////////////////////////////
// baseband signal select
reg [17:0] baseband_sel_i = 'b0;
reg [17:0] baseband_sel_q = 'b0;
always @(posedge clk) begin
if (rst) begin
baseband_sel_i <= 'b0;
baseband_sel_q <= 'b0;
end
else begin
case (waveform_sel[1:0])
2'd0: begin
baseband_sel_i <= {hrc_wave_i_48[16:0],1'b0};
baseband_sel_q <= {hrc_wave_q_48[16:0],1'b0};
end
2'd1: begin
baseband_sel_i <= {hrc_wave_i_12[16:0],1'b0};
baseband_sel_q <= {hrc_wave_q_12[16:0],1'b0};
end
2'd2: begin
baseband_sel_i <= {hrc_wave_i_1p5[16:0],1'b0};
baseband_sel_q <= {hrc_wave_q_1p5[16:0],1'b0};
end
2'd3: begin
baseband_sel_i <= 18'b01_1111_1111_1111_1111;
baseband_sel_q <= 18'b0;
end
default: begin
baseband_sel_i <= {hrc_wave_i_48[16:0],1'b0};
baseband_sel_q <= {hrc_wave_q_48[16:0],1'b0};
end
endcase
end
end
// hopping control, 3750hop/s
reg [23:0] sweep_rom_addr = 'b0;
wire [31:0] freq_sweep;
always @(posedge clk) begin
if (rst) begin
sweep_rom_addr <= 'b0;
end
else if (sweep_on) begin
sweep_rom_addr <= sweep_rom_addr + 24'b1;
end
else begin
sweep_rom_addr <= 'b0;
end
end
hop_rom u_sweep_rom
(
.clka (clk ), // input wire clka
.addra (sweep_rom_addr[23:16] ), // input wire [7 : 0] addra
.douta (freq_sweep ) // output wire [31 : 0] douta
);
// choose the actual frequency word
reg [31:0] freq_word = 'b0;
always @(posedge clk) begin
if (rst) begin
freq_word <= 'b0;
end
else if (sweep_on) begin
// frequency sweep
freq_word <= freq_sweep;
end
else begin
// normal operation
freq_word <= freq_set;
end
end
// baseband frequency shift carrier generation
wire [ 7:0] cos_dds;
wire [ 7:0] sin_dds;
reg [ 7:0] cos = 'b0;
reg [ 7:0] sin = 'b0;
dds_32b_8b u_dds_bb_shift (
.aclk (clk ), // input wire aclk
.s_axis_config_tvalid (~rst ), // input wire s_axis_config_tvalid
.s_axis_config_tdata (freq_word ), // input wire [31 : 0] s_axis_config_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata ({sin_dds,cos_dds}) // output wire [31 : 0] m_axis_data_tdata
);
always @(posedge clk) begin
if (rst) begin
cos <= 'b0;
sin <= 'b0;
end
else if (freq_word == 'b0) begin
// to make sure the carriers stay at the right position when freq = 0
cos <= 8'b0111_1111;
sin <= 8'b0111_1111;
end
else begin
cos <= cos_dds;
sin <= sin_dds;
end
end
// baseband frequency shift modulation
wire [47:0] mod_cmpy_a;
wire [15:0] mod_cmpy_b;
wire [63:0] mod_cmpy_out;
wire [26:0] baseband_mult_i;
wire [26:0] baseband_mult_q;
assign mod_cmpy_a = {6'b0,baseband_sel_q,6'b0,baseband_sel_i};
assign mod_cmpy_b = {-sin,cos};
assign baseband_mult_i = mod_cmpy_out[58:32];
assign baseband_mult_q = mod_cmpy_out[26: 0];
cmpy_18x8 u_cmpy_18x8
(
.aclk (clk ), // input wire aclk
.s_axis_a_tvalid (1'b1 ), // input wire s_axis_a_tvalid
.s_axis_a_tdata (mod_cmpy_a ), // input wire [47 : 0] s_axis_a_tdata
.s_axis_b_tvalid (1'b1 ), // input wire s_axis_b_tvalid
.s_axis_b_tdata (mod_cmpy_b ), // input wire [15 : 0] s_axis_b_tdata
.m_axis_dout_tvalid ( ), // output wire m_axis_dout_tvalid
.m_axis_dout_tdata (mod_cmpy_out ) // output wire [63 : 0] m_axis_dout_tdata
);
// truncate to 16-bit
reg signed [15:0] baseband_i = 'b0;
reg signed [15:0] baseband_q = 'b0;
always @(posedge clk) begin
if (rst) begin
baseband_i <= 'b0;
baseband_q <= 'b0;
end
else begin
case (waveform_sel[1:0])
2'd0: begin
// scale rasied-cosine-shaped bpsk signal by 1.125 or 1.625
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[25:10];
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[25:10];
end
2'd1: begin
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[25:10];
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[25:10];
end
2'd2: begin
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[25:10];
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[25:10];
end
2'd3: begin
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[24:9];
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[24:9];
end
default: begin
// scale rasied-cosine-shaped bpsk signal by 1.125
baseband_i <= baseband_mult_i[25:10];
baseband_q <= baseband_mult_q[25:10];
end
endcase
end
end
// iq selection & baseband right shift
reg signed [15:0] baseband_data_i = 'b0;
reg signed [15:0] baseband_data_q = 'b0;
always @(posedge clk) begin
if (rst) begin
baseband_data_i <= 'b0;
baseband_data_q <= 'b0;
end
else begin
// inphase selection
if (iq_sel[1]) begin
baseband_data_i <= baseband_i >>> bb_rshift;
end
else begin
baseband_data_i <= 'b0;
end
// quadrature selection
if (iq_sel[0]) begin
baseband_data_q <= baseband_q >>> bb_rshift;
end
else begin
baseband_data_q <= 'b0;
end
end
end
// output data to ports
assign tx_data_i = baseband_data_i[15 -: DATA_WIDTH];
assign tx_data_q = baseband_data_q[15 -: DATA_WIDTH];
endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2020/12/08 12:43:46
// Design Name:
// Module Name: tb_tx_qpsk
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// module tb_tx_qpsk;
// reg clk = 1'b0 ;
// reg rst = 1'b1 ;
// reg tx_on = 1'b1 ;
// reg [31:0] freq_set ;
// reg [ 1:0] waveform_sel = 2'b00;
// reg [ 1:0] iq_sel = 2'b11 ;
// wire [11:0] tx_data_i ;
// wire [11:0] tx_data_q ;
// reg [ 3:0] bb_rshift = 5'b0 ;
// tx_qpsk u_tx_qpsk
// (
// .clk (clk ),
// .rst (rst ),
// .tx_data_i (tx_data_i ),
// .tx_data_q (tx_data_q ),
// .waveform_sel (waveform_sel ),
// .sweep_on (1'b0 ),
// // .freq_set (32'd447392426 ),
// .freq_set (32'd0 ),
// .iq_sel (iq_sel ),
// .bb_rshift (bb_rshift )
// );
// initial begin
// #102
// rst = 1'b0;
// // freq_set = 32'd873813333;
// // waveform_sel = 2'b00;
// // bb_rshift = 5'd0;
// // #5000
// // bb_rshift = 5'd1;
// // #5000
// // bb_rshift = 5'd2;
// // #5000
// // bb_rshift = 5'd3;
// // #5000
// // bb_rshift = 5'd4;
// // #5000
// // bb_rshift = 5'd5;
// // #5000
// // bb_rshift = 5'd6;
// // #5000
// // bb_rshift = 5'd7;
// // #5000
// // bb_rshift = 5'd8;
// // #5000
// // bb_rshift = 5'd9;
// // #5000
// // bb_rshift = 5'd14;
// // #5000
// // bb_rshift = 5'd15;
// // #5000
// // bb_rshift = 5'd16;
// // freq_set = 32'd0;
// // func_sel = 3'b010;
// // #7777
// // freq_set = 32'd536870912;
// // func_sel = 3'b100;
// // #7777
// // freq_set = 32'd0;
// // func_sel = 3'b100;
// // #7777
// // freq_set = 32'd536870912;
// // func_sel = 3'b010;
// // #7777
// // freq_set = 32'd0;
// // func_sel = 3'b010;
// // freq_set = 32'd536870912;
// // iq_sel = 2'b00;
// // #7777
// // freq_set = 32'd536870912;
// // iq_sel = 2'b01;
// // #7777
// // freq_set = 32'd536870912;
// // iq_sel = 2'b10;
// // #7777
// // freq_set = 32'd536870912;
// // iq_sel = 2'b11;
// end
// always #5 clk = ~clk;
// // integer i;
// // integer w_file;
// // initial begin
// // w_file = $fopen("D:\\qpsk_josh.txt","w");
// // for (i = 0; i <= 35000; i = i + 1) begin
// // wait(clk);
// // #10;
// // $fdisplay(w_file,"%d %d",$signed(tx_data_i),
// // $signed(tx_data_q));
// // if (i == 35000) begin
// // $fclose(w_file);
// // $stop;
// // end
// // end
// // end
// endmodule
zc706_cx9261a_demo/zc706_cx9261a_demo.xpr
+301 -174
View File
@@ -67,13 +67,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="28"/>
<Option Name="WTModelSimExportSim" Val="28"/>
<Option Name="WTQuestaExportSim" Val="28"/>
<Option Name="WTXSimExportSim" Val="39"/>
<Option Name="WTModelSimExportSim" Val="39"/>
<Option Name="WTQuestaExportSim" Val="39"/>
<Option Name="WTIesExportSim" Val="27"/>
<Option Name="WTVcsExportSim" Val="28"/>
<Option Name="WTRivieraExportSim" Val="28"/>
<Option Name="WTActivehdlExportSim" Val="28"/>
<Option Name="WTVcsExportSim" Val="39"/>
<Option Name="WTRivieraExportSim" Val="39"/>
<Option Name="WTActivehdlExportSim" Val="39"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@@ -97,9 +97,6 @@
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci">
<Proxy FileSetName="system_bd_auto_pc_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci">
<Proxy FileSetName="system_bd_axi_spi_engine_0_0"/>
</CompFileExtendedInfo>
@@ -112,6 +109,9 @@
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_spi_engine_execution_0_1/system_bd_spi_engine_execution_0_1.xci">
<Proxy FileSetName="system_bd_spi_engine_execution_0_1"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_system_ila_0_0/system_bd_system_ila_0_0.xci">
<Proxy FileSetName="system_bd_system_ila_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_xadc_wiz_0_0/system_bd_xadc_wiz_0_0.xci">
<Proxy FileSetName="system_bd_xadc_wiz_0_0"/>
</CompFileExtendedInfo>
@@ -154,7 +154,7 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/tx_qpsk.v">
<File Path="$PSRCDIR/sources_1/new/tx_qpsk_v1.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
@@ -168,6 +168,14 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/tx_qpsk.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/ip/coe/sweep_freq.coe">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -180,6 +188,24 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/ip/coe/hrc_16_12_03.coe">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/ip/coe/hrc_128_12_03.coe">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/ip/coe/hrc_4_12_03.coe">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="system_top"/>
@@ -221,12 +247,6 @@
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="system_bd_axi_spi_engine_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_axi_spi_engine_0_0" RelGenDir="$PGENDIR/system_bd_axi_spi_engine_0_0">
<Config>
<Option Name="TopModule" Val="system_bd_axi_spi_engine_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_processing_system7_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_processing_system7_0_0" RelGenDir="$PGENDIR/system_bd_processing_system7_0_0">
<Config>
<Option Name="TopModule" Val="system_bd_processing_system7_0_0"/>
@@ -313,6 +333,7 @@
<FileSet Name="hrc_64_12_025" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hrc_64_12_025" RelGenDir="$PGENDIR/hrc_64_12_025">
<File Path="$PSRCDIR/sources_1/ip/hrc_64_12_025/hrc_64_12_025.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -349,19 +370,6 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="ila_trx_fb" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_trx_fb" RelGenDir="$PGENDIR/ila_trx_fb">
<File Path="$PSRCDIR/sources_1/ip/ila_trx_fb/ila_trx_fb.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="ila_trx_fb"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="vio_mode_sel" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_mode_sel" RelGenDir="$PGENDIR/vio_mode_sel">
<File Path="$PSRCDIR/sources_1/ip/vio_mode_sel/vio_mode_sel.xci">
<FileInfo>
@@ -400,9 +408,80 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_auto_pc_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_auto_pc_0" RelGenDir="$PGENDIR/system_bd_auto_pc_0">
<FileSet Name="hrc_4_12_03" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hrc_4_12_03" RelGenDir="$PGENDIR/hrc_4_12_03">
<File Path="$PSRCDIR/sources_1/ip/hrc_4_12_03/hrc_4_12_03.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="system_bd_auto_pc_0"/>
<Option Name="TopModule" Val="hrc_4_12_03"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="hrc_16_12_03" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hrc_16_12_03" RelGenDir="$PGENDIR/hrc_16_12_03">
<File Path="$PSRCDIR/sources_1/ip/hrc_16_12_03/hrc_16_12_03.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="hrc_16_12_03"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="hrc_128_12_03" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hrc_128_12_03" RelGenDir="$PGENDIR/hrc_128_12_03">
<File Path="$PSRCDIR/sources_1/ip/hrc_128_12_03/hrc_128_12_03.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="hrc_128_12_03"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="cx9261a_fifo" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cx9261a_fifo" RelGenDir="$PGENDIR/cx9261a_fifo">
<File Path="$PSRCDIR/sources_1/ip/cx9261a_fifo/cx9261a_fifo.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="cx9261a_fifo"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="sys_clk_gen" Type="BlockSrcs" RelSrcDir="$PSRCDIR/sys_clk_gen" RelGenDir="$PGENDIR/sys_clk_gen">
<File Path="$PSRCDIR/sources_1/ip/sys_clk_gen/sys_clk_gen.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="sys_clk_gen"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_system_ila_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_system_ila_0_0" RelGenDir="$PGENDIR/system_bd_system_ila_0_0">
<Config>
<Option Name="TopModule" Val="system_bd_system_ila_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_axi_spi_engine_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_axi_spi_engine_0_0" RelGenDir="$PGENDIR/system_bd_axi_spi_engine_0_0">
<Config>
<Option Name="TopModule" Val="system_bd_axi_spi_engine_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
@@ -430,18 +509,6 @@
</Simulators>
<Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z045ffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_axi_spi_engine_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_axi_spi_engine_0_0" Part="xc7z045ffg900-2" ConstrsSet="system_bd_axi_spi_engine_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_axi_spi_engine_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
@@ -463,9 +530,7 @@
</Run>
<Run Id="vio_hop_synth_1" Type="Ft3:Synth" SrcSet="vio_hop" Part="xc7z045ffg900-2" ConstrsSet="vio_hop" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_hop_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_hop_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_hop_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -475,9 +540,7 @@
</Run>
<Run Id="system_bd_xadc_wiz_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_xadc_wiz_0_0" Part="xc7z045ffg900-2" ConstrsSet="system_bd_xadc_wiz_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_xadc_wiz_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xadc_wiz_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xadc_wiz_0_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -487,9 +550,7 @@
</Run>
<Run Id="system_bd_rst_ps7_50M_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_rst_ps7_50M_0" Part="xc7z045ffg900-2" ConstrsSet="system_bd_rst_ps7_50M_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_rst_ps7_50M_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_rst_ps7_50M_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_rst_ps7_50M_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -499,9 +560,7 @@
</Run>
<Run Id="vio_mclk_delay_synth_1" Type="Ft3:Synth" SrcSet="vio_mclk_delay" Part="xc7z045ffg900-2" ConstrsSet="vio_mclk_delay" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_mclk_delay_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_mclk_delay_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_mclk_delay_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -511,9 +570,7 @@
</Run>
<Run Id="cmpy_18x8_synth_1" Type="Ft3:Synth" SrcSet="cmpy_18x8" Part="xc7z045ffg900-2" ConstrsSet="cmpy_18x8" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/cmpy_18x8_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_18x8_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_18x8_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -523,9 +580,7 @@
</Run>
<Run Id="dds_32b_8b_synth_1" Type="Ft3:Synth" SrcSet="dds_32b_8b" Part="xc7z045ffg900-2" ConstrsSet="dds_32b_8b" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dds_32b_8b_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dds_32b_8b_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dds_32b_8b_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -535,9 +590,7 @@
</Run>
<Run Id="hop_rom_synth_1" Type="Ft3:Synth" SrcSet="hop_rom" Part="xc7z045ffg900-2" ConstrsSet="hop_rom" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hop_rom_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hop_rom_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hop_rom_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -547,9 +600,7 @@
</Run>
<Run Id="hrc_64_12_025_synth_1" Type="Ft3:Synth" SrcSet="hrc_64_12_025" Part="xc7z045ffg900-2" ConstrsSet="hrc_64_12_025" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hrc_64_12_025_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -559,9 +610,7 @@
</Run>
<Run Id="ila_trx_synth_1" Type="Ft3:Synth" SrcSet="ila_trx" Part="xc7z045ffg900-2" ConstrsSet="ila_trx" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_trx_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_trx_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_trx_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -571,21 +620,7 @@
</Run>
<Run Id="vio_manual_ctrl_synth_1" Type="Ft3:Synth" SrcSet="vio_manual_ctrl" Part="xc7z045ffg900-2" ConstrsSet="vio_manual_ctrl" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_manual_ctrl_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="ila_trx_fb_synth_1" Type="Ft3:Synth" SrcSet="ila_trx_fb" Part="xc7z045ffg900-2" ConstrsSet="ila_trx_fb" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_trx_fb_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_trx_fb_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_trx_fb_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -595,9 +630,7 @@
</Run>
<Run Id="vio_mode_sel_synth_1" Type="Ft3:Synth" SrcSet="vio_mode_sel" Part="xc7z045ffg900-2" ConstrsSet="vio_mode_sel" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_mode_sel_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_mode_sel_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_mode_sel_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -607,9 +640,7 @@
</Run>
<Run Id="ila_cx9261a_synth_1" Type="Ft3:Synth" SrcSet="ila_cx9261a" Part="xc7z045ffg900-2" ConstrsSet="ila_cx9261a" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_cx9261a_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_cx9261a_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_cx9261a_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -619,9 +650,7 @@
</Run>
<Run Id="system_bd_spi_engine_execution_0_1_synth_1" Type="Ft3:Synth" SrcSet="system_bd_spi_engine_execution_0_1" Part="xc7z045ffg900-2" ConstrsSet="system_bd_spi_engine_execution_0_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_spi_engine_execution_0_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_1_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -630,6 +659,66 @@
<RQSFiles/>
</Run>
<Run Id="system_bd_xbar_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_xbar_0" Part="xc7z045ffg900-2" ConstrsSet="system_bd_xbar_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_xbar_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="hrc_4_12_03_synth_1" Type="Ft3:Synth" SrcSet="hrc_4_12_03" Part="xc7z045ffg900-2" ConstrsSet="hrc_4_12_03" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hrc_4_12_03_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_4_12_03_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_4_12_03_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="hrc_16_12_03_synth_1" Type="Ft3:Synth" SrcSet="hrc_16_12_03" Part="xc7z045ffg900-2" ConstrsSet="hrc_16_12_03" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hrc_16_12_03_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_16_12_03_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_16_12_03_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="hrc_128_12_03_synth_1" Type="Ft3:Synth" SrcSet="hrc_128_12_03" Part="xc7z045ffg900-2" ConstrsSet="hrc_128_12_03" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hrc_128_12_03_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_128_12_03_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_128_12_03_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="cx9261a_fifo_synth_1" Type="Ft3:Synth" SrcSet="cx9261a_fifo" Part="xc7z045ffg900-2" ConstrsSet="cx9261a_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/cx9261a_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cx9261a_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cx9261a_fifo_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="sys_clk_gen_synth_1" Type="Ft3:Synth" SrcSet="sys_clk_gen" Part="xc7z045ffg900-2" ConstrsSet="sys_clk_gen" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/sys_clk_gen_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/sys_clk_gen_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/sys_clk_gen_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_system_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_system_ila_0_0" Part="xc7z045ffg900-2" ConstrsSet="system_bd_system_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_system_ila_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_system_ila_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_system_ila_0_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
@@ -641,7 +730,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_auto_pc_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_auto_pc_0" Part="xc7z045ffg900-2" ConstrsSet="system_bd_auto_pc_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_auto_pc_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_auto_pc_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_auto_pc_0_synth_1" ParallelReportGen="true">
<Run Id="system_bd_axi_spi_engine_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_axi_spi_engine_0_0" Part="xc7z045ffg900-2" ConstrsSet="system_bd_axi_spi_engine_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_axi_spi_engine_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
@@ -654,26 +743,6 @@
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 16 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_axi_spi_engine_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="system_bd_axi_spi_engine_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_axi_spi_engine_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
@@ -686,6 +755,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
@@ -709,9 +779,7 @@
</Run>
<Run Id="vio_hop_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="vio_hop" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_hop_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_hop_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_hop_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -728,9 +796,7 @@
</Run>
<Run Id="system_bd_xadc_wiz_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="system_bd_xadc_wiz_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_xadc_wiz_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xadc_wiz_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xadc_wiz_0_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -747,9 +813,7 @@
</Run>
<Run Id="system_bd_rst_ps7_50M_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="system_bd_rst_ps7_50M_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_rst_ps7_50M_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_rst_ps7_50M_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_rst_ps7_50M_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -766,9 +830,7 @@
</Run>
<Run Id="vio_mclk_delay_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="vio_mclk_delay" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_mclk_delay_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_mclk_delay_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_mclk_delay_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -785,9 +847,7 @@
</Run>
<Run Id="cmpy_18x8_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="cmpy_18x8" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="cmpy_18x8_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_18x8_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_18x8_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -804,9 +864,7 @@
</Run>
<Run Id="dds_32b_8b_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="dds_32b_8b" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="dds_32b_8b_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dds_32b_8b_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dds_32b_8b_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -823,9 +881,7 @@
</Run>
<Run Id="hop_rom_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="hop_rom" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hop_rom_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hop_rom_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hop_rom_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -842,9 +898,7 @@
</Run>
<Run Id="hrc_64_12_025_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="hrc_64_12_025" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hrc_64_12_025_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -861,9 +915,7 @@
</Run>
<Run Id="ila_trx_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="ila_trx" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_trx_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_trx_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_trx_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -880,28 +932,7 @@
</Run>
<Run Id="vio_manual_ctrl_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="vio_manual_ctrl" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_manual_ctrl_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="ila_trx_fb_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="ila_trx_fb" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_trx_fb_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_trx_fb_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_trx_fb_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -918,9 +949,7 @@
</Run>
<Run Id="vio_mode_sel_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="vio_mode_sel" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_mode_sel_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_mode_sel_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_mode_sel_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -937,9 +966,7 @@
</Run>
<Run Id="ila_cx9261a_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="ila_cx9261a" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_cx9261a_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_cx9261a_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_cx9261a_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -956,9 +983,7 @@
</Run>
<Run Id="system_bd_spi_engine_execution_0_1_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="system_bd_spi_engine_execution_0_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_spi_engine_execution_0_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_1_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -974,6 +999,108 @@
<RQSFiles/>
</Run>
<Run Id="system_bd_xbar_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="system_bd_xbar_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_xbar_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="hrc_4_12_03_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="hrc_4_12_03" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hrc_4_12_03_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_4_12_03_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_4_12_03_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="hrc_16_12_03_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="hrc_16_12_03" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hrc_16_12_03_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_16_12_03_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_16_12_03_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="hrc_128_12_03_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="hrc_128_12_03" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hrc_128_12_03_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_128_12_03_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_128_12_03_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="cx9261a_fifo_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="cx9261a_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="cx9261a_fifo_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cx9261a_fifo_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cx9261a_fifo_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="sys_clk_gen_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="sys_clk_gen" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="sys_clk_gen_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/sys_clk_gen_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/sys_clk_gen_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_system_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="system_bd_system_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_system_ila_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_system_ila_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_system_ila_0_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
@@ -992,7 +1119,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_auto_pc_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="system_bd_auto_pc_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_auto_pc_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_auto_pc_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_auto_pc_0_impl_1" ParallelReportGen="true">
<Run Id="system_bd_axi_spi_engine_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="system_bd_axi_spi_engine_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_axi_spi_engine_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>