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fix: 修改spi时钟频率和时钟源,修改跳频控制时钟源,修改跳频逻辑

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josh
2025-05-23 10:57:27 +08:00
parent d3f2a27299
commit b8dda6c20b
15 changed files with 134 additions and 65 deletions
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zc706_cx9261a_demo/system_top.xsa
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zc706_cx9261a_demo/vitis_classic_autobuild/source_zc706_cx9261a/hwconfig.c
+6 -1
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@@ -923,6 +923,7 @@ int32_t Hardware_Init(void)
static int hop_cnt = 0;
static int next_pll_index = 2;
static double curr_freq;
static double hop_freq = MIN_FREQ + FREQ_SEP;
static double next_freq = MIN_FREQ;
@@ -943,7 +944,11 @@ int32_t Hardware_Init(void)
}
else
{
next_freq = (curr_freq + FREQ_SEP > MAX_FREQ) ? MIN_FREQ : curr_freq + FREQ_SEP;
hop_freq += FREQ_SEP;
if( hop_freq > MAX_FREQ){
hop_freq = MIN_FREQ + FREQ_SEP;
}
next_freq = hop_freq;
}
if (next_pll_index == 2)
zc706_cx9261a_demo/zc706_cx9261a_demo.runs/impl_1/system_top.bit
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zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci
+3 -3
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@@ -135,7 +135,7 @@
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI3", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "12", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -213,7 +213,7 @@
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -272,7 +272,7 @@
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci
+4 -4
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@@ -117,7 +117,7 @@
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -225,10 +225,10 @@
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "spi_engine_ctrl", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "spi_resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "2e+08", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK1", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
@@ -255,7 +255,7 @@
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "spi_engine_offload_ctrl0:s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci
+9 -9
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@@ -137,7 +137,7 @@
"PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ": [ { "value": "133.333333", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
"PCW_PCAP_PERIPHERAL_FREQMHZ": [ { "value": "200", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PCW_TPIU_PERIPHERAL_FREQMHZ": [ { "value": "200", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
"PCW_FPGA0_PERIPHERAL_FREQMHZ": [ { "value": "50", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PCW_FPGA0_PERIPHERAL_FREQMHZ": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PCW_FPGA1_PERIPHERAL_FREQMHZ": [ { "value": "200", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PCW_FPGA2_PERIPHERAL_FREQMHZ": [ { "value": "50", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PCW_FPGA3_PERIPHERAL_FREQMHZ": [ { "value": "50", "resolve_type": "user", "format": "float", "usage": "all" } ],
@@ -161,7 +161,7 @@
"PCW_ACT_TTC_PERIPHERAL_FREQMHZ": [ { "value": "50", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": [ { "value": "200.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": [ { "value": "200.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": [ { "value": "50.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": [ { "value": "100.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": [ { "value": "200.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
@@ -171,7 +171,7 @@
"PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": [ { "value": "111.111115", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": [ { "value": "111.111115", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": [ { "value": "111.111115", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PCW_CLK0_FREQ": [ { "value": "50000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PCW_CLK0_FREQ": [ { "value": "100000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PCW_CLK1_FREQ": [ { "value": "200000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PCW_CLK2_FREQ": [ { "value": "10000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PCW_CLK3_FREQ": [ { "value": "10000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
@@ -189,7 +189,7 @@
"PCW_FCLK1_PERIPHERAL_DIVISOR0": [ { "value": "5", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"PCW_FCLK2_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"PCW_FCLK3_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"PCW_FCLK0_PERIPHERAL_DIVISOR1": [ { "value": "4", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"PCW_FCLK0_PERIPHERAL_DIVISOR1": [ { "value": "2", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"PCW_FCLK1_PERIPHERAL_DIVISOR1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"PCW_FCLK2_PERIPHERAL_DIVISOR1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"PCW_FCLK3_PERIPHERAL_DIVISOR1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
@@ -255,7 +255,7 @@
"PCW_USE_S_AXI_HP1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PCW_USE_S_AXI_HP2": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PCW_USE_S_AXI_HP3": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PCW_M_AXI_GP0_FREQMHZ": [ { "value": "50.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PCW_M_AXI_GP0_FREQMHZ": [ { "value": "100", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PCW_M_AXI_GP1_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"PCW_S_AXI_GP0_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"PCW_S_AXI_GP1_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
@@ -1132,7 +1132,7 @@
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI3", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"ID_WIDTH": [ { "value": "12", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
@@ -1205,7 +1205,7 @@
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "master",
"parameters": {
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
@@ -1221,7 +1221,7 @@
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "master",
"parameters": {
"FREQ_HZ": [ { "value": "2e+08", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"FREQ_HZ": [ { "value": "200000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK1", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
@@ -1262,7 +1262,7 @@
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_GP0", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_rst_ps7_50M_0/system_bd_rst_ps7_50M_0.xci
+1 -1
View File
@@ -76,7 +76,7 @@
"mode": "slave",
"parameters": {
"ASSOCIATED_RESET": [ { "value": "mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_1/system_bd_spi_engine_execution_0_1.xci
+2 -2
View File
@@ -147,10 +147,10 @@
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "spi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "2e+08", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK1", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_system_ila_0_0/system_bd_system_ila_0_0.xci
+2 -2
View File
@@ -3881,10 +3881,10 @@
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"FREQ_HZ": [ { "value": "2e+08", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xadc_wiz_0_0/system_bd_xadc_wiz_0_0.xci
+2 -2
View File
@@ -312,7 +312,7 @@
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "11", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -369,7 +369,7 @@
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "s_axi_lite:M_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.xci
+6 -6
View File
@@ -2,7 +2,7 @@
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "system_bd_xbar_0",
"cell_name": "axi_interconnect_0_upgraded_ipi/xbar",
"cell_name": "axi_interconnect_0/xbar",
"component_reference": "xilinx.com:ip:axi_crossbar:2.1",
"ip_revision": "33",
"gen_directory": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_xbar_0",
@@ -1316,7 +1316,7 @@
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
"TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
"TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
@@ -1329,7 +1329,7 @@
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
@@ -1347,7 +1347,7 @@
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -1406,7 +1406,7 @@
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -1465,7 +1465,7 @@
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "5e+07", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/system_bd.bd
+36 -7
View File
@@ -1,7 +1,7 @@
{
"design": {
"design_info": {
"boundary_crc": "0xF1CD24C62BCF098C",
"boundary_crc": "0x1057130E5C906B3B",
"device": "xc7z045ffg900-2",
"gen_directory": "../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd",
"name": "system_bd",
@@ -313,6 +313,31 @@
"direction": "I",
"left": "0",
"right": "0"
},
"ps_clk_100M": {
"type": "clk",
"direction": "O",
"parameters": {
"CLK_DOMAIN": {
"value": "system_bd_processing_system7_0_0_FCLK_CLK0",
"value_src": "default_prop"
},
"FREQ_HZ": {
"value": "100000000"
},
"FREQ_TOLERANCE_HZ": {
"value": "0",
"value_src": "default"
},
"INSERT_VIP": {
"value": "0",
"value_src": "default"
},
"PHASE": {
"value": "0.000",
"value_src": "default"
}
}
}
},
"components": {
@@ -339,7 +364,7 @@
"value": "10.000000"
},
"PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": {
"value": "50.000000"
"value": "100.000000"
},
"PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": {
"value": "200.000000"
@@ -399,7 +424,7 @@
"value": "0"
},
"PCW_CLK0_FREQ": {
"value": "50000000"
"value": "100000000"
},
"PCW_CLK1_FREQ": {
"value": "200000000"
@@ -479,6 +504,9 @@
"PCW_FCLK_CLK1_BUF": {
"value": "TRUE"
},
"PCW_FPGA0_PERIPHERAL_FREQMHZ": {
"value": "100"
},
"PCW_FPGA1_PERIPHERAL_FREQMHZ": {
"value": "200"
},
@@ -2055,15 +2083,16 @@
"axi_interconnect_0/ACLK",
"axi_interconnect_0/S00_ACLK",
"axi_interconnect_0/M00_ACLK",
"axi_interconnect_0/M01_ACLK"
"axi_interconnect_0/M01_ACLK",
"ps_clk_100M",
"system_ila_spi/clk",
"axi_spi_engine/spi_clk"
]
},
"processing_system7_FCLK_CLK1": {
"ports": [
"processing_system7/FCLK_CLK1",
"ps_clk_200M",
"axi_spi_engine/spi_clk",
"system_ila_spi/clk"
"ps_clk_200M"
]
},
"processing_system7_FCLK_RESET0_N": {
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui
+18 -17
View File
@@ -1,7 +1,7 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"1.29739",
"Default View_TopLeft":"-372,-135",
"Default View_ScaleFactor":"0.798637",
"Default View_TopLeft":"-490,-19",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
# -string -flagsOSRD
@@ -11,6 +11,7 @@ preplace port Vp_Vn -pg 1 -lvl 0 -x -10 -y 590 -defaultsOSRD
preplace port spi -pg 1 -lvl 3 -x 1080 -y 930 -defaultsOSRD
preplace port port-id_spi_active -pg 1 -lvl 3 -x 1080 -y 70 -defaultsOSRD
preplace port port-id_ps_clk_200M -pg 1 -lvl 3 -x 1080 -y 190 -defaultsOSRD
preplace port port-id_ps_clk_100M -pg 1 -lvl 3 -x 1080 -y 0 -defaultsOSRD
preplace portBus gpio_i -pg 1 -lvl 3 -x 1080 -y 90 -defaultsOSRD -right
preplace portBus gpio_o -pg 1 -lvl 3 -x 1080 -y 110 -defaultsOSRD
preplace portBus gpio_t -pg 1 -lvl 3 -x 1080 -y 130 -defaultsOSRD
@@ -23,27 +24,27 @@ preplace inst axi_interconnect_0 -pg 1 -lvl 1 -x 260 -y 740 -defaultsOSRD
preplace inst xlconcat_irq -pg 1 -lvl 2 -x 770 -y 420 -defaultsOSRD -orient R180
preplace inst system_management -pg 1 -lvl 2 -x 770 -y 600 -defaultsOSRD
preplace inst system_ila_spi -pg 1 -lvl 2 -x 770 -y 90 -defaultsOSRD
preplace netloc GPIO_I_0_1 1 1 2 570 710 970
preplace netloc axi_spi_engine_active 1 1 2 580J 760 1010
preplace netloc GPIO_I_0_1 1 1 2 580 490 980
preplace netloc axi_spi_engine_active 1 1 2 570J 760 1020
preplace netloc axi_spi_engine_irq 1 1 2 N 970 950
preplace netloc processing_system7_FCLK_CLK0 1 0 2 20 10 590
preplace netloc processing_system7_FCLK_CLK1 1 0 3 10 570 490J 730 1030J
preplace netloc processing_system7_FCLK_RESET0_N 1 1 1 560 250n
preplace netloc processing_system7_GPIO_O 1 1 2 530J 720 990J
preplace netloc processing_system7_GPIO_T 1 1 2 510J 750 1020J
preplace netloc probe1_0_1 1 0 2 10J 0 500J
preplace netloc processing_system7_FCLK_CLK0 1 0 3 20 10 590 710 970
preplace netloc processing_system7_FCLK_RESET0_N 1 1 1 550 250n
preplace netloc processing_system7_GPIO_O 1 1 2 540J 720 1000J
preplace netloc processing_system7_GPIO_T 1 1 2 520J 750 1040J
preplace netloc rst_ps7_50M_peripheral_aresetn1 1 0 3 40 580 510 740 990
preplace netloc system_management_ip2intc_irpt 1 2 1 960 410n
preplace netloc xlconcat_irq_dout 1 0 2 50 420 N
preplace netloc rst_ps7_50M_peripheral_aresetn1 1 0 3 30 580 480 740 980
preplace netloc probe1_0_1 1 0 2 10J 0 510J
preplace netloc processing_system7_FCLK_CLK1 1 1 2 530 730 1030J
preplace netloc Vp_Vn_0_1 1 0 2 NJ 590 NJ
preplace netloc axi_interconnect_0_M00_AXI 1 0 2 50 600 470
preplace netloc axi_interconnect_0_M01_AXI 1 1 1 500 570n
preplace netloc axi_spi_engine_spi 1 1 2 550J 930 NJ
preplace netloc processing_system7_DDR 1 1 2 520J 0 1000
preplace netloc processing_system7_FIXED_IO 1 1 2 540J 490 1000
preplace netloc processing_system7_M_AXI_GP0 1 0 2 40 390 470
preplace netloc axi_interconnect_0_M01_AXI 1 1 1 480 570n
preplace netloc axi_spi_engine_spi 1 1 2 560J 930 NJ
preplace netloc processing_system7_DDR 1 1 2 480J -10 1010
preplace netloc processing_system7_FIXED_IO 1 1 2 530J 0 960
preplace netloc processing_system7_M_AXI_GP0 1 0 2 30 390 480
levelinfo -pg 1 -10 260 770 1080
pagesize -pg 1 -db -bbox -sgen -170 -10 1320 1130
pagesize -pg 1 -db -bbox -sgen -170 -20 1320 1130
"
}
{
zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/new/system_top.v
+4 -2
View File
@@ -143,6 +143,7 @@ assign cx9261a_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
assign spi_sdi = spi_three_wire ? cx9261a_spi_mosi : cx9261a_spi_miso;
// ps clock
wire ps_clk_100M;
wire ps_clk_200M;
wire ps_rstn;
@@ -192,6 +193,7 @@ system_bd_wrapper system_bd
.spi_active (spi_active ), // output spi_active
// ps clock
.ps_clk_100M (ps_clk_100M ), // output ps_clk_100M
.ps_clk_200M (ps_clk_200M ), // output ps_clk_200M
.ps_rstn (ps_rstn ), // output ps_rstn
@@ -416,7 +418,7 @@ reg hop_trig_d = 'b0;
assign hop_flag = hop_flag_buf;
always @(posedge ps_clk_200M or negedge ps_rstn) begin
always @(posedge ps_clk_100M or negedge ps_rstn) begin
if (!ps_rstn) begin
hop_cnt <= 'b0;
hop_flag_buf <= 'b0;
@@ -441,7 +443,7 @@ end
////////////////////////////////////////////////////////////////////////////////
vio_hop u_vio_hop
(
.clk (sys_clk_64M), // input wire clk
.clk (ps_clk_100M), // input wire clk
.probe_out0 (hop_inter ), // output wire [31 : 0] probe_out0
.probe_out1 (hop_en ), // output wire [0 : 0] probe_out1
.probe_out2 (hop_trig ) // output wire [0 : 0] probe_out2
zc706_cx9261a_demo/zc706_cx9261a_demo.xpr
+38 -6
View File
@@ -97,6 +97,9 @@
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci">
<Proxy FileSetName="system_bd_auto_pc_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci">
<Proxy FileSetName="system_bd_axi_spi_engine_0_0"/>
</CompFileExtendedInfo>
@@ -485,6 +488,12 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_auto_pc_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_auto_pc_0" RelGenDir="$PGENDIR/system_bd_auto_pc_0">
<Config>
<Option Name="TopModule" Val="system_bd_auto_pc_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
@@ -720,9 +729,7 @@
</Run>
<Run Id="system_bd_system_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_system_ila_0_0" Part="xc7z045ffg900-2" ConstrsSet="system_bd_system_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_system_ila_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_system_ila_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_system_ila_0_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -731,6 +738,16 @@
<RQSFiles/>
</Run>
<Run Id="system_bd_xbar_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_xbar_0" Part="xc7z045ffg900-2" ConstrsSet="system_bd_xbar_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_xbar_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_auto_pc_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_auto_pc_0" Part="xc7z045ffg900-2" ConstrsSet="system_bd_auto_pc_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_auto_pc_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_auto_pc_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_auto_pc_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
@@ -1102,9 +1119,7 @@
</Run>
<Run Id="system_bd_system_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="system_bd_system_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_system_ila_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_system_ila_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_system_ila_0_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -1120,6 +1135,23 @@
<RQSFiles/>
</Run>
<Run Id="system_bd_xbar_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="system_bd_xbar_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_xbar_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_auto_pc_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="system_bd_auto_pc_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_auto_pc_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_auto_pc_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_auto_pc_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>