add multirate qpsk transmitter, modify frequency hopping procedure

.gitignore

@@ -0,0 +1,20 @@
+# System generated files
+# -- macOS
+.DS_Store
+.AppleDouble
+.LSOverride
+._*
+
+# -- Windows
+Thumbs.db
+ehthumbs.db
+Desktop.ini
+
+# -- Linux
+*~
+
+# IDEs and editors' files
+*.idea
+*.vscode
+*.sublime-workspace
+*.sublime-project

cx9261a_demo_cmos_20240513/.gitignore

@@ -117,3 +117,14 @@ Desktop.ini
 *.vscode
 *.sublime-workspace
 *.sublime-project
+
+################################################################################
+############################### Project Specific ###############################
+################################################################################
+
+!/bootimage/
+!/bootimage/**/*
+!/ip_repo/
+!/ip_repo/**/*
+!/rom_data/
+!/rom_data/**/*

cx9261a_demo_cmos_20240513/bootimage/20240315/v20240315.bif

@@ -0,0 +1,7 @@
+//arch = zynq; split = false; format = BIN
+the_ROM_image:
+{
+	[bootloader]C:\Users\cxlab\Desktop\fpga_project\01_CX7045_demo\cmos\CX9261A_FPGA_DEMO240318\project_fix_dac.sdk\FSBL\Debug\FSBL.elf
+	C:\Users\cxlab\Desktop\fpga_project\01_CX7045_demo\cmos\CX9261A_FPGA_DEMO240318\project_fix_dac.runs\impl_2\CX9261A_ZC706.bit
+	C:\Users\cxlab\Desktop\fpga_project\01_CX7045_demo\cmos\CX9261A_FPGA_DEMO240318\project_fix_dac.sdk\CX9261A_DEMO\Debug\CX9261A_DEMO.elf
+}

cx9261a_demo_cmos_20240513/bootimage/20240407/v20240407.bif

@@ -0,0 +1,7 @@
+//arch = zynq; split = false; format = BIN
+the_ROM_image:
+{
+	[bootloader]C:\Users\cxlab\Desktop\fpga_project\01_CX7045_demo\cmos\CX9261A_FPGA_DEMO240318\project_fix_dac.sdk\FSBL\Debug\FSBL.elf
+	C:\Users\cxlab\Desktop\fpga_project\01_CX7045_demo\cmos\CX9261A_FPGA_DEMO240318\project_fix_dac.runs\impl_1\CX9261A_ZC706.bit
+	C:\Users\cxlab\Desktop\fpga_project\01_CX7045_demo\cmos\CX9261A_FPGA_DEMO240318\project_fix_dac.sdk\CX9261A_DEMO\Debug\CX9261A_DEMO.elf
+}

cx9261a_demo_cmos_20240513/ip_repo/Axis_adc_data_packer_1.0/bd/bd.tcl

@@ -0,0 +1,86 @@
+
+proc init { cellpath otherInfo } {                                                                   
+                                                                                                             
+	set cell_handle [get_bd_cells $cellpath]                                                                 
+	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
+	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+	set full_sbusif_list [list  ]
+			                                                                                                 
+	foreach busif $all_busif {                                                                               
+		if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {                            
+			set busif_param_list [list]                                                                      
+			set busif_name [get_property NAME $busif]					                                     
+			if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {					         
+			    continue                                                                                     
+			}                                                                                                
+			foreach tparam $axi_standard_param_list {                                                        
+				lappend busif_param_list "C_${busif_name}_${tparam}"                                       
+			}                                                                                                
+			bd::mark_propagate_only $cell_handle $busif_param_list			                                 
+		}		                                                                                             
+	}                                                                                                        
+}
+
+
+proc pre_propagate {cellpath otherInfo } {                                                           
+                                                                                                             
+	set cell_handle [get_bd_cells $cellpath]                                                                 
+	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
+	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+	                                                                                                         
+	foreach busif $all_busif {	                                                                             
+		if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {                  
+			continue                                                                                         
+		}                                                                                                    
+		if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {                           
+			continue                                                                                         
+		}			                                                                                         
+		                                                                                                     
+		set busif_name [get_property NAME $busif]			                                                 
+		foreach tparam $axi_standard_param_list {		                                                     
+			set busif_param_name "C_${busif_name}_${tparam}"			                                     
+			                                                                                                 
+			set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]                                  
+			set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]                           
+			                                                                                                 
+			if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {                          
+				if { $val_on_cell != "" } {                                                                  
+					set_property CONFIG.${tparam} $val_on_cell $busif                                        
+				}                                                                                            
+			}			                                                                                     
+		}		                                                                                             
+	}                                                                                                        
+}
+
+
+proc propagate {cellpath otherInfo } {                                                               
+                                                                                                             
+	set cell_handle [get_bd_cells $cellpath]                                                                 
+	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
+	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+	                                                                                                         
+	foreach busif $all_busif {                                                                               
+		if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {                  
+			continue                                                                                         
+		}                                                                                                    
+		if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {                            
+			continue                                                                                         
+		}			                                                                                         
+	                                                                                                         
+		set busif_name [get_property NAME $busif]		                                                     
+		foreach tparam $axi_standard_param_list {			                                                 
+			set busif_param_name "C_${busif_name}_${tparam}"			                                     
+                                                                                                             
+			set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]                                  
+			set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]                           
+			                                                                                                 
+			if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {                          
+				#override property of bd_interface_net to bd_cell -- only for slaves.  May check for supported values..
+				if { $val_on_cell_intf_pin != "" } {                                                         
+					set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle               
+				}                                                                                            
+			}                                                                                                
+		}		                                                                                             
+	}                                                                                                        
+}
+

cx9261a_demo_cmos_20240513/ip_repo/Axis_adc_data_packer_1.0/drivers/Axis_adc_data_packer_v1_0/data/Axis_adc_data_packer.mdd

@@ -0,0 +1,10 @@
+
+
+OPTION psf_version = 2.1;
+
+BEGIN DRIVER Axis_adc_data_packer
+	OPTION supported_peripherals = (Axis_adc_data_packer);
+	OPTION copyfiles = all;
+	OPTION VERSION = 1.0;
+	OPTION NAME = Axis_adc_data_packer;
+END DRIVER

cx9261a_demo_cmos_20240513/ip_repo/Axis_adc_data_packer_1.0/drivers/Axis_adc_data_packer_v1_0/data/Axis_adc_data_packer.tcl

@@ -0,0 +1,5 @@
+
+
+proc generate {drv_handle} {
+	xdefine_include_file $drv_handle "xparameters.h" "Axis_adc_data_packer" "NUM_INSTANCES" "DEVICE_ID"  "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
+}

cx9261a_demo_cmos_20240513/ip_repo/Axis_adc_data_packer_1.0/drivers/Axis_adc_data_packer_v1_0/src/Axis_adc_data_packer.c

@@ -0,0 +1,6 @@
+
+
+/***************************** Include Files *******************************/
+#include "Axis_adc_data_packer.h"
+
+/************************** Function Definitions ***************************/

cx9261a_demo_cmos_20240513/ip_repo/Axis_adc_data_packer_1.0/drivers/Axis_adc_data_packer_v1_0/src/Axis_adc_data_packer.h

@@ -0,0 +1,79 @@
+
+#ifndef AXIS_ADC_DATA_PACKER_H
+#define AXIS_ADC_DATA_PACKER_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG0_OFFSET 0
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG1_OFFSET 4
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG2_OFFSET 8
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG3_OFFSET 12
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a AXIS_ADC_DATA_PACKER register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param   BaseAddress is the base address of the AXIS_ADC_DATA_PACKERdevice.
+ * @param   RegOffset is the register offset from the base to write to.
+ * @param   Data is the data written to the register.
+ *
+ * @return  None.
+ *
+ * @note
+ * C-style signature:
+ * 	void AXIS_ADC_DATA_PACKER_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define AXIS_ADC_DATA_PACKER_mWriteReg(BaseAddress, RegOffset, Data) \
+  	Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a AXIS_ADC_DATA_PACKER register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param   BaseAddress is the base address of the AXIS_ADC_DATA_PACKER device.
+ * @param   RegOffset is the register offset from the base to write to.
+ *
+ * @return  Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * 	u32 AXIS_ADC_DATA_PACKER_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define AXIS_ADC_DATA_PACKER_mReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the AXIS_ADC_DATA_PACKER instance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus AXIS_ADC_DATA_PACKER_Reg_SelfTest(void * baseaddr_p);
+
+#endif // AXIS_ADC_DATA_PACKER_H

cx9261a_demo_cmos_20240513/ip_repo/Axis_adc_data_packer_1.0/drivers/Axis_adc_data_packer_v1_0/src/Axis_adc_data_packer_selftest.c

@@ -0,0 +1,60 @@
+
+/***************************** Include Files *******************************/
+#include "Axis_adc_data_packer.h"
+#include "xparameters.h"
+#include "stdio.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+#define READ_WRITE_MUL_FACTOR 0x10
+
+/************************** Function Definitions ***************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the AXIS_ADC_DATA_PACKERinstance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus AXIS_ADC_DATA_PACKER_Reg_SelfTest(void * baseaddr_p)
+{
+	u32 baseaddr;
+	int write_loop_index;
+	int read_loop_index;
+	int Index;
+
+	baseaddr = (u32) baseaddr_p;
+
+	xil_printf("******************************\n\r");
+	xil_printf("* User Peripheral Self Test\n\r");
+	xil_printf("******************************\n\n\r");
+
+	/*
+	 * Write to user logic slave module register(s) and read back
+	 */
+	xil_printf("User logic slave module test...\n\r");
+
+	for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
+	  AXIS_ADC_DATA_PACKER_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
+	for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
+	  if ( AXIS_ADC_DATA_PACKER_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
+	    xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
+	    return XST_FAILURE;
+	  }
+
+	xil_printf("   - slave register write/read passed\n\n\r");
+
+	return XST_SUCCESS;
+}

cx9261a_demo_cmos_20240513/ip_repo/Axis_adc_data_packer_1.0/drivers/Axis_adc_data_packer_v1_0/src/Makefile

@@ -0,0 +1,26 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+	echo "Compiling Axis_adc_data_packer..."
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+	make clean
+
+include:
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}

cx9261a_demo_cmos_20240513/ip_repo/Axis_adc_data_packer_1.0/example_designs/bfm_design/Axis_adc_data_packer_v1_0_tb.sv

@@ -0,0 +1,197 @@
+
+`timescale 1ns / 1ps
+`include "Axis_adc_data_packer_v1_0_tb_include.svh"
+
+import axi_vip_pkg::*;
+import Axis_adc_data_packer_v1_0_bfm_1_master_0_0_pkg::*;
+
+module Axis_adc_data_packer_v1_0_tb();
+
+
+xil_axi_uint                            error_cnt = 0;
+xil_axi_uint                            comparison_cnt = 0;
+axi_transaction                         wr_transaction;   
+axi_transaction                         rd_transaction;   
+axi_monitor_transaction                 mst_monitor_transaction;  
+axi_monitor_transaction                 master_moniter_transaction_queue[$];  
+xil_axi_uint                            master_moniter_transaction_queue_size =0;  
+axi_monitor_transaction                 mst_scb_transaction;  
+axi_monitor_transaction                 passthrough_monitor_transaction;  
+axi_monitor_transaction                 passthrough_master_moniter_transaction_queue[$];  
+xil_axi_uint                            passthrough_master_moniter_transaction_queue_size =0;  
+axi_monitor_transaction                 passthrough_mst_scb_transaction;  
+axi_monitor_transaction                 passthrough_slave_moniter_transaction_queue[$];  
+xil_axi_uint                            passthrough_slave_moniter_transaction_queue_size =0;  
+axi_monitor_transaction                 passthrough_slv_scb_transaction;  
+axi_monitor_transaction                 slv_monitor_transaction;  
+axi_monitor_transaction                 slave_moniter_transaction_queue[$];  
+xil_axi_uint                            slave_moniter_transaction_queue_size =0;  
+axi_monitor_transaction                 slv_scb_transaction;  
+xil_axi_uint                           mst_agent_verbosity = 0;  
+xil_axi_uint                           slv_agent_verbosity = 0;  
+xil_axi_uint                           passthrough_agent_verbosity = 0;  
+bit                                     clock;
+bit                                     reset;
+integer result_slave;  
+bit [31:0] S00_AXI_test_data[3:0]; 
+ localparam LC_AXI_BURST_LENGTH = 8; 
+ localparam LC_AXI_DATA_WIDTH = 32; 
+task automatic COMPARE_DATA; 
+  input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]expected; 
+  input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]actual; 
+  begin 
+    if (expected === 'hx || actual === 'hx) begin 
+      $display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!"); 
+ result_slave = 0;    $stop; 
+  end 
+  if (actual != expected) begin 
+    $display("TESTBENCH ERROR! Data expected is not equal to actual.",     " expected = 0x%h",expected,     " actual   = 0x%h",actual); 
+    result_slave = 0; 
+    $stop; 
+  end 
+  else  
+    begin 
+     $display("TESTBENCH Passed! Data expected is equal to actual.", 
+              " expected = 0x%h",expected,               " actual   = 0x%h",actual); 
+    end 
+  end 
+endtask 
+integer                                 i; 
+integer                                 j;  
+xil_axi_uint                            trans_cnt_before_switch = 48;  
+xil_axi_uint                            passthrough_cmd_switch_cnt = 0;  
+event                                   passthrough_mastermode_start_event;  
+event                                   passthrough_mastermode_end_event;  
+event                                   passthrough_slavemode_end_event;  
+xil_axi_uint                            mtestID;  
+xil_axi_ulong                           mtestADDR;  
+xil_axi_len_t                           mtestBurstLength;  
+xil_axi_size_t                          mtestDataSize;   
+xil_axi_burst_t                         mtestBurstType;   
+xil_axi_lock_t                          mtestLOCK;  
+xil_axi_cache_t                         mtestCacheType = 0;  
+xil_axi_prot_t                          mtestProtectionType = 3'b000;  
+xil_axi_region_t                        mtestRegion = 4'b000;  
+xil_axi_qos_t                           mtestQOS = 4'b000;  
+xil_axi_data_beat                       dbeat;  
+xil_axi_data_beat [255:0]               mtestWUSER;   
+xil_axi_data_beat                       mtestAWUSER = 'h0;  
+xil_axi_data_beat                       mtestARUSER = 0;  
+xil_axi_data_beat [255:0]               mtestRUSER;      
+xil_axi_uint                            mtestBUSER = 0;  
+xil_axi_resp_t                          mtestBresp;  
+xil_axi_resp_t[255:0]                   mtestRresp;  
+bit [63:0]                              mtestWDataL; 
+bit [63:0]                              mtestRDataL; 
+axi_transaction                         pss_wr_transaction;   
+axi_transaction                         pss_rd_transaction;   
+axi_transaction                         reactive_transaction;   
+axi_transaction                         rd_payload_transaction;  
+axi_transaction                         wr_rand;  
+axi_transaction                         rd_rand;  
+axi_transaction                         wr_reactive;  
+axi_transaction                         rd_reactive;  
+axi_transaction                         wr_reactive2;   
+axi_transaction                         rd_reactive2;  
+axi_ready_gen                           bready_gen;  
+axi_ready_gen                           rready_gen;  
+axi_ready_gen                           awready_gen;  
+axi_ready_gen                           wready_gen;  
+axi_ready_gen                           arready_gen;  
+axi_ready_gen                           bready_gen2;  
+axi_ready_gen                           rready_gen2;  
+axi_ready_gen                           awready_gen2;  
+axi_ready_gen                           wready_gen2;  
+axi_ready_gen                           arready_gen2;  
+xil_axi_payload_byte                    data_mem[xil_axi_ulong];  
+Axis_adc_data_packer_v1_0_bfm_1_master_0_0_mst_t          mst_agent_0;
+
+  `BD_WRAPPER DUT(
+      .ARESETN(reset), 
+      .ACLK(clock) 
+    ); 
+  
+initial begin
+     mst_agent_0 = new("master vip agent",DUT.`BD_INST_NAME.master_0.inst.IF);//ms  
+   mst_agent_0.vif_proxy.set_dummy_drive_type(XIL_AXI_VIF_DRIVE_NONE); 
+   mst_agent_0.set_agent_tag("Master VIP"); 
+   mst_agent_0.set_verbosity(mst_agent_verbosity); 
+   mst_agent_0.start_master(); 
+     $timeformat (-12, 1, " ps", 1);
+  end
+  initial begin
+    reset <= 1'b0;
+    #200ns;
+    reset <= 1'b1;
+    repeat (5) @(negedge clock); 
+  end
+  always #5 clock <= ~clock;
+  initial begin
+      S_AXI_TEST ( );
+
+      #1ns;
+      $finish;
+  end
+task automatic S_AXI_TEST;  
+begin   
+#1; 
+   $display("Sequential write transfers example similar to  AXI BFM WRITE_BURST method starts"); 
+   mtestID = 0; 
+   mtestADDR = 64'h00000000; 
+   mtestBurstLength = 0; 
+   mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); 
+   mtestBurstType = XIL_AXI_BURST_TYPE_INCR;  
+   mtestLOCK = XIL_AXI_ALOCK_NOLOCK;  
+   mtestCacheType = 0;  
+   mtestProtectionType = 0;  
+   mtestRegion = 0; 
+   mtestQOS = 0; 
+   result_slave = 1; 
+  mtestWDataL[31:0] = 32'h00000001; 
+  for(int i = 0; i < 4;i++) begin 
+  S00_AXI_test_data[i] <= mtestWDataL[31:0];   
+  mst_agent_0.AXI4LITE_WRITE_BURST( 
+  mtestADDR, 
+  mtestProtectionType, 
+  mtestWDataL, 
+  mtestBresp 
+  );   
+  mtestWDataL[31:0] = mtestWDataL[31:0] + 1; 
+  mtestADDR = mtestADDR + 64'h4; 
+  end 
+     $display("Sequential write transfers example similar to  AXI BFM WRITE_BURST method completes"); 
+     $display("Sequential read transfers example similar to  AXI BFM READ_BURST method starts"); 
+     mtestID = 0; 
+     mtestADDR = 64'h00000000; 
+     mtestBurstLength = 0; 
+     mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); 
+     mtestBurstType = XIL_AXI_BURST_TYPE_INCR;  
+     mtestLOCK = XIL_AXI_ALOCK_NOLOCK;  
+     mtestCacheType = 0;  
+     mtestProtectionType = 0;  
+     mtestRegion = 0; 
+     mtestQOS = 0; 
+ for(int i = 0; i < 4;i++) begin 
+   mst_agent_0.AXI4LITE_READ_BURST( 
+        mtestADDR, 
+        mtestProtectionType, 
+        mtestRDataL, 
+        mtestRresp 
+      ); 
+   mtestADDR = mtestADDR + 64'h4; 
+   COMPARE_DATA(S00_AXI_test_data[i],mtestRDataL); 
+ end 
+     $display("Sequential read transfers example similar to  AXI BFM READ_BURST method completes"); 
+     $display("Sequential read transfers example similar to  AXI VIP READ_BURST method completes"); 
+     $display("---------------------------------------------------------"); 
+     $display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!"); 
+     if ( result_slave ) begin                    
+       $display("PTGEN_TEST: PASSED!");                  
+     end    else begin                                       
+       $display("PTGEN_TEST: FAILED!");                  
+     end                                
+     $display("---------------------------------------------------------"); 
+  end 
+endtask  
+
+endmodule

cx9261a_demo_cmos_20240513/ip_repo/Axis_adc_data_packer_1.0/example_designs/bfm_design/design.tcl

@@ -0,0 +1,88 @@
+proc create_ipi_design { offsetfile design_name } {
+	create_bd_design $design_name
+	open_bd_design $design_name
+
+	# Create Clock and Reset Ports
+	set ACLK [ create_bd_port -dir I -type clk ACLK ]
+	set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
+	set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
+	set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}  ] $ARESETN
+	set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
+
+	# Create instance: Axis_adc_data_packer_0, and set properties
+	set Axis_adc_data_packer_0 [ create_bd_cell -type ip -vlnv labnet.com:user:Axis_adc_data_packer:1.0 Axis_adc_data_packer_0]
+
+	# Create instance: master_0, and set properties
+	set master_0 [ create_bd_cell -type ip -vlnv  xilinx.com:ip:axi_vip master_0]
+	set_property -dict [ list CONFIG.PROTOCOL {AXI4LITE} CONFIG.INTERFACE_MODE {MASTER} ] $master_0
+
+	# Create interface connections
+	connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI ] [get_bd_intf_pins Axis_adc_data_packer_0/S00_AXI]
+
+	# Create port connections
+	connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/ACLK] [get_bd_pins Axis_adc_data_packer_0/S00_AXI_ACLK]
+	connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/ARESETN] [get_bd_pins Axis_adc_data_packer_0/S00_AXI_ARESETN]
+set_property target_simulator XSim [current_project]
+set_property -name {xsim.simulate.runtime} -value {100ms} -objects [get_filesets sim_1]
+
+	# Auto assign address
+	assign_bd_address
+
+	# Copy all address to interface_address.vh file
+	set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
+	upvar 1 $offsetfile offset_file
+	set offset_file "${bd_path}/Axis_adc_data_packer_v1_0_tb_include.svh"
+	set fp [open $offset_file "w"]
+	puts $fp "`ifndef Axis_adc_data_packer_v1_0_tb_include_vh_"
+	puts $fp "`define Axis_adc_data_packer_v1_0_tb_include_vh_\n"
+	puts $fp "//Configuration current bd names"
+	puts $fp "`define BD_NAME ${design_name}"
+	puts $fp "`define BD_INST_NAME ${design_name}_i"
+	puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
+	puts $fp "//Configuration address parameters"
+
+	puts $fp "`endif"
+	close $fp
+}
+
+set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores labnet.com:user:Axis_adc_data_packer:1.0]]]]
+set test_bench_file ${ip_path}/example_designs/bfm_design/Axis_adc_data_packer_v1_0_tb.sv
+set interface_address_vh_file ""
+
+# Set IP Repository and Update IP Catalogue 
+set repo_paths [get_property ip_repo_paths [current_fileset]] 
+if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
+	set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
+	update_ip_catalog
+}
+
+set design_name ""
+set all_bd {}
+set all_bd_files [get_files *.bd -quiet]
+foreach file $all_bd_files {
+set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
+set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
+lappend all_bd $bd_name
+}
+
+for { set i 1 } { 1 } { incr i } {
+	set design_name "Axis_adc_data_packer_v1_0_bfm_${i}"
+	if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
+		break
+	}
+}
+
+create_ipi_design interface_address_vh_file ${design_name}
+validate_bd_design
+
+set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
+import_files -force -norecurse $wrapper_file
+
+set_property SOURCE_SET sources_1 [get_filesets sim_1]
+import_files -fileset sim_1 -norecurse -force $test_bench_file
+remove_files -quiet -fileset sim_1 Axis_adc_data_packer_v1_0_tb_include.vh
+import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
+set_property top Axis_adc_data_packer_v1_0_tb [get_filesets sim_1]
+set_property top_lib {} [get_filesets sim_1]
+set_property top_file {} [get_filesets sim_1]
+launch_simulation -simset sim_1 -mode behavioral

cx9261a_demo_cmos_20240513/ip_repo/Axis_adc_data_packer_1.0/example_designs/debug_hw_design/Axis_adc_data_packer_v1_0_hw_test.tcl

@@ -0,0 +1,45 @@
+# Runtime Tcl commands to interact with - Axis_adc_data_packer_v1_0
+
+# Sourcing design address info tcl
+set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
+source ${bd_path}/Axis_adc_data_packer_v1_0_include.tcl
+
+# jtag axi master interface hardware name, change as per your design.
+set jtag_axi_master hw_axi_1
+set ec 0
+
+# hw test script
+# Delete all previous axis transactions
+if { [llength [get_hw_axi_txns -quiet]] } {
+	delete_hw_axi_txn [get_hw_axi_txns -quiet]
+}
+
+
+# Test all lite slaves.
+set wdata_1 abcd1234
+
+# Test: S00_AXI
+# Create a write transaction at s00_axi_addr address
+create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1
+# Create a read transaction at s00_axi_addr address
+create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr
+# Initiate transactions
+run_hw_axi r_s00_axi_addr
+run_hw_axi w_s00_axi_addr
+run_hw_axi r_s00_axi_addr
+set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]]
+# Compare read data
+if { $rdata_tmp == $wdata_1 } {
+	puts "Data comparison test pass for - S00_AXI"
+} else {
+	puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp"
+	inc ec
+}
+
+# Check error flag
+if { $ec == 0 } {
+	 puts "PTGEN_TEST: PASSED!" 
+} else {
+	 puts "PTGEN_TEST: FAILED!" 
+}
+

cx9261a_demo_cmos_20240513/ip_repo/Axis_adc_data_packer_1.0/example_designs/debug_hw_design/design.tcl

@@ -0,0 +1,118 @@
+
+proc create_ipi_design { offsetfile design_name } {
+
+	create_bd_design $design_name
+	open_bd_design $design_name
+
+	# Create and configure Clock/Reset
+	create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
+	create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
+
+	#Constraints will be provided manually while pin planning.
+		create_bd_port -dir I -type rst reset_rtl
+		set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
+		connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
+		connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
+		set external_reset_port reset_rtl
+		create_bd_port -dir I -type clk clock_rtl
+		connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
+		set external_clock_port clock_rtl
+	
+	#Avoid IPI DRC, make clock port synchronous to reset
+	if { $external_clock_port ne "" && $external_reset_port ne "" } {
+		set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
+	}
+
+	# Connect other sys_reset pins
+	connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
+
+	# Create instance: Axis_adc_data_packer_0, and set properties
+	set Axis_adc_data_packer_0 [ create_bd_cell -type ip -vlnv labnet.com:user:Axis_adc_data_packer:1.0 Axis_adc_data_packer_0 ]
+
+	# Create instance: jtag_axi_0, and set properties
+	set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
+	set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
+	connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+	# Create instance: axi_peri_interconnect, and set properties
+	set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
+	connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
+	set_property -dict [ list CONFIG.NUM_SI {1}  ] $axi_peri_interconnect
+	connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
+	connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
+
+	set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect
+	connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+	# Connect all clock & reset of Axis_adc_data_packer_0 slave interfaces..
+	connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins Axis_adc_data_packer_0/S00_AXI]
+	connect_bd_net [get_bd_pins Axis_adc_data_packer_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins Axis_adc_data_packer_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+
+	# Auto assign address
+	assign_bd_address
+
+	# Copy all address to Axis_adc_data_packer_v1_0_include.tcl file
+	set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
+	upvar 1 $offsetfile offset_file
+	set offset_file "${bd_path}/Axis_adc_data_packer_v1_0_include.tcl"
+	set fp [open $offset_file "w"]
+	puts $fp "# Configuration address parameters"
+
+	set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_Axis_adc_data_packer_0_S00_AXI_* ]]
+	puts $fp "set s00_axi_addr ${offset}"
+
+	close $fp
+}
+
+# Set IP Repository and Update IP Catalogue 
+set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores labnet.com:user:Axis_adc_data_packer:1.0]]]]
+set hw_test_file ${ip_path}/example_designs/debug_hw_design/Axis_adc_data_packer_v1_0_hw_test.tcl
+
+set repo_paths [get_property ip_repo_paths [current_fileset]] 
+if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
+	set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
+	update_ip_catalog
+}
+
+set design_name ""
+set all_bd {}
+set all_bd_files [get_files *.bd -quiet]
+foreach file $all_bd_files {
+set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
+set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
+lappend all_bd $bd_name
+}
+
+for { set i 1 } { 1 } { incr i } {
+	set design_name "Axis_adc_data_packer_v1_0_hw_${i}"
+	if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
+		break
+	}
+}
+
+set intf_address_include_file ""
+create_ipi_design intf_address_include_file ${design_name}
+save_bd_design
+validate_bd_design
+
+set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
+import_files -force -norecurse $wrapper_file
+
+puts "-------------------------------------------------------------------------------------------------"
+puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
+puts "   please perform following steps to test design in targeted board."
+puts "1. Generate bitstream"
+puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
+puts "3. Download generated bitstream"
+puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
+puts "   to every interface present in the peripheral : xilinx.com:user:myip:1.0"
+puts "   : source -notrace ${hw_test_file}"
+puts "-------------------------------------------------------------------------------------------------"
+

cx9261a_demo_cmos_20240513/ip_repo/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v

@@ -0,0 +1,98 @@
+`timescale 1 ns / 1 ps
+
+	module Axis_adc_data_packer_v1_0 #
+	(
+		// Users to add parameters here
+
+		// User parameters ends
+		// Do not modify the parameters beyond this line
+
+
+		// Parameters of Axi Slave Bus Interface S00_AXI
+		parameter integer C_S00_AXI_DATA_WIDTH	= 32,
+		parameter integer C_S00_AXI_ADDR_WIDTH	= 4
+	)
+	(
+		// Users to add ports here
+    input wire aclk,		
+    input wire aresetn,
+    input wire  axis_tvalid,
+    input wire axis_tlast,
+    output wire axis_ready,
+    input  wire [63:0] axis_tdata,
+      
+    output wire m_axis_tvalid,
+    output wire m_axis_tlast,
+    input wire m_axis_ready,
+    output wire [63:0] m_axis_tdata,
+		// User ports ends
+		
+		// Do not modify the ports beyond this line
+
+
+		// Ports of Axi Slave Bus Interface S00_AXI
+		input wire  s00_axi_aclk,
+		input wire  s00_axi_aresetn,
+		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
+		input wire [2 : 0] s00_axi_awprot,
+		input wire  s00_axi_awvalid,
+		output wire  s00_axi_awready,
+		input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
+		input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
+		input wire  s00_axi_wvalid,
+		output wire  s00_axi_wready,
+		output wire [1 : 0] s00_axi_bresp,
+		output wire  s00_axi_bvalid,
+		input wire  s00_axi_bready,
+		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
+		input wire [2 : 0] s00_axi_arprot,
+		input wire  s00_axi_arvalid,
+		output wire  s00_axi_arready,
+		output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
+		output wire [1 : 0] s00_axi_rresp,
+		output wire  s00_axi_rvalid,
+		input wire  s00_axi_rready
+	);
+// Instantiation of Axi Bus Interface S00_AXI
+	Axis_adc_data_packer_v1_0_S00_AXI # ( 
+		.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
+		.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
+	) Axis_adc_data_packer_v1_0_S00_AXI_inst (
+		.S_AXI_ACLK(s00_axi_aclk),
+		.S_AXI_ARESETN(s00_axi_aresetn),
+		.S_AXI_AWADDR(s00_axi_awaddr),
+		.S_AXI_AWPROT(s00_axi_awprot),
+		.S_AXI_AWVALID(s00_axi_awvalid),
+		.S_AXI_AWREADY(s00_axi_awready),
+		.S_AXI_WDATA(s00_axi_wdata),
+		.S_AXI_WSTRB(s00_axi_wstrb),
+		.S_AXI_WVALID(s00_axi_wvalid),
+		.S_AXI_WREADY(s00_axi_wready),
+		.S_AXI_BRESP(s00_axi_bresp),
+		.S_AXI_BVALID(s00_axi_bvalid),
+		.S_AXI_BREADY(s00_axi_bready),
+		.S_AXI_ARADDR(s00_axi_araddr),
+		.S_AXI_ARPROT(s00_axi_arprot),
+		.S_AXI_ARVALID(s00_axi_arvalid),
+		.S_AXI_ARREADY(s00_axi_arready),
+		.S_AXI_RDATA(s00_axi_rdata),
+		.S_AXI_RRESP(s00_axi_rresp),
+		.S_AXI_RVALID(s00_axi_rvalid),
+		.S_AXI_RREADY(s00_axi_rready),
+    .axis_tvalid(axis_tvalid),
+    .axis_ready(axis_ready),
+    .axis_tdata(axis_tdata),
+    
+    .aclk(aclk),
+    .aresetn(aresetn),
+    .m_axis_tvalid(m_axis_tvalid),
+    .m_axis_tlast(m_axis_tlast),
+    .m_axis_ready(m_axis_ready),
+    .m_axis_tdata(m_axis_tdata)   
+	);
+
+	// Add user logic here
+
+	// User logic ends
+
+	endmodule

cx9261a_demo_cmos_20240513/ip_repo/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v

@@ -0,0 +1,469 @@
+`timescale 1 ns / 1 ps
+
+	module Axis_adc_data_packer_v1_0_S00_AXI #
+	(
+		// Users to add parameters here
+
+		// User parameters ends
+		// Do not modify the parameters beyond this line
+
+		// Width of S_AXI data bus
+		parameter integer C_S_AXI_DATA_WIDTH	= 32,
+		// Width of S_AXI address bus
+		parameter integer C_S_AXI_ADDR_WIDTH	= 4
+	)
+	(
+		// Users to add ports here
+	input wire aclk,
+    input wire aresetn,
+    input wire axis_tvalid,
+    output wire  axis_ready,
+    input wire [63:0] axis_tdata,
+      
+    output wire m_axis_tvalid,
+    output wire m_axis_tlast,
+    input wire m_axis_ready,
+    output wire [63:0] m_axis_tdata,
+
+		// User ports ends
+		// Do not modify the ports beyond this line
+
+		// Global Clock Signal
+		input wire  S_AXI_ACLK,
+		// Global Reset Signal. This Signal is Active LOW
+		input wire  S_AXI_ARESETN,
+		// Write address (issued by master, acceped by Slave)
+		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
+		// Write channel Protection type. This signal indicates the
+    		// privilege and security level of the transaction, and whether
+    		// the transaction is a data access or an instruction access.
+		input wire [2 : 0] S_AXI_AWPROT,
+		// Write address valid. This signal indicates that the master signaling
+    		// valid write address and control information.
+		input wire  S_AXI_AWVALID,
+		// Write address ready. This signal indicates that the slave is ready
+    		// to accept an address and associated control signals.
+		output wire  S_AXI_AWREADY,
+		// Write data (issued by master, acceped by Slave) 
+		input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
+		// Write strobes. This signal indicates which byte lanes hold
+    		// valid data. There is one write strobe bit for each eight
+    		// bits of the write data bus.    
+		input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
+		// Write valid. This signal indicates that valid write
+    		// data and strobes are available.
+		input wire  S_AXI_WVALID,
+		// Write ready. This signal indicates that the slave
+    		// can accept the write data.
+		output wire  S_AXI_WREADY,
+		// Write response. This signal indicates the status
+    		// of the write transaction.
+		output wire [1 : 0] S_AXI_BRESP,
+		// Write response valid. This signal indicates that the channel
+    		// is signaling a valid write response.
+		output wire  S_AXI_BVALID,
+		// Response ready. This signal indicates that the master
+    		// can accept a write response.
+		input wire  S_AXI_BREADY,
+		// Read address (issued by master, acceped by Slave)
+		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
+		// Protection type. This signal indicates the privilege
+    		// and security level of the transaction, and whether the
+    		// transaction is a data access or an instruction access.
+		input wire [2 : 0] S_AXI_ARPROT,
+		// Read address valid. This signal indicates that the channel
+    		// is signaling valid read address and control information.
+		input wire  S_AXI_ARVALID,
+		// Read address ready. This signal indicates that the slave is
+    		// ready to accept an address and associated control signals.
+		output wire  S_AXI_ARREADY,
+		// Read data (issued by slave)
+		output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
+		// Read response. This signal indicates the status of the
+    		// read transfer.
+		output wire [1 : 0] S_AXI_RRESP,
+		// Read valid. This signal indicates that the channel is
+    		// signaling the required read data.
+		output wire  S_AXI_RVALID,
+		// Read ready. This signal indicates that the master can
+    		// accept the read data and response information.
+		input wire  S_AXI_RREADY
+	);
+
+	// AXI4LITE signals
+	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
+	reg  	axi_awready;
+	reg  	axi_wready;
+	reg [1 : 0] 	axi_bresp;
+	reg  	axi_bvalid;
+	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
+	reg  	axi_arready;
+	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
+	reg [1 : 0] 	axi_rresp;
+	reg  	axi_rvalid;
+
+	// Example-specific design signals
+	// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
+	// ADDR_LSB is used for addressing 32/64 bit registers/memories
+	// ADDR_LSB = 2 for 32 bits (n downto 2)
+	// ADDR_LSB = 3 for 64 bits (n downto 3)
+	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
+	localparam integer OPT_MEM_ADDR_BITS = 1;
+	//----------------------------------------------
+	//-- Signals for user logic register space example
+	//------------------------------------------------
+	//-- Number of Slave Registers 4
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg0;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg1;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg2;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg3;
+	wire	 slv_reg_rden;
+	wire	 slv_reg_wren;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
+	integer	 byte_index;
+	reg	 aw_en;
+
+	// I/O Connections assignments
+
+	assign S_AXI_AWREADY	= axi_awready;
+	assign S_AXI_WREADY	= axi_wready;
+	assign S_AXI_BRESP	= axi_bresp;
+	assign S_AXI_BVALID	= axi_bvalid;
+	assign S_AXI_ARREADY	= axi_arready;
+	assign S_AXI_RDATA	= axi_rdata;
+	assign S_AXI_RRESP	= axi_rresp;
+	assign S_AXI_RVALID	= axi_rvalid;
+	// Implement axi_awready generation
+	// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
+	// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
+	// de-asserted when reset is low.
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_awready <= 1'b0;
+	      aw_en <= 1'b1;
+	    end 
+	  else
+	    begin    
+	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
+	        begin
+	          // slave is ready to accept write address when 
+	          // there is a valid write address and write data
+	          // on the write address and data bus. This design 
+	          // expects no outstanding transactions. 
+	          axi_awready <= 1'b1;
+	          aw_en <= 1'b0;
+	        end
+	        else if (S_AXI_BREADY && axi_bvalid)
+	            begin
+	              aw_en <= 1'b1;
+	              axi_awready <= 1'b0;
+	            end
+	      else           
+	        begin
+	          axi_awready <= 1'b0;
+	        end
+	    end 
+	end       
+
+	// Implement axi_awaddr latching
+	// This process is used to latch the address when both 
+	// S_AXI_AWVALID and S_AXI_WVALID are valid. 
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_awaddr <= 0;
+	    end 
+	  else
+	    begin    
+	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
+	        begin
+	          // Write Address latching 
+	          axi_awaddr <= S_AXI_AWADDR;
+	        end
+	    end 
+	end       
+
+	// Implement axi_wready generation
+	// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
+	// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is 
+	// de-asserted when reset is low. 
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_wready <= 1'b0;
+	    end 
+	  else
+	    begin    
+	      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
+	        begin
+	          // slave is ready to accept write data when 
+	          // there is a valid write address and write data
+	          // on the write address and data bus. This design 
+	          // expects no outstanding transactions. 
+	          axi_wready <= 1'b1;
+	        end
+	      else
+	        begin
+	          axi_wready <= 1'b0;
+	        end
+	    end 
+	end       
+
+	// Implement memory mapped register select and write logic generation
+	// The write data is accepted and written to memory mapped registers when
+	// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
+	// select byte enables of slave registers while writing.
+	// These registers are cleared when reset (active low) is applied.
+	// Slave register write enable is asserted when valid address and data are available
+	// and the slave is ready to accept the write address and write data.
+	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      slv_reg0 <= 0;
+	      slv_reg1 <= 0;
+	      slv_reg2 <= 0;
+	      slv_reg3 <= 0;
+	    end 
+	  else begin
+	    if (slv_reg_wren)
+	      begin
+	        case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
+	          2'h0:
+	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+	                // Respective byte enables are asserted as per write strobes 
+	                // Slave register 0
+	                slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+	              end  
+	          2'h1:
+	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+	                // Respective byte enables are asserted as per write strobes 
+	                // Slave register 1
+	                slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+	              end  
+	          2'h2:
+	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+	                // Respective byte enables are asserted as per write strobes 
+	                // Slave register 2
+	                slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+	              end  
+	          2'h3:
+	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+	                // Respective byte enables are asserted as per write strobes 
+	                // Slave register 3
+	                slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+	              end  
+	          default : begin
+	                      slv_reg0 <= slv_reg0;
+	                      slv_reg1 <= slv_reg1;
+	                      slv_reg2 <= slv_reg2;
+	                      slv_reg3 <= slv_reg3;
+	                    end
+	        endcase
+	      end
+	  end
+	end    
+
+	// Implement write response logic generation
+	// The write response and response valid signals are asserted by the slave 
+	// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.  
+	// This marks the acceptance of address and indicates the status of 
+	// write transaction.
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_bvalid  <= 0;
+	      axi_bresp   <= 2'b0;
+	    end 
+	  else
+	    begin    
+	      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
+	        begin
+	          // indicates a valid write response is available
+	          axi_bvalid <= 1'b1;
+	          axi_bresp  <= 2'b0; // 'OKAY' response 
+	        end                   // work error responses in future
+	      else
+	        begin
+	          if (S_AXI_BREADY && axi_bvalid) 
+	            //check if bready is asserted while bvalid is high) 
+	            //(there is a possibility that bready is always asserted high)   
+	            begin
+	              axi_bvalid <= 1'b0; 
+	            end  
+	        end
+	    end
+	end   
+
+	// Implement axi_arready generation
+	// axi_arready is asserted for one S_AXI_ACLK clock cycle when
+	// S_AXI_ARVALID is asserted. axi_awready is 
+	// de-asserted when reset (active low) is asserted. 
+	// The read address is also latched when S_AXI_ARVALID is 
+	// asserted. axi_araddr is reset to zero on reset assertion.
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_arready <= 1'b0;
+	      axi_araddr  <= 32'b0;
+	    end 
+	  else
+	    begin    
+	      if (~axi_arready && S_AXI_ARVALID)
+	        begin
+	          // indicates that the slave has acceped the valid read address
+	          axi_arready <= 1'b1;
+	          // Read address latching
+	          axi_araddr  <= S_AXI_ARADDR;
+	        end
+	      else
+	        begin
+	          axi_arready <= 1'b0;
+	        end
+	    end 
+	end       
+
+	// Implement axi_arvalid generation
+	// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both 
+	// S_AXI_ARVALID and axi_arready are asserted. The slave registers 
+	// data are available on the axi_rdata bus at this instance. The 
+	// assertion of axi_rvalid marks the validity of read data on the 
+	// bus and axi_rresp indicates the status of read transaction.axi_rvalid 
+	// is deasserted on reset (active low). axi_rresp and axi_rdata are 
+	// cleared to zero on reset (active low).  
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_rvalid <= 0;
+	      axi_rresp  <= 0;
+	    end 
+	  else
+	    begin    
+	      if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
+	        begin
+	          // Valid read data is available at the read data bus
+	          axi_rvalid <= 1'b1;
+	          axi_rresp  <= 2'b0; // 'OKAY' response
+	        end   
+	      else if (axi_rvalid && S_AXI_RREADY)
+	        begin
+	          // Read data is accepted by the master
+	          axi_rvalid <= 1'b0;
+	        end                
+	    end
+	end    
+
+	// Implement memory mapped register select and read logic generation
+	// Slave register read enable is asserted when valid address is available
+	// and the slave is ready to accept the read address.
+	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
+	always @(*)
+	begin
+	      // Address decoding for reading registers
+	      case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
+	        2'h0   : reg_data_out <= slv_reg0;
+	        2'h1   : reg_data_out <= slv_reg1;
+	        2'h2   : reg_data_out <= slv_reg2;
+	        2'h3   : reg_data_out <= slv_reg3;
+	        default : reg_data_out <= 0;
+	      endcase
+	end
+
+	// Output register or memory read data
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_rdata  <= 0;
+	    end 
+	  else
+	    begin    
+	      // When there is a valid read address (S_AXI_ARVALID) with 
+	      // acceptance of read address by the slave (axi_arready), 
+	      // output the read dada 
+	      if (slv_reg_rden)
+	        begin
+	          axi_rdata <= reg_data_out;     // register read data
+	        end   
+	    end
+	end    
+	
+	wire capture_cdc;
+	wire [25:0] length_cdc;
+	
+	   xpm_cdc_array_single #(
+      .DEST_SYNC_FF(4),   // DECIMAL; range: 2-10
+      .INIT_SYNC_FF(0),   // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
+      .SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      .SRC_INPUT_REG(1),  // DECIMAL; 0=do not register input, 1=register input
+      .WIDTH(1)           // DECIMAL; range: 1-1024
+   )
+   xpm_cdc_array_single_inst0 (
+      .dest_out(capture_cdc), // WIDTH-bit output: src_in synchronized to the destination clock domain. This
+                           // output is registered.
+
+      .dest_clk(aclk), // 1-bit input: Clock signal for the destination clock domain.
+      .src_clk(S_AXI_ACLK),   // 1-bit input: optional; required when SRC_INPUT_REG = 1
+      .src_in(slv_reg0[0])      // WIDTH-bit input: Input single-bit array to be synchronized to destination clock
+                           // domain. It is assumed that each bit of the array is unrelated to the others. This
+                           // is reflected in the constraints applied to this macro. To transfer a binary value
+                           // losslessly across the two clock domains, use the XPM_CDC_GRAY macro instead.
+
+   );
+   
+   	   xpm_cdc_array_single #(
+      .DEST_SYNC_FF(4),   // DECIMAL; range: 2-10
+      .INIT_SYNC_FF(0),   // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
+      .SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      .SRC_INPUT_REG(1),  // DECIMAL; 0=do not register input, 1=register input
+      .WIDTH(26)           // DECIMAL; range: 1-1024
+   )
+   xpm_cdc_array_single_inst1 (
+      .dest_out(length_cdc), // WIDTH-bit output: src_in synchronized to the destination clock domain. This
+                           // output is registered.
+
+      .dest_clk(aclk), // 1-bit input: Clock signal for the destination clock domain.
+      .src_clk(S_AXI_ACLK),   // 1-bit input: optional; required when SRC_INPUT_REG = 1
+      .src_in(slv_reg1[25:0])      // WIDTH-bit input: Input single-bit array to be synchronized to destination clock
+                           // domain. It is assumed that each bit of the array is unrelated to the others. This
+                           // is reflected in the constraints applied to this macro. To transfer a binary value
+                           // losslessly across the two clock domains, use the XPM_CDC_GRAY macro instead.
+
+   );
+   
+	
+	// Add user logic here
+    axis_adc_data_packer axis_adc_data_packer(
+    .aclk(aclk),
+    .aresetn(aresetn),
+    .axis_tvalid(axis_tvalid),
+    .axis_ready(axis_ready),
+    .axis_tdata(axis_tdata),
+    .capture(capture_cdc),
+    .length(length_cdc),
+    .m_axis_tvalid(m_axis_tvalid),
+    .m_axis_tlast(m_axis_tlast),
+    .m_axis_ready(m_axis_ready),
+    .m_axis_tdata(m_axis_tdata)     
+    );
+	// User logic ends
+
+	endmodule

cx9261a_demo_cmos_20240513/ip_repo/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v

@@ -0,0 +1,104 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2021/09/07 14:33:53
+// Design Name: 
+// Module Name: axis_adc_data_packer
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module axis_adc_data_packer(
+aclk,aresetn,axis_tvalid,axis_ready,axis_tdata,
+capture,length,
+m_axis_tvalid,m_axis_tlast,m_axis_ready,m_axis_tdata
+    );
+    input wire aclk;
+    input wire aresetn;
+    input wire axis_tvalid;
+    output reg axis_ready;
+    input wire [63:0] axis_tdata;
+    
+    input capture;
+    input [25:0] length; 
+   
+    output reg m_axis_tvalid;
+    output reg m_axis_tlast;
+    input wire m_axis_ready;
+    output reg [63:0] m_axis_tdata;
+    
+    reg [7:0]capture_d;
+    always@(posedge aclk)begin
+        if(~aresetn)begin
+            capture_d<='d0;
+        end
+        begin
+            capture_d<={capture_d[6:0],capture};
+        end
+    end
+    
+       (* keep="true" *)reg [25:0] cnt;
+       (* keep="true" *)reg [7:0] state;
+    always@(posedge aclk)begin
+        if(~aresetn)begin
+            cnt<='d0;
+            axis_ready<='d0;
+            m_axis_tvalid<='d0;
+            m_axis_tlast<='d0;
+            m_axis_tdata<='d0;      
+            state  <='d0;   
+        end
+        else begin
+            case(state)
+            0:begin
+            m_axis_tlast<=1'b0;
+            m_axis_tvalid<=1'b0;
+			m_axis_tdata<=m_axis_tdata;
+			cnt<='d0;
+                if(capture_d == 8'b01111111)begin
+                    state<=1;
+                end
+				else state<=0;
+            end
+            1:begin
+              if(axis_tvalid)begin
+                m_axis_tdata<=axis_tdata;
+                m_axis_tvalid<=axis_tvalid;
+                if(cnt >= (length-1))begin
+                    cnt<='d0;
+                    state<='d0;
+                    m_axis_tlast<=1'b1;
+                end
+                else begin
+                    cnt<=cnt+1'b1;
+                    m_axis_tlast<=1'b0;
+                end
+              end
+              else begin
+                m_axis_tdata<=m_axis_tdata;
+                m_axis_tvalid<=1'b0;
+                m_axis_tlast<=1'b0;              
+              end  
+            end
+			default:begin
+				state<='d0;
+			end
+            endcase
+        
+        
+        end
+        
+    end     
+    endmodule

cx9261a_demo_cmos_20240513/ip_repo/Axis_adc_data_packer_1.0/xgui/Axis_adc_data_packer_v1_0.tcl

@@ -0,0 +1,62 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  set C_S00_AXI_DATA_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox]
+  set_property tooltip {Width of S_AXI data bus} ${C_S00_AXI_DATA_WIDTH}
+  set C_S00_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}]
+  set_property tooltip {Width of S_AXI address bus} ${C_S00_AXI_ADDR_WIDTH}
+  ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+	# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+	# Procedure called to validate C_S00_AXI_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+	# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+	# Procedure called to validate C_S00_AXI_ADDR_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
+	# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
+	# Procedure called to validate C_S00_AXI_BASEADDR
+	return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
+	# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
+	# Procedure called to validate C_S00_AXI_HIGHADDR
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
+}
+

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cx9261a_demo_cmos_20240513/ip_repo/edit_Axis_adc_data_packer_v1_0.cache/wt/webtalk_pa.xml

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+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Fri Dec 24 10:35:31 2021">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="8b6833958267472dad005008c4feb711" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+<item name="Java Command Handlers">
+<property name="AddBusInterfaceHandler" value="2" type="JavaHandler"/>
+<property name="EditUndo" value="7" type="JavaHandler"/>
+<property name="FlipToViewTaskSynthesis" value="1" type="JavaHandler"/>
+<property name="IPPackagerHandler" value="6" type="JavaHandler"/>
+<property name="ReportClockInteraction" value="1" type="JavaHandler"/>
+<property name="RunSchematic" value="7" type="JavaHandler"/>
+<property name="RunSynthesis" value="2" type="JavaHandler"/>
+<property name="SaveFileProxyHandler" value="1" type="JavaHandler"/>
+<property name="TimingConstraintsWizard" value="1" type="JavaHandler"/>
+<property name="ToolsSettings" value="1" type="JavaHandler"/>
+<property name="ToolsTemplates" value="2" type="JavaHandler"/>
+<property name="ViewTaskProjectManager" value="1" type="JavaHandler"/>
+<property name="ViewTaskSynthesis" value="1" type="JavaHandler"/>
+</item>
+<item name="Gui Handlers">
+<property name="AbstractSearchablePanel_SHOW_SEARCH" value="2" type="GuiHandlerData"/>
+<property name="BaseDialog_CANCEL" value="24" type="GuiHandlerData"/>
+<property name="BaseDialog_OK" value="26" type="GuiHandlerData"/>
+<property name="ConstraintsChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
+<property name="ConstraintsChooserPanel_FILE_TABLE" value="1" type="GuiHandlerData"/>
+<property name="CreateConstraintsFilePanel_FILE_NAME" value="1" type="GuiHandlerData"/>
+<property name="EditInterfaceDialog_TABBED_PANE" value="10" type="GuiHandlerData"/>
+<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="25" type="GuiHandlerData"/>
+<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="11" type="GuiHandlerData"/>
+<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="12" type="GuiHandlerData"/>
+<property name="InterfaceConfigurationPanel_NAME" value="3" type="GuiHandlerData"/>
+<property name="InterfaceDefinitionChooser_INTERFACE_DEFINITION_CHOOSER" value="1" type="GuiHandlerData"/>
+<property name="InterfaceDefinitionTreeTable_INTERFACES_TREE_TABLE" value="1" type="GuiHandlerData"/>
+<property name="InterfacePortMappingPanel_INTERFACES_LOGICAL_PORTS" value="4" type="GuiHandlerData"/>
+<property name="InterfacePortMappingPanel_IPS_PHYSICAL_PORTS" value="3" type="GuiHandlerData"/>
+<property name="InterfacePortMappingPanel_MAP_PORTS" value="1" type="GuiHandlerData"/>
+<property name="LanguageTemplatesDialog_TEMPLATES_TREE" value="6" type="GuiHandlerData"/>
+<property name="MessageBanner_CHANGES_DETECTED_IN_IP_THAT_REQUIRE" value="1" type="GuiHandlerData"/>
+<property name="MessageBanner_CHANGES_DETECTED_IN_VIVADO_PROJECT_THAT" value="4" type="GuiHandlerData"/>
+<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="7" type="GuiHandlerData"/>
+<property name="MsgView_CLEAR_MESSAGES_RESULTING_FROM_USER_EXECUTED" value="1" type="GuiHandlerData"/>
+<property name="NetlistTreeView_NETLIST_TREE" value="12" type="GuiHandlerData"/>
+<property name="PACommandNames_GOTO_NETLIST_DESIGN" value="1" type="GuiHandlerData"/>
+<property name="PACommandNames_PACKAGER_ADD_BUS_INTERFACE" value="2" type="GuiHandlerData"/>
+<property name="PAViews_PACKAGE" value="1" type="GuiHandlerData"/>
+<property name="PAViews_PACKAGE_IP" value="2" type="GuiHandlerData"/>
+<property name="PAViews_PROJECT_SUMMARY" value="2" type="GuiHandlerData"/>
+<property name="PAViews_SCHEMATIC" value="2" type="GuiHandlerData"/>
+<property name="PackagerStepContentPanel_MESSAGES" value="5" type="GuiHandlerData"/>
+<property name="PackagerStepsPanel_PACKAGER_STEPS_LIST" value="34" type="GuiHandlerData"/>
+<property name="PortAndInterfaceContentPanel_REFRESH" value="21" type="GuiHandlerData"/>
+<property name="PortAndInterfaceFacetTable_ASSOCIATE_CLOCKS" value="43" type="GuiHandlerData"/>
+<property name="PortAndInterfaceFacetTable_EDIT_INTERFACE" value="3" type="GuiHandlerData"/>
+<property name="PortAndInterfaceFacetTable_PORT_AND_INTERFACE_FACET_TABLE" value="218" type="GuiHandlerData"/>
+<property name="PortAndInterfaceFacetTable_REMOVE_INTERFACE" value="1" type="GuiHandlerData"/>
+<property name="ReviewContentPanel_EDIT_PACKAGING_SETTINGS" value="1" type="GuiHandlerData"/>
+<property name="ReviewContentPanel_RE_PACKAGE_IP" value="2" type="GuiHandlerData"/>
+<property name="SaveProjectUtils_DONT_SAVE" value="1" type="GuiHandlerData"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="242" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="185" type="TclMode"/>
+</item>
+</section>
+</application>
+</document>

cx9261a_demo_cmos_20240513/ip_repo/edit_Axis_adc_data_packer_v1_0.hw/edit_Axis_adc_data_packer_v1_0.lpr

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2018.3 (64-bit)                     -->
+<!--                                                              -->
+<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0"/>

cx9261a_demo_cmos_20240513/ip_repo/edit_Axis_adc_data_packer_v1_0.ip_user_files/README.txt

@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

cx9261a_demo_cmos_20240513/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/.jobs/vrs_config_1.xml

@@ -0,0 +1,8 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+

cx9261a_demo_cmos_20240513/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/.jobs/vrs_config_2.xml

@@ -0,0 +1,8 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+

cx9261a_demo_cmos_20240513/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/.vivado.begin.rst

@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command="vivado.bat" Owner="swang" Host="HPZ240A" Pid="8716">
+    </Process>
+</ProcessHandle>

cx9261a_demo_cmos_20240513/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/Axis_adc_data_packer_v1_0.tcl

@@ -0,0 +1,67 @@
+# 
+# Synthesis run script generated by Vivado
+# 
+
+set TIME_start [clock seconds] 
+proc create_report { reportName command } {
+  set status "."
+  append status $reportName ".fail"
+  if { [file exists $status] } {
+    eval file delete [glob $status]
+  }
+  send_msg_id runtcl-4 info "Executing : $command"
+  set retval [eval catch { $command } msg]
+  if { $retval != 0 } {
+    set fp [open $status w]
+    close $fp
+    send_msg_id runtcl-5 warning "$msg"
+  }
+}
+set_param power.BramSDPPropagationFix 1
+set_param power.enableUnconnectedCarry8PinPower 1
+set_param power.enableCarry8RouteBelPower 1
+set_param power.enableLutRouteBelPower 1
+set_msg_config -id {HDL-1065} -limit 10000
+create_project -in_memory -part xczu7ev-ffvc1156-2-e
+
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_property webtalk.parent_dir C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.cache/wt [current_project]
+set_property parent.project_path C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.xpr [current_project]
+set_property XPM_LIBRARIES XPM_CDC [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language Verilog [current_project]
+set_property board_part xilinx.com:zcu106:part0:2.3 [current_project]
+set_property ip_repo_paths c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work [current_project]
+update_ip_catalog
+set_property ip_output_repo c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.cache/ip [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+read_verilog -library "" {
+  C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v
+  C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v
+}
+read_verilog -library xil_defaultlib C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v
+# Mark all dcp files as not used in implementation to prevent them from being
+# stitched into the results of this synthesis run. Any black boxes in the
+# design are intentionally left as such for best results. Dcp files will be
+# stitched into the design at a later time, either when this synthesis run is
+# opened, or when it is stitched into a dependent implementation run.
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
+  set_property used_in_implementation false $dcp
+}
+read_xdc C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.srcs/constrs_1/new/constrains.xdc
+set_property used_in_implementation false [get_files C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.srcs/constrs_1/new/constrains.xdc]
+
+set_param ips.enableIPCacheLiteLoad 1
+close [open __synthesis_is_running__ w]
+
+synth_design -top Axis_adc_data_packer_v1_0 -part xczu7ev-ffvc1156-2-e
+
+
+# disable binary constraint mode for synth run checkpoints
+set_param constraints.enableBinaryConstraints false
+write_checkpoint -force -noxdef Axis_adc_data_packer_v1_0.dcp
+create_report "synth_1_synth_report_utilization_0" "report_utilization -file Axis_adc_data_packer_v1_0_utilization_synth.rpt -pb Axis_adc_data_packer_v1_0_utilization_synth.pb"
+file delete __synthesis_is_running__
+close [open __synthesis_is_complete__ w]

cx9261a_demo_cmos_20240513/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/Axis_adc_data_packer_v1_0.vds

@@ -0,0 +1,410 @@
+#-----------------------------------------------------------
+# Vivado v2018.3 (64-bit)
+# SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
+# IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
+# Start of session at: Thu Dec 23 15:59:40 2021
+# Process ID: 9796
+# Current directory: C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1
+# Command line: vivado.exe -log Axis_adc_data_packer_v1_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Axis_adc_data_packer_v1_0.tcl
+# Log file: C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1/Axis_adc_data_packer_v1_0.vds
+# Journal file: C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1\vivado.jou
+#-----------------------------------------------------------
+source Axis_adc_data_packer_v1_0.tcl -notrace
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work'.
+WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1'.)
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/xilinx/Vivado/2018.3/data/ip'.
+WARNING: [IP_Flow 19-4995] The host OS only allows 260 characters in a normal path. The IP cache path is more than 80 characters. If you experience issues with IP caching, please consider changing the IP cache to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. 
+Current IP cache path is c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.cache/ip 
+WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:]
+WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v:]
+Command: synth_design -top Axis_adc_data_packer_v1_0 -part xczu7ev-ffvc1156-2-e
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xczu7ev'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu7ev'
+INFO: Launching helper process for spawning children vivado processes
+INFO: Helper process launched with PID 1944 
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 465.340 ; gain = 103.711
+---------------------------------------------------------------------------------
+INFO: [Synth 8-6157] synthesizing module 'Axis_adc_data_packer_v1_0' [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v:3]
+	Parameter C_S00_AXI_DATA_WIDTH bound to: 32 - type: integer 
+	Parameter C_S00_AXI_ADDR_WIDTH bound to: 4 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'Axis_adc_data_packer_v1_0_S00_AXI' [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:3]
+	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
+	Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer 
+	Parameter ADDR_LSB bound to: 2 - type: integer 
+	Parameter OPT_MEM_ADDR_BITS bound to: 1 - type: integer 
+INFO: [Synth 8-226] default block is never used [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:240]
+INFO: [Synth 8-226] default block is never used [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:381]
+INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_array_single' [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
+	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
+	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
+	Parameter SRC_INPUT_REG bound to: 1 - type: integer 
+	Parameter VERSION bound to: 0 - type: integer 
+	Parameter WIDTH bound to: 1 - type: integer 
+INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:958]
+INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_array_single' (1#1) [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_array_single__parameterized0' [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
+	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
+	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
+	Parameter SRC_INPUT_REG bound to: 1 - type: integer 
+	Parameter VERSION bound to: 0 - type: integer 
+	Parameter WIDTH bound to: 26 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_array_single__parameterized0' (1#1) [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+INFO: [Synth 8-6157] synthesizing module 'axis_adc_data_packer' [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:23]
+INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:52]
+INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:53]
+INFO: [Synth 8-6155] done synthesizing module 'axis_adc_data_packer' (2#1) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:23]
+INFO: [Synth 8-6155] done synthesizing module 'Axis_adc_data_packer_v1_0_S00_AXI' (3#1) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:3]
+INFO: [Synth 8-6155] done synthesizing module 'Axis_adc_data_packer_v1_0' (4#1) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v:3]
+WARNING: [Synth 8-3331] design axis_adc_data_packer has unconnected port m_axis_ready
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_AWPROT[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_AWPROT[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_AWPROT[0]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_ARPROT[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_ARPROT[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_ARPROT[0]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port axis_tlast
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 515.703 ; gain = 154.074
+---------------------------------------------------------------------------------
+
+Report Check Netlist: 
++------+------------------+-------+---------+-------+------------------+
+|      |Item              |Errors |Warnings |Status |Description       |
++------+------------------+-------+---------+-------+------------------+
+|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 515.703 ; gain = 154.074
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 515.703 ; gain = 154.074
+---------------------------------------------------------------------------------
+INFO: [Device 21-403] Loading part xczu7ev-ffvc1156-2-e
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.srcs/constrs_1/new/constrains.xdc]
+Finished Parsing XDC File [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.srcs/constrs_1/new/constrains.xdc]
+Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst0'
+Finished Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst0'
+Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst1'
+Finished Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst1'
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/Axis_adc_data_packer_v1_0_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/Axis_adc_data_packer_v1_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1584.711 ; gain = 0.000
+WARNING: [Constraints 18-5210] No constraints selected for write.
+Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1584.711 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1584.711 ; gain = 0.000
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1584.711 ; gain = 0.000
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xczu7ev-ffvc1156-2-e
+INFO: [Synth 8-6742] Reading net delay rules and data
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property DONT_TOUCH = true for Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst0. (constraint file  auto generated constraint, line ).
+Applied set_property DONT_TOUCH = true for Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst1. (constraint file  auto generated constraint, line ).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axis_adc_data_packer'
+INFO: [Synth 8-5546] ROM "cnt" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-6159] Found Keep on FSM register 'state_reg' in module 'axis_adc_data_packer', re-encoding will not be performed
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+*
+                  iSTATE |                         00000000 |                         00000000
+                 iSTATE0 |                         00000001 |                         00000001
+---------------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start RTL Component Statistics 
+---------------------------------------------------------------------------------
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input     32 Bit       Adders := 1     
+	   2 Input     26 Bit       Adders := 1     
++---Registers : 
+	               64 Bit    Registers := 1     
+	               32 Bit    Registers := 5     
+	               26 Bit    Registers := 6     
+	                8 Bit    Registers := 1     
+	                4 Bit    Registers := 2     
+	                2 Bit    Registers := 2     
+	                1 Bit    Registers := 14    
++---Muxes : 
+	   2 Input     32 Bit        Muxes := 4     
+	   4 Input     32 Bit        Muxes := 5     
+	   2 Input     26 Bit        Muxes := 4     
+	   3 Input      8 Bit        Muxes := 1     
+	   2 Input      8 Bit        Muxes := 2     
+	   2 Input      1 Bit        Muxes := 14    
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics 
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Hierarchical Component Statistics 
+---------------------------------------------------------------------------------
+Hierarchical RTL Component report 
+Module xpm_cdc_array_single 
+Detailed RTL Component Info : 
++---Registers : 
+	                1 Bit    Registers := 5     
+Module xpm_cdc_array_single__parameterized0 
+Detailed RTL Component Info : 
++---Registers : 
+	               26 Bit    Registers := 5     
+Module axis_adc_data_packer 
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input     32 Bit       Adders := 1     
+	   2 Input     26 Bit       Adders := 1     
++---Registers : 
+	               64 Bit    Registers := 1     
+	               26 Bit    Registers := 1     
+	                8 Bit    Registers := 1     
+	                1 Bit    Registers := 3     
++---Muxes : 
+	   2 Input     26 Bit        Muxes := 4     
+	   3 Input      8 Bit        Muxes := 1     
+	   2 Input      8 Bit        Muxes := 2     
+	   2 Input      1 Bit        Muxes := 9     
+Module Axis_adc_data_packer_v1_0_S00_AXI 
+Detailed RTL Component Info : 
++---Registers : 
+	               32 Bit    Registers := 5     
+	                4 Bit    Registers := 2     
+	                2 Bit    Registers := 2     
+	                1 Bit    Registers := 6     
++---Muxes : 
+	   2 Input     32 Bit        Muxes := 4     
+	   4 Input     32 Bit        Muxes := 5     
+	   2 Input      1 Bit        Muxes := 5     
+---------------------------------------------------------------------------------
+Finished RTL Hierarchical Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 1728 (col length:144)
+BRAMs: 624 (col length: RAMB18 144 RAMB36 72)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+Warning: Parallel synthesis criteria is not met 
+INFO: [Synth 8-5546] ROM "Axis_adc_data_packer_v1_0_S00_AXI_inst/axis_adc_data_packer/state" won't be mapped to RAM because it is too sparse
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port axis_tlast
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port m_axis_ready
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_awprot[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_awprot[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_awprot[0]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_arprot[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_arprot[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_arprot[0]
+INFO: [Synth 8-3886] merging instance 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_rresp_reg[0]' (FDRE) to 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_rresp_reg[1]'
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_rresp_reg[1] )
+INFO: [Synth 8-3886] merging instance 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_bresp_reg[0]' (FDRE) to 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_bresp_reg[1]'
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_bresp_reg[1] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Axis_adc_data_packer_v1_0_S00_AXI_inst/axis_adc_data_packer/axis_ready_reg )
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1995.184 ; gain = 1633.555
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1995.496 ; gain = 1633.867
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+
+Report Check Netlist: 
++------+------------------+-------+---------+-------+------------------+
+|      |Item              |Errors |Warnings |Status |Description       |
++------+------------------+-------+---------+-------+------------------+
+|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes: 
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage: 
++------+-------+------+
+|      |Cell   |Count |
++------+-------+------+
+|1     |BUFG   |     2|
+|2     |CARRY8 |    10|
+|3     |LUT1   |    27|
+|4     |LUT2   |     3|
+|5     |LUT3   |     2|
+|6     |LUT4   |    49|
+|7     |LUT5   |    25|
+|8     |LUT6   |    38|
+|9     |FDRE   |   412|
+|10    |FDSE   |     1|
+|11    |IBUF   |   114|
+|12    |OBUF   |   108|
++------+-------+------+
+
+Report Instance Areas: 
++------+-----------------------------------------+-------------------------------------+------+
+|      |Instance                                 |Module                               |Cells |
++------+-----------------------------------------+-------------------------------------+------+
+|1     |top                                      |                                     |   791|
+|2     |  Axis_adc_data_packer_v1_0_S00_AXI_inst |Axis_adc_data_packer_v1_0_S00_AXI    |   567|
+|3     |    xpm_cdc_array_single_inst0           |xpm_cdc_array_single                 |     5|
+|4     |    xpm_cdc_array_single_inst1           |xpm_cdc_array_single__parameterized0 |   130|
+|5     |    axis_adc_data_packer                 |axis_adc_data_packer                 |   205|
++------+-----------------------------------------+-------------------------------------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 8 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 2007.641 ; gain = 577.004
+Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+INFO: [Project 1-571] Translating synthesized netlist
+INFO: [Netlist 29-17] Analyzing 126 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2043.539 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 116 instances were transformed.
+  BUFG => BUFGCE: 2 instances
+  IBUF => IBUF (IBUFCTRL, INBUF): 114 instances
+
+INFO: [Common 17-83] Releasing license: Synthesis
+41 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2043.539 ; gain = 1693.754
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2043.539 ; gain = 0.000
+WARNING: [Constraints 18-5210] No constraints selected for write.
+Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
+INFO: [Common 17-1381] The checkpoint 'C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1/Axis_adc_data_packer_v1_0.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_utilization -file Axis_adc_data_packer_v1_0_utilization_synth.rpt -pb Axis_adc_data_packer_v1_0_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Thu Dec 23 16:00:12 2021...

cx9261a_demo_cmos_20240513/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/Axis_adc_data_packer_v1_0_utilization_synth.rpt

@@ -0,0 +1,189 @@
+Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
+| Date         : Thu Dec 23 16:00:12 2021
+| Host         : HPZ240A running 64-bit Service Pack 1  (build 7601)
+| Command      : report_utilization -file Axis_adc_data_packer_v1_0_utilization_synth.rpt -pb Axis_adc_data_packer_v1_0_utilization_synth.pb
+| Design       : Axis_adc_data_packer_v1_0
+| Device       : xczu7evffvc1156-2
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. CLB Logic
+1.1 Summary of Registers by Type
+2. BLOCKRAM
+3. ARITHMETIC
+4. I/O
+5. CLOCK
+6. ADVANCED
+7. CONFIGURATION
+8. Primitives
+9. Black Boxes
+10. Instantiated Netlists
+
+1. CLB Logic
+------------
+
++-------------------------+------+-------+-----------+-------+
+|        Site Type        | Used | Fixed | Available | Util% |
++-------------------------+------+-------+-----------+-------+
+| CLB LUTs*               |  130 |     0 |    230400 |  0.06 |
+|   LUT as Logic          |  130 |     0 |    230400 |  0.06 |
+|   LUT as Memory         |    0 |     0 |    101760 |  0.00 |
+| CLB Registers           |  413 |     0 |    460800 |  0.09 |
+|   Register as Flip Flop |  413 |     0 |    460800 |  0.09 |
+|   Register as Latch     |    0 |     0 |    460800 |  0.00 |
+| CARRY8                  |   10 |     0 |     28800 |  0.03 |
+| F7 Muxes                |    0 |     0 |    115200 |  0.00 |
+| F8 Muxes                |    0 |     0 |     57600 |  0.00 |
+| F9 Muxes                |    0 |     0 |     28800 |  0.00 |
++-------------------------+------+-------+-----------+-------+
+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0     |            _ |           - |            - |
+| 0     |            _ |           - |          Set |
+| 0     |            _ |           - |        Reset |
+| 0     |            _ |         Set |            - |
+| 0     |            _ |       Reset |            - |
+| 0     |          Yes |           - |            - |
+| 0     |          Yes |           - |          Set |
+| 0     |          Yes |           - |        Reset |
+| 1     |          Yes |         Set |            - |
+| 412   |          Yes |       Reset |            - |
++-------+--------------+-------------+--------------+
+
+
+2. BLOCKRAM
+-----------
+
++----------------+------+-------+-----------+-------+
+|    Site Type   | Used | Fixed | Available | Util% |
++----------------+------+-------+-----------+-------+
+| Block RAM Tile |    0 |     0 |       312 |  0.00 |
+|   RAMB36/FIFO* |    0 |     0 |       312 |  0.00 |
+|   RAMB18       |    0 |     0 |       624 |  0.00 |
+| URAM           |    0 |     0 |        96 |  0.00 |
++----------------+------+-------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2
+
+
+3. ARITHMETIC
+-------------
+
++-----------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++-----------+------+-------+-----------+-------+
+| DSPs      |    0 |     0 |      1728 |  0.00 |
++-----------+------+-------+-----------+-------+
+
+
+4. I/O
+------
+
++------------+------+-------+-----------+-------+
+|  Site Type | Used | Fixed | Available | Util% |
++------------+------+-------+-----------+-------+
+| Bonded IOB |  222 |     0 |       360 | 61.67 |
++------------+------+-------+-----------+-------+
+
+
+5. CLOCK
+--------
+
++----------------------+------+-------+-----------+-------+
+|       Site Type      | Used | Fixed | Available | Util% |
++----------------------+------+-------+-----------+-------+
+| GLOBAL CLOCK BUFFERs |    2 |     0 |       544 |  0.37 |
+|   BUFGCE             |    2 |     0 |       208 |  0.96 |
+|   BUFGCE_DIV         |    0 |     0 |        32 |  0.00 |
+|   BUFG_GT            |    0 |     0 |       144 |  0.00 |
+|   BUFG_PS            |    0 |     0 |        96 |  0.00 |
+|   BUFGCTRL*          |    0 |     0 |        64 |  0.00 |
+| PLL                  |    0 |     0 |        16 |  0.00 |
+| MMCM                 |    0 |     0 |         8 |  0.00 |
++----------------------+------+-------+-----------+-------+
+* Note: Each used BUFGCTRL counts as two global buffer resources. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.
+
+
+6. ADVANCED
+-----------
+
++-----------------+------+-------+-----------+-------+
+|    Site Type    | Used | Fixed | Available | Util% |
++-----------------+------+-------+-----------+-------+
+| GTHE4_CHANNEL   |    0 |     0 |        20 |  0.00 |
+| GTHE4_COMMON    |    0 |     0 |         5 |  0.00 |
+| OBUFDS_GTE4     |    0 |     0 |        10 |  0.00 |
+| OBUFDS_GTE4_ADV |    0 |     0 |        10 |  0.00 |
+| PCIE40E4        |    0 |     0 |         2 |  0.00 |
+| PS8             |    0 |     0 |         1 |  0.00 |
+| SYSMONE4        |    0 |     0 |         1 |  0.00 |
+| VCU             |    0 |     0 |         1 |  0.00 |
++-----------------+------+-------+-----------+-------+
+
+
+7. CONFIGURATION
+----------------
+
++-------------+------+-------+-----------+-------+
+|  Site Type  | Used | Fixed | Available | Util% |
++-------------+------+-------+-----------+-------+
+| BSCANE2     |    0 |     0 |         4 |  0.00 |
+| DNA_PORTE2  |    0 |     0 |         1 |  0.00 |
+| EFUSE_USR   |    0 |     0 |         1 |  0.00 |
+| FRAME_ECCE4 |    0 |     0 |         1 |  0.00 |
+| ICAPE3      |    0 |     0 |         2 |  0.00 |
+| MASTER_JTAG |    0 |     0 |         1 |  0.00 |
+| STARTUPE3   |    0 |     0 |         1 |  0.00 |
++-------------+------+-------+-----------+-------+
+
+
+8. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+| FDRE     |  412 |            Register |
+| INBUF    |  114 |                 I/O |
+| IBUFCTRL |  114 |              Others |
+| OBUF     |  108 |                 I/O |
+| LUT4     |   49 |                 CLB |
+| LUT6     |   38 |                 CLB |
+| LUT1     |   27 |                 CLB |
+| LUT5     |   25 |                 CLB |
+| CARRY8   |   10 |                 CLB |
+| LUT2     |    3 |                 CLB |
+| LUT3     |    2 |                 CLB |
+| BUFGCE   |    2 |               Clock |
+| FDSE     |    1 |            Register |
++----------+------+---------------------+
+
+
+9. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+10. Instantiated Netlists
+-------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+

cx9261a_demo_cmos_20240513/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/ISEWrap.js

@@ -0,0 +1,244 @@
+//
+//  Vivado(TM)
+//  ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+//  Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. 
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+  // 1. RUN DIR setup
+  var ISEScrFP = WScript.ScriptFullName;
+  var ISEScrN = WScript.ScriptName;
+  ISERunDir = 
+    ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+  // 2. LOG file setup
+  ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  // 3. LOG echo?
+  var ISEScriptArgs = WScript.Arguments;
+  for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+    if ( ISEScriptArgs(loopi) == "-quiet" ) {
+      ISELogEcho = false;
+      break;
+    }
+  }
+
+  // 4. WSH version check
+  var ISEOptimalVersionWSH = 5.6;
+  var ISECurrentVersionWSH = WScript.Version;
+  if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+    ISEStdErr( "" );
+    ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+	       ISEOptimalVersionWSH + " or higher. Downloads" );
+    ISEStdErr( "         for upgrading your Windows Scripting Host can be found here: " );
+    ISEStdErr( "             http://msdn.microsoft.com/downloads/list/webdev.asp" );
+    ISEStdErr( "" );
+
+    ISEOldVersionWSH = true;
+  }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+  // CHECK for a STOP FILE
+  if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+    ISEStdErr( "" );
+    ISEStdErr( "*** Halting run - EA reset detected ***" );
+    ISEStdErr( "" );
+    WScript.Quit( 1 );
+  }
+
+  // WRITE STEP HEADER to LOG
+  ISEStdOut( "" );
+  ISEStdOut( "*** Running " + ISEProg );
+  ISEStdOut( "    with args " + ISEArgs );
+  ISEStdOut( "" );
+
+  // LAUNCH!
+  var ISEExitCode = ISEExec( ISEProg, ISEArgs );  
+  if ( ISEExitCode != 0 ) {
+    WScript.Quit( ISEExitCode );
+  }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+  var ISEStep = ISEProg;
+  if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+    ISEProg += ".bat";
+  }
+
+  var ISECmdLine = ISEProg + " " + ISEArgs;
+  var ISEExitCode = 1;
+
+  if ( ISEOldVersionWSH ) { // WSH 5.1
+
+    // BEGIN file creation
+    ISETouchFile( ISEStep, "begin" );
+
+    // LAUNCH!
+    ISELogFileStr.Close();
+    ISECmdLine = 
+      "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+    ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+    ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  } else {  // WSH 5.6
+
+    // LAUNCH!
+    ISEShell.CurrentDirectory = ISERunDir;
+
+    // Redirect STDERR to STDOUT
+    ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+    var ISEProcess = ISEShell.Exec( ISECmdLine );
+    
+    // BEGIN file creation
+    var ISENetwork = WScript.CreateObject( "WScript.Network" );
+    var ISEHost = ISENetwork.ComputerName;
+    var ISEUser = ISENetwork.UserName;
+    var ISEPid = ISEProcess.ProcessID;
+    var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+    ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+    ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+    ISEBeginFile.WriteLine( "    <Process Command=\"" + ISEProg + 
+			    "\" Owner=\"" + ISEUser + 
+			    "\" Host=\"" + ISEHost + 
+			    "\" Pid=\"" + ISEPid +
+			    "\">" );
+    ISEBeginFile.WriteLine( "    </Process>" );
+    ISEBeginFile.WriteLine( "</ProcessHandle>" );
+    ISEBeginFile.Close();
+    
+    var ISEOutStr = ISEProcess.StdOut;
+    var ISEErrStr = ISEProcess.StdErr;
+    
+    // WAIT for ISEStep to finish
+    while ( ISEProcess.Status == 0 ) {
+      
+      // dump stdout then stderr - feels a little arbitrary
+      while ( !ISEOutStr.AtEndOfStream ) {
+        ISEStdOut( ISEOutStr.ReadLine() );
+      }  
+      
+      WScript.Sleep( 100 );
+    }
+
+    ISEExitCode = ISEProcess.ExitCode;
+  }
+
+  ISELogFileStr.Close();
+
+  // END/ERROR file creation
+  if ( ISEExitCode != 0 ) {    
+    ISETouchFile( ISEStep, "error" );
+    
+  } else {
+    ISETouchFile( ISEStep, "end" );
+  }
+
+  return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+  ISELogFileStr.WriteLine( ISELine );
+  
+  if ( ISELogEcho ) {
+    WScript.StdOut.WriteLine( ISELine );
+  }
+}
+
+function ISEStdErr( ISELine ) {
+  
+  ISELogFileStr.WriteLine( ISELine );
+
+  if ( ISELogEcho ) {
+    WScript.StdErr.WriteLine( ISELine );
+  }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+  var ISETFile = 
+    ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+  ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+  // This function has been updated to deal with a problem seen in CR #870871.
+  // In that case the user runs a script that runs impl_1, and then turns around
+  // and runs impl_1 -to_step write_bitstream. That second run takes place in
+  // the same directory, which means we may hit some of the same files, and in
+  // particular, we will open the runme.log file. Even though this script closes
+  // the file (now), we see cases where a subsequent attempt to open the file
+  // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+  // play? In any case, we try to work around this by first waiting if the file
+  // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+  // and try to open the file 10 times with a one second delay after each attempt.
+  // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+  // If there is an unrecognized exception when trying to open the file, we output
+  // an error message and write details to an exception.log file.
+  var ISEFullPath = ISERunDir + "/" + ISEFilename;
+  if (ISEFileSys.FileExists(ISEFullPath)) {
+    // File is already there. This could be a problem. Wait in case it is still in use.
+    WScript.Sleep(5000);
+  }
+  var i;
+  for (i = 0; i < 10; ++i) {
+    try {
+      return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+    } catch (exception) {
+      var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+      if (error_code == 52) { // 52 is bad file name or number.
+        // Wait a second and try again.
+        WScript.Sleep(1000);
+        continue;
+      } else {
+        WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+        var exceptionFilePath = ISERunDir + "/exception.log";
+        if (!ISEFileSys.FileExists(exceptionFilePath)) {
+          WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+          var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+          exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+          exceptionFile.WriteLine("\tException name: " + exception.name);
+          exceptionFile.WriteLine("\tException error code: " + error_code);
+          exceptionFile.WriteLine("\tException message: " + exception.message);
+          exceptionFile.Close();
+        }
+        throw exception;
+      }
+    }
+  }
+  // If we reached this point, we failed to open the file after 10 attempts.
+  // We need to error out.
+  WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+  WScript.Quit(1);
+}

cx9261a_demo_cmos_20240513/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/ISEWrap.sh

@@ -0,0 +1,63 @@
+#!/bin/sh
+
+#
+#  Vivado(TM)
+#  ISEWrap.sh: Vivado Runs Script for UNIX
+#  Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. 
+#
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo ""                                        >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo ""                                        >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo ""                      >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo "    with args $@"      >> $HD_LOG
+echo ""                      >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+if [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST     #csh
+fi
+ISE_USER=$USER
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>"                                                                     >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">"                                                   >> $ISE_BEGINFILE
+echo "    <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\">" >> $ISE_BEGINFILE
+echo "    </Process>"                                                                              >> $ISE_BEGINFILE
+echo "</ProcessHandle>"                                                                            >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+    /bin/touch .$ISE_STEP.end.rst
+else
+    /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+

cx9261a_demo_cmos_20240513/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/gen_run.xml

@@ -0,0 +1,66 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="synth_1" LaunchPart="xczu7ev-ffvc1156-2-e" LaunchTime="1640246379">
+  <File Type="PA-TCL" Name="Axis_adc_data_packer_v1_0.tcl"/>
+  <File Type="REPORTS-TCL" Name="Axis_adc_data_packer_v1_0_reports.tcl"/>
+  <File Type="RDS-RDS" Name="Axis_adc_data_packer_v1_0.vds"/>
+  <File Type="RDS-UTIL" Name="Axis_adc_data_packer_v1_0_utilization_synth.rpt"/>
+  <File Type="RDS-UTIL-PB" Name="Axis_adc_data_packer_v1_0_utilization_synth.pb"/>
+  <File Type="RDS-DCP" Name="Axis_adc_data_packer_v1_0.dcp"/>
+  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+    <Filter Type="Srcs"/>
+    <File Path="$PPRDIR/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v">
+      <FileInfo>
+        <Attr Name="Library" Val=""/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v">
+      <FileInfo>
+        <Attr Name="Library" Val=""/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/Axis_adc_data_packer_1.0/component.xml">
+      <FileInfo SFType="IPXACT"/>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopModule" Val="Axis_adc_data_packer_v1_0"/>
+      <Option Name="TopRTLFile" Val="$PPRDIR/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PSRCDIR/constrs_1/new/constrains.xdc">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/constrains.xdc"/>
+      <Option Name="ConstrsType" Val="XDC"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+    <Filter Type="Utils"/>
+    <Config>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <Strategy Version="1" Minor="2">
+    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
+    <Step Id="synth_design"/>
+  </Strategy>
+</GenRun>

cx9261a_demo_cmos_20240513/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/htr.txt

@@ -0,0 +1,9 @@
+REM
+REM Vivado(TM)
+REM htr.txt: a Vivado-generated description of how-to-repeat the
+REM          the basic steps of a run.  Note that runme.bat/sh needs
+REM          to be invoked for Vivado to track run status.
+REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+REM
+
+vivado -log Axis_adc_data_packer_v1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Axis_adc_data_packer_v1_0.tcl

cx9261a_demo_cmos_20240513/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/project.wdf

@@ -0,0 +1,31 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:34:00:00
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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
+5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6335643931336632613664323462303262616164333333346666633564313432:506172656e742050412070726f6a656374204944:00
+eof:7738646

cx9261a_demo_cmos_20240513/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/rundef.js

@@ -0,0 +1,36 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+//
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+  PathVal = "D:/xilinx/SDK/2018.3/bin;D:/xilinx/Vivado/2018.3/ids_lite/ISE/bin/nt64;D:/xilinx/Vivado/2018.3/ids_lite/ISE/lib/nt64;D:/xilinx/Vivado/2018.3/bin;";
+} else {
+  PathVal = "D:/xilinx/SDK/2018.3/bin;D:/xilinx/Vivado/2018.3/ids_lite/ISE/bin/nt64;D:/xilinx/Vivado/2018.3/ids_lite/ISE/lib/nt64;D:/xilinx/Vivado/2018.3/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+ISEStep( "vivado",
+         "-log Axis_adc_data_packer_v1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Axis_adc_data_packer_v1_0.tcl" );
+
+
+
+function EAInclude( EAInclFilename ) {
+  var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+  var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+  var EAIFContents = EAInclFile.ReadAll();
+  EAInclFile.Close();
+  return EAIFContents;
+}

cx9261a_demo_cmos_20240513/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/runme.bat

@@ -0,0 +1,10 @@
+@echo off
+
+rem  Vivado (TM)
+rem  runme.bat: a Vivado-generated Script
+rem  Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*

cx9261a_demo_cmos_20240513/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/runme.log

@@ -0,0 +1,417 @@
+
+*** Running vivado
+    with args -log Axis_adc_data_packer_v1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Axis_adc_data_packer_v1_0.tcl
+
+
+****** Vivado v2018.3 (64-bit)
+  **** SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
+  **** IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
+    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+
+source Axis_adc_data_packer_v1_0.tcl -notrace
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work'.
+WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1'.)
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/xilinx/Vivado/2018.3/data/ip'.
+WARNING: [IP_Flow 19-4995] The host OS only allows 260 characters in a normal path. The IP cache path is more than 80 characters. If you experience issues with IP caching, please consider changing the IP cache to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. 
+Current IP cache path is c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.cache/ip 
+WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:]
+WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v:]
+Command: synth_design -top Axis_adc_data_packer_v1_0 -part xczu7ev-ffvc1156-2-e
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xczu7ev'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu7ev'
+INFO: Launching helper process for spawning children vivado processes
+INFO: Helper process launched with PID 1944 
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 465.340 ; gain = 103.711
+---------------------------------------------------------------------------------
+INFO: [Synth 8-6157] synthesizing module 'Axis_adc_data_packer_v1_0' [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v:3]
+	Parameter C_S00_AXI_DATA_WIDTH bound to: 32 - type: integer 
+	Parameter C_S00_AXI_ADDR_WIDTH bound to: 4 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'Axis_adc_data_packer_v1_0_S00_AXI' [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:3]
+	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
+	Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer 
+	Parameter ADDR_LSB bound to: 2 - type: integer 
+	Parameter OPT_MEM_ADDR_BITS bound to: 1 - type: integer 
+INFO: [Synth 8-226] default block is never used [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:240]
+INFO: [Synth 8-226] default block is never used [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:381]
+INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_array_single' [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
+	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
+	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
+	Parameter SRC_INPUT_REG bound to: 1 - type: integer 
+	Parameter VERSION bound to: 0 - type: integer 
+	Parameter WIDTH bound to: 1 - type: integer 
+INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:958]
+INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_array_single' (1#1) [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_array_single__parameterized0' [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
+	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
+	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
+	Parameter SRC_INPUT_REG bound to: 1 - type: integer 
+	Parameter VERSION bound to: 0 - type: integer 
+	Parameter WIDTH bound to: 26 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_array_single__parameterized0' (1#1) [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+INFO: [Synth 8-6157] synthesizing module 'axis_adc_data_packer' [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:23]
+INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:52]
+INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:53]
+INFO: [Synth 8-6155] done synthesizing module 'axis_adc_data_packer' (2#1) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:23]
+INFO: [Synth 8-6155] done synthesizing module 'Axis_adc_data_packer_v1_0_S00_AXI' (3#1) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:3]
+INFO: [Synth 8-6155] done synthesizing module 'Axis_adc_data_packer_v1_0' (4#1) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v:3]
+WARNING: [Synth 8-3331] design axis_adc_data_packer has unconnected port m_axis_ready
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_AWPROT[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_AWPROT[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_AWPROT[0]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_ARPROT[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_ARPROT[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_ARPROT[0]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port axis_tlast
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 515.703 ; gain = 154.074
+---------------------------------------------------------------------------------
+
+Report Check Netlist: 
++------+------------------+-------+---------+-------+------------------+
+|      |Item              |Errors |Warnings |Status |Description       |
++------+------------------+-------+---------+-------+------------------+
+|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 515.703 ; gain = 154.074
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 515.703 ; gain = 154.074
+---------------------------------------------------------------------------------
+INFO: [Device 21-403] Loading part xczu7ev-ffvc1156-2-e
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.srcs/constrs_1/new/constrains.xdc]
+Finished Parsing XDC File [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.srcs/constrs_1/new/constrains.xdc]
+Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst0'
+Finished Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst0'
+Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst1'
+Finished Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst1'
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/Axis_adc_data_packer_v1_0_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/Axis_adc_data_packer_v1_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1584.711 ; gain = 0.000
+WARNING: [Constraints 18-5210] No constraints selected for write.
+Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1584.711 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1584.711 ; gain = 0.000
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1584.711 ; gain = 0.000
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xczu7ev-ffvc1156-2-e
+INFO: [Synth 8-6742] Reading net delay rules and data
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property DONT_TOUCH = true for Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst0. (constraint file  auto generated constraint, line ).
+Applied set_property DONT_TOUCH = true for Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst1. (constraint file  auto generated constraint, line ).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+.p 4
+.s 3
+.r iSTATE
+	 Default iSTATE 
+	 iSTATE iSTATE0 
+	 iSTATE iSTATE 
+	 iSTATE0 iSTATE 
+.e
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axis_adc_data_packer'
+INFO: [Synth 8-5546] ROM "cnt" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-6159] Found Keep on FSM register 'state_reg' in module 'axis_adc_data_packer', re-encoding will not be performed
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+*
+                  iSTATE |                         00000000 |                         00000000
+                 iSTATE0 |                         00000001 |                         00000001
+---------------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start RTL Component Statistics 
+---------------------------------------------------------------------------------
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input     32 Bit       Adders := 1     
+	   2 Input     26 Bit       Adders := 1     
++---Registers : 
+	               64 Bit    Registers := 1     
+	               32 Bit    Registers := 5     
+	               26 Bit    Registers := 6     
+	                8 Bit    Registers := 1     
+	                4 Bit    Registers := 2     
+	                2 Bit    Registers := 2     
+	                1 Bit    Registers := 14    
++---Muxes : 
+	   2 Input     32 Bit        Muxes := 4     
+	   4 Input     32 Bit        Muxes := 5     
+	   2 Input     26 Bit        Muxes := 4     
+	   3 Input      8 Bit        Muxes := 1     
+	   2 Input      8 Bit        Muxes := 2     
+	   2 Input      1 Bit        Muxes := 14    
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics 
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Hierarchical Component Statistics 
+---------------------------------------------------------------------------------
+Hierarchical RTL Component report 
+Module xpm_cdc_array_single 
+Detailed RTL Component Info : 
++---Registers : 
+	                1 Bit    Registers := 5     
+Module xpm_cdc_array_single__parameterized0 
+Detailed RTL Component Info : 
++---Registers : 
+	               26 Bit    Registers := 5     
+Module axis_adc_data_packer 
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input     32 Bit       Adders := 1     
+	   2 Input     26 Bit       Adders := 1     
++---Registers : 
+	               64 Bit    Registers := 1     
+	               26 Bit    Registers := 1     
+	                8 Bit    Registers := 1     
+	                1 Bit    Registers := 3     
++---Muxes : 
+	   2 Input     26 Bit        Muxes := 4     
+	   3 Input      8 Bit        Muxes := 1     
+	   2 Input      8 Bit        Muxes := 2     
+	   2 Input      1 Bit        Muxes := 9     
+Module Axis_adc_data_packer_v1_0_S00_AXI 
+Detailed RTL Component Info : 
++---Registers : 
+	               32 Bit    Registers := 5     
+	                4 Bit    Registers := 2     
+	                2 Bit    Registers := 2     
+	                1 Bit    Registers := 6     
++---Muxes : 
+	   2 Input     32 Bit        Muxes := 4     
+	   4 Input     32 Bit        Muxes := 5     
+	   2 Input      1 Bit        Muxes := 5     
+---------------------------------------------------------------------------------
+Finished RTL Hierarchical Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 1728 (col length:144)
+BRAMs: 624 (col length: RAMB18 144 RAMB36 72)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+Warning: Parallel synthesis criteria is not met 
+INFO: [Synth 8-5546] ROM "Axis_adc_data_packer_v1_0_S00_AXI_inst/axis_adc_data_packer/state" won't be mapped to RAM because it is too sparse
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port axis_tlast
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port m_axis_ready
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_awprot[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_awprot[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_awprot[0]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_arprot[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_arprot[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_arprot[0]
+INFO: [Synth 8-3886] merging instance 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_rresp_reg[0]' (FDRE) to 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_rresp_reg[1]'
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_rresp_reg[1] )
+INFO: [Synth 8-3886] merging instance 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_bresp_reg[0]' (FDRE) to 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_bresp_reg[1]'
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_bresp_reg[1] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Axis_adc_data_packer_v1_0_S00_AXI_inst/axis_adc_data_packer/axis_ready_reg )
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1995.184 ; gain = 1633.555
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1995.496 ; gain = 1633.867
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+
+Report Check Netlist: 
++------+------------------+-------+---------+-------+------------------+
+|      |Item              |Errors |Warnings |Status |Description       |
++------+------------------+-------+---------+-------+------------------+
+|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes: 
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage: 
++------+-------+------+
+|      |Cell   |Count |
++------+-------+------+
+|1     |BUFG   |     2|
+|2     |CARRY8 |    10|
+|3     |LUT1   |    27|
+|4     |LUT2   |     3|
+|5     |LUT3   |     2|
+|6     |LUT4   |    49|
+|7     |LUT5   |    25|
+|8     |LUT6   |    38|
+|9     |FDRE   |   412|
+|10    |FDSE   |     1|
+|11    |IBUF   |   114|
+|12    |OBUF   |   108|
++------+-------+------+
+
+Report Instance Areas: 
++------+-----------------------------------------+-------------------------------------+------+
+|      |Instance                                 |Module                               |Cells |
++------+-----------------------------------------+-------------------------------------+------+
+|1     |top                                      |                                     |   791|
+|2     |  Axis_adc_data_packer_v1_0_S00_AXI_inst |Axis_adc_data_packer_v1_0_S00_AXI    |   567|
+|3     |    xpm_cdc_array_single_inst0           |xpm_cdc_array_single                 |     5|
+|4     |    xpm_cdc_array_single_inst1           |xpm_cdc_array_single__parameterized0 |   130|
+|5     |    axis_adc_data_packer                 |axis_adc_data_packer                 |   205|
++------+-----------------------------------------+-------------------------------------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 8 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 2007.641 ; gain = 577.004
+Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+INFO: [Project 1-571] Translating synthesized netlist
+INFO: [Netlist 29-17] Analyzing 126 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2043.539 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 116 instances were transformed.
+  BUFG => BUFGCE: 2 instances
+  IBUF => IBUF (IBUFCTRL, INBUF): 114 instances
+
+INFO: [Common 17-83] Releasing license: Synthesis
+41 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2043.539 ; gain = 1693.754
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2043.539 ; gain = 0.000
+WARNING: [Constraints 18-5210] No constraints selected for write.
+Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
+INFO: [Common 17-1381] The checkpoint 'C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1/Axis_adc_data_packer_v1_0.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_utilization -file Axis_adc_data_packer_v1_0_utilization_synth.rpt -pb Axis_adc_data_packer_v1_0_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Thu Dec 23 16:00:12 2021...

cx9261a_demo_cmos_20240513/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/runme.sh

@@ -0,0 +1,43 @@
+#!/bin/sh
+
+# 
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+# 
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
+exit
+
+if [ -z "$PATH" ]; then
+  PATH=D:/xilinx/SDK/2018.3/bin;D:/xilinx/Vivado/2018.3/ids_lite/ISE/bin/nt64;D:/xilinx/Vivado/2018.3/ids_lite/ISE/lib/nt64:D:/xilinx/Vivado/2018.3/bin
+else
+  PATH=D:/xilinx/SDK/2018.3/bin;D:/xilinx/Vivado/2018.3/ids_lite/ISE/bin/nt64;D:/xilinx/Vivado/2018.3/ids_lite/ISE/lib/nt64:D:/xilinx/Vivado/2018.3/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+  LD_LIBRARY_PATH=
+else
+  LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+     $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+     if [ $? -ne 0 ]
+     then
+         exit
+     fi
+}
+
+EAStep vivado -log Axis_adc_data_packer_v1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Axis_adc_data_packer_v1_0.tcl

cx9261a_demo_cmos_20240513/ip_repo/edit_Axis_adc_data_packer_v1_0.runs/synth_1/vivado.jou

@@ -0,0 +1,12 @@
+#-----------------------------------------------------------
+# Vivado v2018.3 (64-bit)
+# SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
+# IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
+# Start of session at: Thu Dec 23 15:59:40 2021
+# Process ID: 9796
+# Current directory: C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1
+# Command line: vivado.exe -log Axis_adc_data_packer_v1_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Axis_adc_data_packer_v1_0.tcl
+# Log file: C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1/Axis_adc_data_packer_v1_0.vds
+# Journal file: C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1\vivado.jou
+#-----------------------------------------------------------
+source Axis_adc_data_packer_v1_0.tcl -notrace

cx9261a_demo_cmos_20240513/ip_repo/edit_Axis_adc_data_packer_v1_0.xpr

@@ -0,0 +1,200 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2018.3 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="39" Path="C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="c5d913f2a6d24b02baad3334ffc5d142"/>
+    <Option Name="Part" Val="xczu7ev-ffvc1156-2-e"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="BoardPart" Val="xilinx.com:zcu106:part0:2.3"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPRepoPath" Val="$PPRDIR/."/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSAVendor" Val="xilinx"/>
+    <Option Name="DSABoardId" Val="zcu106"/>
+    <Option Name="DSANumComputeUnits" Val="60"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v">
+        <FileInfo>
+          <Attr Name="Library" Val=""/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v">
+        <FileInfo>
+          <Attr Name="Library" Val=""/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/Axis_adc_data_packer_1.0/component.xml">
+        <FileInfo SFType="IPXACT"/>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="Axis_adc_data_packer_v1_0"/>
+        <Option Name="TopRTLFile" Val="$PPRDIR/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="Axis_adc_data_packer_v1_0"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="10">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xczu7ev-ffvc1156-2-e" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xczu7ev-ffvc1156-2-e" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+  </Runs>
+  <Board>
+    <Jumpers/>
+  </Board>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+  <BootPmcSettings Version="1" Minor="0">
+    <Parameters/>
+  </BootPmcSettings>
+</Project>

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/.gitignore

@@ -0,0 +1,35 @@
+# keep compiled libs
+!*.a
+
+# Buid folder
+build/
+
+# Xilinx tools generated files
+.metadata/
+.settings/
+.wsdata/
+.Xil/
+logs/
+Packages/
+*.log*
+
+# System generated files
+# -- macOS
+.DS_Store
+.AppleDouble
+.LSOverride
+._*
+
+# -- Windows
+Thumbs.db
+ehthumbs.db
+Desktop.ini
+
+# -- Linux
+*~
+
+# IDEs and editors' files
+*.idea
+*.vscode
+*.sublime-workspace
+*.sublime-project

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/Makefile

@@ -0,0 +1,8 @@
+include ../../scripts/generic_variables.mk
+
+PLATFORM := xilinx
+CONFIG_FILE := $(PROJECT)/config.json
+XILINX_VITIS_CLASSIC = y
+SCRIPT_DIR = ../../scripts
+
+include ../../scripts/generic.mk

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/config.json

@@ -0,0 +1,84 @@
+{
+    "project_name": "cx9261a_demo_cmos_20240513",
+    "version": "20240513",
+    "hw_design": "../CX9261A_ZC706.xsa",
+    "hw_version": "20241031",
+    "apps": {
+        "cx9261a_api_app": {
+            "sources": ["source_cx9261a_api_1_9_0/"],
+            "target_cpu": "ps7_cortexa9_0",
+            "os": "standalone",
+            "language": "C++",
+            "mem_layout" : {
+                "heap_size": "0x80000",
+                "stack_size": "0x4000"
+            }
+        },
+        "cx9261a_api_lib_app": {
+            "sources": ["source_cx9261a_api_lib_c/"],
+            "target_cpu": "ps7_cortexa9_0",
+            "os": "standalone",
+            "language": "C",
+            "mem_layout" : {
+                "heap_size": "0x80000",
+                "stack_size": "0x4000"
+            },
+            "build_config": {
+                "debug": {
+                    "include-path": ["source_cx9261a_api_lib_c/include"],
+                    "libraries": ["cx9261a_c_dbg", "stdc++", "m"],
+                    "library-search-path": ["source_cx9261a_api_lib_c/drivers/rf-transceiver/cx9261a/lib"]
+                },
+                "release": {
+                    "include-path": ["source_cx9261a_api_lib_c/include"],
+                    "libraries": ["cx9261a_c", "stdc++", "m"],
+                    "library-search-path": ["source_cx9261a_api_lib_c/drivers/rf-transceiver/cx9261a/lib"]
+                }
+            }
+        },
+        "CX9261A_DEMO": {
+            "sources": ["source_CX9261A_DEMO/"],
+            "target_cpu": "ps7_cortexa9_0",
+            "os": "freertos10_xilinx",
+            "language": "C",
+            "mem_layout" : {
+                "heap_size": "0x80000",
+                "stack_size": "0x4000"
+            },
+            "bsp_lib": {
+                "lwip220": {
+                    "version": "1.0",
+                    "config": {
+                        "api_mode": "SOCKET_API",
+                        "pbuf_pool_size": 2048
+                    }
+                },
+                "xilffs": {
+                    "version": "5.2"
+                }
+            }
+        },
+        "CX9261A_HOP": {
+            "sources": ["source_CX9261A_HOP/"],
+            "target_cpu": "ps7_cortexa9_0",
+            "os": "freertos10_xilinx",
+            "language": "C",
+            "mem_layout" : {
+                "heap_size": "0x80000",
+                "stack_size": "0x4000"
+            },
+            "bsp_lib": {
+                "lwip220": {
+                    "version": "1.0",
+                    "config": {
+                        "api_mode": "SOCKET_API",
+                        "pbuf_pool_size": 2048
+                    }
+                },
+                "xilffs": {
+                    "version": "5.2"
+                }
+            }
+        }
+    }
+}

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_DEMO/cx9261a_076_config.c

@@ -0,0 +1,342 @@
+/*
+ * cx9261a_076_config.c
+ *
+ *  Created on: 2023年11月30日
+ *      Author: cxlab
+ */
+
+
+#include "xilinx_io.h"
+#include "sleep.h"
+void cx9261a_076_config(void){
+u8 rx_data;
+int temp;
+
+//setPin(pin,value)
+GpioSetPinDir(0,0x01);
+GpioWritePin(0,1);
+GpioSetPinDir(32,0x01);
+GpioWritePin(32,1);
+GpioSetPinDir(33,0x01);
+GpioWritePin(33,1);
+GpioSetPinDir(34,0x01);
+GpioWritePin(34,0);
+GpioSetPinDir(35,0x01); //tx:0-rx:1
+GpioWritePin(35,1); //tx:0-rx:1
+GpioSetPinDir(36,0x01); //fdd:0-tdd:1
+GpioWritePin(36,1); //fdd:0-tdd:1
+GpioSetPinDir(37,0x01); //1r1t:0-2r2t:1
+GpioWritePin(37,0); //1r1t:0-2r2t:1
+GpioSetPinDir(38,0x01); //dualport:0-singleport:1
+GpioWritePin(38,1); //dualport:0-singleport:1
+GpioSetPinDir(39,0x01);
+GpioWritePin(39,1);
+GpioSetPinDir(40,0x01);
+GpioWritePin(40,1);
+//三个通道共同控制
+SpiPs_write_read1(0x000,0x02,&rx_data);
+//电源管理自定义
+//断电模式
+SpiPs_write_read1(0x031,0x00,&rx_data);
+SpiPs_write_read1(0x032,0x7F,&rx_data);
+SpiPs_write_read1(0x033,0xFF,&rx_data);
+SpiPs_write_read1(0x034,0xFF,&rx_data);
+//休眠模式
+SpiPs_write_read1(0x035,0x00,&rx_data);
+SpiPs_write_read1(0x036,0x3D,&rx_data);
+SpiPs_write_read1(0x037,0xFF,&rx_data);
+SpiPs_write_read1(0x038,0xEB,&rx_data);
+//警戒模式
+SpiPs_write_read1(0x039,0x00,&rx_data);
+SpiPs_write_read1(0x03A,0x3D,&rx_data);
+SpiPs_write_read1(0x03B,0xFF,&rx_data);
+SpiPs_write_read1(0x03C,0xE0,&rx_data);
+//校准模式
+SpiPs_write_read1(0x03D,0x1B,&rx_data);
+SpiPs_write_read1(0x03E,0x39,&rx_data);
+SpiPs_write_read1(0x03F,0x27,&rx_data);
+SpiPs_write_read1(0x040,0xE0,&rx_data);
+//接收模式
+SpiPs_write_read1(0x041,0x03,&rx_data);
+SpiPs_write_read1(0x042,0x3D,&rx_data);
+SpiPs_write_read1(0x043,0xE7,&rx_data);
+SpiPs_write_read1(0x044,0xF8,&rx_data);
+//发射模式
+SpiPs_write_read1(0x045,0x1B,&rx_data);
+SpiPs_write_read1(0x046,0x3D,&rx_data);
+SpiPs_write_read1(0x047,0x26,&rx_data);
+SpiPs_write_read1(0x048,0x7E,&rx_data);
+//FDD模式
+SpiPs_write_read1(0x049,0x1B,&rx_data);
+SpiPs_write_read1(0x04A,0x3D,&rx_data);
+SpiPs_write_read1(0x04B,0x27,&rx_data);
+SpiPs_write_read1(0x04C,0xE0,&rx_data);
+//观测模式
+SpiPs_write_read1(0x04D,0x04,&rx_data);
+SpiPs_write_read1(0x04E,0x3D,&rx_data);
+SpiPs_write_read1(0x04F,0xD9,&rx_data);
+SpiPs_write_read1(0x050,0xFE,&rx_data);
+//带隙基准
+SpiPs_write_read1(0x773,0x53,&rx_data);
+SpiPs_write_read1(0x774,0x86,&rx_data);
+//参考时钟设置
+SpiPs_write_read1(0x789,0x00,&rx_data);
+SpiPs_write_read1(0x785,0x49,&rx_data);
+SpiPs_write_read1(0x788,0x24,&rx_data);
+usleep(10000);
+SpiPs_write_read1(0x788,0xA4,&rx_data);
+//BBPLL
+SpiPs_write_read1(0x0C0,0x50,&rx_data);
+SpiPs_write_read1(0x0C1,0x50,&rx_data);
+SpiPs_write_read1(0x0C2,0x50,&rx_data);
+SpiPs_write_read1(0x601,0x0F,&rx_data);
+SpiPs_write_read1(0x602,0x21,&rx_data);
+SpiPs_write_read1(0x60D,0x0C,&rx_data);
+SpiPs_write_read1(0x60E,0x66,&rx_data);
+SpiPs_write_read1(0x60F,0x66,&rx_data);
+SpiPs_write_read1(0x610,0x66,&rx_data);
+SpiPs_write_read1(0x611,0x13,&rx_data);
+SpiPs_write_read1(0x612,0x00,&rx_data);
+//ADC
+SpiPs_write_read1(0x70B,0x0E,&rx_data);
+SpiPs_write_read1(0x727,0x0E,&rx_data);
+SpiPs_write_read1(0x743,0x0E,&rx_data);
+SpiPs_write_read1(0x70D,0x3F,&rx_data);
+SpiPs_write_read1(0x729,0x3F,&rx_data);
+SpiPs_write_read1(0x745,0x3F,&rx_data);
+SpiPs_write_read1(0x70E,0x48,&rx_data);
+SpiPs_write_read1(0x72A,0x48,&rx_data);
+SpiPs_write_read1(0x746,0x48,&rx_data);
+SpiPs_write_read1(0x70F,0xA0,&rx_data);
+SpiPs_write_read1(0x72B,0xA0,&rx_data);
+SpiPs_write_read1(0x747,0xA0,&rx_data);
+//通道时钟来源
+SpiPs_write_read1(0x77D,0xC0,&rx_data);
+SpiPs_write_read1(0x775,0x24,&rx_data);
+SpiPs_write_read1(0x6C3,0x00,&rx_data);
+//PLL1
+SpiPs_write_read1(0x620,0x81,&rx_data);
+SpiPs_write_read1(0x61D,0x00,&rx_data);
+SpiPs_write_read1(0xB06,0x00,&rx_data);
+SpiPs_write_read1(0xB07,0x64,&rx_data);
+SpiPs_write_read1(0xB08,0x00,&rx_data);
+SpiPs_write_read1(0xB09,0x00,&rx_data);
+SpiPs_write_read1(0xB0A,0x00,&rx_data);
+SpiPs_write_read1(0x61A,0x0B,&rx_data);
+SpiPs_write_read1(0x61B,0x20,&rx_data);
+SpiPs_write_read1(0x61C,0x13,&rx_data);
+SpiPs_write_read1(0x624,0x11,&rx_data);
+SpiPs_write_read1(0x625,0x11,&rx_data);
+SpiPs_write_read1(0x62A,0x00,&rx_data);
+SpiPs_write_read1(0x61E,0x30,&rx_data);
+SpiPs_write_read1(0x61F,0x08,&rx_data);
+SpiPs_write_read1(0x621,0x4D,&rx_data);
+SpiPs_write_read1(0x622,0x19,&rx_data);
+SpiPs_write_read1(0x627,0x10,&rx_data);
+//Rx通道设置
+SpiPs_write_read1(0x700,0x56,&rx_data);
+SpiPs_write_read1(0x71C,0x56,&rx_data);
+SpiPs_write_read1(0x738,0x56,&rx_data);
+SpiPs_write_read1(0x701,0x02,&rx_data);
+SpiPs_write_read1(0x702,0x35,&rx_data);
+SpiPs_write_read1(0x71D,0x02,&rx_data);
+SpiPs_write_read1(0x71E,0x35,&rx_data);
+SpiPs_write_read1(0x739,0x02,&rx_data);
+SpiPs_write_read1(0x73A,0x35,&rx_data);
+SpiPs_write_read1(0x703,0xF6,&rx_data);
+SpiPs_write_read1(0x71F,0xF6,&rx_data);
+SpiPs_write_read1(0x73B,0xF6,&rx_data);
+SpiPs_write_read1(0x704,0xC8,&rx_data);
+SpiPs_write_read1(0x720,0xC8,&rx_data);
+SpiPs_write_read1(0x73C,0xC8,&rx_data);
+SpiPs_write_read1(0x907,0x1F,&rx_data);
+SpiPs_write_read1(0x705,0xFC,&rx_data);
+SpiPs_write_read1(0x721,0xFC,&rx_data);
+SpiPs_write_read1(0x73D,0xFC,&rx_data);
+SpiPs_write_read1(0x706,0x65,&rx_data);
+SpiPs_write_read1(0x722,0x65,&rx_data);
+SpiPs_write_read1(0x73E,0x65,&rx_data);
+SpiPs_write_read1(0x707,0x91,&rx_data);
+SpiPs_write_read1(0x723,0x91,&rx_data);
+SpiPs_write_read1(0x73F,0x91,&rx_data);
+SpiPs_write_read1(0x708,0x04,&rx_data);
+SpiPs_write_read1(0x724,0x04,&rx_data);
+SpiPs_write_read1(0x740,0x04,&rx_data);
+SpiPs_write_read1(0x709,0x94,&rx_data);
+SpiPs_write_read1(0x725,0x94,&rx_data);
+SpiPs_write_read1(0x741,0x94,&rx_data);
+SpiPs_write_read1(0x70A,0xFC,&rx_data);
+SpiPs_write_read1(0x726,0xFC,&rx_data);
+SpiPs_write_read1(0x742,0xFC,&rx_data);
+SpiPs_write_read1(0x75A,0x83,&rx_data);
+SpiPs_write_read1(0x75B,0xDA,&rx_data);
+usleep(10000);
+SpiPs_write_read1(0x75B,0x9A,&rx_data);
+SpiPs_write_read1(0x75C,0x81,&rx_data);
+SpiPs_write_read1(0x75D,0xF8,&rx_data);
+SpiPs_write_read1(0x75E,0xA7,&rx_data);
+SpiPs_write_read1(0x75F,0x51,&rx_data);
+SpiPs_write_read1(0x760,0xFF,&rx_data);
+SpiPs_write_read1(0x761,0x04,&rx_data);
+SpiPs_write_read1(0x762,0x70,&rx_data);
+SpiPs_write_read1(0x763,0x04,&rx_data);
+SpiPs_write_read1(0x764,0x83,&rx_data);
+SpiPs_write_read1(0x765,0xDA,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x765,0x9A,&rx_data);
+SpiPs_write_read1(0x766,0x81,&rx_data);
+SpiPs_write_read1(0x767,0xF8,&rx_data);
+SpiPs_write_read1(0x768,0xA7,&rx_data);
+SpiPs_write_read1(0x769,0x51,&rx_data);
+SpiPs_write_read1(0x76A,0xFF,&rx_data);
+SpiPs_write_read1(0x76B,0x04,&rx_data);
+SpiPs_write_read1(0x76C,0x70,&rx_data);
+SpiPs_write_read1(0x76D,0x04,&rx_data);
+//Rx滤波器
+SpiPs_write_read1(0x106,0x02,&rx_data);
+//Tx滤波器
+SpiPs_write_read1(0x107,0x00,&rx_data);
+SpiPs_write_read1(0x108,0xD0,&rx_data);
+//Rx NCO
+SpiPs_write_read1(0x11C,0x00,&rx_data);
+SpiPs_write_read1(0xA07,0x00,&rx_data);
+SpiPs_write_read1(0xA08,0x00,&rx_data);
+SpiPs_write_read1(0xA16,0x00,&rx_data);
+SpiPs_write_read1(0xA17,0x00,&rx_data);
+SpiPs_write_read1(0xA18,0x00,&rx_data);
+SpiPs_write_read1(0xA19,0x00,&rx_data);
+SpiPs_write_read1(0xA1A,0x00,&rx_data);
+SpiPs_write_read1(0xA1B,0x00,&rx_data);
+//Tx NCO
+SpiPs_write_read1(0x128,0x10,&rx_data);
+SpiPs_write_read1(0x11B,0x00,&rx_data);
+SpiPs_write_read1(0x11E,0x00,&rx_data);
+SpiPs_write_read1(0x161,0x00,&rx_data);
+SpiPs_write_read1(0x162,0x00,&rx_data);
+SpiPs_write_read1(0x164,0x00,&rx_data);
+SpiPs_write_read1(0x165,0x00,&rx_data);
+SpiPs_write_read1(0x166,0x00,&rx_data);
+SpiPs_write_read1(0x167,0x00,&rx_data);
+SpiPs_write_read1(0x168,0x00,&rx_data);
+SpiPs_write_read1(0x169,0x00,&rx_data);
+//AGC配置
+SpiPs_write_read1(0x900,0x00,&rx_data);
+SpiPs_write_read1(0x901,0x00,&rx_data);
+SpiPs_write_read1(0x903,0x11,&rx_data);
+SpiPs_write_read1(0x908,0x77,&rx_data);
+SpiPs_write_read1(0x909,0x03,&rx_data);
+SpiPs_write_read1(0x90A,0x32,&rx_data);
+SpiPs_write_read1(0x90D,0x00,&rx_data);
+SpiPs_write_read1(0x90E,0x0F,&rx_data);
+SpiPs_write_read1(0x90F,0x65,&rx_data);
+SpiPs_write_read1(0x910,0x32,&rx_data);
+SpiPs_write_read1(0x911,0x00,&rx_data);
+SpiPs_write_read1(0x912,0x0F,&rx_data);
+SpiPs_write_read1(0x913,0x3A,&rx_data);
+SpiPs_write_read1(0x914,0x37,&rx_data);
+SpiPs_write_read1(0x915,0x34,&rx_data);
+SpiPs_write_read1(0x916,0x31,&rx_data);
+//进入休眠模式
+SpiPs_write_read1(0x02E,0x01,&rx_data);
+usleep(1000000);
+//进入校准模式
+SpiPs_write_read1(0x02E,0x03,&rx_data);
+//BBPLL AFC
+SpiPs_write_read1(0x600,0x00,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x600,0x11,&rx_data);
+//PLL1 AFC
+SpiPs_write_read1(0x617,0x00,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x617,0x03,&rx_data);
+//接口配置
+SpiPs_write_read1(0x02E,0x06,&rx_data);
+SpiPs_write_read1(0x003,0x33,&rx_data);
+SpiPs_write_read1(0x200,0x00,&rx_data);
+SpiPs_write_read1(0x201,0x00,&rx_data);
+SpiPs_write_read1(0x202,0x03,&rx_data);
+SpiPs_write_read1(0x209,0x00,&rx_data);
+SpiPs_write_read1(0x780,0x11,&rx_data);
+SpiPs_write_read1(0x781,0x6F,&rx_data);
+SpiPs_write_read1(0x782,0x01,&rx_data);
+SpiPs_write_read1(0x783,0x01,&rx_data);
+SpiPs_write_read1(0x784,0x01,&rx_data);
+//ADC校准
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x70F,0xA0,&rx_data);
+SpiPs_write_read1(0x710,0x83,&rx_data);
+SpiPs_write_read1(0x711,0xF0,&rx_data);
+SpiPs_write_read1(0x72B,0xA0,&rx_data);
+SpiPs_write_read1(0x72C,0x83,&rx_data);
+SpiPs_write_read1(0x72D,0xF0,&rx_data);
+SpiPs_write_read1(0x747,0xA0,&rx_data);
+SpiPs_write_read1(0x748,0x83,&rx_data);
+SpiPs_write_read1(0x749,0xF0,&rx_data);
+SpiPs_write_read1(0x713,0x80,&rx_data);
+SpiPs_write_read1(0x72F,0x80,&rx_data);
+SpiPs_write_read1(0x74B,0x80,&rx_data);
+SpiPs_write_read1(0x70B,0x9E,&rx_data);
+SpiPs_write_read1(0x727,0x9E,&rx_data);
+SpiPs_write_read1(0x743,0x9E,&rx_data);
+SpiPs_write_read1(0x70B,0x9A,&rx_data);
+SpiPs_write_read1(0x727,0x9A,&rx_data);
+SpiPs_write_read1(0x743,0x9A,&rx_data);
+SpiPs_write_read1(0x70B,0x9E,&rx_data);
+SpiPs_write_read1(0x727,0x9E,&rx_data);
+SpiPs_write_read1(0x743,0x9E,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x713,0xC0,&rx_data);
+SpiPs_write_read1(0x72F,0xC0,&rx_data);
+SpiPs_write_read1(0x74B,0xC0,&rx_data);
+//Flash校准
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x715,0x80,&rx_data);
+SpiPs_write_read1(0x731,0x80,&rx_data);
+SpiPs_write_read1(0x74D,0x80,&rx_data);
+SpiPs_write_read1(0x715,0xC0,&rx_data);
+SpiPs_write_read1(0x731,0xC0,&rx_data);
+SpiPs_write_read1(0x74D,0xC0,&rx_data);
+SpiPs_write_read1(0x716,0x40,&rx_data);
+SpiPs_write_read1(0x732,0x40,&rx_data);
+SpiPs_write_read1(0x74E,0x40,&rx_data);
+SpiPs_write_read1(0x70B,0x16,&rx_data);
+SpiPs_write_read1(0x727,0x16,&rx_data);
+SpiPs_write_read1(0x743,0x16,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x715,0x80,&rx_data);
+SpiPs_write_read1(0x731,0x80,&rx_data);
+SpiPs_write_read1(0x74D,0x80,&rx_data);
+SpiPs_write_read1(0x716,0x00,&rx_data);
+SpiPs_write_read1(0x732,0x00,&rx_data);
+SpiPs_write_read1(0x74E,0x00,&rx_data);
+SpiPs_write_read1(0x109,0x11,&rx_data);
+SpiPs_write_read1(0x10A,0x70,&rx_data);
+SpiPs_write_read1(0x11F,0x33,&rx_data);
+usleep(1000);
+SpiPs_write_read2(0x615,0x00,&rx_data);
+temp=rx_data;
+SpiPs_write_read2(0x635,0x00,&rx_data);
+temp=rx_data;
+////配置Tx NCO BIST ON
+//SpiPs_write_read1(0x11B,0x01,&rx_data);
+//SpiPs_write_read1(0x11E,0x01,&rx_data);
+//SpiPs_write_read1(0x161,0x01,&rx_data);
+//SpiPs_write_read1(0x162,0x01,&rx_data);
+////配置Tx NCO频率 1MHz
+//SpiPs_write_read1(0x164,0x05,&rx_data);
+//SpiPs_write_read1(0x165,0x55,&rx_data);
+//SpiPs_write_read1(0x166,0x55,&rx_data);
+//SpiPs_write_read1(0x167,0x55,&rx_data);
+//SpiPs_write_read1(0x168,0x55,&rx_data);
+//SpiPs_write_read1(0x169,0x55,&rx_data);
+}

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_DEMO/cx9261a_151_config.c

@@ -0,0 +1,708 @@
+/*
+ * cx9261_config.c
+ *
+ *  Created on: 2023年10月16日
+ *      Author: cxlab
+ */
+
+#include "xilinx_io.h"
+#include "sleep.h"
+void cx9261a_151_config(void){
+u8 rx_data;
+int temp;
+
+//setPin(pin,value)
+GpioSetPinDir(0,0x01);
+GpioWritePin(0,1);
+GpioSetPinDir(32,0x01);
+GpioWritePin(32,1);
+GpioSetPinDir(33,0x01);
+GpioWritePin(33,1);
+GpioSetPinDir(34,0x01);
+GpioWritePin(34,0);
+GpioSetPinDir(35,0x01); //tx:0-rx:1
+GpioWritePin(35,1); //tx:0-rx:1
+GpioSetPinDir(36,0x01); //fdd:0-tdd:1
+GpioWritePin(36,1); //fdd:0-tdd:1
+GpioSetPinDir(37,0x01); //1r1t:0-2r2t:1
+GpioWritePin(37,0); //1r1t:0-2r2t:1
+GpioSetPinDir(38,0x01); //dualport:0-singleport:1
+GpioWritePin(38,1); //dualport:0-singleport:1
+GpioSetPinDir(39,0x01);
+GpioWritePin(39,1);
+GpioSetPinDir(40,0x01);
+GpioWritePin(40,1);
+//三个通道共同控制
+SpiPs_write_read1(0x000,0x02,&rx_data);
+//电源管理自定义
+//断电模式
+SpiPs_write_read1(0x031,0x00,&rx_data);
+SpiPs_write_read1(0x032,0x7F,&rx_data);
+SpiPs_write_read1(0x033,0xFF,&rx_data);
+SpiPs_write_read1(0x034,0xFF,&rx_data);
+//休眠模式
+SpiPs_write_read1(0x035,0x00,&rx_data);
+SpiPs_write_read1(0x036,0x3D,&rx_data);
+SpiPs_write_read1(0x037,0xFF,&rx_data);
+SpiPs_write_read1(0x038,0xEB,&rx_data);
+//警戒模式
+SpiPs_write_read1(0x039,0x00,&rx_data);
+SpiPs_write_read1(0x03A,0x3D,&rx_data);
+SpiPs_write_read1(0x03B,0xFF,&rx_data);
+SpiPs_write_read1(0x03C,0xE0,&rx_data);
+//校准模式
+SpiPs_write_read1(0x03D,0x1B,&rx_data);
+SpiPs_write_read1(0x03E,0x39,&rx_data);
+SpiPs_write_read1(0x03F,0x27,&rx_data);
+SpiPs_write_read1(0x040,0xE0,&rx_data);
+//接收模式
+SpiPs_write_read1(0x041,0x03,&rx_data);
+SpiPs_write_read1(0x042,0x3D,&rx_data);
+SpiPs_write_read1(0x043,0xE7,&rx_data);
+SpiPs_write_read1(0x044,0xF8,&rx_data);
+//发射模式
+SpiPs_write_read1(0x045,0x18,&rx_data);
+SpiPs_write_read1(0x046,0x3D,&rx_data);
+SpiPs_write_read1(0x047,0x3F,&rx_data);
+SpiPs_write_read1(0x048,0xF8,&rx_data);
+//FDD模式
+SpiPs_write_read1(0x049,0x1B,&rx_data);
+SpiPs_write_read1(0x04A,0x3D,&rx_data);
+SpiPs_write_read1(0x04B,0x27,&rx_data);
+SpiPs_write_read1(0x04C,0xE0,&rx_data);
+//观测模式
+SpiPs_write_read1(0x04D,0x04,&rx_data);
+SpiPs_write_read1(0x04E,0x3D,&rx_data);
+SpiPs_write_read1(0x04F,0xD9,&rx_data);
+SpiPs_write_read1(0x050,0xFE,&rx_data);
+//带隙基准
+SpiPs_write_read1(0x773,0x53,&rx_data);
+SpiPs_write_read1(0x774,0x86,&rx_data);
+//参考时钟设置
+SpiPs_write_read1(0x789,0x00,&rx_data);
+SpiPs_write_read1(0x785,0x49,&rx_data);
+SpiPs_write_read1(0x788,0x24,&rx_data);
+usleep(10000);
+SpiPs_write_read1(0x788,0xA4,&rx_data);
+//BBPLL
+SpiPs_write_read1(0x0C0,0x50,&rx_data);
+SpiPs_write_read1(0x0C1,0x50,&rx_data);
+SpiPs_write_read1(0x0C2,0x50,&rx_data);
+SpiPs_write_read1(0x601,0x0F,&rx_data);
+SpiPs_write_read1(0x602,0x21,&rx_data);
+SpiPs_write_read1(0x60D,0x0C,&rx_data);
+SpiPs_write_read1(0x60E,0x66,&rx_data);
+SpiPs_write_read1(0x60F,0x66,&rx_data);
+SpiPs_write_read1(0x610,0x66,&rx_data);
+SpiPs_write_read1(0x611,0x13,&rx_data);
+SpiPs_write_read1(0x612,0x00,&rx_data);
+//ADC
+SpiPs_write_read1(0x70B,0x0E,&rx_data);
+SpiPs_write_read1(0x727,0x0E,&rx_data);
+SpiPs_write_read1(0x743,0x0E,&rx_data);
+SpiPs_write_read1(0x70D,0x3F,&rx_data);
+SpiPs_write_read1(0x729,0x3F,&rx_data);
+SpiPs_write_read1(0x745,0x3F,&rx_data);
+SpiPs_write_read1(0x70E,0x48,&rx_data);
+SpiPs_write_read1(0x72A,0x48,&rx_data);
+SpiPs_write_read1(0x746,0x48,&rx_data);
+SpiPs_write_read1(0x70F,0xA0,&rx_data);
+SpiPs_write_read1(0x72B,0xA0,&rx_data);
+SpiPs_write_read1(0x747,0xA0,&rx_data);
+//通道时钟来源
+SpiPs_write_read1(0x77D,0xCF,&rx_data);
+SpiPs_write_read1(0x775,0x24,&rx_data);
+SpiPs_write_read1(0x6C3,0x00,&rx_data);
+//PLL1
+SpiPs_write_read1(0x620,0x81,&rx_data);
+SpiPs_write_read1(0x61D,0x07,&rx_data);
+SpiPs_write_read1(0xB06,0x00,&rx_data);
+SpiPs_write_read1(0xB07,0x64,&rx_data);
+SpiPs_write_read1(0xB08,0x00,&rx_data);
+SpiPs_write_read1(0xB09,0x00,&rx_data);
+SpiPs_write_read1(0xB0A,0x00,&rx_data);
+SpiPs_write_read1(0x61A,0x0B,&rx_data);
+SpiPs_write_read1(0x61B,0x20,&rx_data);
+SpiPs_write_read1(0x61C,0x13,&rx_data);
+SpiPs_write_read1(0x624,0x11,&rx_data);
+SpiPs_write_read1(0x625,0x11,&rx_data);
+SpiPs_write_read1(0x62A,0x00,&rx_data);
+SpiPs_write_read1(0x61E,0x30,&rx_data);
+SpiPs_write_read1(0x61F,0x08,&rx_data);
+SpiPs_write_read1(0x621,0x4D,&rx_data);
+SpiPs_write_read1(0x622,0x19,&rx_data);
+SpiPs_write_read1(0x627,0x10,&rx_data);
+//PLL2
+SpiPs_write_read1(0x642,0x91,&rx_data);
+SpiPs_write_read1(0x63F,0x36,&rx_data);
+SpiPs_write_read1(0xB14,0x00,&rx_data);
+SpiPs_write_read1(0xB15,0x70,&rx_data);
+SpiPs_write_read1(0xB16,0x00,&rx_data);
+SpiPs_write_read1(0xB17,0x00,&rx_data);
+SpiPs_write_read1(0xB18,0x00,&rx_data);
+SpiPs_write_read1(0x63C,0x0C,&rx_data);
+SpiPs_write_read1(0x63D,0x20,&rx_data);
+SpiPs_write_read1(0x63E,0x0C,&rx_data);
+SpiPs_write_read1(0x646,0x11,&rx_data);
+SpiPs_write_read1(0x647,0x11,&rx_data);
+SpiPs_write_read1(0x64C,0x00,&rx_data);
+SpiPs_write_read1(0x640,0x30,&rx_data);
+SpiPs_write_read1(0x641,0x08,&rx_data);
+SpiPs_write_read1(0x643,0x4D,&rx_data);
+SpiPs_write_read1(0x644,0x19,&rx_data);
+SpiPs_write_read1(0x649,0x10,&rx_data);
+//PLL3
+SpiPs_write_read1(0x664,0x91,&rx_data);
+SpiPs_write_read1(0x661,0x36,&rx_data);
+SpiPs_write_read1(0xB22,0x00,&rx_data);
+SpiPs_write_read1(0xB23,0x80,&rx_data);
+SpiPs_write_read1(0xB24,0x00,&rx_data);
+SpiPs_write_read1(0xB25,0x00,&rx_data);
+SpiPs_write_read1(0xB26,0x00,&rx_data);
+SpiPs_write_read1(0x65E,0x0D,&rx_data);
+SpiPs_write_read1(0x65F,0x20,&rx_data);
+SpiPs_write_read1(0x660,0x0F,&rx_data);
+SpiPs_write_read1(0x668,0x11,&rx_data);
+SpiPs_write_read1(0x669,0x11,&rx_data);
+SpiPs_write_read1(0x66E,0x00,&rx_data);
+SpiPs_write_read1(0x662,0x30,&rx_data);
+SpiPs_write_read1(0x663,0x08,&rx_data);
+SpiPs_write_read1(0x665,0x4D,&rx_data);
+SpiPs_write_read1(0x666,0x19,&rx_data);
+SpiPs_write_read1(0x66B,0x10,&rx_data);
+//PLL4
+SpiPs_write_read1(0x686,0x81,&rx_data);
+SpiPs_write_read1(0x683,0x37,&rx_data);
+SpiPs_write_read1(0xB30,0x00,&rx_data);
+SpiPs_write_read1(0xB31,0x48,&rx_data);
+SpiPs_write_read1(0xB32,0x00,&rx_data);
+SpiPs_write_read1(0xB33,0x00,&rx_data);
+SpiPs_write_read1(0xB34,0x00,&rx_data);
+SpiPs_write_read1(0x680,0x0C,&rx_data);
+SpiPs_write_read1(0x681,0x20,&rx_data);
+SpiPs_write_read1(0x682,0x11,&rx_data);
+SpiPs_write_read1(0x68A,0x11,&rx_data);
+SpiPs_write_read1(0x68B,0x11,&rx_data);
+SpiPs_write_read1(0x690,0x00,&rx_data);
+SpiPs_write_read1(0x684,0x30,&rx_data);
+SpiPs_write_read1(0x685,0x08,&rx_data);
+SpiPs_write_read1(0x687,0x4D,&rx_data);
+SpiPs_write_read1(0x688,0x19,&rx_data);
+SpiPs_write_read1(0x68D,0x10,&rx_data);
+//PLL5
+SpiPs_write_read1(0x6A8,0x81,&rx_data);
+SpiPs_write_read1(0x6A5,0x37,&rx_data);
+SpiPs_write_read1(0xB3E,0x00,&rx_data);
+SpiPs_write_read1(0xB3F,0x50,&rx_data);
+SpiPs_write_read1(0xB40,0x00,&rx_data);
+SpiPs_write_read1(0xB41,0x00,&rx_data);
+SpiPs_write_read1(0xB42,0x00,&rx_data);
+SpiPs_write_read1(0x6A2,0x0C,&rx_data);
+SpiPs_write_read1(0x6A3,0x20,&rx_data);
+SpiPs_write_read1(0x6A4,0x11,&rx_data);
+SpiPs_write_read1(0x6AC,0x11,&rx_data);
+SpiPs_write_read1(0x6AD,0x11,&rx_data);
+SpiPs_write_read1(0x6B2,0x00,&rx_data);
+SpiPs_write_read1(0x6A6,0x30,&rx_data);
+SpiPs_write_read1(0x6A7,0x08,&rx_data);
+SpiPs_write_read1(0x6A9,0x4D,&rx_data);
+SpiPs_write_read1(0x6AA,0x19,&rx_data);
+SpiPs_write_read1(0x6AF,0x10,&rx_data);
+//Rx通道设置
+SpiPs_write_read1(0x700,0x56,&rx_data);
+SpiPs_write_read1(0x71C,0x56,&rx_data);
+SpiPs_write_read1(0x738,0x56,&rx_data);
+SpiPs_write_read1(0x701,0x02,&rx_data);
+SpiPs_write_read1(0x702,0x35,&rx_data);
+SpiPs_write_read1(0x71D,0x02,&rx_data);
+SpiPs_write_read1(0x71E,0x35,&rx_data);
+SpiPs_write_read1(0x739,0x02,&rx_data);
+SpiPs_write_read1(0x73A,0x35,&rx_data);
+SpiPs_write_read1(0x703,0xF6,&rx_data);
+SpiPs_write_read1(0x71F,0xF6,&rx_data);
+SpiPs_write_read1(0x73B,0xF6,&rx_data);
+SpiPs_write_read1(0x704,0xC8,&rx_data);
+SpiPs_write_read1(0x720,0xC8,&rx_data);
+SpiPs_write_read1(0x73C,0xC8,&rx_data);
+SpiPs_write_read1(0x907,0x1F,&rx_data);
+SpiPs_write_read1(0x705,0xFC,&rx_data);
+SpiPs_write_read1(0x721,0xFC,&rx_data);
+SpiPs_write_read1(0x73D,0xFC,&rx_data);
+SpiPs_write_read1(0x706,0x65,&rx_data);
+SpiPs_write_read1(0x722,0x65,&rx_data);
+SpiPs_write_read1(0x73E,0x65,&rx_data);
+SpiPs_write_read1(0x707,0x91,&rx_data);
+SpiPs_write_read1(0x723,0x91,&rx_data);
+SpiPs_write_read1(0x73F,0x91,&rx_data);
+SpiPs_write_read1(0x708,0x04,&rx_data);
+SpiPs_write_read1(0x724,0x04,&rx_data);
+SpiPs_write_read1(0x740,0x04,&rx_data);
+SpiPs_write_read1(0x709,0x94,&rx_data);
+SpiPs_write_read1(0x725,0x94,&rx_data);
+SpiPs_write_read1(0x741,0x94,&rx_data);
+SpiPs_write_read1(0x70A,0xFC,&rx_data);
+SpiPs_write_read1(0x726,0xFC,&rx_data);
+SpiPs_write_read1(0x742,0xFC,&rx_data);
+SpiPs_write_read1(0x75A,0x83,&rx_data);
+SpiPs_write_read1(0x75B,0xDA,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x75B,0x9A,&rx_data);
+SpiPs_write_read1(0x75C,0x81,&rx_data);
+SpiPs_write_read1(0x75D,0xF8,&rx_data);
+SpiPs_write_read1(0x75E,0xA7,&rx_data);
+SpiPs_write_read1(0x75F,0x50,&rx_data);
+SpiPs_write_read1(0x760,0xFF,&rx_data);
+SpiPs_write_read1(0x761,0x07,&rx_data);
+SpiPs_write_read1(0x762,0x6C,&rx_data);
+SpiPs_write_read1(0x763,0x04,&rx_data);
+SpiPs_write_read1(0x764,0x83,&rx_data);
+SpiPs_write_read1(0x765,0xDA,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x765,0x9A,&rx_data);
+SpiPs_write_read1(0x766,0x81,&rx_data);
+SpiPs_write_read1(0x767,0xF8,&rx_data);
+SpiPs_write_read1(0x768,0xA7,&rx_data);
+SpiPs_write_read1(0x769,0x50,&rx_data);
+SpiPs_write_read1(0x76A,0xFF,&rx_data);
+SpiPs_write_read1(0x76B,0x07,&rx_data);
+SpiPs_write_read1(0x76C,0x6C,&rx_data);
+SpiPs_write_read1(0x76D,0x04,&rx_data);
+//Rx滤波器
+SpiPs_write_read1(0x106,0x02,&rx_data);
+//Tx滤波器
+SpiPs_write_read1(0x107,0x00,&rx_data);
+SpiPs_write_read1(0x108,0xD0,&rx_data);
+//Rx NCO
+SpiPs_write_read1(0x11C,0x00,&rx_data);
+SpiPs_write_read1(0xA07,0x00,&rx_data);
+SpiPs_write_read1(0xA08,0x00,&rx_data);
+SpiPs_write_read1(0xA16,0x00,&rx_data);
+SpiPs_write_read1(0xA17,0x00,&rx_data);
+SpiPs_write_read1(0xA18,0x00,&rx_data);
+SpiPs_write_read1(0xA19,0x00,&rx_data);
+SpiPs_write_read1(0xA1A,0x00,&rx_data);
+SpiPs_write_read1(0xA1B,0x00,&rx_data);
+//Tx NCO
+SpiPs_write_read1(0x128,0x10,&rx_data);
+SpiPs_write_read1(0x11B,0x01,&rx_data);
+SpiPs_write_read1(0x11E,0x01,&rx_data);
+SpiPs_write_read1(0x161,0x01,&rx_data);
+SpiPs_write_read1(0x162,0x01,&rx_data);
+SpiPs_write_read1(0x164,0x05,&rx_data);
+SpiPs_write_read1(0x165,0x55,&rx_data);
+SpiPs_write_read1(0x166,0x55,&rx_data);
+SpiPs_write_read1(0x167,0x55,&rx_data);
+SpiPs_write_read1(0x168,0x55,&rx_data);
+SpiPs_write_read1(0x169,0x55,&rx_data);
+//AGC配置
+SpiPs_write_read1(0x900,0x00,&rx_data);
+SpiPs_write_read1(0x901,0x00,&rx_data);
+SpiPs_write_read1(0x903,0x11,&rx_data);
+SpiPs_write_read1(0x908,0x77,&rx_data);
+SpiPs_write_read1(0x909,0x03,&rx_data);
+SpiPs_write_read1(0x90A,0x32,&rx_data);
+SpiPs_write_read1(0x90D,0x00,&rx_data);
+SpiPs_write_read1(0x90E,0x0F,&rx_data);
+SpiPs_write_read1(0x90F,0x65,&rx_data);
+SpiPs_write_read1(0x910,0x32,&rx_data);
+SpiPs_write_read1(0x911,0x00,&rx_data);
+SpiPs_write_read1(0x912,0x0F,&rx_data);
+SpiPs_write_read1(0x913,0x3A,&rx_data);
+SpiPs_write_read1(0x914,0x37,&rx_data);
+SpiPs_write_read1(0x915,0x34,&rx_data);
+SpiPs_write_read1(0x916,0x31,&rx_data);
+//进入休眠模式
+SpiPs_write_read1(0x02E,0x01,&rx_data);
+usleep(1000000);
+//进入校准模式
+SpiPs_write_read1(0x02E,0x03,&rx_data);
+usleep(100000);
+//BBPLL AFC
+SpiPs_write_read1(0x600,0x00,&rx_data);
+SpiPs_write_read1(0x600,0x11,&rx_data);
+usleep(50);
+//PLL1 AFC
+while(temp != 48)
+{
+SpiPs_write_read1(0x617,0x00,&rx_data);
+SpiPs_write_read1(0x617,0x03,&rx_data);
+usleep(100);
+SpiPs_write_read2(0x635,0x00,&rx_data);
+temp=rx_data;
+}
+//接口配置
+SpiPs_write_read1(0x02E,0x06,&rx_data);
+SpiPs_write_read1(0x003,0x33,&rx_data);
+SpiPs_write_read1(0x200,0x00,&rx_data);
+SpiPs_write_read1(0x201,0x00,&rx_data);
+SpiPs_write_read1(0x202,0x03,&rx_data);
+SpiPs_write_read1(0x208,0x00,&rx_data);
+SpiPs_write_read1(0x209,0x00,&rx_data);
+SpiPs_write_read1(0x780,0x11,&rx_data);
+SpiPs_write_read1(0x781,0x6F,&rx_data);
+SpiPs_write_read1(0x782,0x01,&rx_data);
+SpiPs_write_read1(0x783,0x01,&rx_data);
+SpiPs_write_read1(0x784,0x01,&rx_data);
+//ADC校准
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x70F,0xA0,&rx_data);
+SpiPs_write_read1(0x710,0x83,&rx_data);
+SpiPs_write_read1(0x711,0xF0,&rx_data);
+SpiPs_write_read1(0x72B,0xA0,&rx_data);
+SpiPs_write_read1(0x72C,0x83,&rx_data);
+SpiPs_write_read1(0x72D,0xF0,&rx_data);
+SpiPs_write_read1(0x747,0xA0,&rx_data);
+SpiPs_write_read1(0x748,0x83,&rx_data);
+SpiPs_write_read1(0x749,0xF0,&rx_data);
+SpiPs_write_read1(0x713,0x80,&rx_data);
+SpiPs_write_read1(0x72F,0x80,&rx_data);
+SpiPs_write_read1(0x74B,0x80,&rx_data);
+SpiPs_write_read1(0x70B,0x9E,&rx_data);
+SpiPs_write_read1(0x727,0x9E,&rx_data);
+SpiPs_write_read1(0x743,0x9E,&rx_data);
+SpiPs_write_read1(0x70B,0x9A,&rx_data);
+SpiPs_write_read1(0x727,0x9A,&rx_data);
+SpiPs_write_read1(0x743,0x9A,&rx_data);
+SpiPs_write_read1(0x70B,0x9E,&rx_data);
+SpiPs_write_read1(0x727,0x9E,&rx_data);
+SpiPs_write_read1(0x743,0x9E,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x713,0xC0,&rx_data);
+SpiPs_write_read1(0x72F,0xC0,&rx_data);
+SpiPs_write_read1(0x74B,0xC0,&rx_data);
+//Flash校准
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x715,0x80,&rx_data);
+SpiPs_write_read1(0x731,0x80,&rx_data);
+SpiPs_write_read1(0x74D,0x80,&rx_data);
+SpiPs_write_read1(0x715,0xC0,&rx_data);
+SpiPs_write_read1(0x731,0xC0,&rx_data);
+SpiPs_write_read1(0x74D,0xC0,&rx_data);
+SpiPs_write_read1(0x716,0x40,&rx_data);
+SpiPs_write_read1(0x732,0x40,&rx_data);
+SpiPs_write_read1(0x74E,0x40,&rx_data);
+SpiPs_write_read1(0x70B,0x16,&rx_data);
+SpiPs_write_read1(0x727,0x16,&rx_data);
+SpiPs_write_read1(0x743,0x16,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x715,0x80,&rx_data);
+SpiPs_write_read1(0x731,0x80,&rx_data);
+SpiPs_write_read1(0x74D,0x80,&rx_data);
+SpiPs_write_read1(0x716,0x00,&rx_data);
+SpiPs_write_read1(0x732,0x00,&rx_data);
+SpiPs_write_read1(0x74E,0x00,&rx_data);
+SpiPs_write_read1(0x109,0x11,&rx_data);
+SpiPs_write_read1(0x10A,0x70,&rx_data);
+SpiPs_write_read1(0x11F,0x33,&rx_data);
+//QEC校准
+//Rx TST Calibration
+SpiPs_write_read1(0x000,0x12,&rx_data);
+SpiPs_write_read1(0x109,0x00,&rx_data);
+SpiPs_write_read1(0x77E,0x50,&rx_data);
+SpiPs_write_read1(0x14E,0x00,&rx_data);
+// 修改校准模式电源管理
+SpiPs_write_read1(0x03D,0x09,&rx_data);
+SpiPs_write_read1(0x03E,0x39,&rx_data);
+SpiPs_write_read1(0x03F,0xB6,&rx_data);
+SpiPs_write_read1(0x040,0x78,&rx_data);
+//修改电源模式
+SpiPs_write_read1(0x02E,0x03,&rx_data);
+//Calibration PLL Source
+// 修改Pll来源
+SpiPs_write_read1(0x77D,0x90,&rx_data);
+SpiPs_write_read1(0x6C3,0x05,&rx_data);
+SpiPs_write_read1(0x775,0x24,&rx_data);
+//修改Pll4频率
+//PLL4
+SpiPs_write_read1(0x686,0x81,&rx_data);
+SpiPs_write_read1(0x683,0x07,&rx_data);
+SpiPs_write_read1(0xB30,0x00,&rx_data);
+SpiPs_write_read1(0xB31,0x63,&rx_data);
+SpiPs_write_read1(0xB32,0xEB,&rx_data);
+SpiPs_write_read1(0xB33,0x85,&rx_data);
+SpiPs_write_read1(0xB34,0x1E,&rx_data);
+SpiPs_write_read1(0x680,0x0B,&rx_data);
+SpiPs_write_read1(0x681,0x20,&rx_data);
+SpiPs_write_read1(0x682,0x13,&rx_data);
+SpiPs_write_read1(0x68A,0x11,&rx_data);
+SpiPs_write_read1(0x68B,0x11,&rx_data);
+SpiPs_write_read1(0x690,0x0B,&rx_data);
+SpiPs_write_read1(0x684,0x30,&rx_data);
+SpiPs_write_read1(0x685,0x08,&rx_data);
+SpiPs_write_read1(0x687,0x4D,&rx_data);
+SpiPs_write_read1(0x688,0x19,&rx_data);
+SpiPs_write_read1(0x68D,0x10,&rx_data);
+//PLL4 AFC
+while(temp != 48)
+{
+SpiPs_write_read1(0x67D,0x00,&rx_data);
+SpiPs_write_read1(0x67D,0x03,&rx_data);
+usleep(100);
+SpiPs_write_read2(0x69B,0x00,&rx_data);
+temp=rx_data;
+}
+SpiPs_write_read1(0x02A,0x00,&rx_data);
+SpiPs_write_read1(0x121,0x00,&rx_data);
+SpiPs_write_read1(0x11F,0x73,&rx_data);
+SpiPs_write_read1(0x124,0xFF,&rx_data);
+SpiPs_write_read1(0x120,0x00,&rx_data);
+SpiPs_write_read1(0x122,0x03,&rx_data);
+SpiPs_write_read1(0x126,0x01,&rx_data);
+SpiPs_write_read1(0x02A,0x12,&rx_data);
+
+SpiPs_write_read2(0x14D,0x00,&rx_data);
+temp=rx_data & 0x10;
+while(temp != 16){
+SpiPs_write_read2(0x14D,0x00,&rx_data);
+temp=rx_data & 0x10;
+usleep(100000);
+}
+
+SpiPs_write_read1(0x77E,0x00,&rx_data);
+SpiPs_write_read1(0x775,0x24,&rx_data);
+SpiPs_write_read1(0x77D,0xCF,&rx_data);
+SpiPs_write_read1(0x6C3,0x00,&rx_data);
+//Rx TST Calibration
+SpiPs_write_read1(0x000,0x22,&rx_data);
+SpiPs_write_read1(0x109,0x00,&rx_data);
+SpiPs_write_read1(0x77E,0x0A,&rx_data);
+SpiPs_write_read1(0x14E,0x00,&rx_data);
+// 修改校准模式电源管理
+SpiPs_write_read1(0x03D,0x12,&rx_data);
+SpiPs_write_read1(0x03E,0x39,&rx_data);
+SpiPs_write_read1(0x03F,0x6E,&rx_data);
+SpiPs_write_read1(0x040,0x78,&rx_data);
+//修改电源模式
+SpiPs_write_read1(0x02E,0x03,&rx_data);
+//Calibration PLL Source
+// 修改Pll来源
+SpiPs_write_read1(0x77D,0x60,&rx_data);
+SpiPs_write_read1(0x6C3,0x0A,&rx_data);
+SpiPs_write_read1(0x775,0x24,&rx_data);
+//修改Pll4频率
+//PLL4
+SpiPs_write_read1(0x686,0x81,&rx_data);
+SpiPs_write_read1(0x683,0x07,&rx_data);
+SpiPs_write_read1(0xB30,0x00,&rx_data);
+SpiPs_write_read1(0xB31,0x63,&rx_data);
+SpiPs_write_read1(0xB32,0xEB,&rx_data);
+SpiPs_write_read1(0xB33,0x85,&rx_data);
+SpiPs_write_read1(0xB34,0x1E,&rx_data);
+SpiPs_write_read1(0x680,0x0B,&rx_data);
+SpiPs_write_read1(0x681,0x20,&rx_data);
+SpiPs_write_read1(0x682,0x13,&rx_data);
+SpiPs_write_read1(0x68A,0x11,&rx_data);
+SpiPs_write_read1(0x68B,0x11,&rx_data);
+SpiPs_write_read1(0x690,0x0B,&rx_data);
+SpiPs_write_read1(0x684,0x30,&rx_data);
+SpiPs_write_read1(0x685,0x08,&rx_data);
+SpiPs_write_read1(0x687,0x4D,&rx_data);
+SpiPs_write_read1(0x688,0x19,&rx_data);
+SpiPs_write_read1(0x68D,0x10,&rx_data);
+//PLL4 AFC
+while(temp != 48)
+{
+SpiPs_write_read1(0x67D,0x00,&rx_data);
+SpiPs_write_read1(0x67D,0x03,&rx_data);
+usleep(100);
+SpiPs_write_read2(0x69B,0x00,&rx_data);
+temp=rx_data;
+}
+SpiPs_write_read1(0x02B,0x00,&rx_data);
+SpiPs_write_read1(0x121,0x00,&rx_data);
+SpiPs_write_read1(0x11F,0x73,&rx_data);
+SpiPs_write_read1(0x124,0xFF,&rx_data);
+SpiPs_write_read1(0x120,0x00,&rx_data);
+SpiPs_write_read1(0x122,0x03,&rx_data);
+SpiPs_write_read1(0x126,0x01,&rx_data);
+SpiPs_write_read1(0x02B,0x12,&rx_data);
+
+SpiPs_write_read2(0x14D,0x00,&rx_data);
+temp=rx_data & 0x10;
+while(temp != 16){
+SpiPs_write_read2(0x14D,0x00,&rx_data);
+temp=rx_data & 0x10;
+usleep(100000);
+}
+
+SpiPs_write_read1(0x77E,0x00,&rx_data);
+SpiPs_write_read1(0x775,0x24,&rx_data);
+SpiPs_write_read1(0x77D,0xCF,&rx_data);
+SpiPs_write_read1(0x6C3,0x00,&rx_data);
+SpiPs_write_read1(0x02C,0x00,&rx_data);
+SpiPs_write_read1(0x02B,0x00,&rx_data);
+SpiPs_write_read1(0x02A,0x00,&rx_data);
+//恢复校准前设置
+SpiPs_write_read1(0x000,0x02,&rx_data);
+SpiPs_write_read1(0x02E,0x06,&rx_data);
+SpiPs_write_read1(0x03D,0x1B,&rx_data);
+SpiPs_write_read1(0x03E,0x39,&rx_data);
+SpiPs_write_read1(0x03F,0x27,&rx_data);
+SpiPs_write_read1(0x040,0xF8,&rx_data);
+SpiPs_write_read1(0x109,0x11,&rx_data);
+SpiPs_write_read1(0x10A,0x70,&rx_data);
+SpiPs_write_read1(0x11B,0x01,&rx_data);
+SpiPs_write_read1(0x11E,0x01,&rx_data);
+SpiPs_write_read1(0x11F,0x33,&rx_data);
+SpiPs_write_read1(0x128,0x10,&rx_data);
+SpiPs_write_read1(0x161,0x01,&rx_data);
+SpiPs_write_read1(0x162,0x01,&rx_data);
+SpiPs_write_read1(0x164,0x05,&rx_data);
+SpiPs_write_read1(0x165,0x55,&rx_data);
+SpiPs_write_read1(0x166,0x55,&rx_data);
+SpiPs_write_read1(0x167,0x55,&rx_data);
+SpiPs_write_read1(0x168,0x55,&rx_data);
+SpiPs_write_read1(0x169,0x55,&rx_data);
+SpiPs_write_read1(0xA07,0x00,&rx_data);
+SpiPs_write_read1(0xA08,0x00,&rx_data);
+SpiPs_write_read1(0xA16,0x00,&rx_data);
+SpiPs_write_read1(0xA17,0x00,&rx_data);
+SpiPs_write_read1(0xA18,0x00,&rx_data);
+SpiPs_write_read1(0xA19,0x00,&rx_data);
+SpiPs_write_read1(0xA1A,0x00,&rx_data);
+SpiPs_write_read1(0xA1B,0x00,&rx_data);
+SpiPs_write_read1(0xA1C,0x00,&rx_data);
+SpiPs_write_read1(0xA2D,0x00,&rx_data);
+// TX二分法校准
+// 修改校准模式电源管理
+SpiPs_write_read1(0x03D,0x1B,&rx_data);
+SpiPs_write_read1(0x03E,0x39,&rx_data);
+SpiPs_write_read1(0x03F,0x27,&rx_data);
+SpiPs_write_read1(0x040,0xF8,&rx_data);
+//修改电源模式
+SpiPs_write_read1(0x02E,0x03,&rx_data);
+SpiPs_write_read1(0x128,0x11,&rx_data);
+SpiPs_write_read1(0x11E,0x01,&rx_data);
+SpiPs_write_read1(0x77E,0x24,&rx_data);
+SpiPs_write_read1(0x11F,0x01,&rx_data);
+SpiPs_write_read1(0x121,0x02,&rx_data);
+SpiPs_write_read1(0x11B,0x01,&rx_data);
+SpiPs_write_read1(0x161,0x01,&rx_data);
+SpiPs_write_read1(0x162,0x01,&rx_data);
+SpiPs_write_read1(0x163,0x00,&rx_data);
+SpiPs_write_read1(0x164,0x05,&rx_data);
+SpiPs_write_read1(0x165,0x55,&rx_data);
+SpiPs_write_read1(0x166,0x55,&rx_data);
+SpiPs_write_read1(0x167,0x55,&rx_data);
+SpiPs_write_read1(0x168,0x55,&rx_data);
+SpiPs_write_read1(0x169,0x55,&rx_data);
+SpiPs_write_read1(0xA2D,0x02,&rx_data);
+SpiPs_write_read1(0xA07,0x00,&rx_data);
+SpiPs_write_read1(0xA08,0x0F,&rx_data);
+SpiPs_write_read1(0xA1C,0x01,&rx_data);
+SpiPs_write_read1(0xA16,0x2A,&rx_data);
+SpiPs_write_read1(0xA17,0xAA,&rx_data);
+SpiPs_write_read1(0xA18,0xAA,&rx_data);
+SpiPs_write_read1(0xA19,0xAA,&rx_data);
+SpiPs_write_read1(0xA1A,0xAA,&rx_data);
+SpiPs_write_read1(0xA1B,0xAA,&rx_data);
+SpiPs_write_read1(0x186,0x01,&rx_data);
+SpiPs_write_read1(0x763,0x34,&rx_data);
+SpiPs_write_read1(0x76D,0x34,&rx_data);
+SpiPs_write_read1(0x101,0xEF,&rx_data);
+SpiPs_write_read1(0x101,0xFF,&rx_data);
+SpiPs_write_read1(0x800,0x00,&rx_data);
+SpiPs_write_read1(0x81A,0xF7,&rx_data);
+SpiPs_write_read1(0x81B,0x34,&rx_data);
+SpiPs_write_read1(0x81C,0x33,&rx_data);
+SpiPs_write_read1(0x81D,0x12,&rx_data);
+SpiPs_write_read1(0x81E,0x00,&rx_data);
+SpiPs_write_read1(0x81F,0xFF,&rx_data);
+SpiPs_write_read1(0x820,0x00,&rx_data);
+SpiPs_write_read1(0x821,0xFF,&rx_data);
+SpiPs_write_read1(0x800,0x80,&rx_data);
+SpiPs_write_read1(0x800,0x81,&rx_data);
+//最少0.1s
+usleep(100000);
+SpiPs_write_read1(0x77E,0x00,&rx_data);
+SpiPs_write_read1(0x77E,0x24,&rx_data);
+SpiPs_write_read1(0x11F,0x03,&rx_data);
+SpiPs_write_read1(0x121,0x02,&rx_data);
+SpiPs_write_read1(0x11B,0x01,&rx_data);
+SpiPs_write_read1(0x11E,0x01,&rx_data);
+SpiPs_write_read1(0x161,0x01,&rx_data);
+SpiPs_write_read1(0x162,0x01,&rx_data);
+SpiPs_write_read1(0x164,0x05,&rx_data);
+SpiPs_write_read1(0x165,0x55,&rx_data);
+SpiPs_write_read1(0x166,0x55,&rx_data);
+SpiPs_write_read1(0x167,0x55,&rx_data);
+SpiPs_write_read1(0x168,0x55,&rx_data);
+SpiPs_write_read1(0x169,0x55,&rx_data);
+SpiPs_write_read1(0xA2D,0x02,&rx_data);
+SpiPs_write_read1(0xA07,0x00,&rx_data);
+SpiPs_write_read1(0xA08,0x0F,&rx_data);
+SpiPs_write_read1(0xA1C,0x01,&rx_data);
+SpiPs_write_read1(0xA16,0x15,&rx_data);
+SpiPs_write_read1(0xA17,0x55,&rx_data);
+SpiPs_write_read1(0xA18,0x55,&rx_data);
+SpiPs_write_read1(0xA19,0x55,&rx_data);
+SpiPs_write_read1(0xA1A,0x55,&rx_data);
+SpiPs_write_read1(0xA1B,0x55,&rx_data);
+SpiPs_write_read1(0x81A,0xF7,&rx_data);
+SpiPs_write_read1(0x81B,0x44,&rx_data);
+SpiPs_write_read1(0x81C,0x33,&rx_data);
+SpiPs_write_read1(0x81D,0x14,&rx_data);
+SpiPs_write_read1(0x800,0x80,&rx_data);
+SpiPs_write_read1(0x800,0x82,&rx_data);
+//最少0.1s
+usleep(500000);
+SpiPs_write_read1(0x77E,0x00,&rx_data);
+//恢复校准前设置
+SpiPs_write_read1(0x000,0x02,&rx_data);
+SpiPs_write_read1(0x02E,0x06,&rx_data);
+SpiPs_write_read1(0x03D,0x1B,&rx_data);
+SpiPs_write_read1(0x03E,0x39,&rx_data);
+SpiPs_write_read1(0x03F,0x27,&rx_data);
+SpiPs_write_read1(0x040,0xF8,&rx_data);
+SpiPs_write_read1(0x109,0x11,&rx_data);
+SpiPs_write_read1(0x10A,0x70,&rx_data);
+SpiPs_write_read1(0x11B,0x01,&rx_data);
+SpiPs_write_read1(0x11E,0x01,&rx_data);
+SpiPs_write_read1(0x11F,0x33,&rx_data);
+SpiPs_write_read1(0x128,0x10,&rx_data);
+SpiPs_write_read1(0x161,0x01,&rx_data);
+SpiPs_write_read1(0x162,0x01,&rx_data);
+SpiPs_write_read1(0x164,0x05,&rx_data);
+SpiPs_write_read1(0x165,0x55,&rx_data);
+SpiPs_write_read1(0x166,0x55,&rx_data);
+SpiPs_write_read1(0x167,0x55,&rx_data);
+SpiPs_write_read1(0x168,0x55,&rx_data);
+SpiPs_write_read1(0x169,0x55,&rx_data);
+SpiPs_write_read1(0xA07,0x00,&rx_data);
+SpiPs_write_read1(0xA08,0x00,&rx_data);
+SpiPs_write_read1(0xA16,0x00,&rx_data);
+SpiPs_write_read1(0xA17,0x00,&rx_data);
+SpiPs_write_read1(0xA18,0x00,&rx_data);
+SpiPs_write_read1(0xA19,0x00,&rx_data);
+SpiPs_write_read1(0xA1A,0x00,&rx_data);
+SpiPs_write_read1(0xA1B,0x00,&rx_data);
+SpiPs_write_read1(0xA1C,0x00,&rx_data);
+SpiPs_write_read1(0xA2D,0x00,&rx_data);
+usleep(1000);
+SpiPs_write_read2(0x615,0x00,&rx_data);
+temp=rx_data;
+SpiPs_write_read2(0x635,0x00,&rx_data);
+temp=rx_data;
+////配置Tx NCO BIST ON
+//SpiPs_write_read1(0x11B,0x01,&rx_data);
+//SpiPs_write_read1(0x11E,0x01,&rx_data);
+//SpiPs_write_read1(0x161,0x01,&rx_data);
+//SpiPs_write_read1(0x162,0x01,&rx_data);
+////配置Tx NCO频率 1MHz
+//SpiPs_write_read1(0x164,0x05,&rx_data);
+//SpiPs_write_read1(0x165,0x55,&rx_data);
+//SpiPs_write_read1(0x166,0x55,&rx_data);
+//SpiPs_write_read1(0x167,0x55,&rx_data);
+//SpiPs_write_read1(0x168,0x55,&rx_data);
+//SpiPs_write_read1(0x169,0x55,&rx_data);
+}

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_DEMO/cx9261a_710_config.c

@@ -0,0 +1,835 @@
+/*
+ * cx9261a_710_config.c
+ *
+ *  Created on: 2024年3月21日
+ *      Author: cxlab
+ */
+
+
+/*
+ * cx9261a_076_config.c
+ *
+ *  Created on: 2023年11月30日
+ *      Author: cxlab
+ */
+
+
+#include "xilinx_io.h"
+#include "sleep.h"
+void cx9261a_710_config(void){
+u8 rx_data;
+u8 temp,r13D,r13E;
+
+//setPin(pin,value)
+GpioSetPinDir(0,0x01);
+GpioWritePin(0,1);
+GpioSetPinDir(32,0x01);
+GpioWritePin(32,1);
+GpioSetPinDir(33,0x01);
+GpioWritePin(33,1);
+GpioSetPinDir(34,0x01);
+GpioWritePin(34,0);
+GpioSetPinDir(35,0x01); //tx:0-rx:1
+GpioWritePin(35,1); //tx:0-rx:1
+GpioSetPinDir(36,0x01); //fdd:0-tdd:1
+GpioWritePin(36,1); //fdd:0-tdd:1
+GpioSetPinDir(37,0x01); //1r1t:0-2r2t:1
+GpioWritePin(37,1); //1r1t:0-2r2t:1
+GpioSetPinDir(38,0x01); //dualport:0-singleport:1
+GpioWritePin(38,1); //dualport:0-singleport:1
+GpioSetPinDir(39,0x01);
+GpioWritePin(39,1);
+GpioSetPinDir(40,0x01);
+GpioWritePin(40,1);
+//配置芯片
+//初始化芯片
+SpiPs_write_read1(0x000,0x02,&rx_data);
+SpiPs_write_read1(0x773,0x53,&rx_data);
+SpiPs_write_read1(0x774,0x86,&rx_data);
+SpiPs_write_read1(0x781,0x6F,&rx_data);
+SpiPs_write_read1(0x70B,0x0E,&rx_data);
+SpiPs_write_read1(0x727,0x0E,&rx_data);
+SpiPs_write_read1(0x743,0x0E,&rx_data);
+SpiPs_write_read1(0x624,0x11,&rx_data);
+SpiPs_write_read1(0x625,0x11,&rx_data);
+SpiPs_write_read1(0x61E,0x30,&rx_data);
+SpiPs_write_read1(0x61F,0x08,&rx_data);
+SpiPs_write_read1(0x621,0x4D,&rx_data);
+SpiPs_write_read1(0x622,0x19,&rx_data);
+SpiPs_write_read1(0x627,0x10,&rx_data);
+SpiPs_write_read1(0x646,0x11,&rx_data);
+SpiPs_write_read1(0x647,0x11,&rx_data);
+SpiPs_write_read1(0x640,0x30,&rx_data);
+SpiPs_write_read1(0x641,0x08,&rx_data);
+SpiPs_write_read1(0x643,0x4D,&rx_data);
+SpiPs_write_read1(0x644,0x19,&rx_data);
+SpiPs_write_read1(0x649,0x10,&rx_data);
+SpiPs_write_read1(0x668,0x11,&rx_data);
+SpiPs_write_read1(0x669,0x11,&rx_data);
+SpiPs_write_read1(0x662,0x30,&rx_data);
+SpiPs_write_read1(0x663,0x08,&rx_data);
+SpiPs_write_read1(0x665,0x4D,&rx_data);
+SpiPs_write_read1(0x666,0x19,&rx_data);
+SpiPs_write_read1(0x66B,0x10,&rx_data);
+SpiPs_write_read1(0x68A,0x11,&rx_data);
+SpiPs_write_read1(0x68B,0x11,&rx_data);
+SpiPs_write_read1(0x684,0x30,&rx_data);
+SpiPs_write_read1(0x685,0x08,&rx_data);
+SpiPs_write_read1(0x687,0x4D,&rx_data);
+SpiPs_write_read1(0x688,0x19,&rx_data);
+SpiPs_write_read1(0x68D,0x10,&rx_data);
+SpiPs_write_read1(0x6AC,0x11,&rx_data);
+SpiPs_write_read1(0x6AD,0x11,&rx_data);
+SpiPs_write_read1(0x6A6,0x30,&rx_data);
+SpiPs_write_read1(0x6A7,0x08,&rx_data);
+SpiPs_write_read1(0x6A9,0x4D,&rx_data);
+SpiPs_write_read1(0x6AA,0x19,&rx_data);
+SpiPs_write_read1(0x6AF,0x10,&rx_data);
+SpiPs_write_read1(0x705,0xFC,&rx_data);
+SpiPs_write_read1(0x706,0x6D,&rx_data);
+SpiPs_write_read1(0x707,0x91,&rx_data);
+SpiPs_write_read1(0x708,0x04,&rx_data);
+SpiPs_write_read1(0x709,0x94,&rx_data);
+SpiPs_write_read1(0x70A,0xFC,&rx_data);
+SpiPs_write_read1(0x70C,0xC0,&rx_data);
+SpiPs_write_read1(0x721,0xFC,&rx_data);
+SpiPs_write_read1(0x722,0x6D,&rx_data);
+SpiPs_write_read1(0x723,0x91,&rx_data);
+SpiPs_write_read1(0x724,0x04,&rx_data);
+SpiPs_write_read1(0x725,0x94,&rx_data);
+SpiPs_write_read1(0x726,0xFC,&rx_data);
+SpiPs_write_read1(0x728,0xC0,&rx_data);
+SpiPs_write_read1(0x73D,0xFC,&rx_data);
+SpiPs_write_read1(0x73E,0x6D,&rx_data);
+SpiPs_write_read1(0x73F,0x91,&rx_data);
+SpiPs_write_read1(0x740,0x04,&rx_data);
+SpiPs_write_read1(0x741,0x94,&rx_data);
+SpiPs_write_read1(0x742,0xFC,&rx_data);
+SpiPs_write_read1(0x744,0xC0,&rx_data);
+SpiPs_write_read1(0x75A,0x83,&rx_data);
+SpiPs_write_read1(0x75B,0xDA,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x75B,0x9A,&rx_data);
+SpiPs_write_read1(0x75C,0x81,&rx_data);
+SpiPs_write_read1(0x763,0x04,&rx_data);
+SpiPs_write_read1(0x764,0x83,&rx_data);
+SpiPs_write_read1(0x765,0xDA,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x765,0x9A,&rx_data);
+SpiPs_write_read1(0x766,0x81,&rx_data);
+SpiPs_write_read1(0x76D,0x04,&rx_data);
+//初始化电源
+SpiPs_write_read1(0x031,0x00,&rx_data);
+SpiPs_write_read1(0x032,0x7F,&rx_data);
+SpiPs_write_read1(0x033,0xFF,&rx_data);
+SpiPs_write_read1(0x034,0xFF,&rx_data);
+SpiPs_write_read1(0x035,0x00,&rx_data);
+SpiPs_write_read1(0x036,0x3D,&rx_data);
+SpiPs_write_read1(0x037,0xFF,&rx_data);
+SpiPs_write_read1(0x038,0xFB,&rx_data);
+SpiPs_write_read1(0x039,0x00,&rx_data);
+SpiPs_write_read1(0x03A,0x3D,&rx_data);
+SpiPs_write_read1(0x03B,0xFF,&rx_data);
+SpiPs_write_read1(0x03C,0xF8,&rx_data);
+SpiPs_write_read1(0x03D,0x1B,&rx_data);
+SpiPs_write_read1(0x03E,0x39,&rx_data);
+SpiPs_write_read1(0x03F,0x26,&rx_data);
+SpiPs_write_read1(0x040,0x78,&rx_data);
+SpiPs_write_read1(0x041,0x03,&rx_data);
+SpiPs_write_read1(0x042,0x3D,&rx_data);
+SpiPs_write_read1(0x043,0xE7,&rx_data);
+SpiPs_write_read1(0x044,0xF8,&rx_data);
+SpiPs_write_read1(0x045,0x18,&rx_data);
+SpiPs_write_read1(0x046,0x3D,&rx_data);
+SpiPs_write_read1(0x047,0x3F,&rx_data);
+SpiPs_write_read1(0x048,0xF8,&rx_data);
+SpiPs_write_read1(0x049,0x1F,&rx_data);
+SpiPs_write_read1(0x04A,0x3D,&rx_data);
+SpiPs_write_read1(0x04B,0x07,&rx_data);
+SpiPs_write_read1(0x04C,0xF8,&rx_data);
+SpiPs_write_read1(0x04D,0x04,&rx_data);
+SpiPs_write_read1(0x04E,0x3D,&rx_data);
+SpiPs_write_read1(0x04F,0xD9,&rx_data);
+SpiPs_write_read1(0x050,0xFE,&rx_data);
+//自定义接收模式
+SpiPs_write_read1(0x041,0x03,&rx_data);
+SpiPs_write_read1(0x042,0x3D,&rx_data);
+SpiPs_write_read1(0x043,0xE7,&rx_data);
+SpiPs_write_read1(0x044,0xF8,&rx_data);
+//自定义发射模式
+SpiPs_write_read1(0x045,0x18,&rx_data);
+SpiPs_write_read1(0x046,0x3D,&rx_data);
+SpiPs_write_read1(0x047,0x3F,&rx_data);
+SpiPs_write_read1(0x048,0xF8,&rx_data);
+//自定义FDD模式
+SpiPs_write_read1(0x049,0x1B,&rx_data);
+SpiPs_write_read1(0x04A,0x3D,&rx_data);
+SpiPs_write_read1(0x04B,0x27,&rx_data);
+SpiPs_write_read1(0x04C,0xF8,&rx_data);
+//配置BBPLL
+SpiPs_write_read1(0x789,0x10,&rx_data);
+SpiPs_write_read1(0x785,0x49,&rx_data);
+SpiPs_write_read1(0x788,0x24,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x788,0xA4,&rx_data);
+SpiPs_write_read1(0x0C0,0x50,&rx_data);
+SpiPs_write_read1(0x0C1,0x50,&rx_data);
+SpiPs_write_read1(0x0C2,0x50,&rx_data);
+SpiPs_write_read1(0x601,0x0F,&rx_data);
+SpiPs_write_read1(0x602,0x21,&rx_data);
+SpiPs_write_read1(0x60D,0x0D,&rx_data);
+SpiPs_write_read1(0x60E,0xFF,&rx_data);
+SpiPs_write_read1(0x60F,0xFF,&rx_data);
+SpiPs_write_read1(0x610,0xFF,&rx_data);
+SpiPs_write_read1(0x611,0x2F,&rx_data);
+SpiPs_write_read1(0x612,0x00,&rx_data);
+SpiPs_write_read1(0x70E,0x6B,&rx_data);
+SpiPs_write_read1(0x72A,0x6B,&rx_data);
+SpiPs_write_read1(0x746,0x6B,&rx_data);
+SpiPs_write_read1(0x70F,0xE0,&rx_data);
+SpiPs_write_read1(0x72B,0xE0,&rx_data);
+SpiPs_write_read1(0x747,0xE0,&rx_data);
+SpiPs_write_read1(0x70D,0x43,&rx_data);
+SpiPs_write_read1(0x729,0x43,&rx_data);
+SpiPs_write_read1(0x745,0x43,&rx_data);
+SpiPs_write_read1(0x782,0x76,&rx_data);
+SpiPs_write_read1(0x783,0x76,&rx_data);
+SpiPs_write_read1(0x784,0x06,&rx_data);
+//配置PLL来源
+SpiPs_write_read1(0x77D,0xCF,&rx_data);
+SpiPs_write_read1(0x775,0x24,&rx_data);
+SpiPs_write_read1(0x6C3,0x00,&rx_data);
+//配置PLL1
+SpiPs_write_read1(0x620,0x91,&rx_data);
+SpiPs_write_read1(0x61D,0x37,&rx_data);
+SpiPs_write_read1(0xB06,0x00,&rx_data);
+SpiPs_write_read1(0xB07,0xCB,&rx_data);
+SpiPs_write_read1(0xB08,0x20,&rx_data);
+SpiPs_write_read1(0xB09,0x00,&rx_data);
+SpiPs_write_read1(0xB0A,0x00,&rx_data);
+SpiPs_write_read1(0x61A,0x0C,&rx_data);
+SpiPs_write_read1(0x61B,0x30,&rx_data);
+SpiPs_write_read1(0x61C,0x08,&rx_data);
+SpiPs_write_read1(0x62A,0x0B,&rx_data);
+//配置PLL2
+SpiPs_write_read1(0x642,0x91,&rx_data);
+SpiPs_write_read1(0x63F,0x35,&rx_data);
+SpiPs_write_read1(0xB14,0x00,&rx_data);
+SpiPs_write_read1(0xB15,0xFA,&rx_data);
+SpiPs_write_read1(0xB16,0x00,&rx_data);
+SpiPs_write_read1(0xB17,0x00,&rx_data);
+SpiPs_write_read1(0xB18,0x00,&rx_data);
+SpiPs_write_read1(0x63C,0x0D,&rx_data);
+SpiPs_write_read1(0x63D,0x30,&rx_data);
+SpiPs_write_read1(0x63E,0x0B,&rx_data);
+SpiPs_write_read1(0x64C,0x00,&rx_data);
+//配置PLL3
+SpiPs_write_read1(0x664,0x81,&rx_data);
+SpiPs_write_read1(0x661,0x36,&rx_data);
+SpiPs_write_read1(0xB22,0x00,&rx_data);
+SpiPs_write_read1(0xB23,0xBB,&rx_data);
+SpiPs_write_read1(0xB24,0x80,&rx_data);
+SpiPs_write_read1(0xB25,0x00,&rx_data);
+SpiPs_write_read1(0xB26,0x00,&rx_data);
+SpiPs_write_read1(0x65E,0x0B,&rx_data);
+SpiPs_write_read1(0x65F,0x30,&rx_data);
+SpiPs_write_read1(0x660,0x0E,&rx_data);
+SpiPs_write_read1(0x66E,0x0B,&rx_data);
+//配置PLL4
+SpiPs_write_read1(0x686,0x91,&rx_data);
+SpiPs_write_read1(0x683,0x36,&rx_data);
+SpiPs_write_read1(0xB30,0x00,&rx_data);
+SpiPs_write_read1(0xB31,0xDA,&rx_data);
+SpiPs_write_read1(0xB32,0xC0,&rx_data);
+SpiPs_write_read1(0xB33,0x00,&rx_data);
+SpiPs_write_read1(0xB34,0x00,&rx_data);
+SpiPs_write_read1(0x680,0x0C,&rx_data);
+SpiPs_write_read1(0x681,0x30,&rx_data);
+SpiPs_write_read1(0x682,0x08,&rx_data);
+SpiPs_write_read1(0x690,0x0B,&rx_data);
+//配置PLL5
+SpiPs_write_read1(0x6A8,0x81,&rx_data);
+SpiPs_write_read1(0x6A5,0x36,&rx_data);
+SpiPs_write_read1(0xB3E,0x00,&rx_data);
+SpiPs_write_read1(0xB3F,0x9C,&rx_data);
+SpiPs_write_read1(0xB40,0x40,&rx_data);
+SpiPs_write_read1(0xB41,0x00,&rx_data);
+SpiPs_write_read1(0xB42,0x00,&rx_data);
+SpiPs_write_read1(0x6A2,0x0C,&rx_data);
+SpiPs_write_read1(0x6A3,0x30,&rx_data);
+SpiPs_write_read1(0x6A4,0x0C,&rx_data);
+SpiPs_write_read1(0x6B2,0x0B,&rx_data);
+//配置Tx1通道频率相关寄存器
+SpiPs_write_read1(0x75F,0x55,&rx_data);
+SpiPs_write_read1(0x761,0x04,&rx_data);
+SpiPs_write_read1(0x762,0x70,&rx_data);
+//配置Tx1通道频率相关寄存器
+SpiPs_write_read1(0x769,0x55,&rx_data);
+SpiPs_write_read1(0x76B,0x04,&rx_data);
+SpiPs_write_read1(0x76C,0x70,&rx_data);
+//配置Rx1通道
+SpiPs_write_read1(0x700,0x56,&rx_data);
+SpiPs_write_read1(0x701,0x00,&rx_data);
+SpiPs_write_read1(0x702,0xDB,&rx_data);
+SpiPs_write_read1(0x703,0x45,&rx_data);
+SpiPs_write_read1(0x704,0xF8,&rx_data);
+SpiPs_write_read1(0x907,0x1F,&rx_data);
+//配置Rx2通道
+SpiPs_write_read1(0x71C,0x56,&rx_data);
+SpiPs_write_read1(0x71D,0x00,&rx_data);
+SpiPs_write_read1(0x71E,0xDB,&rx_data);
+SpiPs_write_read1(0x71F,0x45,&rx_data);
+SpiPs_write_read1(0x720,0xF8,&rx_data);
+SpiPs_write_read1(0x907,0x1F,&rx_data);
+//配置Rx3通道
+SpiPs_write_read1(0x738,0x56,&rx_data);
+SpiPs_write_read1(0x739,0x00,&rx_data);
+SpiPs_write_read1(0x73A,0xDB,&rx_data);
+SpiPs_write_read1(0x73B,0x45,&rx_data);
+SpiPs_write_read1(0x73C,0xF8,&rx_data);
+SpiPs_write_read1(0x907,0x1F,&rx_data);
+//配置Tx1通道
+SpiPs_write_read1(0x75E,0xFF,&rx_data);
+SpiPs_write_read1(0x75D,0x4A,&rx_data);
+SpiPs_write_read1(0x75F,0x7D,&rx_data);
+SpiPs_write_read1(0x760,0xFF,&rx_data);
+//配置Tx2通道
+SpiPs_write_read1(0x768,0xFF,&rx_data);
+SpiPs_write_read1(0x767,0x4A,&rx_data);
+SpiPs_write_read1(0x769,0x7D,&rx_data);
+SpiPs_write_read1(0x76A,0xFF,&rx_data);
+//配置Rx滤波器
+SpiPs_write_read1(0x106,0x02,&rx_data);
+//配置Tx滤波器
+SpiPs_write_read1(0x107,0x00,&rx_data);
+SpiPs_write_read1(0x108,0xD0,&rx_data);
+//配置Rx混频器
+SpiPs_write_read1(0x11C,0x00,&rx_data);
+SpiPs_write_read1(0xA07,0x00,&rx_data);
+SpiPs_write_read1(0xA08,0x00,&rx_data);
+SpiPs_write_read1(0xA09,0x00,&rx_data);
+SpiPs_write_read1(0xA16,0x00,&rx_data);
+SpiPs_write_read1(0xA17,0x00,&rx_data);
+SpiPs_write_read1(0xA18,0x00,&rx_data);
+SpiPs_write_read1(0xA19,0x00,&rx_data);
+SpiPs_write_read1(0xA1A,0x00,&rx_data);
+SpiPs_write_read1(0xA1B,0x00,&rx_data);
+//配置Tx混频器
+SpiPs_write_read1(0x128,0x10,&rx_data);
+SpiPs_write_read1(0x11B,0x00,&rx_data);
+SpiPs_write_read1(0x11E,0x00,&rx_data);
+SpiPs_write_read1(0x161,0x00,&rx_data);
+SpiPs_write_read1(0x162,0x00,&rx_data);
+SpiPs_write_read1(0x164,0x00,&rx_data);
+SpiPs_write_read1(0x165,0x00,&rx_data);
+SpiPs_write_read1(0x166,0x00,&rx_data);
+SpiPs_write_read1(0x167,0x00,&rx_data);
+SpiPs_write_read1(0x168,0x00,&rx_data);
+SpiPs_write_read1(0x169,0x00,&rx_data);
+//配置AGC
+SpiPs_write_read1(0x903,0x11,&rx_data);
+SpiPs_write_read1(0x900,0x00,&rx_data);
+SpiPs_write_read1(0x901,0x00,&rx_data);
+SpiPs_write_read1(0x908,0x77,&rx_data);
+SpiPs_write_read1(0x909,0x03,&rx_data);
+SpiPs_write_read1(0x90A,0x32,&rx_data);
+SpiPs_write_read1(0x90D,0x00,&rx_data);
+SpiPs_write_read1(0x90E,0x0F,&rx_data);
+SpiPs_write_read1(0x90F,0x65,&rx_data);
+SpiPs_write_read1(0x910,0x32,&rx_data);
+SpiPs_write_read1(0x911,0x00,&rx_data);
+SpiPs_write_read1(0x912,0x0F,&rx_data);
+SpiPs_write_read1(0x913,0x3A,&rx_data);
+SpiPs_write_read1(0x914,0x37,&rx_data);
+SpiPs_write_read1(0x915,0x34,&rx_data);
+SpiPs_write_read1(0x916,0x31,&rx_data);
+//切换到休眠模式
+SpiPs_write_read1(0x02E,0x01,&rx_data);
+usleep(1000000);
+//切换到校准模式
+SpiPs_write_read1(0x02E,0x03,&rx_data);
+usleep(100000);
+//BBPll锁定
+SpiPs_write_read1(0x600,0x00,&rx_data);
+SpiPs_write_read1(0x600,0x11,&rx_data);
+usleep(100000);
+//BBPll锁定 成功
+//ADC校准
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x70F,0xE0,&rx_data);
+SpiPs_write_read1(0x710,0x83,&rx_data);
+SpiPs_write_read1(0x711,0xF0,&rx_data);
+SpiPs_write_read1(0x72B,0xE0,&rx_data);
+SpiPs_write_read1(0x72C,0x83,&rx_data);
+SpiPs_write_read1(0x72D,0xF0,&rx_data);
+SpiPs_write_read1(0x747,0xE0,&rx_data);
+SpiPs_write_read1(0x748,0x83,&rx_data);
+SpiPs_write_read1(0x749,0xF0,&rx_data);
+SpiPs_write_read1(0x713,0x80,&rx_data);
+SpiPs_write_read1(0x72F,0x80,&rx_data);
+SpiPs_write_read1(0x74B,0x80,&rx_data);
+SpiPs_write_read1(0x70B,0x9E,&rx_data);
+SpiPs_write_read1(0x727,0x9E,&rx_data);
+SpiPs_write_read1(0x743,0x9E,&rx_data);
+SpiPs_write_read1(0x70B,0x9A,&rx_data);
+SpiPs_write_read1(0x727,0x9A,&rx_data);
+SpiPs_write_read1(0x743,0x9A,&rx_data);
+SpiPs_write_read1(0x70B,0x9E,&rx_data);
+SpiPs_write_read1(0x727,0x9E,&rx_data);
+SpiPs_write_read1(0x743,0x9E,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x713,0xC0,&rx_data);
+SpiPs_write_read1(0x72F,0xC0,&rx_data);
+SpiPs_write_read1(0x74B,0xC0,&rx_data);
+//flash校准
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x715,0x80,&rx_data);
+SpiPs_write_read1(0x731,0x80,&rx_data);
+SpiPs_write_read1(0x74D,0x80,&rx_data);
+SpiPs_write_read1(0x715,0xC0,&rx_data);
+SpiPs_write_read1(0x731,0xC0,&rx_data);
+SpiPs_write_read1(0x74D,0xC0,&rx_data);
+SpiPs_write_read1(0x716,0x40,&rx_data);
+SpiPs_write_read1(0x732,0x40,&rx_data);
+SpiPs_write_read1(0x74E,0x40,&rx_data);
+SpiPs_write_read1(0x70B,0x16,&rx_data);
+SpiPs_write_read1(0x727,0x16,&rx_data);
+SpiPs_write_read1(0x743,0x16,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x715,0x80,&rx_data);
+SpiPs_write_read1(0x731,0x80,&rx_data);
+SpiPs_write_read1(0x74D,0x80,&rx_data);
+SpiPs_write_read1(0x716,0x00,&rx_data);
+SpiPs_write_read1(0x732,0x00,&rx_data);
+SpiPs_write_read1(0x74E,0x00,&rx_data);
+//DC Tracking
+SpiPs_write_read1(0x109,0x11,&rx_data);
+SpiPs_write_read1(0x10A,0x70,&rx_data);
+SpiPs_write_read1(0x11F,0x33,&rx_data);
+//Rx1 QEC校准
+SpiPs_write_read1(0x02E,0x03,&rx_data);
+SpiPs_write_read1(0x03F,0x26,&rx_data);
+SpiPs_write_read1(0x040,0x78,&rx_data);
+SpiPs_write_read1(0x77D,0x90,&rx_data);
+SpiPs_write_read1(0x775,0x24,&rx_data);
+SpiPs_write_read1(0x6C3,0x05,&rx_data);
+SpiPs_write_read1(0x61D,0x27,&rx_data);
+SpiPs_write_read1(0x617,0x00,&rx_data);
+SpiPs_write_read1(0x617,0x03,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x61D,0x37,&rx_data);
+SpiPs_write_read1(0x686,0x81,&rx_data);
+SpiPs_write_read1(0x683,0x36,&rx_data);
+SpiPs_write_read1(0xB30,0x00,&rx_data);
+SpiPs_write_read1(0xB31,0x87,&rx_data);
+SpiPs_write_read1(0xB32,0x04,&rx_data);
+SpiPs_write_read1(0xB33,0x44,&rx_data);
+SpiPs_write_read1(0xB34,0x44,&rx_data);
+SpiPs_write_read1(0x680,0x0C,&rx_data);
+SpiPs_write_read1(0x681,0x30,&rx_data);
+SpiPs_write_read1(0x682,0x0C,&rx_data);
+SpiPs_write_read1(0x690,0x0B,&rx_data);
+SpiPs_write_read1(0x683,0x26,&rx_data);
+SpiPs_write_read1(0x67D,0x00,&rx_data);
+SpiPs_write_read1(0x67D,0x03,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x683,0x36,&rx_data);
+SpiPs_write_read1(0x000,0x12,&rx_data);
+SpiPs_write_read1(0x77E,0x50,&rx_data);
+SpiPs_write_read1(0x11B,0x01,&rx_data);
+SpiPs_write_read1(0x11E,0x01,&rx_data);
+SpiPs_write_read1(0x164,0x00,&rx_data);
+SpiPs_write_read1(0x165,0x00,&rx_data);
+SpiPs_write_read1(0x166,0x00,&rx_data);
+SpiPs_write_read1(0x167,0x00,&rx_data);
+SpiPs_write_read1(0x168,0x00,&rx_data);
+SpiPs_write_read1(0x169,0x00,&rx_data);
+SpiPs_write_read1(0x161,0x00,&rx_data);
+SpiPs_write_read1(0x162,0x00,&rx_data);
+SpiPs_write_read1(0x162,0x01,&rx_data);
+SpiPs_write_read1(0x161,0x01,&rx_data);
+SpiPs_write_read1(0x706,0x65,&rx_data);
+SpiPs_write_read1(0x6C3,0x00,&rx_data);
+SpiPs_write_read1(0x75F,0x7D,&rx_data);
+SpiPs_write_read1(0x11F,0x73,&rx_data);
+SpiPs_write_read1(0x153,0x00,&rx_data);
+SpiPs_write_read1(0x708,0x24,&rx_data);
+SpiPs_write_read1(0x196,0x01,&rx_data);
+SpiPs_write_read1(0x02A,0x12,&rx_data);
+
+do{
+usleep(100);
+SpiPs_write_read2(0x14D,0x00,&rx_data);
+temp=rx_data&0x10;
+}while (temp != 16);
+
+SpiPs_write_read1(0x02A,0x00,&rx_data);
+SpiPs_write_read1(0x196,0x11,&rx_data);
+SpiPs_write_read2(0x13D,0x00,&rx_data);
+r13D = rx_data;
+SpiPs_write_read2(0x13E,0x00,&rx_data);
+r13E = rx_data;
+
+unsigned long B = r13D * 256 + r13E;
+signed long B_s = B - (B >= 32768) * 65536;
+unsigned long B_abs = abs(B_s);
+unsigned short B_b = (unsigned short)B_abs;
+unsigned short B_delay = (B_b>>6) & 0x1ff;
+
+if(B_s > 0)
+{
+   SpiPs_write_read1(0x199, ((B_delay>>8)&0x1),&rx_data);
+   SpiPs_write_read1(0x19A,   B_delay&0xff,&rx_data);
+   SpiPs_write_read1(0x19B, 0,&rx_data);
+   SpiPs_write_read1(0x19C, 0,&rx_data);
+}
+else
+{
+   SpiPs_write_read1(0x199, 0,&rx_data);
+   SpiPs_write_read1(0x19A, 0,&rx_data);
+   SpiPs_write_read1(0x19B, ((B_delay>>8)&0x1),&rx_data);
+   SpiPs_write_read1(0x19C,   B_delay&0xff,&rx_data);
+}
+
+SpiPs_write_read1(0x196,0x10,&rx_data);
+SpiPs_write_read1(0x153,0x00,&rx_data);
+SpiPs_write_read1(0x02A,0x12,&rx_data);
+
+do{
+usleep(100);
+SpiPs_write_read2(0x14D,0x00,&rx_data);
+temp=rx_data&0x10;
+}while (temp != 16);
+
+SpiPs_write_read1(0x02A,0x00,&rx_data);
+SpiPs_write_read1(0x77E,0x00,&rx_data);
+SpiPs_write_read1(0x000,0x02,&rx_data);
+//Rx2 QEC校准
+SpiPs_write_read1(0x02E,0x03,&rx_data);
+SpiPs_write_read1(0x03F,0x26,&rx_data);
+SpiPs_write_read1(0x040,0x78,&rx_data);
+SpiPs_write_read1(0x77D,0x60,&rx_data);
+SpiPs_write_read1(0x775,0x24,&rx_data);
+SpiPs_write_read1(0x6C3,0x0A,&rx_data);
+SpiPs_write_read1(0x61D,0x27,&rx_data);
+SpiPs_write_read1(0x617,0x00,&rx_data);
+SpiPs_write_read1(0x617,0x03,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x61D,0x37,&rx_data);
+SpiPs_write_read1(0x686,0x81,&rx_data);
+SpiPs_write_read1(0x683,0x36,&rx_data);
+SpiPs_write_read1(0xB30,0x00,&rx_data);
+SpiPs_write_read1(0xB31,0x87,&rx_data);
+SpiPs_write_read1(0xB32,0x04,&rx_data);
+SpiPs_write_read1(0xB33,0x44,&rx_data);
+SpiPs_write_read1(0xB34,0x44,&rx_data);
+SpiPs_write_read1(0x680,0x0C,&rx_data);
+SpiPs_write_read1(0x681,0x30,&rx_data);
+SpiPs_write_read1(0x682,0x0C,&rx_data);
+SpiPs_write_read1(0x690,0x0B,&rx_data);
+SpiPs_write_read1(0x683,0x26,&rx_data);
+SpiPs_write_read1(0x67D,0x00,&rx_data);
+SpiPs_write_read1(0x67D,0x03,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x683,0x36,&rx_data);
+SpiPs_write_read1(0x000,0x22,&rx_data);
+SpiPs_write_read1(0x77E,0x0A,&rx_data);
+SpiPs_write_read1(0x11B,0x01,&rx_data);
+SpiPs_write_read1(0x11E,0x01,&rx_data);
+SpiPs_write_read1(0x164,0x00,&rx_data);
+SpiPs_write_read1(0x165,0x00,&rx_data);
+SpiPs_write_read1(0x166,0x00,&rx_data);
+SpiPs_write_read1(0x167,0x00,&rx_data);
+SpiPs_write_read1(0x168,0x00,&rx_data);
+SpiPs_write_read1(0x169,0x00,&rx_data);
+SpiPs_write_read1(0x161,0x00,&rx_data);
+SpiPs_write_read1(0x162,0x00,&rx_data);
+SpiPs_write_read1(0x162,0x01,&rx_data);
+SpiPs_write_read1(0x161,0x01,&rx_data);
+SpiPs_write_read1(0x706,0x65,&rx_data);
+SpiPs_write_read1(0x6C3,0x00,&rx_data);
+SpiPs_write_read1(0x75F,0x7D,&rx_data);
+SpiPs_write_read1(0x11F,0x73,&rx_data);
+SpiPs_write_read1(0x153,0x00,&rx_data);
+SpiPs_write_read1(0x724,0x24,&rx_data);
+SpiPs_write_read1(0x196,0x01,&rx_data);
+SpiPs_write_read1(0x02B,0x12,&rx_data);
+
+do{
+usleep(100);
+SpiPs_write_read2(0x14D,0x00,&rx_data);
+temp=rx_data&0x10;
+}while (temp != 16);
+
+SpiPs_write_read1(0x02B,0x00,&rx_data);
+SpiPs_write_read1(0x196,0x11,&rx_data);
+SpiPs_write_read2(0x13D,0x00,&rx_data);
+r13D = rx_data;
+SpiPs_write_read2(0x13E,0x00,&rx_data);
+r13E = rx_data;
+
+B = r13D * 256 + r13E;
+B_s = B - (B >= 32768) * 65536;
+B_abs = abs(B_s);
+B_b = (unsigned short)B_abs;
+B_delay = (B_b>>6) & 0x1ff;
+
+if(B_s > 0)
+{
+   SpiPs_write_read1(0x199, ((B_delay>>8)&0x1),&rx_data);
+   SpiPs_write_read1(0x19A,   B_delay&0xff,&rx_data);
+   SpiPs_write_read1(0x19B, 0,&rx_data);
+   SpiPs_write_read1(0x19C, 0,&rx_data);
+}
+else
+{
+   SpiPs_write_read1(0x199, 0,&rx_data);
+   SpiPs_write_read1(0x19A, 0,&rx_data);
+   SpiPs_write_read1(0x19B, ((B_delay>>8)&0x1),&rx_data);
+   SpiPs_write_read1(0x19C,   B_delay&0xff,&rx_data);
+}
+
+SpiPs_write_read1(0x196,0x10,&rx_data);
+SpiPs_write_read1(0x153,0x00,&rx_data);
+SpiPs_write_read1(0x02B,0x12,&rx_data);
+
+do{
+usleep(100);
+SpiPs_write_read2(0x14D,0x00,&rx_data);
+temp=rx_data&0x10;
+}while (temp != 16);
+
+SpiPs_write_read1(0x02B,0x00,&rx_data);
+SpiPs_write_read1(0x77E,0x00,&rx_data);
+SpiPs_write_read1(0x000,0x02,&rx_data);
+//恢复校准中被改变的配置
+SpiPs_write_read1(0x000,0x02,&rx_data);
+SpiPs_write_read1(0x02E,0x03,&rx_data);
+SpiPs_write_read1(0x109,0x11,&rx_data);
+SpiPs_write_read1(0x10A,0x70,&rx_data);
+SpiPs_write_read1(0x11B,0x00,&rx_data);
+SpiPs_write_read1(0x11E,0x00,&rx_data);
+SpiPs_write_read1(0x11F,0x33,&rx_data);
+SpiPs_write_read1(0x128,0x10,&rx_data);
+SpiPs_write_read1(0x161,0x00,&rx_data);
+SpiPs_write_read1(0x162,0x00,&rx_data);
+SpiPs_write_read1(0x164,0x00,&rx_data);
+SpiPs_write_read1(0x165,0x00,&rx_data);
+SpiPs_write_read1(0x166,0x00,&rx_data);
+SpiPs_write_read1(0x167,0x00,&rx_data);
+SpiPs_write_read1(0x168,0x00,&rx_data);
+SpiPs_write_read1(0x169,0x00,&rx_data);
+SpiPs_write_read1(0x6C3,0x00,&rx_data);
+SpiPs_write_read1(0x775,0x24,&rx_data);
+SpiPs_write_read1(0x77D,0xCF,&rx_data);
+SpiPs_write_read1(0xA07,0x00,&rx_data);
+SpiPs_write_read1(0xA08,0x00,&rx_data);
+SpiPs_write_read1(0xA16,0x00,&rx_data);
+SpiPs_write_read1(0xA17,0x00,&rx_data);
+SpiPs_write_read1(0xA18,0x00,&rx_data);
+SpiPs_write_read1(0xA19,0x00,&rx_data);
+SpiPs_write_read1(0xA1A,0x00,&rx_data);
+SpiPs_write_read1(0xA1B,0x00,&rx_data);
+SpiPs_write_read1(0x686,0x91,&rx_data);
+SpiPs_write_read1(0x683,0x36,&rx_data);
+SpiPs_write_read1(0xB30,0x00,&rx_data);
+SpiPs_write_read1(0xB31,0xDA,&rx_data);
+SpiPs_write_read1(0xB32,0xC0,&rx_data);
+SpiPs_write_read1(0xB33,0x00,&rx_data);
+SpiPs_write_read1(0xB34,0x00,&rx_data);
+SpiPs_write_read1(0x680,0x0C,&rx_data);
+SpiPs_write_read1(0x681,0x30,&rx_data);
+SpiPs_write_read1(0x682,0x08,&rx_data);
+SpiPs_write_read1(0x690,0x0B,&rx_data);
+//TX校准
+SpiPs_write_read1(0x03F,0x27,&rx_data);
+SpiPs_write_read1(0x040,0xF8,&rx_data);
+SpiPs_write_read1(0x61D,0x27,&rx_data);
+SpiPs_write_read1(0x617,0x00,&rx_data);
+SpiPs_write_read1(0x617,0x03,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x61D,0x37,&rx_data);
+SpiPs_write_read1(0x02E,0x03,&rx_data);
+SpiPs_write_read1(0x128,0x11,&rx_data);
+SpiPs_write_read1(0x11E,0x01,&rx_data);
+SpiPs_write_read1(0x77E,0x24,&rx_data);
+SpiPs_write_read1(0x11F,0x01,&rx_data);
+SpiPs_write_read1(0x121,0x02,&rx_data);
+SpiPs_write_read1(0x11B,0x01,&rx_data);
+SpiPs_write_read1(0x161,0x01,&rx_data);
+SpiPs_write_read1(0x162,0x01,&rx_data);
+SpiPs_write_read1(0x163,0x00,&rx_data);
+SpiPs_write_read1(0x164,0x04,&rx_data);
+SpiPs_write_read1(0x165,0x00,&rx_data);
+SpiPs_write_read1(0x166,0x00,&rx_data);
+SpiPs_write_read1(0x167,0x00,&rx_data);
+SpiPs_write_read1(0x168,0x00,&rx_data);
+SpiPs_write_read1(0x169,0x00,&rx_data);
+SpiPs_write_read1(0xA2D,0x02,&rx_data);
+SpiPs_write_read1(0xA07,0x00,&rx_data);
+SpiPs_write_read1(0xA08,0x0F,&rx_data);
+SpiPs_write_read1(0xA1C,0x01,&rx_data);
+SpiPs_write_read1(0xA16,0x20,&rx_data);
+SpiPs_write_read1(0xA17,0x00,&rx_data);
+SpiPs_write_read1(0xA18,0x00,&rx_data);
+SpiPs_write_read1(0xA19,0x00,&rx_data);
+SpiPs_write_read1(0xA1A,0x00,&rx_data);
+SpiPs_write_read1(0xA1B,0x00,&rx_data);
+SpiPs_write_read1(0x102,0x0F,&rx_data);
+SpiPs_write_read1(0x102,0xFF,&rx_data);
+SpiPs_write_read1(0x186,0x00,&rx_data);
+SpiPs_write_read1(0x186,0x01,&rx_data);
+SpiPs_write_read1(0x763,0x34,&rx_data);
+SpiPs_write_read1(0x76D,0x34,&rx_data);
+SpiPs_write_read1(0x101,0xEF,&rx_data);
+SpiPs_write_read1(0x101,0xFF,&rx_data);
+SpiPs_write_read1(0x800,0x00,&rx_data);
+SpiPs_write_read1(0x81A,0xF7,&rx_data);
+SpiPs_write_read1(0x81B,0x34,&rx_data);
+SpiPs_write_read1(0x81C,0x33,&rx_data);
+SpiPs_write_read1(0x81D,0x12,&rx_data);
+SpiPs_write_read1(0x81E,0x00,&rx_data);
+SpiPs_write_read1(0x81F,0xFF,&rx_data);
+SpiPs_write_read1(0x820,0x00,&rx_data);
+SpiPs_write_read1(0x821,0xFF,&rx_data);
+SpiPs_write_read1(0x800,0x80,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x800,0x81,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x77E,0x00,&rx_data);
+SpiPs_write_read1(0x77E,0x24,&rx_data);
+SpiPs_write_read1(0x11F,0x03,&rx_data);
+SpiPs_write_read1(0x121,0x02,&rx_data);
+SpiPs_write_read1(0x11B,0x01,&rx_data);
+SpiPs_write_read1(0x11E,0x01,&rx_data);
+SpiPs_write_read1(0x161,0x01,&rx_data);
+SpiPs_write_read1(0x162,0x01,&rx_data);
+SpiPs_write_read1(0x164,0x04,&rx_data);
+SpiPs_write_read1(0x165,0x00,&rx_data);
+SpiPs_write_read1(0x166,0x00,&rx_data);
+SpiPs_write_read1(0x167,0x00,&rx_data);
+SpiPs_write_read1(0x168,0x00,&rx_data);
+SpiPs_write_read1(0x169,0x00,&rx_data);
+SpiPs_write_read1(0xA2D,0x02,&rx_data);
+SpiPs_write_read1(0xA07,0x00,&rx_data);
+SpiPs_write_read1(0xA08,0x0F,&rx_data);
+SpiPs_write_read1(0xA1C,0x01,&rx_data);
+SpiPs_write_read1(0xA16,0x10,&rx_data);
+SpiPs_write_read1(0xA17,0x00,&rx_data);
+SpiPs_write_read1(0xA18,0x00,&rx_data);
+SpiPs_write_read1(0xA19,0x00,&rx_data);
+SpiPs_write_read1(0xA1A,0x00,&rx_data);
+SpiPs_write_read1(0xA1B,0x00,&rx_data);
+SpiPs_write_read1(0x81A,0xF7,&rx_data);
+SpiPs_write_read1(0x81B,0x44,&rx_data);
+SpiPs_write_read1(0x81C,0x33,&rx_data);
+SpiPs_write_read1(0x81D,0x14,&rx_data);
+SpiPs_write_read1(0x800,0x80,&rx_data);
+SpiPs_write_read1(0x800,0x82,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x77E,0x00,&rx_data);
+//恢复校准中被改变的配置
+SpiPs_write_read1(0x000,0x02,&rx_data);
+SpiPs_write_read1(0x02E,0x03,&rx_data);
+SpiPs_write_read1(0x109,0x11,&rx_data);
+SpiPs_write_read1(0x10A,0x70,&rx_data);
+SpiPs_write_read1(0x11B,0x00,&rx_data);
+SpiPs_write_read1(0x11E,0x00,&rx_data);
+SpiPs_write_read1(0x11F,0x33,&rx_data);
+SpiPs_write_read1(0x128,0x10,&rx_data);
+SpiPs_write_read1(0x161,0x00,&rx_data);
+SpiPs_write_read1(0x162,0x00,&rx_data);
+SpiPs_write_read1(0x164,0x00,&rx_data);
+SpiPs_write_read1(0x165,0x00,&rx_data);
+SpiPs_write_read1(0x166,0x00,&rx_data);
+SpiPs_write_read1(0x167,0x00,&rx_data);
+SpiPs_write_read1(0x168,0x00,&rx_data);
+SpiPs_write_read1(0x169,0x00,&rx_data);
+SpiPs_write_read1(0x6C3,0x00,&rx_data);
+SpiPs_write_read1(0x775,0x24,&rx_data);
+SpiPs_write_read1(0x77D,0xCF,&rx_data);
+SpiPs_write_read1(0xA07,0x00,&rx_data);
+SpiPs_write_read1(0xA08,0x00,&rx_data);
+SpiPs_write_read1(0xA16,0x00,&rx_data);
+SpiPs_write_read1(0xA17,0x00,&rx_data);
+SpiPs_write_read1(0xA18,0x00,&rx_data);
+SpiPs_write_read1(0xA19,0x00,&rx_data);
+SpiPs_write_read1(0xA1A,0x00,&rx_data);
+SpiPs_write_read1(0xA1B,0x00,&rx_data);
+//Pll1锁定
+SpiPs_write_read1(0x61D,0x27,&rx_data);
+SpiPs_write_read1(0x617,0x00,&rx_data);
+SpiPs_write_read1(0x617,0x03,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x61D,0x37,&rx_data);
+//Pll1锁定 成功
+//Pll2锁定
+SpiPs_write_read1(0x63F,0x25,&rx_data);
+SpiPs_write_read1(0x639,0x00,&rx_data);
+SpiPs_write_read1(0x639,0x03,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x63F,0x35,&rx_data);
+//Pll2锁定 成功
+//Pll3锁定
+SpiPs_write_read1(0x661,0x26,&rx_data);
+SpiPs_write_read1(0x65B,0x00,&rx_data);
+SpiPs_write_read1(0x65B,0x03,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x661,0x36,&rx_data);
+//Pll3锁定 成功
+//Pll4锁定
+SpiPs_write_read1(0x683,0x26,&rx_data);
+SpiPs_write_read1(0x67D,0x00,&rx_data);
+SpiPs_write_read1(0x67D,0x03,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x683,0x36,&rx_data);
+//Pll4锁定 成功
+//Pll5锁定
+SpiPs_write_read1(0x6A5,0x26,&rx_data);
+SpiPs_write_read1(0x69F,0x00,&rx_data);
+SpiPs_write_read1(0x69F,0x03,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x6A5,0x36,&rx_data);
+//Pll5锁定 成功
+//配置接口
+SpiPs_write_read1(0x02E,0x05,&rx_data);
+SpiPs_write_read1(0x003,0x33,&rx_data);
+SpiPs_write_read1(0x200,0x01,&rx_data);
+SpiPs_write_read1(0x201,0x3F,&rx_data);
+SpiPs_write_read1(0x202,0x03,&rx_data);
+SpiPs_write_read1(0x206,0x00,&rx_data);
+SpiPs_write_read1(0x208,0x00,&rx_data);
+SpiPs_write_read1(0x209,0x00,&rx_data);
+SpiPs_write_read1(0x77F,0x00,&rx_data);
+SpiPs_write_read1(0x780,0x33,&rx_data);
+SpiPs_write_read1(0x781,0x6F,&rx_data);
+//配置结束
+
+SpiPs_write_read1(0x02E,0x04,&rx_data);
+SpiPs_write_read1(0x780,0x00,&rx_data);
+
+SpiPs_write_read1(0x11F,0x00,&rx_data);
+SpiPs_write_read1(0x11F,0x33,&rx_data);
+////配置Tx NCO BIST ON
+//SpiPs_write_read1(0x11B,0x01,&rx_data);
+//SpiPs_write_read1(0x11E,0x01,&rx_data);
+//SpiPs_write_read1(0x161,0x01,&rx_data);
+//SpiPs_write_read1(0x162,0x01,&rx_data);
+////配置Tx NCO频率 1MHz
+//SpiPs_write_read1(0x164,0x05,&rx_data);
+//SpiPs_write_read1(0x165,0x55,&rx_data);
+//SpiPs_write_read1(0x166,0x55,&rx_data);
+//SpiPs_write_read1(0x167,0x55,&rx_data);
+//SpiPs_write_read1(0x168,0x55,&rx_data);
+//SpiPs_write_read1(0x169,0x55,&rx_data);
+}

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_DEMO/download_bin.c

@@ -0,0 +1,45 @@
+/*
+ * download_bin.c
+ *
+ *  Created on: 2023Äê11ÔÂ23ÈÕ
+ *      Author: cxlab
+ */
+
+#include "xilinx_io.h"
+#include "sleep.h"
+void download_bin(void){
+
+//	int temp;
+	u8 rx_data;
+	u8 data[4];
+	u32 buf;
+	u8 addr[2];
+	int on = 1;
+	if (on) {
+		SpiPs_write_read1(0x071,0x26,&rx_data);
+		SpiPs_write_read1(0x236,0x0F,&rx_data);
+		SpiPs_write_read1(0x20A,0x01,&rx_data);
+		for(int i=0;i<15448;i++){
+			addr[0]=(i>>8)&0xff;
+			addr[1]= i&0xff;
+			buf=rom_read((u8 *)&addr);
+			data[0]=buf>>24;
+			data[1]=(buf>>16)&0xff;
+			data[2]=(buf>>8)&0xff;
+			data[3]=buf&0xff;
+			for(int j=0;j<4;j++){
+				SpiPs_write_read1(0x070,data[j],&rx_data);
+//				SpiPs_write_read2(0x070,0x00,&rx_data);
+//				temp=rx_data;
+			}
+			if(i==15447){
+				xil_printf("bin download completely");
+			}
+
+		}
+	}
+	else {
+	SpiPs_write_read1(0x071,0x00,&rx_data);
+	}
+
+}

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_DEMO/echo.c

@@ -0,0 +1,461 @@
+/*
+ * Copyright (C) 2016 - 2018 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ */
+
+#include <stdio.h>
+#include <string.h>
+
+#include "lwip/sockets.h"
+#include "netif/xadapter.h"
+#include "lwipopts.h"
+#include "xil_printf.h"
+#include "FreeRTOS.h"
+#include "task.h"
+#include "xilinx_io.h"
+
+#define THREAD_STACKSIZE 1024
+#define ACK 0x01
+u16_t echo_port = 7;
+//#define RECV_BUF_SIZE 65536*16*8
+#define RECV_BUF_SIZE 1024
+//char recv_buf[RECV_BUF_SIZE];
+char recv_buf[1024];
+char recv_buf_temp[3];
+char trans_buf[8192*5];
+struct spi_stack spistack;
+
+
+u16 hop_cnt = 0;
+
+void print_echo_app_header()
+{
+    xil_printf("%20s %6d %s\r\n", "echo server",
+                        echo_port,
+                        "$ telnet <board_ip> 7");
+
+}
+
+
+enum {
+	CMD_VER = 0,
+	CMD_RST = 1,
+	CMD_SPI_WRI = 2 ,
+	CMD_SPI_READ = 3,
+	CMD_DATA_CAPTURE0 = 4,
+	CMD_WAVE_DOWNLOAD = 5,
+	CMD_PIN_SET =  6,
+	CMD_DATA_CAPTURE1 = 8,
+	CMD_DATA_CAPTURE2 = 9,
+	CMD_STACK_OUT = 10,
+	CMD_hopping = 11,
+	CMD_qecbin = 12,
+	CMD_cx9261a_config = 13,
+	CMD_cx3e04_config = 14,
+	CMD_cx3e04_SPI_WRI = 15 ,
+	CMD_cx3e04_SPI_READ = 16,
+    CMD_IMAGE_UPDATE = 22,
+};
+/* thread spawned for each connection */
+void process_echo_request(void *p)
+{
+	int sd = (int)p;
+	int status;
+	int n, nwrote,send_n,total_send;
+	u8 rx_data;
+	u32 capture_length;
+	u8 pin;
+	u8 pin_value;
+	char FPGA_SDK_IP[]="FPGA:20240315-SDK:20231122";
+	spistack.spi_write_num = 0;
+	while (1) {
+		/* read a max of RECV_BUF_SIZE bytes from socket */
+		if ((n = read(sd, recv_buf, 5)) < 0) {
+			xil_printf("%s: error reading from socket %d, closing socket\r\n", __FUNCTION__, sd);
+			break;
+		}
+
+		/* break if the recved message = "quit" */
+		if (!strncmp(recv_buf, "quit", 4))
+			break;
+
+		/* break if client closed connection */
+		if (n <= 0)
+			break;
+
+		else{/* excute cmd if recved message = "cmd"*/
+			n=0;
+			if (!strncmp(recv_buf, "cmd ", 4)){
+//				xil_printf("%d %d %d %d.\r\n", recv_buf[0],recv_buf[1],recv_buf[2],recv_buf[4]);
+				dbg_printf("Rece %d bytes.\r\n",n);
+				switch(recv_buf[4]){
+				case CMD_IMAGE_UPDATE:
+				                {
+
+				                    u32 offset;
+				                    u32 image_size;
+				                    recv_buf[0] = ACK;
+				                    nwrote = write(sd, recv_buf, 1);
+				                    n = read(sd, recv_buf, RECV_BUF_SIZE);
+
+				                    offset = *(u32 *)recv_buf;
+				                    image_size = *(u32 *)(recv_buf + 4);
+				                    xil_printf("offset is 0x%x image_size is 0x%x.\n", offset, image_size);
+
+				                    void *image_ptr = (void *)0x30000000;
+				                    u32 LengthBytes;
+				                    write(sd, recv_buf, 1); // ask for image data
+				                    //// receive flash image to ddr
+				                    LengthBytes = 0;
+				                    while (LengthBytes < image_size)
+				                    {
+				                        n = read(sd, image_ptr + LengthBytes, RECV_BUF_SIZE);
+				                        //				xil_printf("read %d bytes.\n",n);
+				                        LengthBytes = LengthBytes + n;
+				                    }
+
+				                    // image data sumcheck
+
+				                    // program image data into flash
+				                    //QspiStore( (u32) image_ptr, offset, image_size);
+				                    //xil_printf("flash program done.\n", n);
+				                    status = FfsSdWrite(image_ptr, image_size);
+				                    write(sd, recv_buf, 1); // send done
+				                    xil_printf("sd program done.\n", n);
+				                    n = 0;
+				                    break;
+				                }
+
+				case CMD_VER:
+					dbg_printf("Version:FPGA_20240315;SDK_20231122;IP_192.168.1.99.\r\n");
+					n=26;
+					for(int i=0;i<26;i++){
+					recv_buf[i] = FPGA_SDK_IP[i];
+					}
+					break;
+				case CMD_RST:
+					dbg_printf("Rece cmd excute rst.\r\n");
+					GpioSetPinDir(NRST,GPIO_DIR_OUTPUT);
+					DeviceRst();
+					break;
+
+				case CMD_STACK_OUT:
+					dbg_printf("Rece cmd STACK OUT.\r\n");
+					spi_stack_out(&spistack);
+					n=1;
+					recv_buf[0] = 0x55;
+					break;
+				case CMD_SPI_WRI:
+					read(sd, &recv_buf[5], 3);
+					dbg_printf("Rece cmd excute spi write.\r\n");
+					dbg_printf("ADDR 0x%x DATA 0x%x.\r\n",recv_buf[5]*256+recv_buf[6]-32768,recv_buf[7]);
+//					SpiPs_write_read((u8 *)&recv_buf[5],&rx_data);
+					status = spi_stack_in((u8 *)&recv_buf[5],&spistack);
+					if(status){//when memory is near full,start spi write
+						spi_stack_out(&spistack);
+					}
+//					n=1;
+//					recv_buf[0] = rx_data;
+					break;
+				case CMD_SPI_READ:
+					read(sd, &recv_buf[5], 3);
+					dbg_printf("Rece cmd excute spi read.\r\n");
+					dbg_printf("ADDR 0x%x DATA 0x%x.\r\n",recv_buf[5]*256+recv_buf[6],recv_buf[7]);
+					SpiPs_write_read((u8 *)&recv_buf[5],&rx_data);
+					n=1;
+					recv_buf[0] = rx_data;
+					break;
+				case CMD_DATA_CAPTURE0:
+					read(sd, &recv_buf[5], 4);
+					capture_length = *((u32 *) &recv_buf[5]);//num of sample
+					dbg_printf("Rece cmd excute %d sample data capture.\r\n",capture_length);
+					XAxiDmaCapture(xAxiDma0Get(),capture_length);
+					n = capture_length*8;
+					total_send = 0;
+					/* handle request */
+					while(n>0){
+						if(n>1024)
+						    send_n = 1024;
+						else
+						    send_n = n;
+						n= n-send_n;
+						memcpy(recv_buf,TX_BUFFER_BASE + total_send,send_n);
+						total_send = total_send + send_n;
+						if ((nwrote = write(sd, &recv_buf, send_n)) < 0) {
+							xil_printf("%s: ERROR responding to client echo request. received = %d, written = %d\r\n",__FUNCTION__, n, nwrote);
+							xil_printf("Closing socket %d\r\n", sd);
+							break;
+						}
+						else{
+							if(send_n!=nwrote){
+							    xil_printf("%d Bytes Send %d.\r\n", send_n,nwrote);
+							}
+						}
+					}
+					dbg_printf("Send %d bytes.\r\n",n);
+					break;
+				case CMD_DATA_CAPTURE1:
+					read(sd, &recv_buf[5], 4);
+					capture_length = *((u32 *) &recv_buf[5]);//num of sample
+					dbg_printf("Rece cmd excute %d sample data capture.\r\n",capture_length);
+					XAxiDmaCapture(xAxiDma1Get(),capture_length);
+					n = capture_length*8;
+					total_send = 0;
+					/* handle request */
+					while(n>0){
+						if(n>1024)
+						    send_n = 1024;
+						else
+						    send_n = n;
+						n= n-send_n;
+
+						memcpy(recv_buf,TX_BUFFER_BASE + total_send,send_n);
+						total_send = total_send + send_n;
+						if ((nwrote = write(sd, &recv_buf, send_n)) < 0) {
+							xil_printf("%s: ERROR responding to client echo request. received = %d, written = %d\r\n",__FUNCTION__, n, nwrote);
+							xil_printf("Closing socket %d\r\n", sd);
+							break;
+						}
+						else{
+							if(send_n!=nwrote){
+							    xil_printf("%d Bytes Send %d.\r\n", send_n,nwrote);
+							}
+						}
+					}
+					dbg_printf("Send %d bytes.\r\n",n);
+					break;
+				case CMD_DATA_CAPTURE2:
+					read(sd, &recv_buf[5], 4);
+					capture_length = *((u32 *) &recv_buf[5]);//num of sample
+					dbg_printf("Rece cmd excute %d sample data capture.\r\n",capture_length);
+					XAxiDmaCapture(xAxiDma2Get(),capture_length);
+					n = capture_length*8;
+					total_send = 0;
+					/* handle request */
+					while(n>0){
+						if(n>1024)
+						    send_n = 1024;
+						else
+						    send_n = n;
+						n= n-send_n;
+						memcpy(recv_buf,TX_BUFFER_BASE + total_send,send_n);
+						total_send = total_send + send_n;
+						if ((nwrote = write(sd, &recv_buf, send_n)) < 0) {
+							xil_printf("%s: ERROR responding to client echo request. received = %d, written = %d\r\n",__FUNCTION__, n, nwrote);
+							xil_printf("Closing socket %d\r\n", sd);
+							break;
+						}
+						else{
+							if(send_n!=nwrote){
+							    xil_printf("%d Bytes Send %d.\r\n", send_n,nwrote);
+							}
+						}
+					}
+					dbg_printf("Send %d bytes.\r\n",n);
+					break;
+				case CMD_WAVE_DOWNLOAD:
+					dbg_printf("Rece cmd excute wave download.\r\n");
+					while(n<WAVE_LENGTH){
+						dbg_printf("Rece data num in recv_buf is %d.\r\n",n);
+						n =n + read(sd, &trans_buf[n], 512);//
+					}
+					dbg_printf("Rece data num in recv_buf is %d.\r\n",n);
+					DownloadWave((u8 *)&trans_buf[0]);
+					n=0;
+					break;
+				case CMD_PIN_SET:
+					read(sd, &recv_buf[5], 2);
+					pin = (u8) recv_buf[5];
+					pin_value = (u8) recv_buf[6];
+					dbg_printf("Rece cmd excute pin %d set %d.\r\n",pin,pin_value);
+					GpioSetPinDir(pin,GPIO_DIR_OUTPUT);
+					GpioWritePin(pin,pin_value&0x01);//dma_axis_rx_rstn
+//					recv_buf_temp[0]= 0x80;
+//					recv_buf_temp[1]= 0x43;
+//					recv_buf_temp[2]= 0xe7;
+//					if((pin==0x20)&&(pin_value==0x01)){
+//						SpiPs_write_read((u8 *)&recv_buf_temp,&rx_data);
+//					}
+					break;
+
+				case CMD_hopping:
+					    read(sd, &recv_buf[5], 4);
+						int hop_flag=recv_buf[5]&0x01;
+						frqhop_flag(hop_flag);
+						if(hop_flag==1){
+							xil_printf("hopping freqence start.\r\n");
+						}else{
+							xil_printf("hopping freqence end.\r\n");
+						}
+					break;
+				case CMD_qecbin:
+						download_bin();
+					break;
+				case CMD_cx9261a_config:
+				    	read(sd, &recv_buf[5], 1);
+				    	int lo = 5000;
+				    	int f0 = 4;
+				    	int fs = 80;
+				    	int ref= 100;
+				    	int dcCalibEnable = 1;
+				    	int dcCalibLength = 7;
+				    	if(recv_buf[5] == 0){
+							cx9261a_151_config();
+				    	}else if(recv_buf[5] == 1){
+							cx9261a_076_config();
+							configDcCalib(dcCalibEnable,dcCalibLength);
+							rxFFTCalib(lo,fs,ref,8,1);
+							rxFFTCalib(lo,fs,ref,8,2);
+							rxFFTCalib(lo,fs,ref,8,3);
+							txBisectionQecCalib(f0, fs);
+							txBisectionDcCalib(f0, fs);
+				    	}
+					break;
+
+				case CMD_cx3e04_config:
+					cx3e04_config();
+					break;
+
+				case CMD_cx3e04_SPI_WRI:
+					read(sd, &recv_buf[5], 3);
+					dbg_printf("Rece cmd excute cx3e04_spi write.\r\n");
+					dbg_printf("ADDR 0x%x DATA 0x%x.\r\n",recv_buf[5]*256+recv_buf[6]-32768,recv_buf[7]);
+					int addr = recv_buf[5]*256+recv_buf[6];
+				    int value= recv_buf[7];
+					cx3e04_write(addr,value);
+					break;
+				case CMD_cx3e04_SPI_READ:
+					read(sd, &recv_buf[5], 2);
+					dbg_printf("Rece cmd excute cx3e04_spi read.\r\n");
+					dbg_printf("ADDR 0x%x.\r\n",recv_buf[5]*256+recv_buf[6]);
+					addr = recv_buf[5]*256+recv_buf[6];
+					n=1;
+					recv_buf[0] = cx3e04_read(addr);
+					break;
+				default :
+					xil_printf("cmd error 0x%x",recv_buf[4]);
+					break;
+				}
+
+			/*if(recv_buf[4] == 7){
+					read(sd, &recv_buf[5], 4);
+					capture_length = *((u32 *) &recv_buf[5]);//num of sample
+					dbg_printf("Rece cmd excute %d sample data capture.\r\n",capture_length);
+					XAxiDmaCapture2(capture_length);
+//					memcpy(recv_buf,TX_BUFFER_BASE,capture_length*8);
+					n = capture_length*8;
+					total_send = 0;
+					// handle request
+					while(n>0){
+						if(n>1024)
+							send_n = 1024;
+						else
+							send_n = n;
+					n= n-send_n;
+					total_send = total_send + send_n;
+					memcpy(recv_buf,TX_BUFFER_BASE + total_send,send_n);
+					if ((nwrote = write(sd, &recv_buf, send_n)) < 0) {
+						xil_printf("%s: ERROR responding to client echo request. received = %d, written = %d\r\n",
+								__FUNCTION__, n, nwrote);
+						xil_printf("Closing socket %d\r\n", sd);
+						break;
+					}
+					else{
+						if(send_n!=nwrote){
+						xil_printf("%d Bytes Send %d.\r\n", send_n,nwrote);
+						}
+					}
+					}
+					dbg_printf("Send %d bytes.\r\n",n);
+			}*/
+
+		}
+		}
+		/* handle request */
+		if ((nwrote = write(sd, recv_buf, n)) < 0) {
+			xil_printf("%s: ERROR responding to client echo request. received = %d, written = %d\r\n",
+					__FUNCTION__, n, nwrote);
+			xil_printf("Closing socket %d\r\n", sd);
+			break;
+		}
+		else{
+			if(n!=nwrote){
+			xil_printf("%d Bytes Send %d.\r\n", n,nwrote);
+			}
+		}
+	}
+
+	/* close connection */
+	close(sd);
+	vTaskDelete(NULL);
+}
+
+void echo_application_thread()
+{
+	int sock, new_sd;
+	int size;
+#if LWIP_IPV6==0
+	struct sockaddr_in address, remote;
+
+	memset(&address, 0, sizeof(address));
+
+	if ((sock = lwip_socket(AF_INET, SOCK_STREAM, 0)) < 0)
+		return;
+
+	address.sin_family = AF_INET;
+	address.sin_port = htons(echo_port);
+	address.sin_addr.s_addr = INADDR_ANY;
+#else
+	struct sockaddr_in6 address, remote;
+
+	memset(&address, 0, sizeof(address));
+
+	address.sin6_len = sizeof(address);
+	address.sin6_family = AF_INET6;
+	address.sin6_port = htons(echo_port);
+
+	memset(&(address.sin6_addr), 0, sizeof(address.sin6_addr));
+
+	if ((sock = lwip_socket(AF_INET6, SOCK_STREAM, 0)) < 0)
+		return;
+#endif
+
+	if (lwip_bind(sock, (struct sockaddr *)&address, sizeof (address)) < 0)
+		return;
+
+	lwip_listen(sock, 0);
+
+	size = sizeof(remote);
+
+	while (1) {
+		if ((new_sd = lwip_accept(sock, (struct sockaddr *)&remote, (socklen_t *)&size)) > 0) {
+			sys_thread_new("echos", process_echo_request,
+				(void*)new_sd,
+				THREAD_STACKSIZE,
+				DEFAULT_THREAD_PRIO);
+		}
+	}
+}

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_DEMO/frqhop_config.c

@@ -0,0 +1,58 @@
+/*
+ * frqhop_config.c
+ *
+ *  Created on: 2023年11月24日
+ *      Author: cxlab
+ */
+
+#include "xilinx_io.h"
+#include "sleep.h"
+#include "time.h"
+#include "xtime_l.h"
+#include "math.h"
+#include <stdlib.h>
+
+void frqhop_config(int hop_flag){
+	XTime tCur;
+    XTime_GetTime(&tCur);
+    srand(tCur);
+	double hop_freq = (rand()%(800-30))+30+(rand()%(101))/(double)100;//随机产生[30,800)double类型的数
+//    double hop_freq = 400.52;
+	double hop_freq1 = 800.25;
+	static int pll_index=1;
+	static int unlock_pll1_cnt=0,unlock_pll2_cnt=0;
+	if(hop_freq == hop_freq1){
+		if(pll_index == 2){
+			pll_index = 4;
+		}
+		else if(pll_index == 1){
+			pll_index = 3;
+		}
+	}
+	if(hop_flag == 1){
+		if(pll_index == 1 || pll_index == 3){
+				//切换至pll2来源
+				GpioSetPinDir(hop,GPIO_DIR_OUTPUT);
+				GpioWritePin(hop,0x01);
+				trx_ch_pll_config(2);
+				GpioWritePin(hop,0x00);
+				//配置pll1参数
+				unlock_pll1_cnt=PLL_config(1,hop_freq)-1;
+				pll_index = 2;
+		}
+		else if(pll_index == 2 || pll_index == 4){
+				//切换至pll1来源
+				GpioSetPinDir(hop,GPIO_DIR_OUTPUT);
+				GpioWritePin(hop,0x01);
+				trx_ch_pll_config(1);
+				GpioWritePin(hop,0x00);
+				//配置pll2参数
+				unlock_pll2_cnt=PLL_config(2,hop_freq)-1;
+				pll_index = 1;
+		}
+	}
+	hop_freq1 = hop_freq;
+	if(unlock_pll2_cnt!=0 || unlock_pll1_cnt !=0){
+		xil_printf("pll1 unlock num: %d; pll2 unlock num: %d;.\n", unlock_pll1_cnt, unlock_pll2_cnt);
+	}
+}

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_DEMO/iic_phyreset.c

@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2016 - 2018 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ */
+
+#include <stdio.h>
+
+#include "xparameters.h"
+#if defined (__arm__) || defined(__aarch64__)
+#include "xil_printf.h"
+#endif
+
+#ifdef XPS_BOARD_ZCU102
+#ifdef XPAR_XIICPS_0_DEVICE_ID
+#include "xiicps.h"
+
+#define BUF_LEN		10U
+
+#define IOEXPANDER1_ADDR		0x20U
+
+#define IIC_SCLK_RATE_IOEXP		400000
+
+#define CMD_CFG_0_REG		0x06U
+#define CMD_OUTPUT_0_REG	0x02U
+#define DATA_OUTPUT			0x0U
+
+#define DATA_COMMON_CFG		0xE0U
+#define DATA_GT_0000_CFG	0x00U
+
+XIicPs I2c0InstancePtr;
+
+int IicPhyReset(void)
+{
+
+	u8 WriteBuffer[BUF_LEN] = {0};
+	XIicPs_Config *I2c0CfgPtr;
+	int Status = XST_SUCCESS;
+
+	/* Initialize the IIC0 driver so that it is ready to use */
+	I2c0CfgPtr = XIicPs_LookupConfig(XPAR_XIICPS_0_DEVICE_ID);
+	if (I2c0CfgPtr == NULL) {
+		Status = XST_FAILURE;
+		return Status;
+	}
+
+	Status = XIicPs_CfgInitialize(&I2c0InstancePtr, I2c0CfgPtr,
+			I2c0CfgPtr->BaseAddress);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		return Status;
+	}
+
+	/* Set the IIC serial clock rate */
+	XIicPs_SetSClk(&I2c0InstancePtr, IIC_SCLK_RATE_IOEXP);
+
+	/* Configure I/O pins as Output */
+	WriteBuffer[0] = CMD_CFG_0_REG;
+	WriteBuffer[1] = DATA_OUTPUT;
+	Status = XIicPs_MasterSendPolled(&I2c0InstancePtr,
+			WriteBuffer, 2, IOEXPANDER1_ADDR);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		return Status;
+	}
+
+	/* Wait until bus is idle to start another transfer */
+	while (XIicPs_BusIsBusy(&I2c0InstancePtr));
+
+	/*
+	 * Deasserting I2C_MUX_RESETB
+	 * And GEM3 Resetb
+	 * Selecting lanes based on configuration
+	 */
+	WriteBuffer[0] = CMD_OUTPUT_0_REG;
+	/* gt0000 or no GT configuration */
+	WriteBuffer[1] = DATA_COMMON_CFG | DATA_GT_0000_CFG;
+
+	/* Send the Data */
+	Status = XIicPs_MasterSendPolled(&I2c0InstancePtr,
+			WriteBuffer, 2, IOEXPANDER1_ADDR);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		return Status;
+	}
+
+	/* Wait until bus is idle */
+	while (XIicPs_BusIsBusy(&I2c0InstancePtr));
+
+	xil_printf("IIC PHY reset on ZCU102 successful \n\r");
+}
+#endif
+#endif

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_DEMO/main.c

@@ -0,0 +1,300 @@
+/*
+ * Copyright (C) 2016 - 2018 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ */
+
+#include <stdio.h>
+#include "xparameters.h"
+#include "netif/xadapter.h"
+#include "platform_config.h"
+#include "xil_printf.h"
+#include "xilinx_io.h"
+#include "FreeRTOS.h"
+#include "queue.h"
+#include "semphr.h"
+#include "math.h"
+
+#if LWIP_IPV6==1
+#include "lwip/ip.h"
+#else
+#if LWIP_DHCP==1
+#include "lwip/dhcp.h"
+#endif
+#endif
+
+#ifdef XPS_BOARD_ZCU102
+#ifdef XPAR_XIICPS_0_DEVICE_ID
+int IicPhyReset(void);
+#endif
+#endif
+
+int main_thread();
+void print_echo_app_header();
+void echo_application_thread(void *);
+
+void lwip_init();
+
+#if LWIP_IPV6==0
+#if LWIP_DHCP==1
+extern volatile int dhcp_timoutcntr;
+err_t dhcp_start(struct netif *netif);
+#endif
+#endif
+
+#define THREAD_STACKSIZE 1024
+
+static struct netif server_netif;
+struct netif *echo_netif;
+
+#if LWIP_IPV6==1
+void print_ip6(char *msg, ip_addr_t *ip)
+{
+	print(msg);
+	xil_printf(" %x:%x:%x:%x:%x:%x:%x:%x\n\r",
+			IP6_ADDR_BLOCK1(&ip->u_addr.ip6),
+			IP6_ADDR_BLOCK2(&ip->u_addr.ip6),
+			IP6_ADDR_BLOCK3(&ip->u_addr.ip6),
+			IP6_ADDR_BLOCK4(&ip->u_addr.ip6),
+			IP6_ADDR_BLOCK5(&ip->u_addr.ip6),
+			IP6_ADDR_BLOCK6(&ip->u_addr.ip6),
+			IP6_ADDR_BLOCK7(&ip->u_addr.ip6),
+			IP6_ADDR_BLOCK8(&ip->u_addr.ip6));
+}
+
+#else
+void
+print_ip(char *msg, ip_addr_t *ip)
+{
+	xil_printf(msg);
+	xil_printf("%d.%d.%d.%d\n\r", ip4_addr1(ip), ip4_addr2(ip),
+			ip4_addr3(ip), ip4_addr4(ip));
+}
+
+void
+print_ip_settings(ip_addr_t *ip, ip_addr_t *mask, ip_addr_t *gw)
+{
+
+	print_ip("Board IP: ", ip);
+	print_ip("Netmask : ", mask);
+	print_ip("Gateway : ", gw);
+}
+
+#endif
+
+int main()
+{
+	xil_printf("start");
+
+	sys_thread_new("main_thrd", (void(*)(void*))main_thread, 0,
+	                THREAD_STACKSIZE,
+	                DEFAULT_THREAD_PRIO);
+	vTaskStartScheduler();
+
+	while(1);
+
+	return 0;
+}
+
+void network_thread(void *p)
+{
+    struct netif *netif;
+    /* the mac address of the board. this should be unique per board */
+    unsigned char mac_ethernet_address[] = { 0x00, 0x0a, 0x35, 0x00, 0x01, 0x02 };
+#if LWIP_IPV6==0
+    ip_addr_t ipaddr, netmask, gw;
+#if LWIP_DHCP==1
+    int mscnt = 0;
+#endif
+#endif
+
+    netif = &server_netif;
+
+    xil_printf("\r\n\r\n");
+    xil_printf("-----lwIP Socket Mode CX9261  TEST server Application Version 2022.05.31------\r\n");
+
+#if LWIP_IPV6==0
+#if LWIP_DHCP==0
+    /* initliaze IP addresses to be used */
+    IP4_ADDR(&ipaddr,  192, 168, 1, 99);
+    IP4_ADDR(&netmask, 255, 255, 255,  0);
+    IP4_ADDR(&gw,      192, 168, 1, 1);
+#endif
+
+    /* print out IP settings of the board */
+
+#if LWIP_DHCP==0
+    print_ip_settings(&ipaddr, &netmask, &gw);
+    /* print all application headers */
+#endif
+
+#if LWIP_DHCP==1
+	ipaddr.addr = 0;
+	gw.addr = 0;
+	netmask.addr = 0;
+#endif
+#endif
+
+#if LWIP_IPV6==0
+    /* Add network interface to the netif_list, and set it as default */
+    if (!xemac_add(netif, &ipaddr, &netmask, &gw, mac_ethernet_address, PLATFORM_EMAC_BASEADDR)) {
+	xil_printf("Error adding N/W interface\r\n");
+	return;
+    }
+#else
+    /* Add network interface to the netif_list, and set it as default */
+    if (!xemac_add(netif, NULL, NULL, NULL, mac_ethernet_address, PLATFORM_EMAC_BASEADDR)) {
+	xil_printf("Error adding N/W interface\r\n");
+	return;
+    }
+
+    netif->ip6_autoconfig_enabled = 1;
+
+    netif_create_ip6_linklocal_address(netif, 1);
+    netif_ip6_addr_set_state(netif, 0, IP6_ADDR_VALID);
+
+    print_ip6("\n\rBoard IPv6 address ", &netif->ip6_addr[0].u_addr.ip6);
+#endif
+
+    netif_set_default(netif);
+
+    /* specify that the network if is up */
+    netif_set_up(netif);
+
+    /* start packet receive thread - required for lwIP operation */
+    sys_thread_new("xemacif_input_thread", (void(*)(void*))xemacif_input_thread, netif,
+            THREAD_STACKSIZE,
+            DEFAULT_THREAD_PRIO);
+
+#if LWIP_IPV6==0
+#if LWIP_DHCP==1
+    dhcp_start(netif);
+    while (1) {
+		vTaskDelay(DHCP_FINE_TIMER_MSECS / portTICK_RATE_MS);
+		dhcp_fine_tmr();
+		mscnt += DHCP_FINE_TIMER_MSECS;
+		if (mscnt >= DHCP_COARSE_TIMER_SECS*1000) {
+			dhcp_coarse_tmr();
+			mscnt = 0;
+		}
+	}
+#else
+    xil_printf("\r\n");
+    xil_printf("%20s %6s %s\r\n", "Server", "Port", "Connect With..");
+    xil_printf("%20s %6s %s\r\n", "--------------------", "------", "--------------------");
+
+    print_echo_app_header();
+    xil_printf("\r\n");
+    sys_thread_new("echod", echo_application_thread, 0,
+		THREAD_STACKSIZE,
+		DEFAULT_THREAD_PRIO);
+    vTaskDelete(NULL);
+#endif
+#else
+    print_echo_app_header();
+    xil_printf("\r\n");
+    sys_thread_new("echod",echo_application_thread, 0,
+		THREAD_STACKSIZE,
+		DEFAULT_THREAD_PRIO);
+    vTaskDelete(NULL);
+#endif
+    return;
+}
+
+int main_thread()
+{
+#if LWIP_DHCP==1
+	int mscnt = 0;
+#endif
+
+#ifdef XPS_BOARD_ZCU102
+	IicPhyReset();
+#endif
+
+	/* initialize lwIP before calling sys_thread_new */
+    lwip_init();
+    SpiPsInit(SPI_DEVICE_ID);
+    GpioInit(GPIO_DEVICE_ID);
+    AXIGpioInit();
+    XScuGicInit();
+    ConfigAXIGPIOIntr();
+    ExceptionInit();
+
+    XAxiDma_Init(xAxiDma0Get(),AXI_DMA_DEVCIE_ID0);
+    XAxiDma_Init(xAxiDma1Get(),AXI_DMA_DEVCIE_ID1);
+    XAxiDma_Init(xAxiDma2Get(),AXI_DMA_DEVCIE_ID2);
+    PackerRst();
+
+	/* cx9261a configuration */
+    peripheral_test();
+    cx3e04_config();
+//    cx9261a_710_config();
+//    frqhop_config(1);
+	int temp = cx3e04_read(0x03A);
+    /* any thread using lwIP should be created using sys_thread_new */
+    sys_thread_new("NW_THRD", network_thread, NULL,
+		THREAD_STACKSIZE,
+            DEFAULT_THREAD_PRIO);
+
+#if LWIP_IPV6==0
+#if LWIP_DHCP==1
+    while (1) {
+	vTaskDelay(DHCP_FINE_TIMER_MSECS / portTICK_RATE_MS);
+		if (server_netif.ip_addr.addr) {
+			xil_printf("DHCP request success\r\n");
+			print_ip_settings(&(server_netif.ip_addr), &(server_netif.netmask), &(server_netif.gw));
+			print_echo_app_header();
+			xil_printf("\r\n");
+			sys_thread_new("echod", echo_application_thread, 0,
+					THREAD_STACKSIZE,
+					DEFAULT_THREAD_PRIO);
+			break;
+		}
+		mscnt += DHCP_FINE_TIMER_MSECS;
+		if (mscnt >= 10000) {
+			xil_printf("ERROR: DHCP request timed out\r\n");
+			xil_printf("Configuring default IP of 192.168.1.100\r\n");
+			IP4_ADDR(&(server_netif.ip_addr),  192, 168, 1, 100);
+			IP4_ADDR(&(server_netif.netmask), 255, 255, 255,  0);
+			IP4_ADDR(&(server_netif.gw),  192, 168, 1, 1);
+			print_ip_settings(&(server_netif.ip_addr), &(server_netif.netmask), &(server_netif.gw));
+			/* print all application headers */
+			xil_printf("\r\n");
+			xil_printf("%20s %6s %s\r\n", "Server", "Port", "Connect With..");
+			xil_printf("%20s %6s %s\r\n", "--------------------", "------", "--------------------");
+
+			print_echo_app_header();
+			xil_printf("\r\n");
+			sys_thread_new("echod", echo_application_thread, 0,
+					THREAD_STACKSIZE,
+					DEFAULT_THREAD_PRIO);
+			break;
+		}
+	}
+#endif
+#endif
+    vTaskDelete(NULL);
+    return 0;
+}

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_DEMO/platform_config.h

@@ -0,0 +1,10 @@
+#ifndef __PLATFORM_CONFIG_H_
+#define __PLATFORM_CONFIG_H_
+
+
+#define PLATFORM_EMAC_BASEADDR XPAR_XEMACPS_0_BASEADDR
+
+#define PLATFORM_ZYNQ 
+
+
+#endif

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_DEMO/rx_wideband_qec.c

@@ -0,0 +1,61 @@
+/*
+ * wideband_qec.c
+ *
+ *  Created on: 2023Äê11ÔÂ30ÈÕ
+ *      Author: cxlab
+ */
+
+#include "xilinx_io.h"
+#include "sleep.h"
+#include "math.h"
+void rxFFTCalib(int lo, int fs,int ref, int firLength, int chan) {
+	u8 rx_data;
+	SpiPs_write_read1(0x000, chan == 1 ? 0x12 : 0x22,&rx_data);
+	SpiPs_write_read1(0x128, 0x00,&rx_data);
+	SpiPs_write_read1(0x11B, 0x01,&rx_data);
+	SpiPs_write_read1(0x11E, 0x01,&rx_data);
+    configTxNcoFreq(0, fs);
+    SpiPs_write_read1(0x161, 0x00,&rx_data);
+    SpiPs_write_read1(0x162, 0x00,&rx_data);
+    SpiPs_write_read1(0x162, 0x01,&rx_data);
+    SpiPs_write_read1(0x161, 0x01,&rx_data);
+    SpiPs_write_read1(0x000, chan == 1 ? 0x12 : chan == 2 ? 0x22 : 0x32,&rx_data);
+    SpiPs_write_read1(0x102, 0x03,&rx_data);
+    SpiPs_write_read1(0x102, 0xFF,&rx_data);
+    SpiPs_write_read1(0x15C, 0x00,&rx_data);
+    SpiPs_write_read1(0x160, 0x01,&rx_data);
+    SpiPs_write_read1(0x77E, chan == 1 ? 0x50 : chan == 2 ? 0x0A : 0x03,&rx_data);
+    SpiPs_write_read1(0x09B, 0x01,&rx_data);  // TXPLL4
+    SpiPs_write_read1(0x09D, firLength,&rx_data);
+    SpiPs_write_read1(0x096, ((u32)round(lo) >> 8) & 0xFF,&rx_data);
+    SpiPs_write_read1(0x097, (u32)round(lo) & 0xFF,&rx_data);
+    SpiPs_write_read1(0x098, ((u32)round(ref * 10) >> 8) & 0xFF,&rx_data);
+    SpiPs_write_read1(0x099, (u32)round(ref * 10) & 0xFF,&rx_data);
+    SpiPs_write_read1(0x09E, ((u32)round(fs * 100) >> 8) & 0xFF,&rx_data);
+    SpiPs_write_read1(0x09F, (u32)round(fs * 100) & 0xFF,&rx_data);
+    SpiPs_write_read1(0x09C, chan,&rx_data);
+    while (1) {
+        if (SpiPs_write_read2(0x0B3,0x00,&rx_data) == 5)
+            break;
+        usleep(10000);
+    }
+    SpiPs_write_read1(0x09C, 0x00,&rx_data);
+    SpiPs_write_read1(0x15C, 0x01,&rx_data);
+    SpiPs_write_read1(0x77E, 0x00,&rx_data);
+
+    //ͨµÀʱÖÓÀ´Ô´
+    u8 r77D=0xC0;
+    u8 r775=0x24;
+    u8 r6C3=0x00;
+    SpiPs_write_read1(0x77D, r77D,&rx_data);
+    SpiPs_write_read1(0x775, r775,&rx_data);
+    SpiPs_write_read1(0x6C3, r6C3,&rx_data);
+}
+
+
+void configDcCalib(int dcCalibEnable,int dcCalibLength) {
+	u8 rx_data;
+	SpiPs_write_read1(0x109, dcCalibEnable ? 0x11 : 0x00,&rx_data);
+	SpiPs_write_read1(0x10A, (dcCalibLength) << 4,&rx_data);
+	SpiPs_write_read1(0x11F, dcCalibEnable ? 0x33 : 0x73,&rx_data);
+}

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_DEMO/sd.c

@@ -0,0 +1,178 @@
+#include "sd.h"
+/************************** Variable Definitions *****************************/
+static FIL fil;		/* File object */
+static FATFS fatfs;
+/*
+ * To test logical drive 0, FileName should be "0:/<File name>" or
+ * "<file_name>". For logical drive 1, FileName should be "1:/<file_name>"
+ */
+static char FileName[32] = "BOOT.bin";
+static char *SD_File;
+
+
+//#define BUFF_SIZE sizeof(image_data)
+#define BUFF_SIZE 0x2000000
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+u8 DestinationAddress[10*1024];
+#pragma data_alignment = 32
+u8 SourceAddress[10*1024];
+#else
+//u8 DestinationAddress[10*1024] __attribute__ ((aligned(32)));
+//u8 SourceAddress[10*1024] __attribute__ ((aligned(32)));
+
+u8 DestinationAddress[BUFF_SIZE] __attribute__ ((aligned(32)));
+u8 SourceAddress[BUFF_SIZE] __attribute__ ((aligned(32)));
+#endif
+
+#define TEST 7
+
+
+
+/*****************************************************************************/
+/**
+*
+* File system example using SD driver to write to and read from an SD card
+* in polled mode. This example creates a new file on an
+* SD card (which is previously formatted with FATFS), write data to the file
+* and reads the same data back to verify.
+*
+* @param	None
+*
+* @return	XST_SUCCESS if successful, otherwise XST_FAILURE.
+*
+* @note		None
+*
+******************************************************************************/
+int FfsSdWrite(u8*image_data, u32 FileSize)
+{
+	int error_flag = 0;
+	FRESULT Res;
+	UINT NumBytesRead;
+	UINT NumBytesWritten;
+	u32 BuffCnt;
+	BYTE work[FF_MAX_SS];
+//	u32 FileSize = (8*1024);
+//	u32 FileSize = sizeof(image_data);
+	/*
+	 * To test logical drive 0, Path should be "0:/"
+	 * For logical drive 1, Path should be "1:/"
+	 */
+	TCHAR *Path = "0:/";
+	u8 checksum = 0;
+
+	for(BuffCnt = 0; BuffCnt < FileSize; BuffCnt++){
+//		SourceAddress[BuffCnt] = TEST + BuffCnt;
+		SourceAddress[BuffCnt] = image_data[BuffCnt];
+		checksum = checksum + image_data[BuffCnt];
+	}
+	xil_printf("checksum is 0x%x.",checksum);
+
+
+	/*
+	 * Register volume work area, initialize device
+	 */
+	Res = f_mount(&fatfs, Path, 0);
+
+	if (Res != FR_OK) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Path - Path to logical driver, 0 - FDISK format.
+	 * 0 - Cluster size is automatically determined based on Vol size.
+	 */
+	Res = f_mkfs(Path, FM_FAT32, 0, work, sizeof work);
+	if (Res != FR_OK) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Open file with required permissions.
+	 * Here - Creating new file with read/write permissions. .
+	 * To open file with write permissions, file system should not
+	 * be in Read Only mode.
+	 */
+	SD_File = (char *)FileName;
+
+	Res = f_open(&fil, SD_File, FA_CREATE_ALWAYS | FA_WRITE | FA_READ);
+	if (Res) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Pointer to beginning of file .
+	 */
+	Res = f_lseek(&fil, 0);
+	if (Res) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Write data to file.
+	 */
+	Res = f_write(&fil, (const void*)SourceAddress, FileSize,
+			&NumBytesWritten);
+	if (Res) {
+		return XST_FAILURE;
+	}
+	/*
+	 * Close file.
+	 */
+	Res = f_close(&fil);
+	if (Res) {
+		return XST_FAILURE;
+	}
+	Res = f_open(&fil, SD_File, FA_READ);
+	if (Res) {
+		return XST_FAILURE;
+	}
+	/*
+	 * Pointer to beginning of file .
+	 */
+	Res = f_lseek(&fil, 0);
+	if (Res) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Read data from file.
+	 */
+	Res = f_read(&fil, (void*)DestinationAddress, FileSize,
+			&NumBytesRead);
+	if (Res) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Data verification
+	 */
+	for(BuffCnt = 0; BuffCnt < FileSize; BuffCnt++){
+		if(SourceAddress[BuffCnt] != DestinationAddress[BuffCnt]){
+//			return XST_FAILURE;
+			error_flag = 1;
+			xil_printf('Data check error.');
+		}
+	}
+
+	/*
+	 * Close file.
+	 */
+	Res = f_close(&fil);
+	if (Res) {
+		return XST_FAILURE;
+	}
+
+	if(error_flag){
+		return XST_FAILURE;
+	}
+
+//	Res = f_unmount(Path);
+//	if (Res) {
+//		return XST_FAILURE;
+//	}
+//
+//	sleep(5);
+
+	return XST_SUCCESS;
+}

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_DEMO/sd.h

@@ -0,0 +1,9 @@
+/***************************** Include Files *********************************/
+#include "xparameters.h"	/* SDK generated parameters */
+#include "xsdps.h"		/* SD device driver */
+#include "xil_printf.h"
+#include "ff.h"
+#include "xil_cache.h"
+#include "xplatform_info.h"
+/************************** Function Prototypes ******************************/
+int FfsSdWrite(u8*image_data, u32 FileSize);

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_DEMO/tx_bisection.c

@@ -0,0 +1,74 @@
+/*
+ * tx_bisection.c
+ *
+ *  Created on: 2023Äê12ÔÂ1ÈÕ
+ *      Author: cxlab
+ */
+
+
+#include "xilinx_io.h"
+#include "sleep.h"
+#include "math.h"
+
+void txBisectionQecCalib(int f0, int fs) {
+	u8 rx_data;
+	SpiPs_write_read1(0x02E, 0x03,&rx_data);
+	SpiPs_write_read1(0x128, 0x11,&rx_data);
+	SpiPs_write_read1(0x11E, 0x01,&rx_data);
+	SpiPs_write_read1(0x77E, 0x24,&rx_data);
+	SpiPs_write_read1(0x11F, 0x01,&rx_data);
+	SpiPs_write_read1(0x121, 0x02,&rx_data);
+	SpiPs_write_read1(0x11B, 0x01,&rx_data);
+	SpiPs_write_read1(0x161, 0x01,&rx_data);
+	SpiPs_write_read1(0x162, 0x01,&rx_data);
+	SpiPs_write_read1(0x163, 0x00,&rx_data);
+    configTxNcoFreq(f0, fs * 4);
+    SpiPs_write_read1(0xA2D, 0x02,&rx_data);
+    SpiPs_write_read1(0xA07, 0x00,&rx_data);
+    SpiPs_write_read1(0xA08, 0x0F,&rx_data);
+    SpiPs_write_read1(0xA1C, 0x01,&rx_data);
+    configRxNcoFreq(f0 * 2, fs);
+    SpiPs_write_read1(0x186, 0x01,&rx_data);
+    SpiPs_write_read1(0x763, 0x34,&rx_data);
+    SpiPs_write_read1(0x76D, 0x34,&rx_data);
+    SpiPs_write_read1(0x101, 0xEF,&rx_data);
+    SpiPs_write_read1(0x101, 0xFF,&rx_data);
+    SpiPs_write_read1(0x800, 0x00,&rx_data);
+    SpiPs_write_read1(0x81A, 0xF7,&rx_data);
+    SpiPs_write_read1(0x81B, 0x34,&rx_data);
+    SpiPs_write_read1(0x81C, 0x33,&rx_data);
+    SpiPs_write_read1(0x81D, 0x12,&rx_data);
+    SpiPs_write_read1(0x81E, 0x00,&rx_data);
+    SpiPs_write_read1(0x81F, 0xFF,&rx_data);
+    SpiPs_write_read1(0x820, 0x00,&rx_data);
+    SpiPs_write_read1(0x821, 0xFF,&rx_data);
+    SpiPs_write_read1(0x800, 0x80,&rx_data);
+    SpiPs_write_read1(0x800, 0x81,&rx_data);
+    usleep(100000);
+    SpiPs_write_read1(0x77E, 0x00,&rx_data);
+}
+
+void txBisectionDcCalib(int f0, int fs) {
+	u8 rx_data;
+	SpiPs_write_read1(0x77E, 0x24,&rx_data);
+	SpiPs_write_read1(0x11F, 0x03,&rx_data);
+	SpiPs_write_read1(0x121, 0x02,&rx_data);
+	SpiPs_write_read1(0x11B, 0x01,&rx_data);
+	SpiPs_write_read1(0x11E, 0x01,&rx_data);
+	SpiPs_write_read1(0x161, 0x01,&rx_data);
+	SpiPs_write_read1(0x162, 0x01,&rx_data);
+    configTxNcoFreq(f0, fs * 4);
+    SpiPs_write_read1(0xA2D, 0x02,&rx_data);
+    SpiPs_write_read1(0xA07, 0x00,&rx_data);
+    SpiPs_write_read1(0xA08, 0x0F,&rx_data);
+    SpiPs_write_read1(0xA1C, 0x01,&rx_data);
+    configRxNcoFreq(f0, fs);
+    SpiPs_write_read1(0x81A, 0xF7,&rx_data);
+    SpiPs_write_read1(0x81B, 0x44,&rx_data);
+    SpiPs_write_read1(0x81C, 0x33,&rx_data);
+    SpiPs_write_read1(0x81D, 0x14,&rx_data);
+    SpiPs_write_read1(0x800, 0x80,&rx_data);
+    SpiPs_write_read1(0x800, 0x82,&rx_data);
+    usleep(500000);
+    SpiPs_write_read1(0x77E, 0x00,&rx_data);
+}

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_DEMO/xilinx_io.c

@@ -0,0 +1,861 @@
+/*
+ * xilinx_io.c
+ *
+ *  Created on: 2021年9月6日
+ *      Author: cxlab
+ */
+
+
+#include "sleep.h"
+#include "math.h"
+#include "xilinx_io.h"		/* SPI device driver */
+
+static XSpiPs SpiInstance;
+XGpioPs Gpio;	/* The driver instance for GPIO Device. */
+XGpio            axi_gpio_inst;                 //PL 端 AXI GPIO 驱动实例
+XScuGic          scugic_inst;                   //中断控制器  驱动实例
+XScuGic_Config * scugic_cfg_ptr;                //中断控制器  配置信息
+int hop_flag,hop_intr_flag;
+
+XAxiDma AxiDma0,AxiDma1,AxiDma2;
+
+XAxiDma* xAxiDma0Get(void){
+	return &AxiDma0;
+}
+
+XAxiDma* xAxiDma1Get(void){
+	return &AxiDma1;
+}
+
+XAxiDma* xAxiDma2Get(void){
+	return &AxiDma2;
+}
+void AXIGpioInit(void){
+    XGpio_Initialize(&axi_gpio_inst, AXI_GPIO_ID);
+   //配置 PL AXI GPIO
+    XGpio_SetDataDirection(&axi_gpio_inst, 1, 1); //设置 AXI GPIO 通道 1 为输入
+    XGpio_InterruptEnable(&axi_gpio_inst, KEY_MASK);        //使能通道 1 中断
+	XGpio_InterruptGlobalEnable(&axi_gpio_inst);            //使能 AXI GPIO 全局中断
+}
+
+void ConfigAXIGPIOIntr(void){
+	//设置中断优先级和触发类型(高电平触发)
+	XScuGic_SetPriorityTriggerType(&scugic_inst, GPIO_INT_ID, 0xA0, 0x1);
+	//关联中断 ID 和中断处理函数
+	XScuGic_Connect(&scugic_inst, GPIO_INT_ID, axi_gpio_handler, &axi_gpio_inst);
+	//使能 AXI GPIO 中断
+	XScuGic_Enable(&scugic_inst, GPIO_INT_ID);
+}
+void axi_gpio_handler(void *CallbackRef){
+	XGpio *GpioPtr = (XGpio *)CallbackRef;
+	print("Interrupt Detected!\n");
+	XGpio_InterruptDisable(GpioPtr, KEY_MASK);              //关闭 AXI GPIO 中断使能
+	frqhop_config(hop_flag);
+	XGpio_InterruptClear(GpioPtr, KEY_MASK);                //清除中断
+	XGpio_InterruptEnable(GpioPtr, KEY_MASK);               //使能 AXI GPIO 中断
+}
+void frqhop_flag(int frqhop_flag){
+	u8 rx_data;
+	hop_flag = frqhop_flag;
+	GpioSetPinDir(hop,GPIO_DIR_OUTPUT);
+	GpioWritePin(hop,0x01);
+	SpiPs_write_read2(0x615,0x00,&rx_data);
+}
+
+void ExceptionInit(void){
+	//设置并打开中断异常处理功能
+	Xil_ExceptionInit();
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)XScuGic_InterruptHandler, &scugic_inst);
+	Xil_ExceptionEnable();
+}
+void XScuGicInit(void){
+	scugic_cfg_ptr = XScuGic_LookupConfig(SCUGIC_ID);
+	XScuGic_CfgInitialize(&scugic_inst, scugic_cfg_ptr, scugic_cfg_ptr->CpuBaseAddress);
+}
+
+int SpiPsInit(u16 SpiDeviceId){
+	int Status;
+	XSpiPs_Config *SpiConfig;
+	/*
+	 * Initialize the SPI driver so that it's ready to use
+	 */
+	SpiConfig = XSpiPs_LookupConfig(SpiDeviceId);
+	if (NULL == SpiConfig) {
+		return XST_FAILURE;
+	}
+	Status = XSpiPs_CfgInitialize((&SpiInstance), SpiConfig,
+					SpiConfig->BaseAddress);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Perform a self-test to check hardware build
+	 */
+	Status = XSpiPs_SelfTest((&SpiInstance));
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+	/*
+	 * The SPI device is a slave by default and the clock phase
+	 * have to be set according to its master. In this example, CPOL is set
+	 * to quiescent high and CPHA is set to 1.
+	 */
+
+	XSpiPs_SetOptions((&SpiInstance), (XSPIPS_CR_CPHA_MASK) |
+				XSPIPS_MASTER_OPTION |
+				XSPIPS_FORCE_SSELECT_OPTION);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+	XSpiPs_SetClkPrescaler((&SpiInstance), XSPIPS_CLK_PRESCALE_8);
+	/*
+	 * Set the Rx FIFO Threshold to the Max Data
+	 */
+//	XSpiPs_SetRXWatermark((&SpiInstance),MAX_DATA);
+	/*
+	 * Enable the device.
+	 */
+	XSpiPs_Enable((&SpiInstance));
+
+return XST_SUCCESS;
+}
+
+int cx3e04_write(int addr , int value)
+{
+	Xil_Out32(AXI4_LITE_SPI_BASEADDR+addr*4,value);
+	return 1;
+}
+
+int cx3e04_read(int addr)
+{
+	return Xil_In32(AXI4_LITE_SPI_BASEADDR+addr*4);
+}
+
+void cx3e04_config(void)
+{
+	//城芯科技CX3E04
+	//Common
+	cx3e04_write(0x000,0x12);
+	cx3e04_write(0x002,0x38);
+	cx3e04_write(0x038,0x01);
+	cx3e04_write(0x003,0x30);
+	cx3e04_write(0x039,0x00);
+	//CLK
+	//clk lvds en
+	cx3e04_write(0x011,0x7F);
+	cx3e04_write(0x012,0x34);
+	cx3e04_write(0x036,0x7F);
+	cx3e04_write(0x01A,0x4B);
+	cx3e04_write(0x013,0x04);
+	cx3e04_write(0x014,0x04);
+	cx3e04_write(0x004,0x00);
+	cx3e04_write(0x008,0x00);
+	cx3e04_write(0x009,0x00);
+	cx3e04_write(0x015,0x04);
+	cx3e04_write(0x016,0x04);
+	cx3e04_write(0x005,0x00);
+	cx3e04_write(0x00A,0x00);
+	cx3e04_write(0x00B,0x00);
+	cx3e04_write(0x017,0x04);
+	cx3e04_write(0x018,0x04);
+	cx3e04_write(0x006,0x00);
+	cx3e04_write(0x00C,0x00);
+	cx3e04_write(0x00D,0x00);
+	cx3e04_write(0x019,0x04);
+	cx3e04_write(0x007,0x00);
+	cx3e04_write(0x00E,0x00);
+	cx3e04_write(0x00F,0x00);
+	cx3e04_write(0x010,0x00);
+	cx3e04_write(0x029,0x00);
+	cx3e04_write(0x02A,0x00);
+	//SYNC
+	//sync lvds en
+	cx3e04_write(0x033,0x7F);
+	cx3e04_write(0x034,0x34);
+	cx3e04_write(0x035,0x7F);
+	cx3e04_write(0x032,0x03);
+	//sync inner div
+	cx3e04_write(0x03A,0x00);
+	cx3e04_write(0x03B,0x00);
+	cx3e04_write(0x03A,0x01);
+	cx3e04_write(0x03B,0xFF);//512分频
+	cx3e04_write(0x03C,0x21);
+	cx3e04_write(0x03D,0x80);
+	cx3e04_write(0x02B,0x04);
+	cx3e04_write(0x02C,0x04);
+	cx3e04_write(0x01B,0x00);
+	cx3e04_write(0x01C,0x00);
+	cx3e04_write(0x022,0x00);
+	cx3e04_write(0x023,0x00);
+	cx3e04_write(0x02D,0x04);
+	cx3e04_write(0x02E,0x04);
+	cx3e04_write(0x01D,0x00);
+	cx3e04_write(0x01E,0x00);
+	cx3e04_write(0x024,0x00);
+	cx3e04_write(0x025,0x00);
+	cx3e04_write(0x02F,0x04);
+	cx3e04_write(0x030,0x04);
+	cx3e04_write(0x01F,0x00);
+	cx3e04_write(0x020,0x00);
+	cx3e04_write(0x026,0x00);
+	cx3e04_write(0x027,0x00);
+	cx3e04_write(0x031,0x04);
+	cx3e04_write(0x021,0x00);
+	cx3e04_write(0x028,0x00);
+	//偏置电流
+	cx3e04_write(0x040,0xFF);
+	cx3e04_write(0x041,0xFF);
+	cx3e04_write(0x042,0xFF);
+	cx3e04_write(0x043,0xF0);
+	cx3e04_write(0x044,0xFF);
+	cx3e04_write(0x045,0xFF);
+	cx3e04_write(0x046,0xFF);
+	cx3e04_write(0x047,0xF0);
+	//Others
+	cx3e04_write(0x037,0x07);
+}
+
+//int SpiPs_write_read(u8 cmd, u16 addr,u8 data,u8 * rx_data){
+int SpiPs_write_read(u8 * data,u8 * rx_data){
+	int Status;
+
+	u8 rx_buffer[3];
+
+	XSpiPs_SetSlaveSelect((&SpiInstance),0x00);
+
+
+	Status = XSpiPs_PolledTransfer((&SpiInstance),data,rx_buffer,3);
+
+	*rx_data = rx_buffer[2];
+return 0;
+}
+int SpiPs_write_read1(u16 addr,u8 data,u8 * rx_data){
+	u8 rx_data1;
+	u16 temp;
+	u8 rx_buffer[3];
+
+	temp= addr&0xff00;
+	rx_buffer[0]= temp/256+128;
+	rx_buffer[1]= addr&0x00ff;
+	rx_buffer[2]= data;
+
+	SpiPs_write_read((u8 *)&rx_buffer,&rx_data1);
+
+	*rx_data = rx_data1;
+return 0;
+}
+int SpiPs_write_read2(u16 addr,u8 data,u8 * rx_data){
+	u8 rx_data1;
+	u16 temp;
+	u8 rx_buffer[3];
+
+	temp= addr&0xff00;
+	rx_buffer[0]= temp/256;
+	rx_buffer[1]= addr&0x00ff;
+	rx_buffer[2]= data;
+
+	SpiPs_write_read((u8 *)&rx_buffer,&rx_data1);
+
+	*rx_data = rx_data1;
+return 0;
+}
+
+int GpioInit(u16 DeviceId)
+{
+	int Status;
+	XGpioPs_Config *ConfigPtr;
+	/* Initialize the GPIO driver. */
+	ConfigPtr = XGpioPs_LookupConfig(DeviceId);
+	Status = XGpioPs_CfgInitialize(&Gpio, ConfigPtr,
+					ConfigPtr->BaseAddr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+	return XST_SUCCESS;
+}
+
+int GpioSetPinDir(u32 Pin,u32 Direction){
+	XGpioPs_SetDirectionPin((&Gpio),GPIO_EMIO_OFFSET + Pin,Direction);
+	return 0;
+}
+int GpioWritePin(u32 Pin,u32 data){
+	XGpioPs_SetOutputEnablePin(&Gpio, GPIO_EMIO_OFFSET + Pin, 1);
+	XGpioPs_WritePin((&Gpio),GPIO_EMIO_OFFSET + Pin,data);
+	return 0;
+}
+
+int GpioReadPin(u32 Pin){
+	return XGpioPs_ReadPin((&Gpio),GPIO_EMIO_OFFSET + Pin);
+}
+
+void DeviceRst(void){
+	GpioWritePin(NRST,0);
+	GpioWritePin(NRST,1);
+}
+
+int XAxiDma_Init(XAxiDma* AxiDma,u16 DeviceId){
+
+	XAxiDma_Config *CfgPtr;
+	int Status;
+	/* Initialize the XAxiDma device.
+	 */
+	CfgPtr = XAxiDma_LookupConfig(DeviceId);
+	if (!CfgPtr) {
+		xil_printf("No config found for %d\r\n", DeviceId);
+		return XST_FAILURE;
+	}
+
+	Status = XAxiDma_CfgInitialize(AxiDma, CfgPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Initialization failed %d\r\n", Status);
+		return XST_FAILURE;
+	}
+
+	if(XAxiDma_HasSg(AxiDma)){
+		xil_printf("Device configured as SG mode \r\n");
+		return XST_FAILURE;
+	}
+
+	/* Disable interrupts, we use polling mode
+	 */
+	XAxiDma_IntrDisable(AxiDma, XAXIDMA_IRQ_ALL_MASK,
+						XAXIDMA_DEVICE_TO_DMA);
+	XAxiDma_IntrDisable(AxiDma, XAXIDMA_IRQ_ALL_MASK,
+						XAXIDMA_DMA_TO_DEVICE);
+return 0;
+}
+
+int XAxiDmaCapture(XAxiDma* AxiDma,u32 data_length){
+	int Status;
+	u8 *TxBufferPtr;
+	u32 MAX_PKT_LEN;
+	MAX_PKT_LEN = data_length;
+	TxBufferPtr = (u8 *)TX_BUFFER_BASE;
+	Xil_DCacheFlushRange((UINTPTR)TxBufferPtr, MAX_PKT_LEN);
+	Status = XAxiDma_Busy(AxiDma,XAXIDMA_DEVICE_TO_DMA);
+	Status = XAxiDma_Busy(AxiDma,XAXIDMA_DMA_TO_DEVICE);
+	XAxiDma_Reset(AxiDma);
+	Status = XAxiDma_ResetIsDone(AxiDma);
+	Status = XAxiDma_Busy(AxiDma,XAXIDMA_DEVICE_TO_DMA);
+	Status = XAxiDma_Busy(AxiDma,XAXIDMA_DMA_TO_DEVICE);
+
+	Status = XAxiDma_SimpleTransfer(AxiDma,(UINTPTR) TxBufferPtr,MAX_PKT_LEN*8, XAXIDMA_DEVICE_TO_DMA);
+	SetPacketSize(AxiDma,MAX_PKT_LEN);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	u32 start_TickCount,current_TickCount=0;
+	start_TickCount = sys_now();
+	u32 offset= 0;
+	//never come out ,reason is stream does't have tlast.Need a module to pack excatly the same length defined in para.
+	while ((offset< 500)&&(XAxiDma_Busy(AxiDma,XAXIDMA_DEVICE_TO_DMA))) {
+		Status = XAxiDma_Busy(AxiDma,XAXIDMA_DEVICE_TO_DMA);
+
+		current_TickCount =sys_now();
+		offset = current_TickCount-start_TickCount;
+//		xil_printf("offset: %d\r\n", offset);
+	}
+	/*
+	u64 offset= 0;
+	//never come out ,reason is stream does't have tlast.Need a module to pack excatly the same length defined in para.
+	while ((offset> 100000)||(XAxiDma_Busy(AxiDma,XAXIDMA_DEVICE_TO_DMA))) {
+		Status = XAxiDma_Busy(AxiDma,XAXIDMA_DEVICE_TO_DMA);
+	}*/
+	return 0;
+}
+
+
+
+int SetPacketSize(XAxiDma* AxiDma,u32 length){
+
+	UINTPTR Addr;
+	if(AxiDma == xAxiDma0Get())
+		Addr = PACKER_BASEADDR0;
+	else if(AxiDma == xAxiDma1Get())
+		Addr = PACKER_BASEADDR1;
+	else
+		Addr = PACKER_BASEADDR2;
+	xil_printf("addr %x .\n",Addr);
+	Xil_Out32(Addr,0);
+	xil_printf("PACKER_BASEADDR DATA %d .\n",Xil_In32(Addr));
+	Xil_Out32(Addr+4,length);
+	xil_printf("PACKER_BASEADDR +4 DATA %d .\n",Xil_In32(Addr + 4));
+	Xil_Out32(Addr,1);
+	xil_printf("PACKER_BASEADDR DATA %d .\n",Xil_In32(Addr));
+	return  0;
+}
+int DownloadWave(u8 * data){
+	u32 * buffer;
+	u64 addr;
+	int i;
+	buffer =  (u32 *) data;
+	addr = BRAM_BASEADDR;
+	for(i=0;i<WAVELENGTH;i++){
+		Xil_Out32(addr+i*4,* (buffer +i));
+//		Xil_Out32(addr+i*4,0x11223344);
+//		xil_printf("ADDR 0x%x DATA 0x%x.\r\n",(buffer +i), * (buffer +i));
+	}
+	addr = BRAM_BASEADDR_1;
+		for(i=0;i<WAVELENGTH;i++){
+			Xil_Out32(addr+i*4,* (buffer +i));
+//			Xil_Out32(addr+i*4,0x11223344);
+//			xil_printf("ADDR 0x%x DATA 0x%x.\r\n",(buffer +i), * (buffer +i));
+		}
+	return 0;
+}
+void dbg_printf( const char8 *ctrl1, ...){
+#ifdef DBGLOG
+	xil_printf( ctrl1 );
+#endif
+}
+void PackerRst(void){
+    GpioSetPinDir(0x03,GPIO_DIR_OUTPUT);
+    GpioWritePin(3,0x0);//dma_axis_rx_rstn
+    GpioWritePin(3,0x01);//dma_axis_rx_rstn
+    GpioSetPinDir(0x09,GPIO_DIR_OUTPUT);
+    GpioWritePin(9,0x01);//data_valid
+}
+int peripheral_test(void){
+u8 spi_test;
+u8 Gpio_test;
+u8 BRAM_test;
+u8 DDR_test;
+//	SPI TEST
+u8 rx_data;
+xil_printf("start spi test.\r\n");
+u8 spi_wr_buff[3]={0x87,0x82,0x5A};
+u8 spi_rd_buff[3]={0x07,0x82,0x00};
+SpiPs_write_read(spi_wr_buff,&rx_data);
+SpiPs_write_read(spi_rd_buff,&rx_data);
+if(rx_data==spi_wr_buff[2])
+{
+	xil_printf("spi test successful.\r\n");
+	spi_test = 1;
+}else
+{
+	xil_printf("spi test unsuccessful.\r\n");
+	spi_test = 0;
+}
+
+
+//BRAM TEST
+xil_printf("start bram test.\r\n");
+BRAM_test = 1;
+//for (int i=0;i<8192;i++){
+//	Xil_Out32(XPAR_BRAM_0_BASEADDR + 4*i,i);
+//	if(i != Xil_In32(XPAR_BRAM_0_BASEADDR + 4*i)){
+////		xil_printf("BRAM ERROR,ADDR %x DATA %d read back is %d.\r\n",XPAR_BRAM_0_BASEADDR + 4*i,i,Xil_In32(XPAR_BRAM_0_BASEADDR + 4*i));
+//		BRAM_test = 0;
+//	}
+////	else{
+////		xil_printf("BRAM PASS,ADDR %x DATA %d read back is %d.\r\n",XPAR_BRAM_0_BASEADDR + 4*i,i,Xil_In32(XPAR_BRAM_0_BASEADDR + 4*i));
+////	}
+//}
+
+//MIG TEST
+xil_printf("start mig test.\r\n");
+DDR_test = 1;
+for (int i=0;i<2048;i++){
+	Xil_Out32(TX_BUFFER_BASE + 4*i,i);
+	if(i != Xil_In32(TX_BUFFER_BASE + 4*i)){
+//		xil_printf("MIG ERROR,ADDR %x DATA %d read back is %d.\r\n",TX_BUFFER_BASE + 4*i,i,Xil_In32(TX_BUFFER_BASE + 4*i));
+		DDR_test = 0;
+	}
+//	else{
+//		xil_printf("BRAM11 PASS,ADDR %x DATA %d read back is %d.\r\n",TX_BUFFER_BASE + 4*i,i,Xil_In32(TX_BUFFER_BASE + 4*i));
+//	}
+}
+
+// GPIO TEST
+int Gpio_data;
+xil_printf("start gpio test.\r\n");
+GpioSetPinDir(NRST,GPIO_DIR_OUTPUT);
+GpioWritePin(NRST,0x00);
+GpioWritePin(NRST,0x01);
+GpioSetPinDir(rst,GPIO_DIR_OUTPUT);
+GpioWritePin(rst,0x01);
+GpioWritePin(rst,0x00);
+GpioSetPinDir(aresetn_0,GPIO_DIR_OUTPUT);
+GpioWritePin(aresetn_0,0x00);
+GpioWritePin(aresetn_0,0x01);
+GpioSetPinDir(aresetn_1,GPIO_DIR_OUTPUT);
+GpioWritePin(aresetn_1,0x00);
+GpioWritePin(aresetn_1,0x01);
+GpioSetPinDir(aresetn_2,GPIO_DIR_OUTPUT);
+GpioWritePin(aresetn_2,0x00);
+GpioWritePin(aresetn_2,0x01);
+GpioSetPinDir(debug_mode,GPIO_DIR_OUTPUT);
+GpioWritePin(debug_mode,0x00);
+GpioSetPinDir(cx3e04_rstn,GPIO_DIR_OUTPUT);
+GpioWritePin(cx3e04_rstn,0x01);
+//GpioSetPinDir(test_temp,GPIO_DIR_INPUT);
+Gpio_data=GpioReadPin(aresetn_1);
+if(Gpio_data==1)
+{
+	xil_printf("GPIO test successful.\r\n");
+	Gpio_test = 1;
+}else
+{
+	xil_printf("GPIO test unsuccessful.\r\n");
+	Gpio_test = 0;
+}
+//GpioSetPinDir(test_temp,GPIO_DIR_OUTPUT);
+//GpioWritePin(test_temp,0x01);
+
+if((spi_test==1)&&(Gpio_test==1)&&(BRAM_test==1)&&(DDR_test==1))
+{
+	xil_printf("peripheral test successful.\r\n");
+	return 1;
+}else
+{
+	xil_printf("peripheral test unsuccessful.\r\n");
+	return 0;
+}
+
+}
+
+int spi_stack_in(u8 * data,struct spi_stack * spistack){
+	spistack->recv_buf[spistack->spi_write_num * 3 + 0] = *(data + 0);
+	spistack->recv_buf[spistack->spi_write_num * 3 + 1] = *(data + 1);
+	spistack->recv_buf[spistack->spi_write_num * 3 + 2] = *(data + 2);
+	spistack->spi_write_num = spistack->spi_write_num + 1;
+	if(spistack->spi_write_num >= SPI_STACK_LENGTH-1){
+		return 1;
+	}
+	else
+		return 0;
+}
+
+void spi_stack_out(struct spi_stack * spistack){
+
+	int i;
+	u8 rx_data;
+	for(i=0;i<spistack->spi_write_num;i++ ){
+	SpiPs_write_read((u8 *)&(spistack->recv_buf[i * 3]),&rx_data);
+	}
+	spistack->spi_write_num = 0;
+}
+
+int rom_read(u8 * data)
+{
+	int addr ;
+	addr = *(data + 0)*256+  *(data + 1);
+	return Xil_In32(BROM_BASEADDR+addr*4);
+}
+
+void trx_ch_pll_config(u8 pll_index)
+{
+	u8 rx_data;
+	u8 recv_buf[3]={0};
+	u32 trx_ch_pll_data;
+
+	if(pll_index==1){
+		trx_ch_pll_data = 0x00077DCF;
+	}else if(pll_index==2){
+		trx_ch_pll_data = 0x00077D0C;
+	}
+
+	recv_buf[0] =(trx_ch_pll_data>>16 & 0xff)|0x80 ;
+	recv_buf[1] = trx_ch_pll_data>>8 & 0xff;
+	recv_buf[2] = trx_ch_pll_data  & 0xff;
+	SpiPs_write_read(recv_buf,&rx_data);
+}
+
+u16 pll1_config_addr[] ={0x0620,0x061D,0x0B06,0x0B07,0x0B08,0x0B09,0x0B0A,0x061A,0x061B,0x061C,0x062A};
+u16 pll2_config_addr[] ={0x0642,0x063F,0x0B14,0x0B15,0x0B16,0x0B17,0x0B18,0x063C,0x063D,0x063E,0x064C};
+u16 pll3_config_addr[] ={0x0664,0x0661,0x0B22,0x0B23,0x0B24,0x0B25,0x0B26,0x065E,0x065F,0x0660,0x066E};
+u16 pll4_config_addr[] ={0x0686,0x0683,0x0B30,0x0B31,0x0B32,0x0B33,0x0B34,0x0680,0x0681,0x0682,0x0690};
+
+int PLL_config(u8 pll_index,double pll_frq)
+{
+
+	int i = 0,afc_cnt=0;
+	u16 pll_config_addr[11];
+	u16 afc_addr,lock_addr;
+	double ref=200;
+	u8 pllreg_buf[11];
+	u8 recv_buf[3];
+	u8 rx_data,pll_div;
+	u16 div_addr;
+
+	switch(pll_index){
+		case 1:for (i = 0; i < 11; i++){pll_config_addr[i] = pll1_config_addr[i];} afc_addr=0x0617;lock_addr=0x0635;break;
+		case 2:for (i = 0; i < 11; i++){pll_config_addr[i] = pll2_config_addr[i];} afc_addr=0x0639;lock_addr=0x0657;break;
+		case 3:for (i = 0; i < 11; i++){pll_config_addr[i] = pll3_config_addr[i];} afc_addr=0x065B;lock_addr=0x0679;break;
+		case 4:for (i = 0; i < 11; i++){pll_config_addr[i] = pll4_config_addr[i];} afc_addr=0x067D;lock_addr=0x069B;break;
+		default :;
+	}
+    //caculate pll frequence word
+	pll_frq_caculation_new(ref,pll_frq,(u8 *)&pllreg_buf);
+	for (i = 0; i < 11; i++)
+	{
+		recv_buf[0] = (pll_config_addr[i]>>8 & 0xff)|0x80 ;
+		recv_buf[1] =  pll_config_addr[i] & 0xff;
+		recv_buf[2] =  pllreg_buf[i] & 0xff;
+		SpiPs_write_read((u8 *)&recv_buf[0],&rx_data);
+	}
+    //afc pll
+	pll_div  = pllreg_buf[1];
+	div_addr = pll_config_addr[1];
+	recv_buf[0] = lock_addr>>8 & 0xff ;
+	recv_buf[1] = lock_addr & 0xff;
+	recv_buf[2] = 0x00;
+	while(rx_data!=48){
+		PLL_afc(afc_addr,div_addr,pll_div);
+		SpiPs_write_read((u8 *)&recv_buf[0],&rx_data);
+		afc_cnt++;
+	}
+    return afc_cnt;
+	//xil_printf("afc lock count: %d.\r\n",afc_cnt);
+
+}
+
+void PLL_afc(u16 afc_addr,u16 div_addr,u8 pll_div){
+
+	u8 recv_buf[3];
+	u8 rx_data;
+	if(pll_div>=48){
+		recv_buf[0] = (div_addr>>8 & 0xff)|0x80 ;
+		recv_buf[1] =  div_addr & 0xff;
+		recv_buf[2] =  pll_div & 0x2f;
+		SpiPs_write_read((u8 *)&recv_buf[0],&rx_data);
+	}
+	recv_buf[0] = (afc_addr>>8 & 0xff)|0x80 ;
+	recv_buf[1] =  afc_addr & 0xff;
+	recv_buf[2] =  0x00;
+	SpiPs_write_read((u8 *)&recv_buf[0],&rx_data);
+	recv_buf[2] =  0x03;
+	SpiPs_write_read((u8 *)&recv_buf[0],&rx_data);
+	usleep(30);
+	if(pll_div>=48){
+		recv_buf[0] = (div_addr>>8 & 0xff)|0x80 ;
+		recv_buf[1] =  div_addr & 0xff;
+		recv_buf[2] =  pll_div & 0xff;
+		SpiPs_write_read((u8 *)&recv_buf[0],&rx_data);
+	}
+
+}
+
+int pll_frq_caculation(double ref,double pll_frq,u8 *reg_data){
+
+    u8 row,column;
+	int vco = pll_frq;
+	int div = 1;
+	while(vco < 7001){
+		vco = vco*2;
+	    div = div*2;
+	}
+	char  coreTable[7][4][3] =  {{{0x0C,0x30,0x08},{0x0B,0x30,0x09},{0x0C,0x30,0x05},{0x0D,0x30,0x08}},
+								 {{0x0C,0x30,0x0C},{0x0B,0x30,0x0E},{0x0C,0x30,0x08},{0x0D,0x30,0x0B}},
+								 {{0x0C,0x20,0x10},{0x0B,0x20,0x10},{0x0C,0x20,0x0A},{0x0D,0x20,0x0D}},
+								 {{0x0C,0x20,0x11},{0x0B,0x20,0x13},{0x0C,0x20,0x0C},{0x0D,0x20,0x0F}},
+								 {{0x0D,0x30,0x14},{0x0D,0x22,0x14},{0x0D,0x20,0x0D},{0x0D,0x15,0x0C}},
+								 {{0x0E,0x30,0x18},{0x0E,0x25,0x16},{0x0E,0x25,0x0F},{0x0E,0x18,0x0F}},
+								 {{0x0F,0x38,0x1A},{0x0F,0x32,0x1C},{0x0F,0x18,0x12},{0x0F,0x18,0x12}}};
+
+	    if (ref >= 28 && ref < 40){
+	        row = 0;
+	    }else if (ref >= 40 && ref < 60){
+	        row = 1;
+		}else if (ref >= 60 && ref < 90){
+	        row = 2;
+		}else if (ref >= 90 && ref < 110){
+	        row = 3;
+		}else if (ref >= 110 && ref < 140){
+	        row = 4;
+		}else if (ref >= 140 && ref < 180){
+	        row = 5;
+		}else if (ref >= 180 && ref <= 240){
+	        row = 6;
+		}
+
+	    if (vco >= 7001 && vco < 8400){
+	        column = 0;
+		}else if (vco >= 8400 && vco < 10500){
+	        column = 1;
+		}else if (vco >= 10500 && vco < 12000){
+	        column = 2;
+		}else if (vco >= 12000 && vco <= 14000){
+	        column = 3;
+		}
+
+		char cp   = coreTable[row][column][0];
+		char c1r3 = coreTable[row][column][1];
+		char r1   = coreTable[row][column][2];
+
+		char dither,nHigh,nLow,fHigh,fMiddle,fLow,outputDiv,core = 0x81;
+	    if(vco > 10500){
+	         core = core + 0x10;
+	    }
+	    if (div == 2){
+	        outputDiv = 0+7;
+	    }else if (div == 4){
+	        outputDiv = 32+7;
+	    }else{
+	        outputDiv = 48 + divBin(div);
+	    }
+
+	    double nf = 1.0*vco / ref;
+	    int n = nf;
+	    double f = nf - n;
+	    if(f > 1e-10){
+	        dither = 11;
+	    }else{
+	        dither = 0;
+	    }
+	    if(n >= 256){
+	        nHigh = 1;
+	    }else{
+	        nHigh = 0;
+	    }
+	    nLow = n & 0xff;
+	    int f1 = f * pow(2,24);
+	    fHigh   = f1>>16 & 0xff;
+	    fMiddle = f1>>8 & 0xff;
+	    fLow    = f1 & 0xff;
+	    reg_data[0]=core;
+	    reg_data[1]=outputDiv;
+	    reg_data[2]=nHigh;
+	    reg_data[3]=nLow;
+	    reg_data[4]=fHigh;
+	    reg_data[5]=fMiddle;
+	    reg_data[6]=fLow;
+	    reg_data[7]=cp;
+	    reg_data[8]=c1r3;
+	    reg_data[9]=r1;
+	    reg_data[10]=dither;
+	return 0;
+}
+int pll_frq_caculation_new(double ref,double pll_frq,u8 *reg_data){
+
+    u8 row,column;
+    double vco = pll_frq;
+	int div = 1;
+	while(vco < 6701){
+		vco = vco*2;
+	    div = div*2;
+	}
+	char  coreTable[7][4][3] =  {{{0x0C,0x30,0x08},{0x0B,0x30,0x09},{0x0C,0x30,0x05},{0x0D,0x30,0x08}},
+								 {{0x0C,0x30,0x0C},{0x0B,0x30,0x0E},{0x0C,0x30,0x08},{0x0D,0x30,0x0B}},
+								 {{0x0C,0x20,0x10},{0x0B,0x20,0x10},{0x0C,0x20,0x0A},{0x0D,0x20,0x0D}},
+								 {{0x0C,0x20,0x11},{0x0B,0x20,0x13},{0x0C,0x20,0x0C},{0x0D,0x20,0x0F}},
+								 {{0x0D,0x30,0x14},{0x0D,0x22,0x14},{0x0D,0x20,0x0D},{0x0D,0x15,0x0C}},
+								 {{0x0E,0x30,0x18},{0x0E,0x25,0x16},{0x0E,0x25,0x0F},{0x0E,0x18,0x0F}},
+								 {{0x0F,0x38,0x1A},{0x0F,0x32,0x1C},{0x0F,0x18,0x12},{0x0F,0x18,0x12}}};
+
+	    if (ref >= 28 && ref < 40){
+	        row = 0;
+	    }else if (ref >= 40 && ref < 60){
+	        row = 1;
+		}else if (ref >= 60 && ref < 90){
+	        row = 2;
+		}else if (ref >= 90 && ref < 110){
+	        row = 3;
+		}else if (ref >= 110 && ref < 140){
+	        row = 4;
+		}else if (ref >= 140 && ref < 180){
+	        row = 5;
+		}else if (ref >= 180 && ref <= 240){
+	        row = 6;
+		}
+
+	    if (vco < 8400){
+	        column = 0;
+		}else if (vco >= 8400 && vco < 10150){
+	        column = 1;
+		}else if (vco >= 10150 && vco < 12000){
+	        column = 2;
+		}else if (vco >= 12000 ){
+	        column = 3;
+		}
+
+		char cp   = coreTable[row][column][0];
+		char c1r3 = coreTable[row][column][1];
+		char r1   = coreTable[row][column][2];
+
+		char dither,nHigh,nLow,fHigh,fMiddle,fLow,outputDiv,core = 0x81;
+	    if(vco > 10150){
+	         core = core + 0x10;
+	    }
+	    if (div == 2){
+	        outputDiv = 0+7;
+	    }else if (div == 4){
+	        outputDiv = 32+7;
+	    }else{
+	        outputDiv = 48 + divBin(div);
+	    }
+
+	    double nf = 1.0*vco / ref;
+	    int n = nf;
+	    double f = nf - n;
+	    if(f > 1e-10){
+	        dither = 11;
+	    }else{
+	        dither = 0;
+	    }
+	    if(n >= 256){
+	        nHigh = 1;
+	    }else{
+	        nHigh = 0;
+	    }
+	    nLow = n & 0xff;
+	    int f1 = f * pow(2,24);
+	    fHigh   = f1>>16 & 0xff;
+	    fMiddle = f1>>8 & 0xff;
+	    fLow    = f1 & 0xff;
+	    reg_data[0]=core;
+	    reg_data[1]=outputDiv;
+	    reg_data[2]=nHigh;
+	    reg_data[3]=nLow;
+	    reg_data[4]=fHigh;
+	    reg_data[5]=fMiddle;
+	    reg_data[6]=fLow;
+	    reg_data[7]=cp;
+	    reg_data[8]=c1r3;
+	    reg_data[9]=r1;
+	    reg_data[10]=dither;
+	return 0;
+}
+char divBin(u16 div){
+
+	switch(div){
+		case   8:return 7;break;
+		case  16:return 6;break;
+		case  32:return 5;break;
+		case  64:return 4;break;
+		case 128:return 3;break;
+		case 256:return 2;break;
+		default :return 2;
+	}
+
+}
+
+void configTxNcoFreq(int freq, int fs) {
+	u8 rx_data;
+	double ratio = (double) freq < 0 ? (freq + fs) / fs : freq / fs;
+	double bin = ratio * pow(2,48);
+	int bin_low = (u32) bin & 0xFFFFFF;
+	int bin_high = (u32)(bin / pow(2,24)) & 0xFFFFFF;
+    SpiPs_write_read1(0x164, (bin_high >> 16) & 0xFF,&rx_data);
+    SpiPs_write_read1(0x165, (bin_high >> 8) & 0xFF,&rx_data);
+    SpiPs_write_read1(0x166,  bin_high & 0xFF,&rx_data);
+    SpiPs_write_read1(0x167, (bin_low >> 16) & 0xFF,&rx_data);
+    SpiPs_write_read1(0x168, (bin_low >> 8) & 0xFF,&rx_data);
+    SpiPs_write_read1(0x169,  bin_low & 0xFF,&rx_data);
+}
+void configRxNcoFreq(int freq, int fs) {
+	u8 rx_data;
+	double ratio = (double) freq < 0 ? (freq + fs) / fs : freq / fs;
+	double bin = ratio * pow(2,48);
+	int bin_low = (u32) bin & 0xFFFFFF;
+	int bin_high = (u32)(bin / pow(2,24)) & 0xFFFFFF;
+    SpiPs_write_read1(0xA16, (bin_high >> 16) & 0xFF,&rx_data);
+    SpiPs_write_read1(0xA17, (bin_high >> 8) & 0xFF,&rx_data);
+    SpiPs_write_read1(0xA18,  bin_high & 0xFF,&rx_data);
+    SpiPs_write_read1(0xA19, (bin_low >> 16) & 0xFF,&rx_data);
+    SpiPs_write_read1(0xA1A, (bin_low >> 8) & 0xFF,&rx_data);
+    SpiPs_write_read1(0xA1B,  bin_low & 0xFF,&rx_data);
+}
+

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_DEMO/xilinx_io.h

@@ -0,0 +1,149 @@
+/*
+ * xilinx_io.h
+ *
+ *  Created on: 2021年9月6日
+ *      Author: cxlab
+ */
+
+#ifndef SRC_XILINX_IO_H_
+#define SRC_XILINX_IO_H_
+
+
+
+#endif /* SRC_XILINX_IO_H_ */
+#include "xspips.h"		/* SPI device driver */
+#include "xgpiops.h"
+#include "xgpio.h"
+#include "xaxidma.h"
+#include "xparameters.h"
+#include "xscugic.h"
+#include "xil_exception.h"
+
+//#define DBGLOG
+#define MAX_DATA		 100
+#define SPI_WRITE		 0x80
+#define SPI_READ		 0x00
+#define GPIO_DIR_INPUT   0x00
+#define GPIO_DIR_OUTPUT  0x01
+#define GPIO_EMIO_OFFSET 54
+
+#define TX_EN  0x08
+#define RX_EN  0x07
+#define GPIO_1  0x06
+#define GPIO_0  0x05
+
+#define NRST 0
+#define ENABLE_TRX1 1
+#define ENABLE_TRX2 2
+#define ENABLE_TRX3 3
+#define TXNRX_TRX1 4
+#define TXNRX_TRX2 5
+#define TXNRX_RX3 6
+
+#define aresetn_0 33
+#define rst 34
+#define tr_sel 35
+#define tdd_fdd_sel 36
+#define r1t1_r2t2_sel 37
+#define sp_dp_sel 38
+#define aresetn_1 39
+#define aresetn_2 40
+#define hop 41
+#define cx3e04_rstn 42
+#define debug_mode 63
+
+#define INTER_SIG3  0x03//dma_axis_rx_rstn
+#define INTER_SIG2  0x02//frame_pattern
+#define INTER_SIG1  0x01//mode_sel_async
+#define INTER_SIG0  0x00//rst_async
+
+#define SPI_DEVICE_ID XPAR_XSPIPS_0_DEVICE_ID
+#define GPIO_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
+
+#define AXI_DMA_DEVCIE_ID0 XPAR_AXI_DMA_0_DEVICE_ID
+#define AXI_DMA_DEVCIE_ID1 XPAR_AXI_DMA_1_DEVICE_ID
+#define AXI_DMA_DEVCIE_ID2 XPAR_AXI_DMA_2_DEVICE_ID
+
+#define BROM_BASEADDR XPAR_M08_AXI_0_BASEADDR
+
+#define AXI4_LITE_SPI_BASEADDR XPAR_AXI4_LITE_SPI_0_BASEADDR
+#define BRAM_BASEADDR XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR
+#define BRAM_BASEADDR_1 XPAR_AXI_BRAM_CTRL_1_S_AXI_BASEADDR
+#define PACKER_BASEADDR0 XPAR_AXIS_ADC_DATA_PACKER_0_S00_AXI_BASEADDR
+#define PACKER_BASEADDR1 XPAR_AXIS_ADC_DATA_PACKER_1_S00_AXI_BASEADDR
+#define PACKER_BASEADDR2 XPAR_AXIS_ADC_DATA_PACKER_2_S00_AXI_BASEADDR
+#define WAVELENGTH 8192
+#define TX_BUFFER_BASE		XPAR_MIG_7SERIES_0_BASEADDR +0x2000
+#define WAVE_LENGTH 8192*4
+
+#define GPIO_INT_ID XPAR_FABRIC_GPIO_0_VEC_ID   //PL 端  AXI GPIO 中断 ID
+#define AXI_GPIO_ID XPAR_AXI_GPIO_0_DEVICE_ID   //PL 端  AXI GPIO 器件 ID
+#define SCUGIC_ID   XPAR_SCUGIC_0_DEVICE_ID     //中断控制器 ID
+
+#define KEY_MASK    XGPIO_IR_CH1_MASK           //通道 1 的位定义
+
+int cx3e04_write(int addr , int value);
+int cx3e04_read(int addr);
+void cx3e04_config(void);
+void cx9261a_710_config(void);
+
+void AXIGpioInit(void);
+void ConfigAXIGPIOIntr(void);
+void axi_gpio_handler(void *CallbackRef);
+void XScuGicInit(void);
+void ExceptionInit(void);
+
+int SpiPsInit(u16 SpiDeviceId);
+//int SpiPs_write_read(u8 cmd, u16 addr,u8 data,u8 * rx_data);
+int SpiPs_write_read(u8 * data,u8 * rx_data);
+int SpiPs_write_read1(u16 addr,u8 data,u8 * rx_data);
+int SpiPs_write_read2(u16 addr,u8 data,u8 * rx_data);
+int GpioInit(u16 DeviceId);
+int GpioSetPinDir(u32 Pin,u32 Direction);
+int GpioWritePin(u32 Pin,u32 data);
+int GpioReadPin(u32 Pin);
+void DeviceRst(void);
+
+//校准
+void cx9261a_151_config(void);
+void cx9261a_076_config(void);
+void rxFFTCalib(int lo, int fs,int ref, int firLength,int chan);
+void configTxNcoFreq(int freq, int fs);
+void configRxNcoFreq(int freq, int fs);
+void configDcCalib(int dcCalibEnable,int dcCalibLength);
+void txBisectionQecCalib(int f0, int fs);
+void txBisectionDcCalib(int f0, int fs);
+
+extern XAxiDma* xAxiDma0Get(void);
+extern XAxiDma* xAxiDma1Get(void);
+extern XAxiDma* xAxiDma2Get(void);
+int XAxiDma_Init(XAxiDma* AxiDma,u16 DeviceId);
+int XAxiDmaCapture(XAxiDma* AxiDma,u32 data_length);
+int XAxiDmaCapture2(XAxiDma* AxiDma,u32 data_length);
+
+int DownloadWave(u8 * data);
+int SetPacketSize(XAxiDma* AxiDma,u32 length);
+void dbg_printf( const char8 *ctrl1, ...);
+void PackerRst(void);
+int peripheral_test(void);
+
+#define SPI_STACK_LENGTH 65536
+struct spi_stack {
+	int spi_write_num;
+	u8 recv_buf[SPI_STACK_LENGTH*3];
+};
+int spi_stack_in(u8 * data,struct spi_stack * spistack);
+
+void spi_stack_out(struct spi_stack * spistack);
+
+int rom_read(u8 * data);
+void download_bin(void);
+//跳频
+void frqhop_config(int hop_flag);
+void frqhop_flag(int frqhop_flag);
+int PLL_config(u8 pll_index,double pll_frq);
+void trx_ch_pll_config(u8 pll_index);
+int pll_frq_caculation(double ref,double pll_frq,u8 *reg_data);
+int pll_frq_caculation_new(double ref,double pll_frq,u8 *reg_data);
+void PLL_afc(u16 afc_addr,u16 div_addr,u8 pll_div);
+char divBin(u16 div);

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_HOP/cx9261a_076_config.c

@@ -0,0 +1,342 @@
+/*
+ * cx9261a_076_config.c
+ *
+ *  Created on: 2023年11月30日
+ *      Author: cxlab
+ */
+
+
+#include "xilinx_io.h"
+#include "sleep.h"
+void cx9261a_076_config(void){
+u8 rx_data;
+int temp;
+
+//setPin(pin,value)
+GpioSetPinDir(0,0x01);
+GpioWritePin(0,1);
+GpioSetPinDir(32,0x01);
+GpioWritePin(32,1);
+GpioSetPinDir(33,0x01);
+GpioWritePin(33,1);
+GpioSetPinDir(34,0x01);
+GpioWritePin(34,0);
+GpioSetPinDir(35,0x01); //tx:0-rx:1
+GpioWritePin(35,1); //tx:0-rx:1
+GpioSetPinDir(36,0x01); //fdd:0-tdd:1
+GpioWritePin(36,1); //fdd:0-tdd:1
+GpioSetPinDir(37,0x01); //1r1t:0-2r2t:1
+GpioWritePin(37,0); //1r1t:0-2r2t:1
+GpioSetPinDir(38,0x01); //dualport:0-singleport:1
+GpioWritePin(38,1); //dualport:0-singleport:1
+GpioSetPinDir(39,0x01);
+GpioWritePin(39,1);
+GpioSetPinDir(40,0x01);
+GpioWritePin(40,1);
+//三个通道共同控制
+SpiPs_write_read1(0x000,0x02,&rx_data);
+//电源管理自定义
+//断电模式
+SpiPs_write_read1(0x031,0x00,&rx_data);
+SpiPs_write_read1(0x032,0x7F,&rx_data);
+SpiPs_write_read1(0x033,0xFF,&rx_data);
+SpiPs_write_read1(0x034,0xFF,&rx_data);
+//休眠模式
+SpiPs_write_read1(0x035,0x00,&rx_data);
+SpiPs_write_read1(0x036,0x3D,&rx_data);
+SpiPs_write_read1(0x037,0xFF,&rx_data);
+SpiPs_write_read1(0x038,0xEB,&rx_data);
+//警戒模式
+SpiPs_write_read1(0x039,0x00,&rx_data);
+SpiPs_write_read1(0x03A,0x3D,&rx_data);
+SpiPs_write_read1(0x03B,0xFF,&rx_data);
+SpiPs_write_read1(0x03C,0xE0,&rx_data);
+//校准模式
+SpiPs_write_read1(0x03D,0x1B,&rx_data);
+SpiPs_write_read1(0x03E,0x39,&rx_data);
+SpiPs_write_read1(0x03F,0x27,&rx_data);
+SpiPs_write_read1(0x040,0xE0,&rx_data);
+//接收模式
+SpiPs_write_read1(0x041,0x03,&rx_data);
+SpiPs_write_read1(0x042,0x3D,&rx_data);
+SpiPs_write_read1(0x043,0xE7,&rx_data);
+SpiPs_write_read1(0x044,0xF8,&rx_data);
+//发射模式
+SpiPs_write_read1(0x045,0x1B,&rx_data);
+SpiPs_write_read1(0x046,0x3D,&rx_data);
+SpiPs_write_read1(0x047,0x26,&rx_data);
+SpiPs_write_read1(0x048,0x7E,&rx_data);
+//FDD模式
+SpiPs_write_read1(0x049,0x1B,&rx_data);
+SpiPs_write_read1(0x04A,0x3D,&rx_data);
+SpiPs_write_read1(0x04B,0x27,&rx_data);
+SpiPs_write_read1(0x04C,0xE0,&rx_data);
+//观测模式
+SpiPs_write_read1(0x04D,0x04,&rx_data);
+SpiPs_write_read1(0x04E,0x3D,&rx_data);
+SpiPs_write_read1(0x04F,0xD9,&rx_data);
+SpiPs_write_read1(0x050,0xFE,&rx_data);
+//带隙基准
+SpiPs_write_read1(0x773,0x53,&rx_data);
+SpiPs_write_read1(0x774,0x86,&rx_data);
+//参考时钟设置
+SpiPs_write_read1(0x789,0x00,&rx_data);
+SpiPs_write_read1(0x785,0x49,&rx_data);
+SpiPs_write_read1(0x788,0x24,&rx_data);
+usleep(10000);
+SpiPs_write_read1(0x788,0xA4,&rx_data);
+//BBPLL
+SpiPs_write_read1(0x0C0,0x50,&rx_data);
+SpiPs_write_read1(0x0C1,0x50,&rx_data);
+SpiPs_write_read1(0x0C2,0x50,&rx_data);
+SpiPs_write_read1(0x601,0x0F,&rx_data);
+SpiPs_write_read1(0x602,0x21,&rx_data);
+SpiPs_write_read1(0x60D,0x0C,&rx_data);
+SpiPs_write_read1(0x60E,0x66,&rx_data);
+SpiPs_write_read1(0x60F,0x66,&rx_data);
+SpiPs_write_read1(0x610,0x66,&rx_data);
+SpiPs_write_read1(0x611,0x13,&rx_data);
+SpiPs_write_read1(0x612,0x00,&rx_data);
+//ADC
+SpiPs_write_read1(0x70B,0x0E,&rx_data);
+SpiPs_write_read1(0x727,0x0E,&rx_data);
+SpiPs_write_read1(0x743,0x0E,&rx_data);
+SpiPs_write_read1(0x70D,0x3F,&rx_data);
+SpiPs_write_read1(0x729,0x3F,&rx_data);
+SpiPs_write_read1(0x745,0x3F,&rx_data);
+SpiPs_write_read1(0x70E,0x48,&rx_data);
+SpiPs_write_read1(0x72A,0x48,&rx_data);
+SpiPs_write_read1(0x746,0x48,&rx_data);
+SpiPs_write_read1(0x70F,0xA0,&rx_data);
+SpiPs_write_read1(0x72B,0xA0,&rx_data);
+SpiPs_write_read1(0x747,0xA0,&rx_data);
+//通道时钟来源
+SpiPs_write_read1(0x77D,0xC0,&rx_data);
+SpiPs_write_read1(0x775,0x24,&rx_data);
+SpiPs_write_read1(0x6C3,0x00,&rx_data);
+//PLL1
+SpiPs_write_read1(0x620,0x81,&rx_data);
+SpiPs_write_read1(0x61D,0x00,&rx_data);
+SpiPs_write_read1(0xB06,0x00,&rx_data);
+SpiPs_write_read1(0xB07,0x64,&rx_data);
+SpiPs_write_read1(0xB08,0x00,&rx_data);
+SpiPs_write_read1(0xB09,0x00,&rx_data);
+SpiPs_write_read1(0xB0A,0x00,&rx_data);
+SpiPs_write_read1(0x61A,0x0B,&rx_data);
+SpiPs_write_read1(0x61B,0x20,&rx_data);
+SpiPs_write_read1(0x61C,0x13,&rx_data);
+SpiPs_write_read1(0x624,0x11,&rx_data);
+SpiPs_write_read1(0x625,0x11,&rx_data);
+SpiPs_write_read1(0x62A,0x00,&rx_data);
+SpiPs_write_read1(0x61E,0x30,&rx_data);
+SpiPs_write_read1(0x61F,0x08,&rx_data);
+SpiPs_write_read1(0x621,0x4D,&rx_data);
+SpiPs_write_read1(0x622,0x19,&rx_data);
+SpiPs_write_read1(0x627,0x10,&rx_data);
+//Rx通道设置
+SpiPs_write_read1(0x700,0x56,&rx_data);
+SpiPs_write_read1(0x71C,0x56,&rx_data);
+SpiPs_write_read1(0x738,0x56,&rx_data);
+SpiPs_write_read1(0x701,0x02,&rx_data);
+SpiPs_write_read1(0x702,0x35,&rx_data);
+SpiPs_write_read1(0x71D,0x02,&rx_data);
+SpiPs_write_read1(0x71E,0x35,&rx_data);
+SpiPs_write_read1(0x739,0x02,&rx_data);
+SpiPs_write_read1(0x73A,0x35,&rx_data);
+SpiPs_write_read1(0x703,0xF6,&rx_data);
+SpiPs_write_read1(0x71F,0xF6,&rx_data);
+SpiPs_write_read1(0x73B,0xF6,&rx_data);
+SpiPs_write_read1(0x704,0xC8,&rx_data);
+SpiPs_write_read1(0x720,0xC8,&rx_data);
+SpiPs_write_read1(0x73C,0xC8,&rx_data);
+SpiPs_write_read1(0x907,0x1F,&rx_data);
+SpiPs_write_read1(0x705,0xFC,&rx_data);
+SpiPs_write_read1(0x721,0xFC,&rx_data);
+SpiPs_write_read1(0x73D,0xFC,&rx_data);
+SpiPs_write_read1(0x706,0x65,&rx_data);
+SpiPs_write_read1(0x722,0x65,&rx_data);
+SpiPs_write_read1(0x73E,0x65,&rx_data);
+SpiPs_write_read1(0x707,0x91,&rx_data);
+SpiPs_write_read1(0x723,0x91,&rx_data);
+SpiPs_write_read1(0x73F,0x91,&rx_data);
+SpiPs_write_read1(0x708,0x04,&rx_data);
+SpiPs_write_read1(0x724,0x04,&rx_data);
+SpiPs_write_read1(0x740,0x04,&rx_data);
+SpiPs_write_read1(0x709,0x94,&rx_data);
+SpiPs_write_read1(0x725,0x94,&rx_data);
+SpiPs_write_read1(0x741,0x94,&rx_data);
+SpiPs_write_read1(0x70A,0xFC,&rx_data);
+SpiPs_write_read1(0x726,0xFC,&rx_data);
+SpiPs_write_read1(0x742,0xFC,&rx_data);
+SpiPs_write_read1(0x75A,0x83,&rx_data);
+SpiPs_write_read1(0x75B,0xDA,&rx_data);
+usleep(10000);
+SpiPs_write_read1(0x75B,0x9A,&rx_data);
+SpiPs_write_read1(0x75C,0x81,&rx_data);
+SpiPs_write_read1(0x75D,0xF8,&rx_data);
+SpiPs_write_read1(0x75E,0xA7,&rx_data);
+SpiPs_write_read1(0x75F,0x51,&rx_data);
+SpiPs_write_read1(0x760,0xFF,&rx_data);
+SpiPs_write_read1(0x761,0x04,&rx_data);
+SpiPs_write_read1(0x762,0x70,&rx_data);
+SpiPs_write_read1(0x763,0x04,&rx_data);
+SpiPs_write_read1(0x764,0x83,&rx_data);
+SpiPs_write_read1(0x765,0xDA,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x765,0x9A,&rx_data);
+SpiPs_write_read1(0x766,0x81,&rx_data);
+SpiPs_write_read1(0x767,0xF8,&rx_data);
+SpiPs_write_read1(0x768,0xA7,&rx_data);
+SpiPs_write_read1(0x769,0x51,&rx_data);
+SpiPs_write_read1(0x76A,0xFF,&rx_data);
+SpiPs_write_read1(0x76B,0x04,&rx_data);
+SpiPs_write_read1(0x76C,0x70,&rx_data);
+SpiPs_write_read1(0x76D,0x04,&rx_data);
+//Rx滤波器
+SpiPs_write_read1(0x106,0x02,&rx_data);
+//Tx滤波器
+SpiPs_write_read1(0x107,0x00,&rx_data);
+SpiPs_write_read1(0x108,0xD0,&rx_data);
+//Rx NCO
+SpiPs_write_read1(0x11C,0x00,&rx_data);
+SpiPs_write_read1(0xA07,0x00,&rx_data);
+SpiPs_write_read1(0xA08,0x00,&rx_data);
+SpiPs_write_read1(0xA16,0x00,&rx_data);
+SpiPs_write_read1(0xA17,0x00,&rx_data);
+SpiPs_write_read1(0xA18,0x00,&rx_data);
+SpiPs_write_read1(0xA19,0x00,&rx_data);
+SpiPs_write_read1(0xA1A,0x00,&rx_data);
+SpiPs_write_read1(0xA1B,0x00,&rx_data);
+//Tx NCO
+SpiPs_write_read1(0x128,0x10,&rx_data);
+SpiPs_write_read1(0x11B,0x00,&rx_data);
+SpiPs_write_read1(0x11E,0x00,&rx_data);
+SpiPs_write_read1(0x161,0x00,&rx_data);
+SpiPs_write_read1(0x162,0x00,&rx_data);
+SpiPs_write_read1(0x164,0x00,&rx_data);
+SpiPs_write_read1(0x165,0x00,&rx_data);
+SpiPs_write_read1(0x166,0x00,&rx_data);
+SpiPs_write_read1(0x167,0x00,&rx_data);
+SpiPs_write_read1(0x168,0x00,&rx_data);
+SpiPs_write_read1(0x169,0x00,&rx_data);
+//AGC配置
+SpiPs_write_read1(0x900,0x00,&rx_data);
+SpiPs_write_read1(0x901,0x00,&rx_data);
+SpiPs_write_read1(0x903,0x11,&rx_data);
+SpiPs_write_read1(0x908,0x77,&rx_data);
+SpiPs_write_read1(0x909,0x03,&rx_data);
+SpiPs_write_read1(0x90A,0x32,&rx_data);
+SpiPs_write_read1(0x90D,0x00,&rx_data);
+SpiPs_write_read1(0x90E,0x0F,&rx_data);
+SpiPs_write_read1(0x90F,0x65,&rx_data);
+SpiPs_write_read1(0x910,0x32,&rx_data);
+SpiPs_write_read1(0x911,0x00,&rx_data);
+SpiPs_write_read1(0x912,0x0F,&rx_data);
+SpiPs_write_read1(0x913,0x3A,&rx_data);
+SpiPs_write_read1(0x914,0x37,&rx_data);
+SpiPs_write_read1(0x915,0x34,&rx_data);
+SpiPs_write_read1(0x916,0x31,&rx_data);
+//进入休眠模式
+SpiPs_write_read1(0x02E,0x01,&rx_data);
+usleep(1000000);
+//进入校准模式
+SpiPs_write_read1(0x02E,0x03,&rx_data);
+//BBPLL AFC
+SpiPs_write_read1(0x600,0x00,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x600,0x11,&rx_data);
+//PLL1 AFC
+SpiPs_write_read1(0x617,0x00,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x617,0x03,&rx_data);
+//接口配置
+SpiPs_write_read1(0x02E,0x06,&rx_data);
+SpiPs_write_read1(0x003,0x33,&rx_data);
+SpiPs_write_read1(0x200,0x00,&rx_data);
+SpiPs_write_read1(0x201,0x00,&rx_data);
+SpiPs_write_read1(0x202,0x03,&rx_data);
+SpiPs_write_read1(0x209,0x00,&rx_data);
+SpiPs_write_read1(0x780,0x11,&rx_data);
+SpiPs_write_read1(0x781,0x6F,&rx_data);
+SpiPs_write_read1(0x782,0x01,&rx_data);
+SpiPs_write_read1(0x783,0x01,&rx_data);
+SpiPs_write_read1(0x784,0x01,&rx_data);
+//ADC校准
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x70F,0xA0,&rx_data);
+SpiPs_write_read1(0x710,0x83,&rx_data);
+SpiPs_write_read1(0x711,0xF0,&rx_data);
+SpiPs_write_read1(0x72B,0xA0,&rx_data);
+SpiPs_write_read1(0x72C,0x83,&rx_data);
+SpiPs_write_read1(0x72D,0xF0,&rx_data);
+SpiPs_write_read1(0x747,0xA0,&rx_data);
+SpiPs_write_read1(0x748,0x83,&rx_data);
+SpiPs_write_read1(0x749,0xF0,&rx_data);
+SpiPs_write_read1(0x713,0x80,&rx_data);
+SpiPs_write_read1(0x72F,0x80,&rx_data);
+SpiPs_write_read1(0x74B,0x80,&rx_data);
+SpiPs_write_read1(0x70B,0x9E,&rx_data);
+SpiPs_write_read1(0x727,0x9E,&rx_data);
+SpiPs_write_read1(0x743,0x9E,&rx_data);
+SpiPs_write_read1(0x70B,0x9A,&rx_data);
+SpiPs_write_read1(0x727,0x9A,&rx_data);
+SpiPs_write_read1(0x743,0x9A,&rx_data);
+SpiPs_write_read1(0x70B,0x9E,&rx_data);
+SpiPs_write_read1(0x727,0x9E,&rx_data);
+SpiPs_write_read1(0x743,0x9E,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x713,0xC0,&rx_data);
+SpiPs_write_read1(0x72F,0xC0,&rx_data);
+SpiPs_write_read1(0x74B,0xC0,&rx_data);
+//Flash校准
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x715,0x80,&rx_data);
+SpiPs_write_read1(0x731,0x80,&rx_data);
+SpiPs_write_read1(0x74D,0x80,&rx_data);
+SpiPs_write_read1(0x715,0xC0,&rx_data);
+SpiPs_write_read1(0x731,0xC0,&rx_data);
+SpiPs_write_read1(0x74D,0xC0,&rx_data);
+SpiPs_write_read1(0x716,0x40,&rx_data);
+SpiPs_write_read1(0x732,0x40,&rx_data);
+SpiPs_write_read1(0x74E,0x40,&rx_data);
+SpiPs_write_read1(0x70B,0x16,&rx_data);
+SpiPs_write_read1(0x727,0x16,&rx_data);
+SpiPs_write_read1(0x743,0x16,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x715,0x80,&rx_data);
+SpiPs_write_read1(0x731,0x80,&rx_data);
+SpiPs_write_read1(0x74D,0x80,&rx_data);
+SpiPs_write_read1(0x716,0x00,&rx_data);
+SpiPs_write_read1(0x732,0x00,&rx_data);
+SpiPs_write_read1(0x74E,0x00,&rx_data);
+SpiPs_write_read1(0x109,0x11,&rx_data);
+SpiPs_write_read1(0x10A,0x70,&rx_data);
+SpiPs_write_read1(0x11F,0x33,&rx_data);
+usleep(1000);
+SpiPs_write_read2(0x615,0x00,&rx_data);
+temp=rx_data;
+SpiPs_write_read2(0x635,0x00,&rx_data);
+temp=rx_data;
+////配置Tx NCO BIST ON
+//SpiPs_write_read1(0x11B,0x01,&rx_data);
+//SpiPs_write_read1(0x11E,0x01,&rx_data);
+//SpiPs_write_read1(0x161,0x01,&rx_data);
+//SpiPs_write_read1(0x162,0x01,&rx_data);
+////配置Tx NCO频率 1MHz
+//SpiPs_write_read1(0x164,0x05,&rx_data);
+//SpiPs_write_read1(0x165,0x55,&rx_data);
+//SpiPs_write_read1(0x166,0x55,&rx_data);
+//SpiPs_write_read1(0x167,0x55,&rx_data);
+//SpiPs_write_read1(0x168,0x55,&rx_data);
+//SpiPs_write_read1(0x169,0x55,&rx_data);
+}

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_HOP/cx9261a_151_config.c

@@ -0,0 +1,708 @@
+/*
+ * cx9261_config.c
+ *
+ *  Created on: 2023年10月16日
+ *      Author: cxlab
+ */
+
+#include "xilinx_io.h"
+#include "sleep.h"
+void cx9261a_151_config(void){
+u8 rx_data;
+int temp;
+
+//setPin(pin,value)
+GpioSetPinDir(0,0x01);
+GpioWritePin(0,1);
+GpioSetPinDir(32,0x01);
+GpioWritePin(32,1);
+GpioSetPinDir(33,0x01);
+GpioWritePin(33,1);
+GpioSetPinDir(34,0x01);
+GpioWritePin(34,0);
+GpioSetPinDir(35,0x01); //tx:0-rx:1
+GpioWritePin(35,1); //tx:0-rx:1
+GpioSetPinDir(36,0x01); //fdd:0-tdd:1
+GpioWritePin(36,1); //fdd:0-tdd:1
+GpioSetPinDir(37,0x01); //1r1t:0-2r2t:1
+GpioWritePin(37,0); //1r1t:0-2r2t:1
+GpioSetPinDir(38,0x01); //dualport:0-singleport:1
+GpioWritePin(38,1); //dualport:0-singleport:1
+GpioSetPinDir(39,0x01);
+GpioWritePin(39,1);
+GpioSetPinDir(40,0x01);
+GpioWritePin(40,1);
+//三个通道共同控制
+SpiPs_write_read1(0x000,0x02,&rx_data);
+//电源管理自定义
+//断电模式
+SpiPs_write_read1(0x031,0x00,&rx_data);
+SpiPs_write_read1(0x032,0x7F,&rx_data);
+SpiPs_write_read1(0x033,0xFF,&rx_data);
+SpiPs_write_read1(0x034,0xFF,&rx_data);
+//休眠模式
+SpiPs_write_read1(0x035,0x00,&rx_data);
+SpiPs_write_read1(0x036,0x3D,&rx_data);
+SpiPs_write_read1(0x037,0xFF,&rx_data);
+SpiPs_write_read1(0x038,0xEB,&rx_data);
+//警戒模式
+SpiPs_write_read1(0x039,0x00,&rx_data);
+SpiPs_write_read1(0x03A,0x3D,&rx_data);
+SpiPs_write_read1(0x03B,0xFF,&rx_data);
+SpiPs_write_read1(0x03C,0xE0,&rx_data);
+//校准模式
+SpiPs_write_read1(0x03D,0x1B,&rx_data);
+SpiPs_write_read1(0x03E,0x39,&rx_data);
+SpiPs_write_read1(0x03F,0x27,&rx_data);
+SpiPs_write_read1(0x040,0xE0,&rx_data);
+//接收模式
+SpiPs_write_read1(0x041,0x03,&rx_data);
+SpiPs_write_read1(0x042,0x3D,&rx_data);
+SpiPs_write_read1(0x043,0xE7,&rx_data);
+SpiPs_write_read1(0x044,0xF8,&rx_data);
+//发射模式
+SpiPs_write_read1(0x045,0x18,&rx_data);
+SpiPs_write_read1(0x046,0x3D,&rx_data);
+SpiPs_write_read1(0x047,0x3F,&rx_data);
+SpiPs_write_read1(0x048,0xF8,&rx_data);
+//FDD模式
+SpiPs_write_read1(0x049,0x1B,&rx_data);
+SpiPs_write_read1(0x04A,0x3D,&rx_data);
+SpiPs_write_read1(0x04B,0x27,&rx_data);
+SpiPs_write_read1(0x04C,0xE0,&rx_data);
+//观测模式
+SpiPs_write_read1(0x04D,0x04,&rx_data);
+SpiPs_write_read1(0x04E,0x3D,&rx_data);
+SpiPs_write_read1(0x04F,0xD9,&rx_data);
+SpiPs_write_read1(0x050,0xFE,&rx_data);
+//带隙基准
+SpiPs_write_read1(0x773,0x53,&rx_data);
+SpiPs_write_read1(0x774,0x86,&rx_data);
+//参考时钟设置
+SpiPs_write_read1(0x789,0x00,&rx_data);
+SpiPs_write_read1(0x785,0x49,&rx_data);
+SpiPs_write_read1(0x788,0x24,&rx_data);
+usleep(10000);
+SpiPs_write_read1(0x788,0xA4,&rx_data);
+//BBPLL
+SpiPs_write_read1(0x0C0,0x50,&rx_data);
+SpiPs_write_read1(0x0C1,0x50,&rx_data);
+SpiPs_write_read1(0x0C2,0x50,&rx_data);
+SpiPs_write_read1(0x601,0x0F,&rx_data);
+SpiPs_write_read1(0x602,0x21,&rx_data);
+SpiPs_write_read1(0x60D,0x0C,&rx_data);
+SpiPs_write_read1(0x60E,0x66,&rx_data);
+SpiPs_write_read1(0x60F,0x66,&rx_data);
+SpiPs_write_read1(0x610,0x66,&rx_data);
+SpiPs_write_read1(0x611,0x13,&rx_data);
+SpiPs_write_read1(0x612,0x00,&rx_data);
+//ADC
+SpiPs_write_read1(0x70B,0x0E,&rx_data);
+SpiPs_write_read1(0x727,0x0E,&rx_data);
+SpiPs_write_read1(0x743,0x0E,&rx_data);
+SpiPs_write_read1(0x70D,0x3F,&rx_data);
+SpiPs_write_read1(0x729,0x3F,&rx_data);
+SpiPs_write_read1(0x745,0x3F,&rx_data);
+SpiPs_write_read1(0x70E,0x48,&rx_data);
+SpiPs_write_read1(0x72A,0x48,&rx_data);
+SpiPs_write_read1(0x746,0x48,&rx_data);
+SpiPs_write_read1(0x70F,0xA0,&rx_data);
+SpiPs_write_read1(0x72B,0xA0,&rx_data);
+SpiPs_write_read1(0x747,0xA0,&rx_data);
+//通道时钟来源
+SpiPs_write_read1(0x77D,0xCF,&rx_data);
+SpiPs_write_read1(0x775,0x24,&rx_data);
+SpiPs_write_read1(0x6C3,0x00,&rx_data);
+//PLL1
+SpiPs_write_read1(0x620,0x81,&rx_data);
+SpiPs_write_read1(0x61D,0x07,&rx_data);
+SpiPs_write_read1(0xB06,0x00,&rx_data);
+SpiPs_write_read1(0xB07,0x64,&rx_data);
+SpiPs_write_read1(0xB08,0x00,&rx_data);
+SpiPs_write_read1(0xB09,0x00,&rx_data);
+SpiPs_write_read1(0xB0A,0x00,&rx_data);
+SpiPs_write_read1(0x61A,0x0B,&rx_data);
+SpiPs_write_read1(0x61B,0x20,&rx_data);
+SpiPs_write_read1(0x61C,0x13,&rx_data);
+SpiPs_write_read1(0x624,0x11,&rx_data);
+SpiPs_write_read1(0x625,0x11,&rx_data);
+SpiPs_write_read1(0x62A,0x00,&rx_data);
+SpiPs_write_read1(0x61E,0x30,&rx_data);
+SpiPs_write_read1(0x61F,0x08,&rx_data);
+SpiPs_write_read1(0x621,0x4D,&rx_data);
+SpiPs_write_read1(0x622,0x19,&rx_data);
+SpiPs_write_read1(0x627,0x10,&rx_data);
+//PLL2
+SpiPs_write_read1(0x642,0x91,&rx_data);
+SpiPs_write_read1(0x63F,0x36,&rx_data);
+SpiPs_write_read1(0xB14,0x00,&rx_data);
+SpiPs_write_read1(0xB15,0x70,&rx_data);
+SpiPs_write_read1(0xB16,0x00,&rx_data);
+SpiPs_write_read1(0xB17,0x00,&rx_data);
+SpiPs_write_read1(0xB18,0x00,&rx_data);
+SpiPs_write_read1(0x63C,0x0C,&rx_data);
+SpiPs_write_read1(0x63D,0x20,&rx_data);
+SpiPs_write_read1(0x63E,0x0C,&rx_data);
+SpiPs_write_read1(0x646,0x11,&rx_data);
+SpiPs_write_read1(0x647,0x11,&rx_data);
+SpiPs_write_read1(0x64C,0x00,&rx_data);
+SpiPs_write_read1(0x640,0x30,&rx_data);
+SpiPs_write_read1(0x641,0x08,&rx_data);
+SpiPs_write_read1(0x643,0x4D,&rx_data);
+SpiPs_write_read1(0x644,0x19,&rx_data);
+SpiPs_write_read1(0x649,0x10,&rx_data);
+//PLL3
+SpiPs_write_read1(0x664,0x91,&rx_data);
+SpiPs_write_read1(0x661,0x36,&rx_data);
+SpiPs_write_read1(0xB22,0x00,&rx_data);
+SpiPs_write_read1(0xB23,0x80,&rx_data);
+SpiPs_write_read1(0xB24,0x00,&rx_data);
+SpiPs_write_read1(0xB25,0x00,&rx_data);
+SpiPs_write_read1(0xB26,0x00,&rx_data);
+SpiPs_write_read1(0x65E,0x0D,&rx_data);
+SpiPs_write_read1(0x65F,0x20,&rx_data);
+SpiPs_write_read1(0x660,0x0F,&rx_data);
+SpiPs_write_read1(0x668,0x11,&rx_data);
+SpiPs_write_read1(0x669,0x11,&rx_data);
+SpiPs_write_read1(0x66E,0x00,&rx_data);
+SpiPs_write_read1(0x662,0x30,&rx_data);
+SpiPs_write_read1(0x663,0x08,&rx_data);
+SpiPs_write_read1(0x665,0x4D,&rx_data);
+SpiPs_write_read1(0x666,0x19,&rx_data);
+SpiPs_write_read1(0x66B,0x10,&rx_data);
+//PLL4
+SpiPs_write_read1(0x686,0x81,&rx_data);
+SpiPs_write_read1(0x683,0x37,&rx_data);
+SpiPs_write_read1(0xB30,0x00,&rx_data);
+SpiPs_write_read1(0xB31,0x48,&rx_data);
+SpiPs_write_read1(0xB32,0x00,&rx_data);
+SpiPs_write_read1(0xB33,0x00,&rx_data);
+SpiPs_write_read1(0xB34,0x00,&rx_data);
+SpiPs_write_read1(0x680,0x0C,&rx_data);
+SpiPs_write_read1(0x681,0x20,&rx_data);
+SpiPs_write_read1(0x682,0x11,&rx_data);
+SpiPs_write_read1(0x68A,0x11,&rx_data);
+SpiPs_write_read1(0x68B,0x11,&rx_data);
+SpiPs_write_read1(0x690,0x00,&rx_data);
+SpiPs_write_read1(0x684,0x30,&rx_data);
+SpiPs_write_read1(0x685,0x08,&rx_data);
+SpiPs_write_read1(0x687,0x4D,&rx_data);
+SpiPs_write_read1(0x688,0x19,&rx_data);
+SpiPs_write_read1(0x68D,0x10,&rx_data);
+//PLL5
+SpiPs_write_read1(0x6A8,0x81,&rx_data);
+SpiPs_write_read1(0x6A5,0x37,&rx_data);
+SpiPs_write_read1(0xB3E,0x00,&rx_data);
+SpiPs_write_read1(0xB3F,0x50,&rx_data);
+SpiPs_write_read1(0xB40,0x00,&rx_data);
+SpiPs_write_read1(0xB41,0x00,&rx_data);
+SpiPs_write_read1(0xB42,0x00,&rx_data);
+SpiPs_write_read1(0x6A2,0x0C,&rx_data);
+SpiPs_write_read1(0x6A3,0x20,&rx_data);
+SpiPs_write_read1(0x6A4,0x11,&rx_data);
+SpiPs_write_read1(0x6AC,0x11,&rx_data);
+SpiPs_write_read1(0x6AD,0x11,&rx_data);
+SpiPs_write_read1(0x6B2,0x00,&rx_data);
+SpiPs_write_read1(0x6A6,0x30,&rx_data);
+SpiPs_write_read1(0x6A7,0x08,&rx_data);
+SpiPs_write_read1(0x6A9,0x4D,&rx_data);
+SpiPs_write_read1(0x6AA,0x19,&rx_data);
+SpiPs_write_read1(0x6AF,0x10,&rx_data);
+//Rx通道设置
+SpiPs_write_read1(0x700,0x56,&rx_data);
+SpiPs_write_read1(0x71C,0x56,&rx_data);
+SpiPs_write_read1(0x738,0x56,&rx_data);
+SpiPs_write_read1(0x701,0x02,&rx_data);
+SpiPs_write_read1(0x702,0x35,&rx_data);
+SpiPs_write_read1(0x71D,0x02,&rx_data);
+SpiPs_write_read1(0x71E,0x35,&rx_data);
+SpiPs_write_read1(0x739,0x02,&rx_data);
+SpiPs_write_read1(0x73A,0x35,&rx_data);
+SpiPs_write_read1(0x703,0xF6,&rx_data);
+SpiPs_write_read1(0x71F,0xF6,&rx_data);
+SpiPs_write_read1(0x73B,0xF6,&rx_data);
+SpiPs_write_read1(0x704,0xC8,&rx_data);
+SpiPs_write_read1(0x720,0xC8,&rx_data);
+SpiPs_write_read1(0x73C,0xC8,&rx_data);
+SpiPs_write_read1(0x907,0x1F,&rx_data);
+SpiPs_write_read1(0x705,0xFC,&rx_data);
+SpiPs_write_read1(0x721,0xFC,&rx_data);
+SpiPs_write_read1(0x73D,0xFC,&rx_data);
+SpiPs_write_read1(0x706,0x65,&rx_data);
+SpiPs_write_read1(0x722,0x65,&rx_data);
+SpiPs_write_read1(0x73E,0x65,&rx_data);
+SpiPs_write_read1(0x707,0x91,&rx_data);
+SpiPs_write_read1(0x723,0x91,&rx_data);
+SpiPs_write_read1(0x73F,0x91,&rx_data);
+SpiPs_write_read1(0x708,0x04,&rx_data);
+SpiPs_write_read1(0x724,0x04,&rx_data);
+SpiPs_write_read1(0x740,0x04,&rx_data);
+SpiPs_write_read1(0x709,0x94,&rx_data);
+SpiPs_write_read1(0x725,0x94,&rx_data);
+SpiPs_write_read1(0x741,0x94,&rx_data);
+SpiPs_write_read1(0x70A,0xFC,&rx_data);
+SpiPs_write_read1(0x726,0xFC,&rx_data);
+SpiPs_write_read1(0x742,0xFC,&rx_data);
+SpiPs_write_read1(0x75A,0x83,&rx_data);
+SpiPs_write_read1(0x75B,0xDA,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x75B,0x9A,&rx_data);
+SpiPs_write_read1(0x75C,0x81,&rx_data);
+SpiPs_write_read1(0x75D,0xF8,&rx_data);
+SpiPs_write_read1(0x75E,0xA7,&rx_data);
+SpiPs_write_read1(0x75F,0x50,&rx_data);
+SpiPs_write_read1(0x760,0xFF,&rx_data);
+SpiPs_write_read1(0x761,0x07,&rx_data);
+SpiPs_write_read1(0x762,0x6C,&rx_data);
+SpiPs_write_read1(0x763,0x04,&rx_data);
+SpiPs_write_read1(0x764,0x83,&rx_data);
+SpiPs_write_read1(0x765,0xDA,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x765,0x9A,&rx_data);
+SpiPs_write_read1(0x766,0x81,&rx_data);
+SpiPs_write_read1(0x767,0xF8,&rx_data);
+SpiPs_write_read1(0x768,0xA7,&rx_data);
+SpiPs_write_read1(0x769,0x50,&rx_data);
+SpiPs_write_read1(0x76A,0xFF,&rx_data);
+SpiPs_write_read1(0x76B,0x07,&rx_data);
+SpiPs_write_read1(0x76C,0x6C,&rx_data);
+SpiPs_write_read1(0x76D,0x04,&rx_data);
+//Rx滤波器
+SpiPs_write_read1(0x106,0x02,&rx_data);
+//Tx滤波器
+SpiPs_write_read1(0x107,0x00,&rx_data);
+SpiPs_write_read1(0x108,0xD0,&rx_data);
+//Rx NCO
+SpiPs_write_read1(0x11C,0x00,&rx_data);
+SpiPs_write_read1(0xA07,0x00,&rx_data);
+SpiPs_write_read1(0xA08,0x00,&rx_data);
+SpiPs_write_read1(0xA16,0x00,&rx_data);
+SpiPs_write_read1(0xA17,0x00,&rx_data);
+SpiPs_write_read1(0xA18,0x00,&rx_data);
+SpiPs_write_read1(0xA19,0x00,&rx_data);
+SpiPs_write_read1(0xA1A,0x00,&rx_data);
+SpiPs_write_read1(0xA1B,0x00,&rx_data);
+//Tx NCO
+SpiPs_write_read1(0x128,0x10,&rx_data);
+SpiPs_write_read1(0x11B,0x01,&rx_data);
+SpiPs_write_read1(0x11E,0x01,&rx_data);
+SpiPs_write_read1(0x161,0x01,&rx_data);
+SpiPs_write_read1(0x162,0x01,&rx_data);
+SpiPs_write_read1(0x164,0x05,&rx_data);
+SpiPs_write_read1(0x165,0x55,&rx_data);
+SpiPs_write_read1(0x166,0x55,&rx_data);
+SpiPs_write_read1(0x167,0x55,&rx_data);
+SpiPs_write_read1(0x168,0x55,&rx_data);
+SpiPs_write_read1(0x169,0x55,&rx_data);
+//AGC配置
+SpiPs_write_read1(0x900,0x00,&rx_data);
+SpiPs_write_read1(0x901,0x00,&rx_data);
+SpiPs_write_read1(0x903,0x11,&rx_data);
+SpiPs_write_read1(0x908,0x77,&rx_data);
+SpiPs_write_read1(0x909,0x03,&rx_data);
+SpiPs_write_read1(0x90A,0x32,&rx_data);
+SpiPs_write_read1(0x90D,0x00,&rx_data);
+SpiPs_write_read1(0x90E,0x0F,&rx_data);
+SpiPs_write_read1(0x90F,0x65,&rx_data);
+SpiPs_write_read1(0x910,0x32,&rx_data);
+SpiPs_write_read1(0x911,0x00,&rx_data);
+SpiPs_write_read1(0x912,0x0F,&rx_data);
+SpiPs_write_read1(0x913,0x3A,&rx_data);
+SpiPs_write_read1(0x914,0x37,&rx_data);
+SpiPs_write_read1(0x915,0x34,&rx_data);
+SpiPs_write_read1(0x916,0x31,&rx_data);
+//进入休眠模式
+SpiPs_write_read1(0x02E,0x01,&rx_data);
+usleep(1000000);
+//进入校准模式
+SpiPs_write_read1(0x02E,0x03,&rx_data);
+usleep(100000);
+//BBPLL AFC
+SpiPs_write_read1(0x600,0x00,&rx_data);
+SpiPs_write_read1(0x600,0x11,&rx_data);
+usleep(50);
+//PLL1 AFC
+while(temp != 48)
+{
+SpiPs_write_read1(0x617,0x00,&rx_data);
+SpiPs_write_read1(0x617,0x03,&rx_data);
+usleep(100);
+SpiPs_write_read2(0x635,0x00,&rx_data);
+temp=rx_data;
+}
+//接口配置
+SpiPs_write_read1(0x02E,0x06,&rx_data);
+SpiPs_write_read1(0x003,0x33,&rx_data);
+SpiPs_write_read1(0x200,0x00,&rx_data);
+SpiPs_write_read1(0x201,0x00,&rx_data);
+SpiPs_write_read1(0x202,0x03,&rx_data);
+SpiPs_write_read1(0x208,0x00,&rx_data);
+SpiPs_write_read1(0x209,0x00,&rx_data);
+SpiPs_write_read1(0x780,0x11,&rx_data);
+SpiPs_write_read1(0x781,0x6F,&rx_data);
+SpiPs_write_read1(0x782,0x01,&rx_data);
+SpiPs_write_read1(0x783,0x01,&rx_data);
+SpiPs_write_read1(0x784,0x01,&rx_data);
+//ADC校准
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x70F,0xA0,&rx_data);
+SpiPs_write_read1(0x710,0x83,&rx_data);
+SpiPs_write_read1(0x711,0xF0,&rx_data);
+SpiPs_write_read1(0x72B,0xA0,&rx_data);
+SpiPs_write_read1(0x72C,0x83,&rx_data);
+SpiPs_write_read1(0x72D,0xF0,&rx_data);
+SpiPs_write_read1(0x747,0xA0,&rx_data);
+SpiPs_write_read1(0x748,0x83,&rx_data);
+SpiPs_write_read1(0x749,0xF0,&rx_data);
+SpiPs_write_read1(0x713,0x80,&rx_data);
+SpiPs_write_read1(0x72F,0x80,&rx_data);
+SpiPs_write_read1(0x74B,0x80,&rx_data);
+SpiPs_write_read1(0x70B,0x9E,&rx_data);
+SpiPs_write_read1(0x727,0x9E,&rx_data);
+SpiPs_write_read1(0x743,0x9E,&rx_data);
+SpiPs_write_read1(0x70B,0x9A,&rx_data);
+SpiPs_write_read1(0x727,0x9A,&rx_data);
+SpiPs_write_read1(0x743,0x9A,&rx_data);
+SpiPs_write_read1(0x70B,0x9E,&rx_data);
+SpiPs_write_read1(0x727,0x9E,&rx_data);
+SpiPs_write_read1(0x743,0x9E,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x713,0xC0,&rx_data);
+SpiPs_write_read1(0x72F,0xC0,&rx_data);
+SpiPs_write_read1(0x74B,0xC0,&rx_data);
+//Flash校准
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x715,0x80,&rx_data);
+SpiPs_write_read1(0x731,0x80,&rx_data);
+SpiPs_write_read1(0x74D,0x80,&rx_data);
+SpiPs_write_read1(0x715,0xC0,&rx_data);
+SpiPs_write_read1(0x731,0xC0,&rx_data);
+SpiPs_write_read1(0x74D,0xC0,&rx_data);
+SpiPs_write_read1(0x716,0x40,&rx_data);
+SpiPs_write_read1(0x732,0x40,&rx_data);
+SpiPs_write_read1(0x74E,0x40,&rx_data);
+SpiPs_write_read1(0x70B,0x16,&rx_data);
+SpiPs_write_read1(0x727,0x16,&rx_data);
+SpiPs_write_read1(0x743,0x16,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x715,0x80,&rx_data);
+SpiPs_write_read1(0x731,0x80,&rx_data);
+SpiPs_write_read1(0x74D,0x80,&rx_data);
+SpiPs_write_read1(0x716,0x00,&rx_data);
+SpiPs_write_read1(0x732,0x00,&rx_data);
+SpiPs_write_read1(0x74E,0x00,&rx_data);
+SpiPs_write_read1(0x109,0x11,&rx_data);
+SpiPs_write_read1(0x10A,0x70,&rx_data);
+SpiPs_write_read1(0x11F,0x33,&rx_data);
+//QEC校准
+//Rx TST Calibration
+SpiPs_write_read1(0x000,0x12,&rx_data);
+SpiPs_write_read1(0x109,0x00,&rx_data);
+SpiPs_write_read1(0x77E,0x50,&rx_data);
+SpiPs_write_read1(0x14E,0x00,&rx_data);
+// 修改校准模式电源管理
+SpiPs_write_read1(0x03D,0x09,&rx_data);
+SpiPs_write_read1(0x03E,0x39,&rx_data);
+SpiPs_write_read1(0x03F,0xB6,&rx_data);
+SpiPs_write_read1(0x040,0x78,&rx_data);
+//修改电源模式
+SpiPs_write_read1(0x02E,0x03,&rx_data);
+//Calibration PLL Source
+// 修改Pll来源
+SpiPs_write_read1(0x77D,0x90,&rx_data);
+SpiPs_write_read1(0x6C3,0x05,&rx_data);
+SpiPs_write_read1(0x775,0x24,&rx_data);
+//修改Pll4频率
+//PLL4
+SpiPs_write_read1(0x686,0x81,&rx_data);
+SpiPs_write_read1(0x683,0x07,&rx_data);
+SpiPs_write_read1(0xB30,0x00,&rx_data);
+SpiPs_write_read1(0xB31,0x63,&rx_data);
+SpiPs_write_read1(0xB32,0xEB,&rx_data);
+SpiPs_write_read1(0xB33,0x85,&rx_data);
+SpiPs_write_read1(0xB34,0x1E,&rx_data);
+SpiPs_write_read1(0x680,0x0B,&rx_data);
+SpiPs_write_read1(0x681,0x20,&rx_data);
+SpiPs_write_read1(0x682,0x13,&rx_data);
+SpiPs_write_read1(0x68A,0x11,&rx_data);
+SpiPs_write_read1(0x68B,0x11,&rx_data);
+SpiPs_write_read1(0x690,0x0B,&rx_data);
+SpiPs_write_read1(0x684,0x30,&rx_data);
+SpiPs_write_read1(0x685,0x08,&rx_data);
+SpiPs_write_read1(0x687,0x4D,&rx_data);
+SpiPs_write_read1(0x688,0x19,&rx_data);
+SpiPs_write_read1(0x68D,0x10,&rx_data);
+//PLL4 AFC
+while(temp != 48)
+{
+SpiPs_write_read1(0x67D,0x00,&rx_data);
+SpiPs_write_read1(0x67D,0x03,&rx_data);
+usleep(100);
+SpiPs_write_read2(0x69B,0x00,&rx_data);
+temp=rx_data;
+}
+SpiPs_write_read1(0x02A,0x00,&rx_data);
+SpiPs_write_read1(0x121,0x00,&rx_data);
+SpiPs_write_read1(0x11F,0x73,&rx_data);
+SpiPs_write_read1(0x124,0xFF,&rx_data);
+SpiPs_write_read1(0x120,0x00,&rx_data);
+SpiPs_write_read1(0x122,0x03,&rx_data);
+SpiPs_write_read1(0x126,0x01,&rx_data);
+SpiPs_write_read1(0x02A,0x12,&rx_data);
+
+SpiPs_write_read2(0x14D,0x00,&rx_data);
+temp=rx_data & 0x10;
+while(temp != 16){
+SpiPs_write_read2(0x14D,0x00,&rx_data);
+temp=rx_data & 0x10;
+usleep(100000);
+}
+
+SpiPs_write_read1(0x77E,0x00,&rx_data);
+SpiPs_write_read1(0x775,0x24,&rx_data);
+SpiPs_write_read1(0x77D,0xCF,&rx_data);
+SpiPs_write_read1(0x6C3,0x00,&rx_data);
+//Rx TST Calibration
+SpiPs_write_read1(0x000,0x22,&rx_data);
+SpiPs_write_read1(0x109,0x00,&rx_data);
+SpiPs_write_read1(0x77E,0x0A,&rx_data);
+SpiPs_write_read1(0x14E,0x00,&rx_data);
+// 修改校准模式电源管理
+SpiPs_write_read1(0x03D,0x12,&rx_data);
+SpiPs_write_read1(0x03E,0x39,&rx_data);
+SpiPs_write_read1(0x03F,0x6E,&rx_data);
+SpiPs_write_read1(0x040,0x78,&rx_data);
+//修改电源模式
+SpiPs_write_read1(0x02E,0x03,&rx_data);
+//Calibration PLL Source
+// 修改Pll来源
+SpiPs_write_read1(0x77D,0x60,&rx_data);
+SpiPs_write_read1(0x6C3,0x0A,&rx_data);
+SpiPs_write_read1(0x775,0x24,&rx_data);
+//修改Pll4频率
+//PLL4
+SpiPs_write_read1(0x686,0x81,&rx_data);
+SpiPs_write_read1(0x683,0x07,&rx_data);
+SpiPs_write_read1(0xB30,0x00,&rx_data);
+SpiPs_write_read1(0xB31,0x63,&rx_data);
+SpiPs_write_read1(0xB32,0xEB,&rx_data);
+SpiPs_write_read1(0xB33,0x85,&rx_data);
+SpiPs_write_read1(0xB34,0x1E,&rx_data);
+SpiPs_write_read1(0x680,0x0B,&rx_data);
+SpiPs_write_read1(0x681,0x20,&rx_data);
+SpiPs_write_read1(0x682,0x13,&rx_data);
+SpiPs_write_read1(0x68A,0x11,&rx_data);
+SpiPs_write_read1(0x68B,0x11,&rx_data);
+SpiPs_write_read1(0x690,0x0B,&rx_data);
+SpiPs_write_read1(0x684,0x30,&rx_data);
+SpiPs_write_read1(0x685,0x08,&rx_data);
+SpiPs_write_read1(0x687,0x4D,&rx_data);
+SpiPs_write_read1(0x688,0x19,&rx_data);
+SpiPs_write_read1(0x68D,0x10,&rx_data);
+//PLL4 AFC
+while(temp != 48)
+{
+SpiPs_write_read1(0x67D,0x00,&rx_data);
+SpiPs_write_read1(0x67D,0x03,&rx_data);
+usleep(100);
+SpiPs_write_read2(0x69B,0x00,&rx_data);
+temp=rx_data;
+}
+SpiPs_write_read1(0x02B,0x00,&rx_data);
+SpiPs_write_read1(0x121,0x00,&rx_data);
+SpiPs_write_read1(0x11F,0x73,&rx_data);
+SpiPs_write_read1(0x124,0xFF,&rx_data);
+SpiPs_write_read1(0x120,0x00,&rx_data);
+SpiPs_write_read1(0x122,0x03,&rx_data);
+SpiPs_write_read1(0x126,0x01,&rx_data);
+SpiPs_write_read1(0x02B,0x12,&rx_data);
+
+SpiPs_write_read2(0x14D,0x00,&rx_data);
+temp=rx_data & 0x10;
+while(temp != 16){
+SpiPs_write_read2(0x14D,0x00,&rx_data);
+temp=rx_data & 0x10;
+usleep(100000);
+}
+
+SpiPs_write_read1(0x77E,0x00,&rx_data);
+SpiPs_write_read1(0x775,0x24,&rx_data);
+SpiPs_write_read1(0x77D,0xCF,&rx_data);
+SpiPs_write_read1(0x6C3,0x00,&rx_data);
+SpiPs_write_read1(0x02C,0x00,&rx_data);
+SpiPs_write_read1(0x02B,0x00,&rx_data);
+SpiPs_write_read1(0x02A,0x00,&rx_data);
+//恢复校准前设置
+SpiPs_write_read1(0x000,0x02,&rx_data);
+SpiPs_write_read1(0x02E,0x06,&rx_data);
+SpiPs_write_read1(0x03D,0x1B,&rx_data);
+SpiPs_write_read1(0x03E,0x39,&rx_data);
+SpiPs_write_read1(0x03F,0x27,&rx_data);
+SpiPs_write_read1(0x040,0xF8,&rx_data);
+SpiPs_write_read1(0x109,0x11,&rx_data);
+SpiPs_write_read1(0x10A,0x70,&rx_data);
+SpiPs_write_read1(0x11B,0x01,&rx_data);
+SpiPs_write_read1(0x11E,0x01,&rx_data);
+SpiPs_write_read1(0x11F,0x33,&rx_data);
+SpiPs_write_read1(0x128,0x10,&rx_data);
+SpiPs_write_read1(0x161,0x01,&rx_data);
+SpiPs_write_read1(0x162,0x01,&rx_data);
+SpiPs_write_read1(0x164,0x05,&rx_data);
+SpiPs_write_read1(0x165,0x55,&rx_data);
+SpiPs_write_read1(0x166,0x55,&rx_data);
+SpiPs_write_read1(0x167,0x55,&rx_data);
+SpiPs_write_read1(0x168,0x55,&rx_data);
+SpiPs_write_read1(0x169,0x55,&rx_data);
+SpiPs_write_read1(0xA07,0x00,&rx_data);
+SpiPs_write_read1(0xA08,0x00,&rx_data);
+SpiPs_write_read1(0xA16,0x00,&rx_data);
+SpiPs_write_read1(0xA17,0x00,&rx_data);
+SpiPs_write_read1(0xA18,0x00,&rx_data);
+SpiPs_write_read1(0xA19,0x00,&rx_data);
+SpiPs_write_read1(0xA1A,0x00,&rx_data);
+SpiPs_write_read1(0xA1B,0x00,&rx_data);
+SpiPs_write_read1(0xA1C,0x00,&rx_data);
+SpiPs_write_read1(0xA2D,0x00,&rx_data);
+// TX二分法校准
+// 修改校准模式电源管理
+SpiPs_write_read1(0x03D,0x1B,&rx_data);
+SpiPs_write_read1(0x03E,0x39,&rx_data);
+SpiPs_write_read1(0x03F,0x27,&rx_data);
+SpiPs_write_read1(0x040,0xF8,&rx_data);
+//修改电源模式
+SpiPs_write_read1(0x02E,0x03,&rx_data);
+SpiPs_write_read1(0x128,0x11,&rx_data);
+SpiPs_write_read1(0x11E,0x01,&rx_data);
+SpiPs_write_read1(0x77E,0x24,&rx_data);
+SpiPs_write_read1(0x11F,0x01,&rx_data);
+SpiPs_write_read1(0x121,0x02,&rx_data);
+SpiPs_write_read1(0x11B,0x01,&rx_data);
+SpiPs_write_read1(0x161,0x01,&rx_data);
+SpiPs_write_read1(0x162,0x01,&rx_data);
+SpiPs_write_read1(0x163,0x00,&rx_data);
+SpiPs_write_read1(0x164,0x05,&rx_data);
+SpiPs_write_read1(0x165,0x55,&rx_data);
+SpiPs_write_read1(0x166,0x55,&rx_data);
+SpiPs_write_read1(0x167,0x55,&rx_data);
+SpiPs_write_read1(0x168,0x55,&rx_data);
+SpiPs_write_read1(0x169,0x55,&rx_data);
+SpiPs_write_read1(0xA2D,0x02,&rx_data);
+SpiPs_write_read1(0xA07,0x00,&rx_data);
+SpiPs_write_read1(0xA08,0x0F,&rx_data);
+SpiPs_write_read1(0xA1C,0x01,&rx_data);
+SpiPs_write_read1(0xA16,0x2A,&rx_data);
+SpiPs_write_read1(0xA17,0xAA,&rx_data);
+SpiPs_write_read1(0xA18,0xAA,&rx_data);
+SpiPs_write_read1(0xA19,0xAA,&rx_data);
+SpiPs_write_read1(0xA1A,0xAA,&rx_data);
+SpiPs_write_read1(0xA1B,0xAA,&rx_data);
+SpiPs_write_read1(0x186,0x01,&rx_data);
+SpiPs_write_read1(0x763,0x34,&rx_data);
+SpiPs_write_read1(0x76D,0x34,&rx_data);
+SpiPs_write_read1(0x101,0xEF,&rx_data);
+SpiPs_write_read1(0x101,0xFF,&rx_data);
+SpiPs_write_read1(0x800,0x00,&rx_data);
+SpiPs_write_read1(0x81A,0xF7,&rx_data);
+SpiPs_write_read1(0x81B,0x34,&rx_data);
+SpiPs_write_read1(0x81C,0x33,&rx_data);
+SpiPs_write_read1(0x81D,0x12,&rx_data);
+SpiPs_write_read1(0x81E,0x00,&rx_data);
+SpiPs_write_read1(0x81F,0xFF,&rx_data);
+SpiPs_write_read1(0x820,0x00,&rx_data);
+SpiPs_write_read1(0x821,0xFF,&rx_data);
+SpiPs_write_read1(0x800,0x80,&rx_data);
+SpiPs_write_read1(0x800,0x81,&rx_data);
+//最少0.1s
+usleep(100000);
+SpiPs_write_read1(0x77E,0x00,&rx_data);
+SpiPs_write_read1(0x77E,0x24,&rx_data);
+SpiPs_write_read1(0x11F,0x03,&rx_data);
+SpiPs_write_read1(0x121,0x02,&rx_data);
+SpiPs_write_read1(0x11B,0x01,&rx_data);
+SpiPs_write_read1(0x11E,0x01,&rx_data);
+SpiPs_write_read1(0x161,0x01,&rx_data);
+SpiPs_write_read1(0x162,0x01,&rx_data);
+SpiPs_write_read1(0x164,0x05,&rx_data);
+SpiPs_write_read1(0x165,0x55,&rx_data);
+SpiPs_write_read1(0x166,0x55,&rx_data);
+SpiPs_write_read1(0x167,0x55,&rx_data);
+SpiPs_write_read1(0x168,0x55,&rx_data);
+SpiPs_write_read1(0x169,0x55,&rx_data);
+SpiPs_write_read1(0xA2D,0x02,&rx_data);
+SpiPs_write_read1(0xA07,0x00,&rx_data);
+SpiPs_write_read1(0xA08,0x0F,&rx_data);
+SpiPs_write_read1(0xA1C,0x01,&rx_data);
+SpiPs_write_read1(0xA16,0x15,&rx_data);
+SpiPs_write_read1(0xA17,0x55,&rx_data);
+SpiPs_write_read1(0xA18,0x55,&rx_data);
+SpiPs_write_read1(0xA19,0x55,&rx_data);
+SpiPs_write_read1(0xA1A,0x55,&rx_data);
+SpiPs_write_read1(0xA1B,0x55,&rx_data);
+SpiPs_write_read1(0x81A,0xF7,&rx_data);
+SpiPs_write_read1(0x81B,0x44,&rx_data);
+SpiPs_write_read1(0x81C,0x33,&rx_data);
+SpiPs_write_read1(0x81D,0x14,&rx_data);
+SpiPs_write_read1(0x800,0x80,&rx_data);
+SpiPs_write_read1(0x800,0x82,&rx_data);
+//最少0.1s
+usleep(500000);
+SpiPs_write_read1(0x77E,0x00,&rx_data);
+//恢复校准前设置
+SpiPs_write_read1(0x000,0x02,&rx_data);
+SpiPs_write_read1(0x02E,0x06,&rx_data);
+SpiPs_write_read1(0x03D,0x1B,&rx_data);
+SpiPs_write_read1(0x03E,0x39,&rx_data);
+SpiPs_write_read1(0x03F,0x27,&rx_data);
+SpiPs_write_read1(0x040,0xF8,&rx_data);
+SpiPs_write_read1(0x109,0x11,&rx_data);
+SpiPs_write_read1(0x10A,0x70,&rx_data);
+SpiPs_write_read1(0x11B,0x01,&rx_data);
+SpiPs_write_read1(0x11E,0x01,&rx_data);
+SpiPs_write_read1(0x11F,0x33,&rx_data);
+SpiPs_write_read1(0x128,0x10,&rx_data);
+SpiPs_write_read1(0x161,0x01,&rx_data);
+SpiPs_write_read1(0x162,0x01,&rx_data);
+SpiPs_write_read1(0x164,0x05,&rx_data);
+SpiPs_write_read1(0x165,0x55,&rx_data);
+SpiPs_write_read1(0x166,0x55,&rx_data);
+SpiPs_write_read1(0x167,0x55,&rx_data);
+SpiPs_write_read1(0x168,0x55,&rx_data);
+SpiPs_write_read1(0x169,0x55,&rx_data);
+SpiPs_write_read1(0xA07,0x00,&rx_data);
+SpiPs_write_read1(0xA08,0x00,&rx_data);
+SpiPs_write_read1(0xA16,0x00,&rx_data);
+SpiPs_write_read1(0xA17,0x00,&rx_data);
+SpiPs_write_read1(0xA18,0x00,&rx_data);
+SpiPs_write_read1(0xA19,0x00,&rx_data);
+SpiPs_write_read1(0xA1A,0x00,&rx_data);
+SpiPs_write_read1(0xA1B,0x00,&rx_data);
+SpiPs_write_read1(0xA1C,0x00,&rx_data);
+SpiPs_write_read1(0xA2D,0x00,&rx_data);
+usleep(1000);
+SpiPs_write_read2(0x615,0x00,&rx_data);
+temp=rx_data;
+SpiPs_write_read2(0x635,0x00,&rx_data);
+temp=rx_data;
+////配置Tx NCO BIST ON
+//SpiPs_write_read1(0x11B,0x01,&rx_data);
+//SpiPs_write_read1(0x11E,0x01,&rx_data);
+//SpiPs_write_read1(0x161,0x01,&rx_data);
+//SpiPs_write_read1(0x162,0x01,&rx_data);
+////配置Tx NCO频率 1MHz
+//SpiPs_write_read1(0x164,0x05,&rx_data);
+//SpiPs_write_read1(0x165,0x55,&rx_data);
+//SpiPs_write_read1(0x166,0x55,&rx_data);
+//SpiPs_write_read1(0x167,0x55,&rx_data);
+//SpiPs_write_read1(0x168,0x55,&rx_data);
+//SpiPs_write_read1(0x169,0x55,&rx_data);
+}

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_HOP/cx9261a_710_config.c

@@ -0,0 +1,835 @@
+/*
+ * cx9261a_710_config.c
+ *
+ *  Created on: 2024年3月21日
+ *      Author: cxlab
+ */
+
+
+/*
+ * cx9261a_076_config.c
+ *
+ *  Created on: 2023年11月30日
+ *      Author: cxlab
+ */
+
+
+#include "xilinx_io.h"
+#include "sleep.h"
+void cx9261a_710_config(void){
+u8 rx_data;
+u8 temp,r13D,r13E;
+
+//setPin(pin,value)
+GpioSetPinDir(0,0x01);
+GpioWritePin(0,1);
+GpioSetPinDir(32,0x01);
+GpioWritePin(32,1);
+GpioSetPinDir(33,0x01);
+GpioWritePin(33,1);
+GpioSetPinDir(34,0x01);
+GpioWritePin(34,0);
+GpioSetPinDir(35,0x01); //tx:0-rx:1
+GpioWritePin(35,1); //tx:0-rx:1
+GpioSetPinDir(36,0x01); //fdd:0-tdd:1
+GpioWritePin(36,1); //fdd:0-tdd:1
+GpioSetPinDir(37,0x01); //1r1t:0-2r2t:1
+GpioWritePin(37,1); //1r1t:0-2r2t:1
+GpioSetPinDir(38,0x01); //dualport:0-singleport:1
+GpioWritePin(38,1); //dualport:0-singleport:1
+GpioSetPinDir(39,0x01);
+GpioWritePin(39,1);
+GpioSetPinDir(40,0x01);
+GpioWritePin(40,1);
+//配置芯片
+//初始化芯片
+SpiPs_write_read1(0x000,0x02,&rx_data);
+SpiPs_write_read1(0x773,0x53,&rx_data);
+SpiPs_write_read1(0x774,0x86,&rx_data);
+SpiPs_write_read1(0x781,0x6F,&rx_data);
+SpiPs_write_read1(0x70B,0x0E,&rx_data);
+SpiPs_write_read1(0x727,0x0E,&rx_data);
+SpiPs_write_read1(0x743,0x0E,&rx_data);
+SpiPs_write_read1(0x624,0x11,&rx_data);
+SpiPs_write_read1(0x625,0x11,&rx_data);
+SpiPs_write_read1(0x61E,0x30,&rx_data);
+SpiPs_write_read1(0x61F,0x08,&rx_data);
+SpiPs_write_read1(0x621,0x4D,&rx_data);
+SpiPs_write_read1(0x622,0x19,&rx_data);
+SpiPs_write_read1(0x627,0x10,&rx_data);
+SpiPs_write_read1(0x646,0x11,&rx_data);
+SpiPs_write_read1(0x647,0x11,&rx_data);
+SpiPs_write_read1(0x640,0x30,&rx_data);
+SpiPs_write_read1(0x641,0x08,&rx_data);
+SpiPs_write_read1(0x643,0x4D,&rx_data);
+SpiPs_write_read1(0x644,0x19,&rx_data);
+SpiPs_write_read1(0x649,0x10,&rx_data);
+SpiPs_write_read1(0x668,0x11,&rx_data);
+SpiPs_write_read1(0x669,0x11,&rx_data);
+SpiPs_write_read1(0x662,0x30,&rx_data);
+SpiPs_write_read1(0x663,0x08,&rx_data);
+SpiPs_write_read1(0x665,0x4D,&rx_data);
+SpiPs_write_read1(0x666,0x19,&rx_data);
+SpiPs_write_read1(0x66B,0x10,&rx_data);
+SpiPs_write_read1(0x68A,0x11,&rx_data);
+SpiPs_write_read1(0x68B,0x11,&rx_data);
+SpiPs_write_read1(0x684,0x30,&rx_data);
+SpiPs_write_read1(0x685,0x08,&rx_data);
+SpiPs_write_read1(0x687,0x4D,&rx_data);
+SpiPs_write_read1(0x688,0x19,&rx_data);
+SpiPs_write_read1(0x68D,0x10,&rx_data);
+SpiPs_write_read1(0x6AC,0x11,&rx_data);
+SpiPs_write_read1(0x6AD,0x11,&rx_data);
+SpiPs_write_read1(0x6A6,0x30,&rx_data);
+SpiPs_write_read1(0x6A7,0x08,&rx_data);
+SpiPs_write_read1(0x6A9,0x4D,&rx_data);
+SpiPs_write_read1(0x6AA,0x19,&rx_data);
+SpiPs_write_read1(0x6AF,0x10,&rx_data);
+SpiPs_write_read1(0x705,0xFC,&rx_data);
+SpiPs_write_read1(0x706,0x6D,&rx_data);
+SpiPs_write_read1(0x707,0x91,&rx_data);
+SpiPs_write_read1(0x708,0x04,&rx_data);
+SpiPs_write_read1(0x709,0x94,&rx_data);
+SpiPs_write_read1(0x70A,0xFC,&rx_data);
+SpiPs_write_read1(0x70C,0xC0,&rx_data);
+SpiPs_write_read1(0x721,0xFC,&rx_data);
+SpiPs_write_read1(0x722,0x6D,&rx_data);
+SpiPs_write_read1(0x723,0x91,&rx_data);
+SpiPs_write_read1(0x724,0x04,&rx_data);
+SpiPs_write_read1(0x725,0x94,&rx_data);
+SpiPs_write_read1(0x726,0xFC,&rx_data);
+SpiPs_write_read1(0x728,0xC0,&rx_data);
+SpiPs_write_read1(0x73D,0xFC,&rx_data);
+SpiPs_write_read1(0x73E,0x6D,&rx_data);
+SpiPs_write_read1(0x73F,0x91,&rx_data);
+SpiPs_write_read1(0x740,0x04,&rx_data);
+SpiPs_write_read1(0x741,0x94,&rx_data);
+SpiPs_write_read1(0x742,0xFC,&rx_data);
+SpiPs_write_read1(0x744,0xC0,&rx_data);
+SpiPs_write_read1(0x75A,0x83,&rx_data);
+SpiPs_write_read1(0x75B,0xDA,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x75B,0x9A,&rx_data);
+SpiPs_write_read1(0x75C,0x81,&rx_data);
+SpiPs_write_read1(0x763,0x04,&rx_data);
+SpiPs_write_read1(0x764,0x83,&rx_data);
+SpiPs_write_read1(0x765,0xDA,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x765,0x9A,&rx_data);
+SpiPs_write_read1(0x766,0x81,&rx_data);
+SpiPs_write_read1(0x76D,0x04,&rx_data);
+//初始化电源
+SpiPs_write_read1(0x031,0x00,&rx_data);
+SpiPs_write_read1(0x032,0x7F,&rx_data);
+SpiPs_write_read1(0x033,0xFF,&rx_data);
+SpiPs_write_read1(0x034,0xFF,&rx_data);
+SpiPs_write_read1(0x035,0x00,&rx_data);
+SpiPs_write_read1(0x036,0x3D,&rx_data);
+SpiPs_write_read1(0x037,0xFF,&rx_data);
+SpiPs_write_read1(0x038,0xFB,&rx_data);
+SpiPs_write_read1(0x039,0x00,&rx_data);
+SpiPs_write_read1(0x03A,0x3D,&rx_data);
+SpiPs_write_read1(0x03B,0xFF,&rx_data);
+SpiPs_write_read1(0x03C,0xF8,&rx_data);
+SpiPs_write_read1(0x03D,0x1B,&rx_data);
+SpiPs_write_read1(0x03E,0x39,&rx_data);
+SpiPs_write_read1(0x03F,0x26,&rx_data);
+SpiPs_write_read1(0x040,0x78,&rx_data);
+SpiPs_write_read1(0x041,0x03,&rx_data);
+SpiPs_write_read1(0x042,0x3D,&rx_data);
+SpiPs_write_read1(0x043,0xE7,&rx_data);
+SpiPs_write_read1(0x044,0xF8,&rx_data);
+SpiPs_write_read1(0x045,0x18,&rx_data);
+SpiPs_write_read1(0x046,0x3D,&rx_data);
+SpiPs_write_read1(0x047,0x3F,&rx_data);
+SpiPs_write_read1(0x048,0xF8,&rx_data);
+SpiPs_write_read1(0x049,0x1F,&rx_data);
+SpiPs_write_read1(0x04A,0x3D,&rx_data);
+SpiPs_write_read1(0x04B,0x07,&rx_data);
+SpiPs_write_read1(0x04C,0xF8,&rx_data);
+SpiPs_write_read1(0x04D,0x04,&rx_data);
+SpiPs_write_read1(0x04E,0x3D,&rx_data);
+SpiPs_write_read1(0x04F,0xD9,&rx_data);
+SpiPs_write_read1(0x050,0xFE,&rx_data);
+//自定义接收模式
+SpiPs_write_read1(0x041,0x03,&rx_data);
+SpiPs_write_read1(0x042,0x3D,&rx_data);
+SpiPs_write_read1(0x043,0xE7,&rx_data);
+SpiPs_write_read1(0x044,0xF8,&rx_data);
+//自定义发射模式
+SpiPs_write_read1(0x045,0x18,&rx_data);
+SpiPs_write_read1(0x046,0x3D,&rx_data);
+SpiPs_write_read1(0x047,0x3F,&rx_data);
+SpiPs_write_read1(0x048,0xF8,&rx_data);
+//自定义FDD模式
+SpiPs_write_read1(0x049,0x1B,&rx_data);
+SpiPs_write_read1(0x04A,0x3D,&rx_data);
+SpiPs_write_read1(0x04B,0x27,&rx_data);
+SpiPs_write_read1(0x04C,0xF8,&rx_data);
+//配置BBPLL
+SpiPs_write_read1(0x789,0x10,&rx_data);
+SpiPs_write_read1(0x785,0x49,&rx_data);
+SpiPs_write_read1(0x788,0x24,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x788,0xA4,&rx_data);
+SpiPs_write_read1(0x0C0,0x50,&rx_data);
+SpiPs_write_read1(0x0C1,0x50,&rx_data);
+SpiPs_write_read1(0x0C2,0x50,&rx_data);
+SpiPs_write_read1(0x601,0x0F,&rx_data);
+SpiPs_write_read1(0x602,0x21,&rx_data);
+SpiPs_write_read1(0x60D,0x0D,&rx_data);
+SpiPs_write_read1(0x60E,0xFF,&rx_data);
+SpiPs_write_read1(0x60F,0xFF,&rx_data);
+SpiPs_write_read1(0x610,0xFF,&rx_data);
+SpiPs_write_read1(0x611,0x2F,&rx_data);
+SpiPs_write_read1(0x612,0x00,&rx_data);
+SpiPs_write_read1(0x70E,0x6B,&rx_data);
+SpiPs_write_read1(0x72A,0x6B,&rx_data);
+SpiPs_write_read1(0x746,0x6B,&rx_data);
+SpiPs_write_read1(0x70F,0xE0,&rx_data);
+SpiPs_write_read1(0x72B,0xE0,&rx_data);
+SpiPs_write_read1(0x747,0xE0,&rx_data);
+SpiPs_write_read1(0x70D,0x43,&rx_data);
+SpiPs_write_read1(0x729,0x43,&rx_data);
+SpiPs_write_read1(0x745,0x43,&rx_data);
+SpiPs_write_read1(0x782,0x76,&rx_data);
+SpiPs_write_read1(0x783,0x76,&rx_data);
+SpiPs_write_read1(0x784,0x06,&rx_data);
+//配置PLL来源
+SpiPs_write_read1(0x77D,0xCF,&rx_data);
+SpiPs_write_read1(0x775,0x24,&rx_data);
+SpiPs_write_read1(0x6C3,0x00,&rx_data);
+//配置PLL1
+SpiPs_write_read1(0x620,0x91,&rx_data);
+SpiPs_write_read1(0x61D,0x37,&rx_data);
+SpiPs_write_read1(0xB06,0x00,&rx_data);
+SpiPs_write_read1(0xB07,0xCB,&rx_data);
+SpiPs_write_read1(0xB08,0x20,&rx_data);
+SpiPs_write_read1(0xB09,0x00,&rx_data);
+SpiPs_write_read1(0xB0A,0x00,&rx_data);
+SpiPs_write_read1(0x61A,0x0C,&rx_data);
+SpiPs_write_read1(0x61B,0x30,&rx_data);
+SpiPs_write_read1(0x61C,0x08,&rx_data);
+SpiPs_write_read1(0x62A,0x0B,&rx_data);
+//配置PLL2
+SpiPs_write_read1(0x642,0x91,&rx_data);
+SpiPs_write_read1(0x63F,0x35,&rx_data);
+SpiPs_write_read1(0xB14,0x00,&rx_data);
+SpiPs_write_read1(0xB15,0xFA,&rx_data);
+SpiPs_write_read1(0xB16,0x00,&rx_data);
+SpiPs_write_read1(0xB17,0x00,&rx_data);
+SpiPs_write_read1(0xB18,0x00,&rx_data);
+SpiPs_write_read1(0x63C,0x0D,&rx_data);
+SpiPs_write_read1(0x63D,0x30,&rx_data);
+SpiPs_write_read1(0x63E,0x0B,&rx_data);
+SpiPs_write_read1(0x64C,0x00,&rx_data);
+//配置PLL3
+SpiPs_write_read1(0x664,0x81,&rx_data);
+SpiPs_write_read1(0x661,0x36,&rx_data);
+SpiPs_write_read1(0xB22,0x00,&rx_data);
+SpiPs_write_read1(0xB23,0xBB,&rx_data);
+SpiPs_write_read1(0xB24,0x80,&rx_data);
+SpiPs_write_read1(0xB25,0x00,&rx_data);
+SpiPs_write_read1(0xB26,0x00,&rx_data);
+SpiPs_write_read1(0x65E,0x0B,&rx_data);
+SpiPs_write_read1(0x65F,0x30,&rx_data);
+SpiPs_write_read1(0x660,0x0E,&rx_data);
+SpiPs_write_read1(0x66E,0x0B,&rx_data);
+//配置PLL4
+SpiPs_write_read1(0x686,0x91,&rx_data);
+SpiPs_write_read1(0x683,0x36,&rx_data);
+SpiPs_write_read1(0xB30,0x00,&rx_data);
+SpiPs_write_read1(0xB31,0xDA,&rx_data);
+SpiPs_write_read1(0xB32,0xC0,&rx_data);
+SpiPs_write_read1(0xB33,0x00,&rx_data);
+SpiPs_write_read1(0xB34,0x00,&rx_data);
+SpiPs_write_read1(0x680,0x0C,&rx_data);
+SpiPs_write_read1(0x681,0x30,&rx_data);
+SpiPs_write_read1(0x682,0x08,&rx_data);
+SpiPs_write_read1(0x690,0x0B,&rx_data);
+//配置PLL5
+SpiPs_write_read1(0x6A8,0x81,&rx_data);
+SpiPs_write_read1(0x6A5,0x36,&rx_data);
+SpiPs_write_read1(0xB3E,0x00,&rx_data);
+SpiPs_write_read1(0xB3F,0x9C,&rx_data);
+SpiPs_write_read1(0xB40,0x40,&rx_data);
+SpiPs_write_read1(0xB41,0x00,&rx_data);
+SpiPs_write_read1(0xB42,0x00,&rx_data);
+SpiPs_write_read1(0x6A2,0x0C,&rx_data);
+SpiPs_write_read1(0x6A3,0x30,&rx_data);
+SpiPs_write_read1(0x6A4,0x0C,&rx_data);
+SpiPs_write_read1(0x6B2,0x0B,&rx_data);
+//配置Tx1通道频率相关寄存器
+SpiPs_write_read1(0x75F,0x55,&rx_data);
+SpiPs_write_read1(0x761,0x04,&rx_data);
+SpiPs_write_read1(0x762,0x70,&rx_data);
+//配置Tx1通道频率相关寄存器
+SpiPs_write_read1(0x769,0x55,&rx_data);
+SpiPs_write_read1(0x76B,0x04,&rx_data);
+SpiPs_write_read1(0x76C,0x70,&rx_data);
+//配置Rx1通道
+SpiPs_write_read1(0x700,0x56,&rx_data);
+SpiPs_write_read1(0x701,0x00,&rx_data);
+SpiPs_write_read1(0x702,0xDB,&rx_data);
+SpiPs_write_read1(0x703,0x45,&rx_data);
+SpiPs_write_read1(0x704,0xF8,&rx_data);
+SpiPs_write_read1(0x907,0x1F,&rx_data);
+//配置Rx2通道
+SpiPs_write_read1(0x71C,0x56,&rx_data);
+SpiPs_write_read1(0x71D,0x00,&rx_data);
+SpiPs_write_read1(0x71E,0xDB,&rx_data);
+SpiPs_write_read1(0x71F,0x45,&rx_data);
+SpiPs_write_read1(0x720,0xF8,&rx_data);
+SpiPs_write_read1(0x907,0x1F,&rx_data);
+//配置Rx3通道
+SpiPs_write_read1(0x738,0x56,&rx_data);
+SpiPs_write_read1(0x739,0x00,&rx_data);
+SpiPs_write_read1(0x73A,0xDB,&rx_data);
+SpiPs_write_read1(0x73B,0x45,&rx_data);
+SpiPs_write_read1(0x73C,0xF8,&rx_data);
+SpiPs_write_read1(0x907,0x1F,&rx_data);
+//配置Tx1通道
+SpiPs_write_read1(0x75E,0xFF,&rx_data);
+SpiPs_write_read1(0x75D,0x4A,&rx_data);
+SpiPs_write_read1(0x75F,0x7D,&rx_data);
+SpiPs_write_read1(0x760,0xFF,&rx_data);
+//配置Tx2通道
+SpiPs_write_read1(0x768,0xFF,&rx_data);
+SpiPs_write_read1(0x767,0x4A,&rx_data);
+SpiPs_write_read1(0x769,0x7D,&rx_data);
+SpiPs_write_read1(0x76A,0xFF,&rx_data);
+//配置Rx滤波器
+SpiPs_write_read1(0x106,0x02,&rx_data);
+//配置Tx滤波器
+SpiPs_write_read1(0x107,0x00,&rx_data);
+SpiPs_write_read1(0x108,0xD0,&rx_data);
+//配置Rx混频器
+SpiPs_write_read1(0x11C,0x00,&rx_data);
+SpiPs_write_read1(0xA07,0x00,&rx_data);
+SpiPs_write_read1(0xA08,0x00,&rx_data);
+SpiPs_write_read1(0xA09,0x00,&rx_data);
+SpiPs_write_read1(0xA16,0x00,&rx_data);
+SpiPs_write_read1(0xA17,0x00,&rx_data);
+SpiPs_write_read1(0xA18,0x00,&rx_data);
+SpiPs_write_read1(0xA19,0x00,&rx_data);
+SpiPs_write_read1(0xA1A,0x00,&rx_data);
+SpiPs_write_read1(0xA1B,0x00,&rx_data);
+//配置Tx混频器
+SpiPs_write_read1(0x128,0x10,&rx_data);
+SpiPs_write_read1(0x11B,0x00,&rx_data);
+SpiPs_write_read1(0x11E,0x00,&rx_data);
+SpiPs_write_read1(0x161,0x00,&rx_data);
+SpiPs_write_read1(0x162,0x00,&rx_data);
+SpiPs_write_read1(0x164,0x00,&rx_data);
+SpiPs_write_read1(0x165,0x00,&rx_data);
+SpiPs_write_read1(0x166,0x00,&rx_data);
+SpiPs_write_read1(0x167,0x00,&rx_data);
+SpiPs_write_read1(0x168,0x00,&rx_data);
+SpiPs_write_read1(0x169,0x00,&rx_data);
+//配置AGC
+SpiPs_write_read1(0x903,0x11,&rx_data);
+SpiPs_write_read1(0x900,0x00,&rx_data);
+SpiPs_write_read1(0x901,0x00,&rx_data);
+SpiPs_write_read1(0x908,0x77,&rx_data);
+SpiPs_write_read1(0x909,0x03,&rx_data);
+SpiPs_write_read1(0x90A,0x32,&rx_data);
+SpiPs_write_read1(0x90D,0x00,&rx_data);
+SpiPs_write_read1(0x90E,0x0F,&rx_data);
+SpiPs_write_read1(0x90F,0x65,&rx_data);
+SpiPs_write_read1(0x910,0x32,&rx_data);
+SpiPs_write_read1(0x911,0x00,&rx_data);
+SpiPs_write_read1(0x912,0x0F,&rx_data);
+SpiPs_write_read1(0x913,0x3A,&rx_data);
+SpiPs_write_read1(0x914,0x37,&rx_data);
+SpiPs_write_read1(0x915,0x34,&rx_data);
+SpiPs_write_read1(0x916,0x31,&rx_data);
+//切换到休眠模式
+SpiPs_write_read1(0x02E,0x01,&rx_data);
+usleep(1000000);
+//切换到校准模式
+SpiPs_write_read1(0x02E,0x03,&rx_data);
+usleep(100000);
+//BBPll锁定
+SpiPs_write_read1(0x600,0x00,&rx_data);
+SpiPs_write_read1(0x600,0x11,&rx_data);
+usleep(100000);
+//BBPll锁定 成功
+//ADC校准
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x70F,0xE0,&rx_data);
+SpiPs_write_read1(0x710,0x83,&rx_data);
+SpiPs_write_read1(0x711,0xF0,&rx_data);
+SpiPs_write_read1(0x72B,0xE0,&rx_data);
+SpiPs_write_read1(0x72C,0x83,&rx_data);
+SpiPs_write_read1(0x72D,0xF0,&rx_data);
+SpiPs_write_read1(0x747,0xE0,&rx_data);
+SpiPs_write_read1(0x748,0x83,&rx_data);
+SpiPs_write_read1(0x749,0xF0,&rx_data);
+SpiPs_write_read1(0x713,0x80,&rx_data);
+SpiPs_write_read1(0x72F,0x80,&rx_data);
+SpiPs_write_read1(0x74B,0x80,&rx_data);
+SpiPs_write_read1(0x70B,0x9E,&rx_data);
+SpiPs_write_read1(0x727,0x9E,&rx_data);
+SpiPs_write_read1(0x743,0x9E,&rx_data);
+SpiPs_write_read1(0x70B,0x9A,&rx_data);
+SpiPs_write_read1(0x727,0x9A,&rx_data);
+SpiPs_write_read1(0x743,0x9A,&rx_data);
+SpiPs_write_read1(0x70B,0x9E,&rx_data);
+SpiPs_write_read1(0x727,0x9E,&rx_data);
+SpiPs_write_read1(0x743,0x9E,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x713,0xC0,&rx_data);
+SpiPs_write_read1(0x72F,0xC0,&rx_data);
+SpiPs_write_read1(0x74B,0xC0,&rx_data);
+//flash校准
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x715,0x80,&rx_data);
+SpiPs_write_read1(0x731,0x80,&rx_data);
+SpiPs_write_read1(0x74D,0x80,&rx_data);
+SpiPs_write_read1(0x715,0xC0,&rx_data);
+SpiPs_write_read1(0x731,0xC0,&rx_data);
+SpiPs_write_read1(0x74D,0xC0,&rx_data);
+SpiPs_write_read1(0x716,0x40,&rx_data);
+SpiPs_write_read1(0x732,0x40,&rx_data);
+SpiPs_write_read1(0x74E,0x40,&rx_data);
+SpiPs_write_read1(0x70B,0x16,&rx_data);
+SpiPs_write_read1(0x727,0x16,&rx_data);
+SpiPs_write_read1(0x743,0x16,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x70B,0x1E,&rx_data);
+SpiPs_write_read1(0x727,0x1E,&rx_data);
+SpiPs_write_read1(0x743,0x1E,&rx_data);
+SpiPs_write_read1(0x715,0x80,&rx_data);
+SpiPs_write_read1(0x731,0x80,&rx_data);
+SpiPs_write_read1(0x74D,0x80,&rx_data);
+SpiPs_write_read1(0x716,0x00,&rx_data);
+SpiPs_write_read1(0x732,0x00,&rx_data);
+SpiPs_write_read1(0x74E,0x00,&rx_data);
+//DC Tracking
+SpiPs_write_read1(0x109,0x11,&rx_data);
+SpiPs_write_read1(0x10A,0x70,&rx_data);
+SpiPs_write_read1(0x11F,0x33,&rx_data);
+//Rx1 QEC校准
+SpiPs_write_read1(0x02E,0x03,&rx_data);
+SpiPs_write_read1(0x03F,0x26,&rx_data);
+SpiPs_write_read1(0x040,0x78,&rx_data);
+SpiPs_write_read1(0x77D,0x90,&rx_data);
+SpiPs_write_read1(0x775,0x24,&rx_data);
+SpiPs_write_read1(0x6C3,0x05,&rx_data);
+SpiPs_write_read1(0x61D,0x27,&rx_data);
+SpiPs_write_read1(0x617,0x00,&rx_data);
+SpiPs_write_read1(0x617,0x03,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x61D,0x37,&rx_data);
+SpiPs_write_read1(0x686,0x81,&rx_data);
+SpiPs_write_read1(0x683,0x36,&rx_data);
+SpiPs_write_read1(0xB30,0x00,&rx_data);
+SpiPs_write_read1(0xB31,0x87,&rx_data);
+SpiPs_write_read1(0xB32,0x04,&rx_data);
+SpiPs_write_read1(0xB33,0x44,&rx_data);
+SpiPs_write_read1(0xB34,0x44,&rx_data);
+SpiPs_write_read1(0x680,0x0C,&rx_data);
+SpiPs_write_read1(0x681,0x30,&rx_data);
+SpiPs_write_read1(0x682,0x0C,&rx_data);
+SpiPs_write_read1(0x690,0x0B,&rx_data);
+SpiPs_write_read1(0x683,0x26,&rx_data);
+SpiPs_write_read1(0x67D,0x00,&rx_data);
+SpiPs_write_read1(0x67D,0x03,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x683,0x36,&rx_data);
+SpiPs_write_read1(0x000,0x12,&rx_data);
+SpiPs_write_read1(0x77E,0x50,&rx_data);
+SpiPs_write_read1(0x11B,0x01,&rx_data);
+SpiPs_write_read1(0x11E,0x01,&rx_data);
+SpiPs_write_read1(0x164,0x00,&rx_data);
+SpiPs_write_read1(0x165,0x00,&rx_data);
+SpiPs_write_read1(0x166,0x00,&rx_data);
+SpiPs_write_read1(0x167,0x00,&rx_data);
+SpiPs_write_read1(0x168,0x00,&rx_data);
+SpiPs_write_read1(0x169,0x00,&rx_data);
+SpiPs_write_read1(0x161,0x00,&rx_data);
+SpiPs_write_read1(0x162,0x00,&rx_data);
+SpiPs_write_read1(0x162,0x01,&rx_data);
+SpiPs_write_read1(0x161,0x01,&rx_data);
+SpiPs_write_read1(0x706,0x65,&rx_data);
+SpiPs_write_read1(0x6C3,0x00,&rx_data);
+SpiPs_write_read1(0x75F,0x7D,&rx_data);
+SpiPs_write_read1(0x11F,0x73,&rx_data);
+SpiPs_write_read1(0x153,0x00,&rx_data);
+SpiPs_write_read1(0x708,0x24,&rx_data);
+SpiPs_write_read1(0x196,0x01,&rx_data);
+SpiPs_write_read1(0x02A,0x12,&rx_data);
+
+do{
+usleep(100);
+SpiPs_write_read2(0x14D,0x00,&rx_data);
+temp=rx_data&0x10;
+}while (temp != 16);
+
+SpiPs_write_read1(0x02A,0x00,&rx_data);
+SpiPs_write_read1(0x196,0x11,&rx_data);
+SpiPs_write_read2(0x13D,0x00,&rx_data);
+r13D = rx_data;
+SpiPs_write_read2(0x13E,0x00,&rx_data);
+r13E = rx_data;
+
+unsigned long B = r13D * 256 + r13E;
+signed long B_s = B - (B >= 32768) * 65536;
+unsigned long B_abs = abs(B_s);
+unsigned short B_b = (unsigned short)B_abs;
+unsigned short B_delay = (B_b>>6) & 0x1ff;
+
+if(B_s > 0)
+{
+   SpiPs_write_read1(0x199, ((B_delay>>8)&0x1),&rx_data);
+   SpiPs_write_read1(0x19A,   B_delay&0xff,&rx_data);
+   SpiPs_write_read1(0x19B, 0,&rx_data);
+   SpiPs_write_read1(0x19C, 0,&rx_data);
+}
+else
+{
+   SpiPs_write_read1(0x199, 0,&rx_data);
+   SpiPs_write_read1(0x19A, 0,&rx_data);
+   SpiPs_write_read1(0x19B, ((B_delay>>8)&0x1),&rx_data);
+   SpiPs_write_read1(0x19C,   B_delay&0xff,&rx_data);
+}
+
+SpiPs_write_read1(0x196,0x10,&rx_data);
+SpiPs_write_read1(0x153,0x00,&rx_data);
+SpiPs_write_read1(0x02A,0x12,&rx_data);
+
+do{
+usleep(100);
+SpiPs_write_read2(0x14D,0x00,&rx_data);
+temp=rx_data&0x10;
+}while (temp != 16);
+
+SpiPs_write_read1(0x02A,0x00,&rx_data);
+SpiPs_write_read1(0x77E,0x00,&rx_data);
+SpiPs_write_read1(0x000,0x02,&rx_data);
+//Rx2 QEC校准
+SpiPs_write_read1(0x02E,0x03,&rx_data);
+SpiPs_write_read1(0x03F,0x26,&rx_data);
+SpiPs_write_read1(0x040,0x78,&rx_data);
+SpiPs_write_read1(0x77D,0x60,&rx_data);
+SpiPs_write_read1(0x775,0x24,&rx_data);
+SpiPs_write_read1(0x6C3,0x0A,&rx_data);
+SpiPs_write_read1(0x61D,0x27,&rx_data);
+SpiPs_write_read1(0x617,0x00,&rx_data);
+SpiPs_write_read1(0x617,0x03,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x61D,0x37,&rx_data);
+SpiPs_write_read1(0x686,0x81,&rx_data);
+SpiPs_write_read1(0x683,0x36,&rx_data);
+SpiPs_write_read1(0xB30,0x00,&rx_data);
+SpiPs_write_read1(0xB31,0x87,&rx_data);
+SpiPs_write_read1(0xB32,0x04,&rx_data);
+SpiPs_write_read1(0xB33,0x44,&rx_data);
+SpiPs_write_read1(0xB34,0x44,&rx_data);
+SpiPs_write_read1(0x680,0x0C,&rx_data);
+SpiPs_write_read1(0x681,0x30,&rx_data);
+SpiPs_write_read1(0x682,0x0C,&rx_data);
+SpiPs_write_read1(0x690,0x0B,&rx_data);
+SpiPs_write_read1(0x683,0x26,&rx_data);
+SpiPs_write_read1(0x67D,0x00,&rx_data);
+SpiPs_write_read1(0x67D,0x03,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x683,0x36,&rx_data);
+SpiPs_write_read1(0x000,0x22,&rx_data);
+SpiPs_write_read1(0x77E,0x0A,&rx_data);
+SpiPs_write_read1(0x11B,0x01,&rx_data);
+SpiPs_write_read1(0x11E,0x01,&rx_data);
+SpiPs_write_read1(0x164,0x00,&rx_data);
+SpiPs_write_read1(0x165,0x00,&rx_data);
+SpiPs_write_read1(0x166,0x00,&rx_data);
+SpiPs_write_read1(0x167,0x00,&rx_data);
+SpiPs_write_read1(0x168,0x00,&rx_data);
+SpiPs_write_read1(0x169,0x00,&rx_data);
+SpiPs_write_read1(0x161,0x00,&rx_data);
+SpiPs_write_read1(0x162,0x00,&rx_data);
+SpiPs_write_read1(0x162,0x01,&rx_data);
+SpiPs_write_read1(0x161,0x01,&rx_data);
+SpiPs_write_read1(0x706,0x65,&rx_data);
+SpiPs_write_read1(0x6C3,0x00,&rx_data);
+SpiPs_write_read1(0x75F,0x7D,&rx_data);
+SpiPs_write_read1(0x11F,0x73,&rx_data);
+SpiPs_write_read1(0x153,0x00,&rx_data);
+SpiPs_write_read1(0x724,0x24,&rx_data);
+SpiPs_write_read1(0x196,0x01,&rx_data);
+SpiPs_write_read1(0x02B,0x12,&rx_data);
+
+do{
+usleep(100);
+SpiPs_write_read2(0x14D,0x00,&rx_data);
+temp=rx_data&0x10;
+}while (temp != 16);
+
+SpiPs_write_read1(0x02B,0x00,&rx_data);
+SpiPs_write_read1(0x196,0x11,&rx_data);
+SpiPs_write_read2(0x13D,0x00,&rx_data);
+r13D = rx_data;
+SpiPs_write_read2(0x13E,0x00,&rx_data);
+r13E = rx_data;
+
+B = r13D * 256 + r13E;
+B_s = B - (B >= 32768) * 65536;
+B_abs = abs(B_s);
+B_b = (unsigned short)B_abs;
+B_delay = (B_b>>6) & 0x1ff;
+
+if(B_s > 0)
+{
+   SpiPs_write_read1(0x199, ((B_delay>>8)&0x1),&rx_data);
+   SpiPs_write_read1(0x19A,   B_delay&0xff,&rx_data);
+   SpiPs_write_read1(0x19B, 0,&rx_data);
+   SpiPs_write_read1(0x19C, 0,&rx_data);
+}
+else
+{
+   SpiPs_write_read1(0x199, 0,&rx_data);
+   SpiPs_write_read1(0x19A, 0,&rx_data);
+   SpiPs_write_read1(0x19B, ((B_delay>>8)&0x1),&rx_data);
+   SpiPs_write_read1(0x19C,   B_delay&0xff,&rx_data);
+}
+
+SpiPs_write_read1(0x196,0x10,&rx_data);
+SpiPs_write_read1(0x153,0x00,&rx_data);
+SpiPs_write_read1(0x02B,0x12,&rx_data);
+
+do{
+usleep(100);
+SpiPs_write_read2(0x14D,0x00,&rx_data);
+temp=rx_data&0x10;
+}while (temp != 16);
+
+SpiPs_write_read1(0x02B,0x00,&rx_data);
+SpiPs_write_read1(0x77E,0x00,&rx_data);
+SpiPs_write_read1(0x000,0x02,&rx_data);
+//恢复校准中被改变的配置
+SpiPs_write_read1(0x000,0x02,&rx_data);
+SpiPs_write_read1(0x02E,0x03,&rx_data);
+SpiPs_write_read1(0x109,0x11,&rx_data);
+SpiPs_write_read1(0x10A,0x70,&rx_data);
+SpiPs_write_read1(0x11B,0x00,&rx_data);
+SpiPs_write_read1(0x11E,0x00,&rx_data);
+SpiPs_write_read1(0x11F,0x33,&rx_data);
+SpiPs_write_read1(0x128,0x10,&rx_data);
+SpiPs_write_read1(0x161,0x00,&rx_data);
+SpiPs_write_read1(0x162,0x00,&rx_data);
+SpiPs_write_read1(0x164,0x00,&rx_data);
+SpiPs_write_read1(0x165,0x00,&rx_data);
+SpiPs_write_read1(0x166,0x00,&rx_data);
+SpiPs_write_read1(0x167,0x00,&rx_data);
+SpiPs_write_read1(0x168,0x00,&rx_data);
+SpiPs_write_read1(0x169,0x00,&rx_data);
+SpiPs_write_read1(0x6C3,0x00,&rx_data);
+SpiPs_write_read1(0x775,0x24,&rx_data);
+SpiPs_write_read1(0x77D,0xCF,&rx_data);
+SpiPs_write_read1(0xA07,0x00,&rx_data);
+SpiPs_write_read1(0xA08,0x00,&rx_data);
+SpiPs_write_read1(0xA16,0x00,&rx_data);
+SpiPs_write_read1(0xA17,0x00,&rx_data);
+SpiPs_write_read1(0xA18,0x00,&rx_data);
+SpiPs_write_read1(0xA19,0x00,&rx_data);
+SpiPs_write_read1(0xA1A,0x00,&rx_data);
+SpiPs_write_read1(0xA1B,0x00,&rx_data);
+SpiPs_write_read1(0x686,0x91,&rx_data);
+SpiPs_write_read1(0x683,0x36,&rx_data);
+SpiPs_write_read1(0xB30,0x00,&rx_data);
+SpiPs_write_read1(0xB31,0xDA,&rx_data);
+SpiPs_write_read1(0xB32,0xC0,&rx_data);
+SpiPs_write_read1(0xB33,0x00,&rx_data);
+SpiPs_write_read1(0xB34,0x00,&rx_data);
+SpiPs_write_read1(0x680,0x0C,&rx_data);
+SpiPs_write_read1(0x681,0x30,&rx_data);
+SpiPs_write_read1(0x682,0x08,&rx_data);
+SpiPs_write_read1(0x690,0x0B,&rx_data);
+//TX校准
+SpiPs_write_read1(0x03F,0x27,&rx_data);
+SpiPs_write_read1(0x040,0xF8,&rx_data);
+SpiPs_write_read1(0x61D,0x27,&rx_data);
+SpiPs_write_read1(0x617,0x00,&rx_data);
+SpiPs_write_read1(0x617,0x03,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x61D,0x37,&rx_data);
+SpiPs_write_read1(0x02E,0x03,&rx_data);
+SpiPs_write_read1(0x128,0x11,&rx_data);
+SpiPs_write_read1(0x11E,0x01,&rx_data);
+SpiPs_write_read1(0x77E,0x24,&rx_data);
+SpiPs_write_read1(0x11F,0x01,&rx_data);
+SpiPs_write_read1(0x121,0x02,&rx_data);
+SpiPs_write_read1(0x11B,0x01,&rx_data);
+SpiPs_write_read1(0x161,0x01,&rx_data);
+SpiPs_write_read1(0x162,0x01,&rx_data);
+SpiPs_write_read1(0x163,0x00,&rx_data);
+SpiPs_write_read1(0x164,0x04,&rx_data);
+SpiPs_write_read1(0x165,0x00,&rx_data);
+SpiPs_write_read1(0x166,0x00,&rx_data);
+SpiPs_write_read1(0x167,0x00,&rx_data);
+SpiPs_write_read1(0x168,0x00,&rx_data);
+SpiPs_write_read1(0x169,0x00,&rx_data);
+SpiPs_write_read1(0xA2D,0x02,&rx_data);
+SpiPs_write_read1(0xA07,0x00,&rx_data);
+SpiPs_write_read1(0xA08,0x0F,&rx_data);
+SpiPs_write_read1(0xA1C,0x01,&rx_data);
+SpiPs_write_read1(0xA16,0x20,&rx_data);
+SpiPs_write_read1(0xA17,0x00,&rx_data);
+SpiPs_write_read1(0xA18,0x00,&rx_data);
+SpiPs_write_read1(0xA19,0x00,&rx_data);
+SpiPs_write_read1(0xA1A,0x00,&rx_data);
+SpiPs_write_read1(0xA1B,0x00,&rx_data);
+SpiPs_write_read1(0x102,0x0F,&rx_data);
+SpiPs_write_read1(0x102,0xFF,&rx_data);
+SpiPs_write_read1(0x186,0x00,&rx_data);
+SpiPs_write_read1(0x186,0x01,&rx_data);
+SpiPs_write_read1(0x763,0x34,&rx_data);
+SpiPs_write_read1(0x76D,0x34,&rx_data);
+SpiPs_write_read1(0x101,0xEF,&rx_data);
+SpiPs_write_read1(0x101,0xFF,&rx_data);
+SpiPs_write_read1(0x800,0x00,&rx_data);
+SpiPs_write_read1(0x81A,0xF7,&rx_data);
+SpiPs_write_read1(0x81B,0x34,&rx_data);
+SpiPs_write_read1(0x81C,0x33,&rx_data);
+SpiPs_write_read1(0x81D,0x12,&rx_data);
+SpiPs_write_read1(0x81E,0x00,&rx_data);
+SpiPs_write_read1(0x81F,0xFF,&rx_data);
+SpiPs_write_read1(0x820,0x00,&rx_data);
+SpiPs_write_read1(0x821,0xFF,&rx_data);
+SpiPs_write_read1(0x800,0x80,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x800,0x81,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x77E,0x00,&rx_data);
+SpiPs_write_read1(0x77E,0x24,&rx_data);
+SpiPs_write_read1(0x11F,0x03,&rx_data);
+SpiPs_write_read1(0x121,0x02,&rx_data);
+SpiPs_write_read1(0x11B,0x01,&rx_data);
+SpiPs_write_read1(0x11E,0x01,&rx_data);
+SpiPs_write_read1(0x161,0x01,&rx_data);
+SpiPs_write_read1(0x162,0x01,&rx_data);
+SpiPs_write_read1(0x164,0x04,&rx_data);
+SpiPs_write_read1(0x165,0x00,&rx_data);
+SpiPs_write_read1(0x166,0x00,&rx_data);
+SpiPs_write_read1(0x167,0x00,&rx_data);
+SpiPs_write_read1(0x168,0x00,&rx_data);
+SpiPs_write_read1(0x169,0x00,&rx_data);
+SpiPs_write_read1(0xA2D,0x02,&rx_data);
+SpiPs_write_read1(0xA07,0x00,&rx_data);
+SpiPs_write_read1(0xA08,0x0F,&rx_data);
+SpiPs_write_read1(0xA1C,0x01,&rx_data);
+SpiPs_write_read1(0xA16,0x10,&rx_data);
+SpiPs_write_read1(0xA17,0x00,&rx_data);
+SpiPs_write_read1(0xA18,0x00,&rx_data);
+SpiPs_write_read1(0xA19,0x00,&rx_data);
+SpiPs_write_read1(0xA1A,0x00,&rx_data);
+SpiPs_write_read1(0xA1B,0x00,&rx_data);
+SpiPs_write_read1(0x81A,0xF7,&rx_data);
+SpiPs_write_read1(0x81B,0x44,&rx_data);
+SpiPs_write_read1(0x81C,0x33,&rx_data);
+SpiPs_write_read1(0x81D,0x14,&rx_data);
+SpiPs_write_read1(0x800,0x80,&rx_data);
+SpiPs_write_read1(0x800,0x82,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x77E,0x00,&rx_data);
+//恢复校准中被改变的配置
+SpiPs_write_read1(0x000,0x02,&rx_data);
+SpiPs_write_read1(0x02E,0x03,&rx_data);
+SpiPs_write_read1(0x109,0x11,&rx_data);
+SpiPs_write_read1(0x10A,0x70,&rx_data);
+SpiPs_write_read1(0x11B,0x00,&rx_data);
+SpiPs_write_read1(0x11E,0x00,&rx_data);
+SpiPs_write_read1(0x11F,0x33,&rx_data);
+SpiPs_write_read1(0x128,0x10,&rx_data);
+SpiPs_write_read1(0x161,0x00,&rx_data);
+SpiPs_write_read1(0x162,0x00,&rx_data);
+SpiPs_write_read1(0x164,0x00,&rx_data);
+SpiPs_write_read1(0x165,0x00,&rx_data);
+SpiPs_write_read1(0x166,0x00,&rx_data);
+SpiPs_write_read1(0x167,0x00,&rx_data);
+SpiPs_write_read1(0x168,0x00,&rx_data);
+SpiPs_write_read1(0x169,0x00,&rx_data);
+SpiPs_write_read1(0x6C3,0x00,&rx_data);
+SpiPs_write_read1(0x775,0x24,&rx_data);
+SpiPs_write_read1(0x77D,0xCF,&rx_data);
+SpiPs_write_read1(0xA07,0x00,&rx_data);
+SpiPs_write_read1(0xA08,0x00,&rx_data);
+SpiPs_write_read1(0xA16,0x00,&rx_data);
+SpiPs_write_read1(0xA17,0x00,&rx_data);
+SpiPs_write_read1(0xA18,0x00,&rx_data);
+SpiPs_write_read1(0xA19,0x00,&rx_data);
+SpiPs_write_read1(0xA1A,0x00,&rx_data);
+SpiPs_write_read1(0xA1B,0x00,&rx_data);
+//Pll1锁定
+SpiPs_write_read1(0x61D,0x27,&rx_data);
+SpiPs_write_read1(0x617,0x00,&rx_data);
+SpiPs_write_read1(0x617,0x03,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x61D,0x37,&rx_data);
+//Pll1锁定 成功
+//Pll2锁定
+SpiPs_write_read1(0x63F,0x25,&rx_data);
+SpiPs_write_read1(0x639,0x00,&rx_data);
+SpiPs_write_read1(0x639,0x03,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x63F,0x35,&rx_data);
+//Pll2锁定 成功
+//Pll3锁定
+SpiPs_write_read1(0x661,0x26,&rx_data);
+SpiPs_write_read1(0x65B,0x00,&rx_data);
+SpiPs_write_read1(0x65B,0x03,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x661,0x36,&rx_data);
+//Pll3锁定 成功
+//Pll4锁定
+SpiPs_write_read1(0x683,0x26,&rx_data);
+SpiPs_write_read1(0x67D,0x00,&rx_data);
+SpiPs_write_read1(0x67D,0x03,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x683,0x36,&rx_data);
+//Pll4锁定 成功
+//Pll5锁定
+SpiPs_write_read1(0x6A5,0x26,&rx_data);
+SpiPs_write_read1(0x69F,0x00,&rx_data);
+SpiPs_write_read1(0x69F,0x03,&rx_data);
+usleep(100000);
+SpiPs_write_read1(0x6A5,0x36,&rx_data);
+//Pll5锁定 成功
+//配置接口
+SpiPs_write_read1(0x02E,0x05,&rx_data);
+SpiPs_write_read1(0x003,0x33,&rx_data);
+SpiPs_write_read1(0x200,0x01,&rx_data);
+SpiPs_write_read1(0x201,0x3F,&rx_data);
+SpiPs_write_read1(0x202,0x03,&rx_data);
+SpiPs_write_read1(0x206,0x00,&rx_data);
+SpiPs_write_read1(0x208,0x00,&rx_data);
+SpiPs_write_read1(0x209,0x00,&rx_data);
+SpiPs_write_read1(0x77F,0x00,&rx_data);
+SpiPs_write_read1(0x780,0x33,&rx_data);
+SpiPs_write_read1(0x781,0x6F,&rx_data);
+//配置结束
+
+SpiPs_write_read1(0x02E,0x04,&rx_data);
+SpiPs_write_read1(0x780,0x00,&rx_data);
+
+SpiPs_write_read1(0x11F,0x00,&rx_data);
+SpiPs_write_read1(0x11F,0x33,&rx_data);
+////配置Tx NCO BIST ON
+//SpiPs_write_read1(0x11B,0x01,&rx_data);
+//SpiPs_write_read1(0x11E,0x01,&rx_data);
+//SpiPs_write_read1(0x161,0x01,&rx_data);
+//SpiPs_write_read1(0x162,0x01,&rx_data);
+////配置Tx NCO频率 1MHz
+//SpiPs_write_read1(0x164,0x05,&rx_data);
+//SpiPs_write_read1(0x165,0x55,&rx_data);
+//SpiPs_write_read1(0x166,0x55,&rx_data);
+//SpiPs_write_read1(0x167,0x55,&rx_data);
+//SpiPs_write_read1(0x168,0x55,&rx_data);
+//SpiPs_write_read1(0x169,0x55,&rx_data);
+}

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_HOP/download_bin.c

@@ -0,0 +1,80 @@
+/*
+ * download_bin.c
+ *
+ *  Created on: 2023年11月23日
+ *      Author: cxlab
+ */
+
+#include "xilinx_io.h"
+#include "sleep.h"
+void download_bin(void){
+
+		int temp;
+		u8 rx_data;
+		u8 data[4];
+		u32 buf;
+		u8 addr[2];
+		int on = 1;
+		if (on) {
+			SpiPs_write_read1(0x079,0x00,&rx_data);//关闭CRC校验
+			SpiPs_write_read1(0x071,0x00,&rx_data);
+			SpiPs_write_read1(0x071,0x09,&rx_data);
+	//		SpiPs_write_read1(0x236,0x0F,&rx_data);
+	//		SpiPs_write_read1(0x20A,0x01,&rx_data);
+			for(int i=0;i<5507;i++){
+				addr[0]=(i>>8)&0xff;
+				addr[1]= i&0xff;
+				buf=rom_read((u8 *)&addr);
+				data[0]=buf>>24;
+				data[1]=(buf>>16)&0xff;
+				data[2]=(buf>>8)&0xff;
+				data[3]=buf&0xff;
+				for(int j=0;j<4;j++){
+					SpiPs_write_read1(0x070,data[j],&rx_data);
+				}
+
+			}
+
+			SpiPs_write_read1(0x071,0x1A,&rx_data);//开启CRC校验
+			SpiPs_write_read1(0x079,0x08,&rx_data);//开启CRC校验
+			usleep(1000);
+			SpiPs_write_read2(0x078,0x00,&rx_data);
+			temp=rx_data;
+
+			if (temp == 0x01) {
+				xil_printf("CRC successful");
+			}
+			else {
+				xil_printf("CRC unsuccessful");
+			}
+			SpiPs_write_read1(0x071,0x06,&rx_data);//处理器门控时钟使能
+			usleep(10000);
+			SpiPs_write_read2(0x0A7,0x00,&rx_data);//处理器运行成果标志
+			temp=rx_data;
+
+			if (temp == 0x11) {
+				xil_printf("core run successful");
+			}
+			else {
+				xil_printf("core run unsuccessful");
+			}
+////////////////////dpd系数加载////////////////////
+			SpiPs_write_read1(0x302,0xDF,&rx_data);
+			SpiPs_write_read1(0x0A3,0x52,&rx_data);
+			usleep(200000);
+			SpiPs_write_read2(0x0A7,0x00,&rx_data);//dpd系数加载完成标志
+			temp=rx_data;
+
+			if (temp == 0x61) {
+				xil_printf("dpd index load successful");
+			}
+			else {
+				xil_printf("dpd index load unsuccessful");
+			}
+		}
+		else {
+		SpiPs_write_read1(0x071,0x00,&rx_data);
+		}
+
+	}
+

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_HOP/echo.c

@@ -0,0 +1,461 @@
+/*
+ * Copyright (C) 2016 - 2018 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ */
+
+#include <stdio.h>
+#include <string.h>
+
+#include "lwip/sockets.h"
+#include "netif/xadapter.h"
+#include "lwipopts.h"
+#include "xil_printf.h"
+#include "FreeRTOS.h"
+#include "task.h"
+#include "xilinx_io.h"
+
+#define THREAD_STACKSIZE 1024
+#define ACK 0x01
+u16_t echo_port = 7;
+//#define RECV_BUF_SIZE 65536*16*8
+#define RECV_BUF_SIZE 1024
+//char recv_buf[RECV_BUF_SIZE];
+char recv_buf[1024];
+char recv_buf_temp[3];
+char trans_buf[8192*5];
+struct spi_stack spistack;
+
+
+u16 hop_cnt = 0;
+
+void print_echo_app_header()
+{
+    xil_printf("%20s %6d %s\r\n", "echo server",
+                        echo_port,
+                        "$ telnet <board_ip> 7");
+
+}
+
+
+enum {
+	CMD_VER = 0,
+	CMD_RST = 1,
+	CMD_SPI_WRI = 2 ,
+	CMD_SPI_READ = 3,
+	CMD_DATA_CAPTURE0 = 4,
+	CMD_WAVE_DOWNLOAD = 5,
+	CMD_PIN_SET =  6,
+	CMD_DATA_CAPTURE1 = 8,
+	CMD_DATA_CAPTURE2 = 9,
+	CMD_STACK_OUT = 10,
+	CMD_hopping = 11,
+	CMD_qecbin = 12,
+	CMD_cx9261a_config = 13,
+	CMD_cx3e04_config = 14,
+	CMD_cx3e04_SPI_WRI = 15 ,
+	CMD_cx3e04_SPI_READ = 16,
+    CMD_IMAGE_UPDATE = 22,
+};
+/* thread spawned for each connection */
+void process_echo_request(void *p)
+{
+	int sd = (int)p;
+	int status;
+	int n, nwrote,send_n,total_send;
+	u8 rx_data;
+	u32 capture_length;
+	u8 pin;
+	u8 pin_value;
+	char FPGA_SDK_IP[]="FPGA:20240513-SDK:20240514";
+	spistack.spi_write_num = 0;
+	while (1) {
+		/* read a max of RECV_BUF_SIZE bytes from socket */
+		if ((n = read(sd, recv_buf, 5)) < 0) {
+			xil_printf("%s: error reading from socket %d, closing socket\r\n", __FUNCTION__, sd);
+			break;
+		}
+
+		/* break if the recved message = "quit" */
+		if (!strncmp(recv_buf, "quit", 4))
+			break;
+
+		/* break if client closed connection */
+		if (n <= 0)
+			break;
+
+		else{/* excute cmd if recved message = "cmd"*/
+			n=0;
+			if (!strncmp(recv_buf, "cmd ", 4)){
+//				xil_printf("%d %d %d %d.\r\n", recv_buf[0],recv_buf[1],recv_buf[2],recv_buf[4]);
+				dbg_printf("Rece %d bytes.\r\n",n);
+				switch(recv_buf[4]){
+				case CMD_IMAGE_UPDATE:
+				                {
+
+				                    u32 offset;
+				                    u32 image_size;
+				                    recv_buf[0] = ACK;
+				                    nwrote = write(sd, recv_buf, 1);
+				                    n = read(sd, recv_buf, RECV_BUF_SIZE);
+
+				                    offset = *(u32 *)recv_buf;
+				                    image_size = *(u32 *)(recv_buf + 4);
+				                    xil_printf("offset is 0x%x image_size is 0x%x.\n", offset, image_size);
+
+				                    void *image_ptr = (void *)0x30000000;
+				                    u32 LengthBytes;
+				                    write(sd, recv_buf, 1); // ask for image data
+				                    //// receive flash image to ddr
+				                    LengthBytes = 0;
+				                    while (LengthBytes < image_size)
+				                    {
+				                        n = read(sd, image_ptr + LengthBytes, RECV_BUF_SIZE);
+				                        //				xil_printf("read %d bytes.\n",n);
+				                        LengthBytes = LengthBytes + n;
+				                    }
+
+				                    // image data sumcheck
+
+				                    // program image data into flash
+				                    //QspiStore( (u32) image_ptr, offset, image_size);
+				                    //xil_printf("flash program done.\n", n);
+				                    status = FfsSdWrite(image_ptr, image_size);
+				                    write(sd, recv_buf, 1); // send done
+				                    xil_printf("sd program done.\n", n);
+				                    n = 0;
+				                    break;
+				                }
+
+				case CMD_VER:
+					dbg_printf("Version:FPGA_20240513;SDK_20240514;IP_192.168.1.99.\r\n");
+					n=26;
+					for(int i=0;i<26;i++){
+					recv_buf[i] = FPGA_SDK_IP[i];
+					}
+					break;
+				case CMD_RST:
+					dbg_printf("Rece cmd excute rst.\r\n");
+					GpioSetPinDir(NRST,GPIO_DIR_OUTPUT);
+					DeviceRst();
+					break;
+
+				case CMD_STACK_OUT:
+					dbg_printf("Rece cmd STACK OUT.\r\n");
+					spi_stack_out(&spistack);
+					n=1;
+					recv_buf[0] = 0x55;
+					break;
+				case CMD_SPI_WRI:
+					read(sd, &recv_buf[5], 3);
+					dbg_printf("Rece cmd excute spi write.\r\n");
+					dbg_printf("ADDR 0x%x DATA 0x%x.\r\n",recv_buf[5]*256+recv_buf[6]-32768,recv_buf[7]);
+//					SpiPs_write_read((u8 *)&recv_buf[5],&rx_data);
+					status = spi_stack_in((u8 *)&recv_buf[5],&spistack);
+					if(status){//when memory is near full,start spi write
+						spi_stack_out(&spistack);
+					}
+//					n=1;
+//					recv_buf[0] = rx_data;
+					break;
+				case CMD_SPI_READ:
+					read(sd, &recv_buf[5], 3);
+					dbg_printf("Rece cmd excute spi read.\r\n");
+					dbg_printf("ADDR 0x%x DATA 0x%x.\r\n",recv_buf[5]*256+recv_buf[6],recv_buf[7]);
+					SpiPs_write_read((u8 *)&recv_buf[5],&rx_data);
+					n=1;
+					recv_buf[0] = rx_data;
+					break;
+				case CMD_DATA_CAPTURE0:
+					read(sd, &recv_buf[5], 4);
+					capture_length = *((u32 *) &recv_buf[5]);//num of sample
+					dbg_printf("Rece cmd excute %d sample data capture.\r\n",capture_length);
+					XAxiDmaCapture(xAxiDma0Get(),capture_length);
+					n = capture_length*8;
+					total_send = 0;
+					/* handle request */
+					while(n>0){
+						if(n>1024)
+						    send_n = 1024;
+						else
+						    send_n = n;
+						n= n-send_n;
+						memcpy(recv_buf,TX_BUFFER_BASE + total_send,send_n);
+						total_send = total_send + send_n;
+						if ((nwrote = write(sd, &recv_buf, send_n)) < 0) {
+							xil_printf("%s: ERROR responding to client echo request. received = %d, written = %d\r\n",__FUNCTION__, n, nwrote);
+							xil_printf("Closing socket %d\r\n", sd);
+							break;
+						}
+						else{
+							if(send_n!=nwrote){
+							    xil_printf("%d Bytes Send %d.\r\n", send_n,nwrote);
+							}
+						}
+					}
+					dbg_printf("Send %d bytes.\r\n",n);
+					break;
+				case CMD_DATA_CAPTURE1:
+					read(sd, &recv_buf[5], 4);
+					capture_length = *((u32 *) &recv_buf[5]);//num of sample
+					dbg_printf("Rece cmd excute %d sample data capture.\r\n",capture_length);
+					XAxiDmaCapture(xAxiDma1Get(),capture_length);
+					n = capture_length*8;
+					total_send = 0;
+					/* handle request */
+					while(n>0){
+						if(n>1024)
+						    send_n = 1024;
+						else
+						    send_n = n;
+						n= n-send_n;
+
+						memcpy(recv_buf,TX_BUFFER_BASE + total_send,send_n);
+						total_send = total_send + send_n;
+						if ((nwrote = write(sd, &recv_buf, send_n)) < 0) {
+							xil_printf("%s: ERROR responding to client echo request. received = %d, written = %d\r\n",__FUNCTION__, n, nwrote);
+							xil_printf("Closing socket %d\r\n", sd);
+							break;
+						}
+						else{
+							if(send_n!=nwrote){
+							    xil_printf("%d Bytes Send %d.\r\n", send_n,nwrote);
+							}
+						}
+					}
+					dbg_printf("Send %d bytes.\r\n",n);
+					break;
+				case CMD_DATA_CAPTURE2:
+					read(sd, &recv_buf[5], 4);
+					capture_length = *((u32 *) &recv_buf[5]);//num of sample
+					dbg_printf("Rece cmd excute %d sample data capture.\r\n",capture_length);
+					XAxiDmaCapture(xAxiDma2Get(),capture_length);
+					n = capture_length*8;
+					total_send = 0;
+					/* handle request */
+					while(n>0){
+						if(n>1024)
+						    send_n = 1024;
+						else
+						    send_n = n;
+						n= n-send_n;
+						memcpy(recv_buf,TX_BUFFER_BASE + total_send,send_n);
+						total_send = total_send + send_n;
+						if ((nwrote = write(sd, &recv_buf, send_n)) < 0) {
+							xil_printf("%s: ERROR responding to client echo request. received = %d, written = %d\r\n",__FUNCTION__, n, nwrote);
+							xil_printf("Closing socket %d\r\n", sd);
+							break;
+						}
+						else{
+							if(send_n!=nwrote){
+							    xil_printf("%d Bytes Send %d.\r\n", send_n,nwrote);
+							}
+						}
+					}
+					dbg_printf("Send %d bytes.\r\n",n);
+					break;
+				case CMD_WAVE_DOWNLOAD:
+					dbg_printf("Rece cmd excute wave download.\r\n");
+					while(n<WAVE_LENGTH){
+						dbg_printf("Rece data num in recv_buf is %d.\r\n",n);
+						n =n + read(sd, &trans_buf[n], 512);//
+					}
+					dbg_printf("Rece data num in recv_buf is %d.\r\n",n);
+					DownloadWave((u8 *)&trans_buf[0]);
+					n=0;
+					break;
+				case CMD_PIN_SET:
+					read(sd, &recv_buf[5], 2);
+					pin = (u8) recv_buf[5];
+					pin_value = (u8) recv_buf[6];
+					dbg_printf("Rece cmd excute pin %d set %d.\r\n",pin,pin_value);
+					GpioSetPinDir(pin,GPIO_DIR_OUTPUT);
+					GpioWritePin(pin,pin_value&0x01);//dma_axis_rx_rstn
+//					recv_buf_temp[0]= 0x80;
+//					recv_buf_temp[1]= 0x43;
+//					recv_buf_temp[2]= 0xe7;
+//					if((pin==0x20)&&(pin_value==0x01)){
+//						SpiPs_write_read((u8 *)&recv_buf_temp,&rx_data);
+//					}
+					break;
+
+				case CMD_hopping:
+					    read(sd, &recv_buf[5], 4);
+						int hop_flag=recv_buf[5]&0x01;
+						frqhop_flag(hop_flag);
+						if(hop_flag==1){
+							xil_printf("hopping freqence start.\r\n");
+						}else{
+							xil_printf("hopping freqence end.\r\n");
+						}
+					break;
+				case CMD_qecbin:
+						download_bin();
+					break;
+				case CMD_cx9261a_config:
+				    	read(sd, &recv_buf[5], 1);
+				    	int lo = 5000;
+				    	int f0 = 4;
+				    	int fs = 80;
+				    	int ref= 100;
+				    	int dcCalibEnable = 1;
+				    	int dcCalibLength = 7;
+				    	if(recv_buf[5] == 0){
+							cx9261a_151_config();
+				    	}else if(recv_buf[5] == 1){
+							cx9261a_076_config();
+							configDcCalib(dcCalibEnable,dcCalibLength);
+							rxFFTCalib(lo,fs,ref,8,1);
+							rxFFTCalib(lo,fs,ref,8,2);
+							rxFFTCalib(lo,fs,ref,8,3);
+							txBisectionQecCalib(f0, fs);
+							txBisectionDcCalib(f0, fs);
+				    	}
+					break;
+
+				case CMD_cx3e04_config:
+					cx3e04_config();
+					break;
+
+				case CMD_cx3e04_SPI_WRI:
+					read(sd, &recv_buf[5], 3);
+					dbg_printf("Rece cmd excute cx3e04_spi write.\r\n");
+					dbg_printf("ADDR 0x%x DATA 0x%x.\r\n",recv_buf[5]*256+recv_buf[6]-32768,recv_buf[7]);
+					int addr = recv_buf[5]*256+recv_buf[6];
+				    int value= recv_buf[7];
+					cx3e04_write(addr,value);
+					break;
+				case CMD_cx3e04_SPI_READ:
+					read(sd, &recv_buf[5], 2);
+					dbg_printf("Rece cmd excute cx3e04_spi read.\r\n");
+					dbg_printf("ADDR 0x%x.\r\n",recv_buf[5]*256+recv_buf[6]);
+					addr = recv_buf[5]*256+recv_buf[6];
+					n=1;
+					recv_buf[0] = cx3e04_read(addr);
+					break;
+				default :
+					xil_printf("cmd error 0x%x",recv_buf[4]);
+					break;
+				}
+
+			/*if(recv_buf[4] == 7){
+					read(sd, &recv_buf[5], 4);
+					capture_length = *((u32 *) &recv_buf[5]);//num of sample
+					dbg_printf("Rece cmd excute %d sample data capture.\r\n",capture_length);
+					XAxiDmaCapture2(capture_length);
+//					memcpy(recv_buf,TX_BUFFER_BASE,capture_length*8);
+					n = capture_length*8;
+					total_send = 0;
+					// handle request
+					while(n>0){
+						if(n>1024)
+							send_n = 1024;
+						else
+							send_n = n;
+					n= n-send_n;
+					total_send = total_send + send_n;
+					memcpy(recv_buf,TX_BUFFER_BASE + total_send,send_n);
+					if ((nwrote = write(sd, &recv_buf, send_n)) < 0) {
+						xil_printf("%s: ERROR responding to client echo request. received = %d, written = %d\r\n",
+								__FUNCTION__, n, nwrote);
+						xil_printf("Closing socket %d\r\n", sd);
+						break;
+					}
+					else{
+						if(send_n!=nwrote){
+						xil_printf("%d Bytes Send %d.\r\n", send_n,nwrote);
+						}
+					}
+					}
+					dbg_printf("Send %d bytes.\r\n",n);
+			}*/
+
+		}
+		}
+		/* handle request */
+		if ((nwrote = write(sd, recv_buf, n)) < 0) {
+			xil_printf("%s: ERROR responding to client echo request. received = %d, written = %d\r\n",
+					__FUNCTION__, n, nwrote);
+			xil_printf("Closing socket %d\r\n", sd);
+			break;
+		}
+		else{
+			if(n!=nwrote){
+			xil_printf("%d Bytes Send %d.\r\n", n,nwrote);
+			}
+		}
+	}
+
+	/* close connection */
+	close(sd);
+	vTaskDelete(NULL);
+}
+
+void echo_application_thread()
+{
+	int sock, new_sd;
+	int size;
+#if LWIP_IPV6==0
+	struct sockaddr_in address, remote;
+
+	memset(&address, 0, sizeof(address));
+
+	if ((sock = lwip_socket(AF_INET, SOCK_STREAM, 0)) < 0)
+		return;
+
+	address.sin_family = AF_INET;
+	address.sin_port = htons(echo_port);
+	address.sin_addr.s_addr = INADDR_ANY;
+#else
+	struct sockaddr_in6 address, remote;
+
+	memset(&address, 0, sizeof(address));
+
+	address.sin6_len = sizeof(address);
+	address.sin6_family = AF_INET6;
+	address.sin6_port = htons(echo_port);
+
+	memset(&(address.sin6_addr), 0, sizeof(address.sin6_addr));
+
+	if ((sock = lwip_socket(AF_INET6, SOCK_STREAM, 0)) < 0)
+		return;
+#endif
+
+	if (lwip_bind(sock, (struct sockaddr *)&address, sizeof (address)) < 0)
+		return;
+
+	lwip_listen(sock, 0);
+
+	size = sizeof(remote);
+
+	while (1) {
+		if ((new_sd = lwip_accept(sock, (struct sockaddr *)&remote, (socklen_t *)&size)) > 0) {
+			sys_thread_new("echos", process_echo_request,
+				(void*)new_sd,
+				THREAD_STACKSIZE,
+				DEFAULT_THREAD_PRIO);
+		}
+	}
+}

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_HOP/frqhop_config.c

@@ -0,0 +1,52 @@
+/*
+ * frqhop_config.c
+ *
+ *  Created on: 2023年11月24日
+ *      Author: cxlab
+ */
+
+#include "xilinx_io.h"
+#include "sleep.h"
+#include "time.h"
+#include "xtime_l.h"
+#include "math.h"
+#include <stdlib.h>
+
+void frqhop_config(int hop_flag){
+	XTime tCur;
+    XTime_GetTime(&tCur);
+    srand(tCur);
+	double hop_freq = (rand()%(800-30))+30+(rand()%(101))/(double)100;//随机产生[30,800)double类型的数
+//    double hop_freq = 400.52;
+	double hop_freq1 = 800.25;
+	static int pll_index=1;
+	static int unlock_pll1_cnt=0,unlock_pll2_cnt=0;
+	if(hop_freq == hop_freq1){
+		if(pll_index == 2){
+			pll_index = 4;
+		}
+		else if(pll_index == 1){
+			pll_index = 3;
+		}
+	}
+	if(hop_flag == 1){
+		if(pll_index == 1 || pll_index == 3){
+				//切换至pll2来源
+				trx_ch_pll_config(2);
+				//配置pll1参数
+				unlock_pll1_cnt=PLL_config(1,hop_freq)-1;
+				pll_index = 2;
+		}
+	else if(pll_index == 2 || pll_index == 4){
+				//切换至pll1来源
+				trx_ch_pll_config(1);
+				//配置pll2参数
+				unlock_pll2_cnt=PLL_config(2,hop_freq)-1;
+				pll_index = 1;
+		}
+	}
+	hop_freq1 = hop_freq;
+	if(unlock_pll2_cnt!=0 || unlock_pll1_cnt !=0){
+		xil_printf("pll1 unlock num: %d; pll2 unlock num: %d;.\n", unlock_pll1_cnt, unlock_pll2_cnt);
+	}
+}

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_HOP/iic_phyreset.c

@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2016 - 2018 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ */
+
+#include <stdio.h>
+
+#include "xparameters.h"
+#if defined (__arm__) || defined(__aarch64__)
+#include "xil_printf.h"
+#endif
+
+#ifdef XPS_BOARD_ZCU102
+#ifdef XPAR_XIICPS_0_DEVICE_ID
+#include "xiicps.h"
+
+#define BUF_LEN		10U
+
+#define IOEXPANDER1_ADDR		0x20U
+
+#define IIC_SCLK_RATE_IOEXP		400000
+
+#define CMD_CFG_0_REG		0x06U
+#define CMD_OUTPUT_0_REG	0x02U
+#define DATA_OUTPUT			0x0U
+
+#define DATA_COMMON_CFG		0xE0U
+#define DATA_GT_0000_CFG	0x00U
+
+XIicPs I2c0InstancePtr;
+
+int IicPhyReset(void)
+{
+
+	u8 WriteBuffer[BUF_LEN] = {0};
+	XIicPs_Config *I2c0CfgPtr;
+	int Status = XST_SUCCESS;
+
+	/* Initialize the IIC0 driver so that it is ready to use */
+	I2c0CfgPtr = XIicPs_LookupConfig(XPAR_XIICPS_0_DEVICE_ID);
+	if (I2c0CfgPtr == NULL) {
+		Status = XST_FAILURE;
+		return Status;
+	}
+
+	Status = XIicPs_CfgInitialize(&I2c0InstancePtr, I2c0CfgPtr,
+			I2c0CfgPtr->BaseAddress);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		return Status;
+	}
+
+	/* Set the IIC serial clock rate */
+	XIicPs_SetSClk(&I2c0InstancePtr, IIC_SCLK_RATE_IOEXP);
+
+	/* Configure I/O pins as Output */
+	WriteBuffer[0] = CMD_CFG_0_REG;
+	WriteBuffer[1] = DATA_OUTPUT;
+	Status = XIicPs_MasterSendPolled(&I2c0InstancePtr,
+			WriteBuffer, 2, IOEXPANDER1_ADDR);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		return Status;
+	}
+
+	/* Wait until bus is idle to start another transfer */
+	while (XIicPs_BusIsBusy(&I2c0InstancePtr));
+
+	/*
+	 * Deasserting I2C_MUX_RESETB
+	 * And GEM3 Resetb
+	 * Selecting lanes based on configuration
+	 */
+	WriteBuffer[0] = CMD_OUTPUT_0_REG;
+	/* gt0000 or no GT configuration */
+	WriteBuffer[1] = DATA_COMMON_CFG | DATA_GT_0000_CFG;
+
+	/* Send the Data */
+	Status = XIicPs_MasterSendPolled(&I2c0InstancePtr,
+			WriteBuffer, 2, IOEXPANDER1_ADDR);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		return Status;
+	}
+
+	/* Wait until bus is idle */
+	while (XIicPs_BusIsBusy(&I2c0InstancePtr));
+
+	xil_printf("IIC PHY reset on ZCU102 successful \n\r");
+}
+#endif
+#endif

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_HOP/main.c

@@ -0,0 +1,300 @@
+/*
+ * Copyright (C) 2016 - 2018 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ */
+
+#include <stdio.h>
+#include "xparameters.h"
+#include "netif/xadapter.h"
+#include "platform_config.h"
+#include "xil_printf.h"
+#include "xilinx_io.h"
+#include "FreeRTOS.h"
+#include "queue.h"
+#include "semphr.h"
+#include "math.h"
+
+#if LWIP_IPV6==1
+#include "lwip/ip.h"
+#else
+#if LWIP_DHCP==1
+#include "lwip/dhcp.h"
+#endif
+#endif
+
+#ifdef XPS_BOARD_ZCU102
+#ifdef XPAR_XIICPS_0_DEVICE_ID
+int IicPhyReset(void);
+#endif
+#endif
+
+int main_thread();
+void print_echo_app_header();
+void echo_application_thread(void *);
+
+void lwip_init();
+
+#if LWIP_IPV6==0
+#if LWIP_DHCP==1
+extern volatile int dhcp_timoutcntr;
+err_t dhcp_start(struct netif *netif);
+#endif
+#endif
+
+#define THREAD_STACKSIZE 1024
+
+static struct netif server_netif;
+struct netif *echo_netif;
+
+#if LWIP_IPV6==1
+void print_ip6(char *msg, ip_addr_t *ip)
+{
+	print(msg);
+	xil_printf(" %x:%x:%x:%x:%x:%x:%x:%x\n\r",
+			IP6_ADDR_BLOCK1(&ip->u_addr.ip6),
+			IP6_ADDR_BLOCK2(&ip->u_addr.ip6),
+			IP6_ADDR_BLOCK3(&ip->u_addr.ip6),
+			IP6_ADDR_BLOCK4(&ip->u_addr.ip6),
+			IP6_ADDR_BLOCK5(&ip->u_addr.ip6),
+			IP6_ADDR_BLOCK6(&ip->u_addr.ip6),
+			IP6_ADDR_BLOCK7(&ip->u_addr.ip6),
+			IP6_ADDR_BLOCK8(&ip->u_addr.ip6));
+}
+
+#else
+void
+print_ip(char *msg, ip_addr_t *ip)
+{
+	xil_printf(msg);
+	xil_printf("%d.%d.%d.%d\n\r", ip4_addr1(ip), ip4_addr2(ip),
+			ip4_addr3(ip), ip4_addr4(ip));
+}
+
+void
+print_ip_settings(ip_addr_t *ip, ip_addr_t *mask, ip_addr_t *gw)
+{
+
+	print_ip("Board IP: ", ip);
+	print_ip("Netmask : ", mask);
+	print_ip("Gateway : ", gw);
+}
+
+#endif
+
+int main()
+{
+	xil_printf("start");
+
+	sys_thread_new("main_thrd", (void(*)(void*))main_thread, 0,
+	                THREAD_STACKSIZE,
+	                DEFAULT_THREAD_PRIO);
+	vTaskStartScheduler();
+
+	while(1);
+
+	return 0;
+}
+
+void network_thread(void *p)
+{
+    struct netif *netif;
+    /* the mac address of the board. this should be unique per board */
+    unsigned char mac_ethernet_address[] = { 0x00, 0x0a, 0x35, 0x00, 0x01, 0x02 };
+#if LWIP_IPV6==0
+    ip_addr_t ipaddr, netmask, gw;
+#if LWIP_DHCP==1
+    int mscnt = 0;
+#endif
+#endif
+
+    netif = &server_netif;
+
+    xil_printf("\r\n\r\n");
+    xil_printf("-----lwIP Socket Mode CX9261  TEST server Application Version 2022.05.31------\r\n");
+
+#if LWIP_IPV6==0
+#if LWIP_DHCP==0
+    /* initliaze IP addresses to be used */
+    IP4_ADDR(&ipaddr,  192, 168, 1, 99);
+    IP4_ADDR(&netmask, 255, 255, 255,  0);
+    IP4_ADDR(&gw,      192, 168, 1, 1);
+#endif
+
+    /* print out IP settings of the board */
+
+#if LWIP_DHCP==0
+    print_ip_settings(&ipaddr, &netmask, &gw);
+    /* print all application headers */
+#endif
+
+#if LWIP_DHCP==1
+	ipaddr.addr = 0;
+	gw.addr = 0;
+	netmask.addr = 0;
+#endif
+#endif
+
+#if LWIP_IPV6==0
+    /* Add network interface to the netif_list, and set it as default */
+    if (!xemac_add(netif, &ipaddr, &netmask, &gw, mac_ethernet_address, PLATFORM_EMAC_BASEADDR)) {
+	xil_printf("Error adding N/W interface\r\n");
+	return;
+    }
+#else
+    /* Add network interface to the netif_list, and set it as default */
+    if (!xemac_add(netif, NULL, NULL, NULL, mac_ethernet_address, PLATFORM_EMAC_BASEADDR)) {
+	xil_printf("Error adding N/W interface\r\n");
+	return;
+    }
+
+    netif->ip6_autoconfig_enabled = 1;
+
+    netif_create_ip6_linklocal_address(netif, 1);
+    netif_ip6_addr_set_state(netif, 0, IP6_ADDR_VALID);
+
+    print_ip6("\n\rBoard IPv6 address ", &netif->ip6_addr[0].u_addr.ip6);
+#endif
+
+    netif_set_default(netif);
+
+    /* specify that the network if is up */
+    netif_set_up(netif);
+
+    /* start packet receive thread - required for lwIP operation */
+    sys_thread_new("xemacif_input_thread", (void(*)(void*))xemacif_input_thread, netif,
+            THREAD_STACKSIZE,
+            DEFAULT_THREAD_PRIO);
+
+#if LWIP_IPV6==0
+#if LWIP_DHCP==1
+    dhcp_start(netif);
+    while (1) {
+		vTaskDelay(DHCP_FINE_TIMER_MSECS / portTICK_RATE_MS);
+		dhcp_fine_tmr();
+		mscnt += DHCP_FINE_TIMER_MSECS;
+		if (mscnt >= DHCP_COARSE_TIMER_SECS*1000) {
+			dhcp_coarse_tmr();
+			mscnt = 0;
+		}
+	}
+#else
+    xil_printf("\r\n");
+    xil_printf("%20s %6s %s\r\n", "Server", "Port", "Connect With..");
+    xil_printf("%20s %6s %s\r\n", "--------------------", "------", "--------------------");
+
+    print_echo_app_header();
+    xil_printf("\r\n");
+    sys_thread_new("echod", echo_application_thread, 0,
+		THREAD_STACKSIZE,
+		DEFAULT_THREAD_PRIO);
+    vTaskDelete(NULL);
+#endif
+#else
+    print_echo_app_header();
+    xil_printf("\r\n");
+    sys_thread_new("echod",echo_application_thread, 0,
+		THREAD_STACKSIZE,
+		DEFAULT_THREAD_PRIO);
+    vTaskDelete(NULL);
+#endif
+    return;
+}
+
+int main_thread()
+{
+#if LWIP_DHCP==1
+	int mscnt = 0;
+#endif
+
+#ifdef XPS_BOARD_ZCU102
+	IicPhyReset();
+#endif
+
+	/* initialize lwIP before calling sys_thread_new */
+    lwip_init();
+    SpiPsInit(SPI_DEVICE_ID);
+    GpioInit(GPIO_DEVICE_ID);
+    AXIGpioInit();
+    XScuGicInit();
+    ConfigAXIGPIOIntr();
+    ExceptionInit();
+
+    XAxiDma_Init(xAxiDma0Get(),AXI_DMA_DEVCIE_ID0);
+    XAxiDma_Init(xAxiDma1Get(),AXI_DMA_DEVCIE_ID1);
+    XAxiDma_Init(xAxiDma2Get(),AXI_DMA_DEVCIE_ID2);
+    PackerRst();
+
+	/* cx9261a configuration */
+    peripheral_test();
+    cx3e04_config();
+//    cx9261a_710_config();
+//    frqhop_config(1);
+	int temp = cx3e04_read(0x03A);
+    /* any thread using lwIP should be created using sys_thread_new */
+    sys_thread_new("NW_THRD", network_thread, NULL,
+		THREAD_STACKSIZE,
+            DEFAULT_THREAD_PRIO);
+
+#if LWIP_IPV6==0
+#if LWIP_DHCP==1
+    while (1) {
+	vTaskDelay(DHCP_FINE_TIMER_MSECS / portTICK_RATE_MS);
+		if (server_netif.ip_addr.addr) {
+			xil_printf("DHCP request success\r\n");
+			print_ip_settings(&(server_netif.ip_addr), &(server_netif.netmask), &(server_netif.gw));
+			print_echo_app_header();
+			xil_printf("\r\n");
+			sys_thread_new("echod", echo_application_thread, 0,
+					THREAD_STACKSIZE,
+					DEFAULT_THREAD_PRIO);
+			break;
+		}
+		mscnt += DHCP_FINE_TIMER_MSECS;
+		if (mscnt >= 10000) {
+			xil_printf("ERROR: DHCP request timed out\r\n");
+			xil_printf("Configuring default IP of 192.168.1.100\r\n");
+			IP4_ADDR(&(server_netif.ip_addr),  192, 168, 1, 100);
+			IP4_ADDR(&(server_netif.netmask), 255, 255, 255,  0);
+			IP4_ADDR(&(server_netif.gw),  192, 168, 1, 1);
+			print_ip_settings(&(server_netif.ip_addr), &(server_netif.netmask), &(server_netif.gw));
+			/* print all application headers */
+			xil_printf("\r\n");
+			xil_printf("%20s %6s %s\r\n", "Server", "Port", "Connect With..");
+			xil_printf("%20s %6s %s\r\n", "--------------------", "------", "--------------------");
+
+			print_echo_app_header();
+			xil_printf("\r\n");
+			sys_thread_new("echod", echo_application_thread, 0,
+					THREAD_STACKSIZE,
+					DEFAULT_THREAD_PRIO);
+			break;
+		}
+	}
+#endif
+#endif
+    vTaskDelete(NULL);
+    return 0;
+}

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_HOP/platform_config.h

@@ -0,0 +1,10 @@
+#ifndef __PLATFORM_CONFIG_H_
+#define __PLATFORM_CONFIG_H_
+
+
+#define PLATFORM_EMAC_BASEADDR XPAR_XEMACPS_0_BASEADDR
+
+#define PLATFORM_ZYNQ 
+
+
+#endif

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_HOP/rx_wideband_qec.c

@@ -0,0 +1,61 @@
+/*
+ * wideband_qec.c
+ *
+ *  Created on: 2023Äê11ÔÂ30ÈÕ
+ *      Author: cxlab
+ */
+
+#include "xilinx_io.h"
+#include "sleep.h"
+#include "math.h"
+void rxFFTCalib(int lo, int fs,int ref, int firLength, int chan) {
+	u8 rx_data;
+	SpiPs_write_read1(0x000, chan == 1 ? 0x12 : 0x22,&rx_data);
+	SpiPs_write_read1(0x128, 0x00,&rx_data);
+	SpiPs_write_read1(0x11B, 0x01,&rx_data);
+	SpiPs_write_read1(0x11E, 0x01,&rx_data);
+    configTxNcoFreq(0, fs);
+    SpiPs_write_read1(0x161, 0x00,&rx_data);
+    SpiPs_write_read1(0x162, 0x00,&rx_data);
+    SpiPs_write_read1(0x162, 0x01,&rx_data);
+    SpiPs_write_read1(0x161, 0x01,&rx_data);
+    SpiPs_write_read1(0x000, chan == 1 ? 0x12 : chan == 2 ? 0x22 : 0x32,&rx_data);
+    SpiPs_write_read1(0x102, 0x03,&rx_data);
+    SpiPs_write_read1(0x102, 0xFF,&rx_data);
+    SpiPs_write_read1(0x15C, 0x00,&rx_data);
+    SpiPs_write_read1(0x160, 0x01,&rx_data);
+    SpiPs_write_read1(0x77E, chan == 1 ? 0x50 : chan == 2 ? 0x0A : 0x03,&rx_data);
+    SpiPs_write_read1(0x09B, 0x01,&rx_data);  // TXPLL4
+    SpiPs_write_read1(0x09D, firLength,&rx_data);
+    SpiPs_write_read1(0x096, ((u32)round(lo) >> 8) & 0xFF,&rx_data);
+    SpiPs_write_read1(0x097, (u32)round(lo) & 0xFF,&rx_data);
+    SpiPs_write_read1(0x098, ((u32)round(ref * 10) >> 8) & 0xFF,&rx_data);
+    SpiPs_write_read1(0x099, (u32)round(ref * 10) & 0xFF,&rx_data);
+    SpiPs_write_read1(0x09E, ((u32)round(fs * 100) >> 8) & 0xFF,&rx_data);
+    SpiPs_write_read1(0x09F, (u32)round(fs * 100) & 0xFF,&rx_data);
+    SpiPs_write_read1(0x09C, chan,&rx_data);
+    while (1) {
+        if (SpiPs_write_read2(0x0B3,0x00,&rx_data) == 5)
+            break;
+        usleep(10000);
+    }
+    SpiPs_write_read1(0x09C, 0x00,&rx_data);
+    SpiPs_write_read1(0x15C, 0x01,&rx_data);
+    SpiPs_write_read1(0x77E, 0x00,&rx_data);
+
+    //ͨµÀʱÖÓÀ´Ô´
+    u8 r77D=0xC0;
+    u8 r775=0x24;
+    u8 r6C3=0x00;
+    SpiPs_write_read1(0x77D, r77D,&rx_data);
+    SpiPs_write_read1(0x775, r775,&rx_data);
+    SpiPs_write_read1(0x6C3, r6C3,&rx_data);
+}
+
+
+void configDcCalib(int dcCalibEnable,int dcCalibLength) {
+	u8 rx_data;
+	SpiPs_write_read1(0x109, dcCalibEnable ? 0x11 : 0x00,&rx_data);
+	SpiPs_write_read1(0x10A, (dcCalibLength) << 4,&rx_data);
+	SpiPs_write_read1(0x11F, dcCalibEnable ? 0x33 : 0x73,&rx_data);
+}

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_HOP/sd.c

@@ -0,0 +1,178 @@
+#include "sd.h"
+/************************** Variable Definitions *****************************/
+static FIL fil;		/* File object */
+static FATFS fatfs;
+/*
+ * To test logical drive 0, FileName should be "0:/<File name>" or
+ * "<file_name>". For logical drive 1, FileName should be "1:/<file_name>"
+ */
+static char FileName[32] = "BOOT.bin";
+static char *SD_File;
+
+
+//#define BUFF_SIZE sizeof(image_data)
+#define BUFF_SIZE 0x2000000
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+u8 DestinationAddress[10*1024];
+#pragma data_alignment = 32
+u8 SourceAddress[10*1024];
+#else
+//u8 DestinationAddress[10*1024] __attribute__ ((aligned(32)));
+//u8 SourceAddress[10*1024] __attribute__ ((aligned(32)));
+
+u8 DestinationAddress[BUFF_SIZE] __attribute__ ((aligned(32)));
+u8 SourceAddress[BUFF_SIZE] __attribute__ ((aligned(32)));
+#endif
+
+#define TEST 7
+
+
+
+/*****************************************************************************/
+/**
+*
+* File system example using SD driver to write to and read from an SD card
+* in polled mode. This example creates a new file on an
+* SD card (which is previously formatted with FATFS), write data to the file
+* and reads the same data back to verify.
+*
+* @param	None
+*
+* @return	XST_SUCCESS if successful, otherwise XST_FAILURE.
+*
+* @note		None
+*
+******************************************************************************/
+int FfsSdWrite(u8*image_data, u32 FileSize)
+{
+	int error_flag = 0;
+	FRESULT Res;
+	UINT NumBytesRead;
+	UINT NumBytesWritten;
+	u32 BuffCnt;
+	BYTE work[FF_MAX_SS];
+//	u32 FileSize = (8*1024);
+//	u32 FileSize = sizeof(image_data);
+	/*
+	 * To test logical drive 0, Path should be "0:/"
+	 * For logical drive 1, Path should be "1:/"
+	 */
+	TCHAR *Path = "0:/";
+	u8 checksum = 0;
+
+	for(BuffCnt = 0; BuffCnt < FileSize; BuffCnt++){
+//		SourceAddress[BuffCnt] = TEST + BuffCnt;
+		SourceAddress[BuffCnt] = image_data[BuffCnt];
+		checksum = checksum + image_data[BuffCnt];
+	}
+	xil_printf("checksum is 0x%x.",checksum);
+
+
+	/*
+	 * Register volume work area, initialize device
+	 */
+	Res = f_mount(&fatfs, Path, 0);
+
+	if (Res != FR_OK) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Path - Path to logical driver, 0 - FDISK format.
+	 * 0 - Cluster size is automatically determined based on Vol size.
+	 */
+	Res = f_mkfs(Path, FM_FAT32, 0, work, sizeof work);
+	if (Res != FR_OK) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Open file with required permissions.
+	 * Here - Creating new file with read/write permissions. .
+	 * To open file with write permissions, file system should not
+	 * be in Read Only mode.
+	 */
+	SD_File = (char *)FileName;
+
+	Res = f_open(&fil, SD_File, FA_CREATE_ALWAYS | FA_WRITE | FA_READ);
+	if (Res) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Pointer to beginning of file .
+	 */
+	Res = f_lseek(&fil, 0);
+	if (Res) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Write data to file.
+	 */
+	Res = f_write(&fil, (const void*)SourceAddress, FileSize,
+			&NumBytesWritten);
+	if (Res) {
+		return XST_FAILURE;
+	}
+	/*
+	 * Close file.
+	 */
+	Res = f_close(&fil);
+	if (Res) {
+		return XST_FAILURE;
+	}
+	Res = f_open(&fil, SD_File, FA_READ);
+	if (Res) {
+		return XST_FAILURE;
+	}
+	/*
+	 * Pointer to beginning of file .
+	 */
+	Res = f_lseek(&fil, 0);
+	if (Res) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Read data from file.
+	 */
+	Res = f_read(&fil, (void*)DestinationAddress, FileSize,
+			&NumBytesRead);
+	if (Res) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Data verification
+	 */
+	for(BuffCnt = 0; BuffCnt < FileSize; BuffCnt++){
+		if(SourceAddress[BuffCnt] != DestinationAddress[BuffCnt]){
+//			return XST_FAILURE;
+			error_flag = 1;
+			xil_printf('Data check error.');
+		}
+	}
+
+	/*
+	 * Close file.
+	 */
+	Res = f_close(&fil);
+	if (Res) {
+		return XST_FAILURE;
+	}
+
+	if(error_flag){
+		return XST_FAILURE;
+	}
+
+//	Res = f_unmount(Path);
+//	if (Res) {
+//		return XST_FAILURE;
+//	}
+//
+//	sleep(5);
+
+	return XST_SUCCESS;
+}

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_HOP/sd.h

@@ -0,0 +1,9 @@
+/***************************** Include Files *********************************/
+#include "xparameters.h"	/* SDK generated parameters */
+#include "xsdps.h"		/* SD device driver */
+#include "xil_printf.h"
+#include "ff.h"
+#include "xil_cache.h"
+#include "xplatform_info.h"
+/************************** Function Prototypes ******************************/
+int FfsSdWrite(u8*image_data, u32 FileSize);

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_HOP/tx_bisection.c

@@ -0,0 +1,74 @@
+/*
+ * tx_bisection.c
+ *
+ *  Created on: 2023Äê12ÔÂ1ÈÕ
+ *      Author: cxlab
+ */
+
+
+#include "xilinx_io.h"
+#include "sleep.h"
+#include "math.h"
+
+void txBisectionQecCalib(int f0, int fs) {
+	u8 rx_data;
+	SpiPs_write_read1(0x02E, 0x03,&rx_data);
+	SpiPs_write_read1(0x128, 0x11,&rx_data);
+	SpiPs_write_read1(0x11E, 0x01,&rx_data);
+	SpiPs_write_read1(0x77E, 0x24,&rx_data);
+	SpiPs_write_read1(0x11F, 0x01,&rx_data);
+	SpiPs_write_read1(0x121, 0x02,&rx_data);
+	SpiPs_write_read1(0x11B, 0x01,&rx_data);
+	SpiPs_write_read1(0x161, 0x01,&rx_data);
+	SpiPs_write_read1(0x162, 0x01,&rx_data);
+	SpiPs_write_read1(0x163, 0x00,&rx_data);
+    configTxNcoFreq(f0, fs * 4);
+    SpiPs_write_read1(0xA2D, 0x02,&rx_data);
+    SpiPs_write_read1(0xA07, 0x00,&rx_data);
+    SpiPs_write_read1(0xA08, 0x0F,&rx_data);
+    SpiPs_write_read1(0xA1C, 0x01,&rx_data);
+    configRxNcoFreq(f0 * 2, fs);
+    SpiPs_write_read1(0x186, 0x01,&rx_data);
+    SpiPs_write_read1(0x763, 0x34,&rx_data);
+    SpiPs_write_read1(0x76D, 0x34,&rx_data);
+    SpiPs_write_read1(0x101, 0xEF,&rx_data);
+    SpiPs_write_read1(0x101, 0xFF,&rx_data);
+    SpiPs_write_read1(0x800, 0x00,&rx_data);
+    SpiPs_write_read1(0x81A, 0xF7,&rx_data);
+    SpiPs_write_read1(0x81B, 0x34,&rx_data);
+    SpiPs_write_read1(0x81C, 0x33,&rx_data);
+    SpiPs_write_read1(0x81D, 0x12,&rx_data);
+    SpiPs_write_read1(0x81E, 0x00,&rx_data);
+    SpiPs_write_read1(0x81F, 0xFF,&rx_data);
+    SpiPs_write_read1(0x820, 0x00,&rx_data);
+    SpiPs_write_read1(0x821, 0xFF,&rx_data);
+    SpiPs_write_read1(0x800, 0x80,&rx_data);
+    SpiPs_write_read1(0x800, 0x81,&rx_data);
+    usleep(100000);
+    SpiPs_write_read1(0x77E, 0x00,&rx_data);
+}
+
+void txBisectionDcCalib(int f0, int fs) {
+	u8 rx_data;
+	SpiPs_write_read1(0x77E, 0x24,&rx_data);
+	SpiPs_write_read1(0x11F, 0x03,&rx_data);
+	SpiPs_write_read1(0x121, 0x02,&rx_data);
+	SpiPs_write_read1(0x11B, 0x01,&rx_data);
+	SpiPs_write_read1(0x11E, 0x01,&rx_data);
+	SpiPs_write_read1(0x161, 0x01,&rx_data);
+	SpiPs_write_read1(0x162, 0x01,&rx_data);
+    configTxNcoFreq(f0, fs * 4);
+    SpiPs_write_read1(0xA2D, 0x02,&rx_data);
+    SpiPs_write_read1(0xA07, 0x00,&rx_data);
+    SpiPs_write_read1(0xA08, 0x0F,&rx_data);
+    SpiPs_write_read1(0xA1C, 0x01,&rx_data);
+    configRxNcoFreq(f0, fs);
+    SpiPs_write_read1(0x81A, 0xF7,&rx_data);
+    SpiPs_write_read1(0x81B, 0x44,&rx_data);
+    SpiPs_write_read1(0x81C, 0x33,&rx_data);
+    SpiPs_write_read1(0x81D, 0x14,&rx_data);
+    SpiPs_write_read1(0x800, 0x80,&rx_data);
+    SpiPs_write_read1(0x800, 0x82,&rx_data);
+    usleep(500000);
+    SpiPs_write_read1(0x77E, 0x00,&rx_data);
+}

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_HOP/xilinx_io.c

@@ -0,0 +1,905 @@
+/*
+ * xilinx_io.c
+ *
+ *  Created on: 2021年9月6日
+ *      Author: cxlab
+ */
+
+
+#include "sleep.h"
+#include "math.h"
+#include "xilinx_io.h"		/* SPI device driver */
+
+static XSpiPs SpiInstance;
+XGpioPs Gpio;	/* The driver instance for GPIO Device. */
+XGpio            axi_gpio_inst;                 //PL 端 AXI GPIO 驱动实例
+XScuGic          scugic_inst;                   //中断控制器  驱动实例
+XScuGic_Config * scugic_cfg_ptr;                //中断控制器  配置信息
+int hop_flag,hop_intr_flag;
+static int spi_select_value=0;
+
+XAxiDma AxiDma0,AxiDma1,AxiDma2;
+
+XAxiDma* xAxiDma0Get(void){
+	return &AxiDma0;
+}
+
+XAxiDma* xAxiDma1Get(void){
+	return &AxiDma1;
+}
+
+XAxiDma* xAxiDma2Get(void){
+	return &AxiDma2;
+}
+void AXIGpioInit(void){
+    XGpio_Initialize(&axi_gpio_inst, AXI_GPIO_ID);
+   //配置 PL AXI GPIO
+    XGpio_SetDataDirection(&axi_gpio_inst, 1, 1); //设置 AXI GPIO 通道 1 为输入
+    XGpio_InterruptEnable(&axi_gpio_inst, KEY_MASK);        //使能通道 1 中断
+	XGpio_InterruptGlobalEnable(&axi_gpio_inst);            //使能 AXI GPIO 全局中断
+}
+
+void ConfigAXIGPIOIntr(void){
+	//设置中断优先级和触发类型(高电平触发)
+	XScuGic_SetPriorityTriggerType(&scugic_inst, GPIO_INT_ID, 0xA0, 0x3);
+	//关联中断 ID 和中断处理函数
+	XScuGic_Connect(&scugic_inst, GPIO_INT_ID, axi_gpio_handler, &axi_gpio_inst);
+	//使能 AXI GPIO 中断
+	XScuGic_Enable(&scugic_inst, GPIO_INT_ID);
+}
+void axi_gpio_handler(void *CallbackRef){
+	XGpio *GpioPtr = (XGpio *)CallbackRef;
+//	print("Interrupt Detected!\n");
+	GpioWritePin(hop,0x01);
+	XGpio_InterruptDisable(GpioPtr, KEY_MASK);              //关闭 AXI GPIO 中断使能
+//    u32 r=XGpio_DiscreteRead(GpioPtr, 1);
+//    if(r == 1){
+    	frqhop_config(hop_flag);
+//    }else{
+//    	print("Interrupt unvalid!\n");
+//    }
+	XGpio_InterruptClear(GpioPtr, KEY_MASK);                //清除中断
+	XGpio_InterruptEnable(GpioPtr, KEY_MASK);               //使能 AXI GPIO 中断
+	GpioWritePin(hop,0x00);
+}
+void frqhop_flag(int frqhop_flag){
+	u8 rx_data;
+	hop_flag = frqhop_flag;
+	GpioSetPinDir(hop,GPIO_DIR_OUTPUT);
+	GpioWritePin(hop,0x01);
+	SpiPs_write_read2(0x615,0x00,&rx_data);
+	GpioWritePin(hop,0x00);
+}
+
+void ExceptionInit(void){
+	//设置并打开中断异常处理功能
+	Xil_ExceptionInit();
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)XScuGic_InterruptHandler, &scugic_inst);
+	Xil_ExceptionEnable();
+}
+void XScuGicInit(void){
+	scugic_cfg_ptr = XScuGic_LookupConfig(SCUGIC_ID);
+	XScuGic_CfgInitialize(&scugic_inst, scugic_cfg_ptr, scugic_cfg_ptr->CpuBaseAddress);
+}
+
+int SpiPsInit(u16 SpiDeviceId){
+	int Status;
+	XSpiPs_Config *SpiConfig;
+	/*
+	 * Initialize the SPI driver so that it's ready to use
+	 */
+	SpiConfig = XSpiPs_LookupConfig(SpiDeviceId);
+	if (NULL == SpiConfig) {
+		return XST_FAILURE;
+	}
+	Status = XSpiPs_CfgInitialize((&SpiInstance), SpiConfig,
+					SpiConfig->BaseAddress);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Perform a self-test to check hardware build
+	 */
+	Status = XSpiPs_SelfTest((&SpiInstance));
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+	/*
+	 * The SPI device is a slave by default and the clock phase
+	 * have to be set according to its master. In this example, CPOL is set
+	 * to quiescent high and CPHA is set to 1.
+	 */
+
+	XSpiPs_SetOptions((&SpiInstance), (XSPIPS_CR_CPHA_MASK) |
+				XSPIPS_MASTER_OPTION |
+				XSPIPS_FORCE_SSELECT_OPTION);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+	XSpiPs_SetClkPrescaler((&SpiInstance), XSPIPS_CLK_PRESCALE_8);
+	/*
+	 * Set the Rx FIFO Threshold to the Max Data
+	 */
+//	XSpiPs_SetRXWatermark((&SpiInstance),MAX_DATA);
+	/*
+	 * Enable the device.
+	 */
+	XSpiPs_Enable((&SpiInstance));
+
+return XST_SUCCESS;
+}
+
+int cx3e04_write(int addr , int value)
+{
+	Xil_Out32(AXI4_LITE0_SPI_BASEADDR+addr*4,value);
+	return 1;
+}
+
+int cx3e04_read(int addr)
+{
+	return Xil_In32(AXI4_LITE0_SPI_BASEADDR+addr*4);
+}
+
+int cx9261a_write(int addr , int value)
+{
+	Xil_Out32(AXI4_LITE1_SPI_BASEADDR+addr*4,value);
+	return 1;
+}
+
+int cx9261a_read(int addr)
+{
+	return Xil_In32(AXI4_LITE1_SPI_BASEADDR+addr*4);
+}
+
+void cx3e04_config(void)
+{
+	//城芯科技CX3E04
+	//Common
+	cx3e04_write(0x000,0x12);
+	cx3e04_write(0x002,0x38);
+	cx3e04_write(0x038,0x01);
+	cx3e04_write(0x003,0x30);
+	cx3e04_write(0x039,0x00);
+	//CLK
+	//clk lvds en
+	cx3e04_write(0x011,0x7F);
+	cx3e04_write(0x012,0x34);
+	cx3e04_write(0x036,0x7F);
+	cx3e04_write(0x01A,0x4B);
+	cx3e04_write(0x013,0x04);
+	cx3e04_write(0x014,0x04);
+	cx3e04_write(0x004,0x00);
+	cx3e04_write(0x008,0x00);
+	cx3e04_write(0x009,0x00);
+	cx3e04_write(0x015,0x04);
+	cx3e04_write(0x016,0x04);
+	cx3e04_write(0x005,0x00);
+	cx3e04_write(0x00A,0x00);
+	cx3e04_write(0x00B,0x00);
+	cx3e04_write(0x017,0x04);
+	cx3e04_write(0x018,0x04);
+	cx3e04_write(0x006,0x00);
+	cx3e04_write(0x00C,0x00);
+	cx3e04_write(0x00D,0x00);
+	cx3e04_write(0x019,0x04);
+	cx3e04_write(0x007,0x00);
+	cx3e04_write(0x00E,0x00);
+	cx3e04_write(0x00F,0x00);
+	cx3e04_write(0x010,0x00);
+	cx3e04_write(0x029,0x00);
+	cx3e04_write(0x02A,0x00);
+	//SYNC
+	//sync lvds en
+	cx3e04_write(0x033,0x7F);
+	cx3e04_write(0x034,0x34);
+	cx3e04_write(0x035,0x7F);
+	cx3e04_write(0x032,0x03);
+	//sync inner div
+	cx3e04_write(0x03A,0x00);
+	cx3e04_write(0x03B,0x00);
+	cx3e04_write(0x03A,0x01);
+	cx3e04_write(0x03B,0xFF);//512分频
+	cx3e04_write(0x03C,0x21);
+	cx3e04_write(0x03D,0x80);
+	cx3e04_write(0x02B,0x04);
+	cx3e04_write(0x02C,0x04);
+	cx3e04_write(0x01B,0x00);
+	cx3e04_write(0x01C,0x00);
+	cx3e04_write(0x022,0x00);
+	cx3e04_write(0x023,0x00);
+	cx3e04_write(0x02D,0x04);
+	cx3e04_write(0x02E,0x04);
+	cx3e04_write(0x01D,0x00);
+	cx3e04_write(0x01E,0x00);
+	cx3e04_write(0x024,0x00);
+	cx3e04_write(0x025,0x00);
+	cx3e04_write(0x02F,0x04);
+	cx3e04_write(0x030,0x04);
+	cx3e04_write(0x01F,0x00);
+	cx3e04_write(0x020,0x00);
+	cx3e04_write(0x026,0x00);
+	cx3e04_write(0x027,0x00);
+	cx3e04_write(0x031,0x04);
+	cx3e04_write(0x021,0x00);
+	cx3e04_write(0x028,0x00);
+	//偏置电流
+	cx3e04_write(0x040,0xFF);
+	cx3e04_write(0x041,0xFF);
+	cx3e04_write(0x042,0xFF);
+	cx3e04_write(0x043,0xF0);
+	cx3e04_write(0x044,0xFF);
+	cx3e04_write(0x045,0xFF);
+	cx3e04_write(0x046,0xFF);
+	cx3e04_write(0x047,0xF0);
+	//Others
+	cx3e04_write(0x037,0x07);
+}
+
+//int SpiPs_write_read(u8 cmd, u16 addr,u8 data,u8 * rx_data){
+int SpiPs_write_read(u8 * data,u8 * rx_data){
+	int Status;
+	u8 rx_buffer[3];
+
+	if(spi_select_value == 0){
+		rx_buffer[0]= *data;
+		rx_buffer[1]= *(data+1);
+		rx_buffer[2]= *(data+2);
+		if(rx_buffer[0] >= 128){
+			cx9261a_write((rx_buffer[0]-128)*256+rx_buffer[1],rx_buffer[2]);
+		}else{
+			*rx_data=cx9261a_read(rx_buffer[0]*256+rx_buffer[1]);
+		}
+	}else{
+
+			XSpiPs_SetSlaveSelect((&SpiInstance),0x00);
+
+			Status = XSpiPs_PolledTransfer((&SpiInstance),data,rx_buffer,3);
+
+			*rx_data = rx_buffer[2];
+
+	}
+
+return 0;
+}
+int SpiPs_write_read1(u16 addr,u8 data,u8 * rx_data){
+	u8 rx_data1;
+	u16 temp;
+	u8 rx_buffer[3];
+
+	temp= addr&0x00ff;
+	rx_buffer[0]= temp/256+128;
+	rx_buffer[1]= addr&0x00ff;
+	rx_buffer[2]= data;
+
+	if(spi_select_value == 0){
+		cx9261a_write(addr,data);
+	}else{
+
+		SpiPs_write_read((u8 *)&rx_buffer,&rx_data1);
+		*rx_data = rx_data1;
+	}
+
+return 0;
+}
+int SpiPs_write_read2(u16 addr,u8 data,u8 * rx_data){
+	u8 rx_data1;
+	u16 temp;
+	u8 rx_buffer[3];
+
+	temp= addr&0x00ff;
+	rx_buffer[0]= temp/256;
+	rx_buffer[1]= addr&0x00ff;
+	rx_buffer[2]= data;
+
+	if(spi_select_value == 0){
+		*rx_data=cx9261a_read(addr);
+	}else{
+		SpiPs_write_read((u8 *)&rx_buffer,&rx_data1);
+		*rx_data = rx_data1;
+	}
+
+return 0;
+}
+
+int GpioInit(u16 DeviceId)
+{
+	int Status;
+	XGpioPs_Config *ConfigPtr;
+	/* Initialize the GPIO driver. */
+	ConfigPtr = XGpioPs_LookupConfig(DeviceId);
+	Status = XGpioPs_CfgInitialize(&Gpio, ConfigPtr,
+					ConfigPtr->BaseAddr);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+	return XST_SUCCESS;
+}
+
+int GpioSetPinDir(u32 Pin,u32 Direction){
+	XGpioPs_SetDirectionPin((&Gpio),GPIO_EMIO_OFFSET + Pin,Direction);
+	return 0;
+}
+int GpioWritePin(u32 Pin,u32 data){
+	XGpioPs_SetOutputEnablePin(&Gpio, GPIO_EMIO_OFFSET + Pin, 1);
+	XGpioPs_WritePin((&Gpio),GPIO_EMIO_OFFSET + Pin,data);
+	return 0;
+}
+
+int GpioReadPin(u32 Pin){
+	return XGpioPs_ReadPin((&Gpio),GPIO_EMIO_OFFSET + Pin);
+}
+
+void DeviceRst(void){
+	GpioWritePin(NRST,0);
+	GpioWritePin(NRST,1);
+}
+
+int XAxiDma_Init(XAxiDma* AxiDma,u16 DeviceId){
+
+	XAxiDma_Config *CfgPtr;
+	int Status;
+	/* Initialize the XAxiDma device.
+	 */
+	CfgPtr = XAxiDma_LookupConfig(DeviceId);
+	if (!CfgPtr) {
+		xil_printf("No config found for %d\r\n", DeviceId);
+		return XST_FAILURE;
+	}
+
+	Status = XAxiDma_CfgInitialize(AxiDma, CfgPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Initialization failed %d\r\n", Status);
+		return XST_FAILURE;
+	}
+
+	if(XAxiDma_HasSg(AxiDma)){
+		xil_printf("Device configured as SG mode \r\n");
+		return XST_FAILURE;
+	}
+
+	/* Disable interrupts, we use polling mode
+	 */
+	XAxiDma_IntrDisable(AxiDma, XAXIDMA_IRQ_ALL_MASK,
+						XAXIDMA_DEVICE_TO_DMA);
+	XAxiDma_IntrDisable(AxiDma, XAXIDMA_IRQ_ALL_MASK,
+						XAXIDMA_DMA_TO_DEVICE);
+return 0;
+}
+
+int XAxiDmaCapture(XAxiDma* AxiDma,u32 data_length){
+	int Status;
+	u8 *TxBufferPtr;
+	u32 MAX_PKT_LEN;
+	MAX_PKT_LEN = data_length;
+	TxBufferPtr = (u8 *)TX_BUFFER_BASE;
+	Xil_DCacheFlushRange((UINTPTR)TxBufferPtr, MAX_PKT_LEN);
+	Status = XAxiDma_Busy(AxiDma,XAXIDMA_DEVICE_TO_DMA);
+	Status = XAxiDma_Busy(AxiDma,XAXIDMA_DMA_TO_DEVICE);
+	XAxiDma_Reset(AxiDma);
+	Status = XAxiDma_ResetIsDone(AxiDma);
+	Status = XAxiDma_Busy(AxiDma,XAXIDMA_DEVICE_TO_DMA);
+	Status = XAxiDma_Busy(AxiDma,XAXIDMA_DMA_TO_DEVICE);
+
+	Status = XAxiDma_SimpleTransfer(AxiDma,(UINTPTR) TxBufferPtr,MAX_PKT_LEN*8, XAXIDMA_DEVICE_TO_DMA);
+	SetPacketSize(AxiDma,MAX_PKT_LEN);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	u32 start_TickCount,current_TickCount=0;
+	start_TickCount = sys_now();
+	u32 offset= 0;
+	//never come out ,reason is stream does't have tlast.Need a module to pack excatly the same length defined in para.
+	while ((offset< 500)&&(XAxiDma_Busy(AxiDma,XAXIDMA_DEVICE_TO_DMA))) {
+		Status = XAxiDma_Busy(AxiDma,XAXIDMA_DEVICE_TO_DMA);
+
+		current_TickCount =sys_now();
+		offset = current_TickCount-start_TickCount;
+//		xil_printf("offset: %d\r\n", offset);
+	}
+	/*
+	u64 offset= 0;
+	//never come out ,reason is stream does't have tlast.Need a module to pack excatly the same length defined in para.
+	while ((offset> 100000)||(XAxiDma_Busy(AxiDma,XAXIDMA_DEVICE_TO_DMA))) {
+		Status = XAxiDma_Busy(AxiDma,XAXIDMA_DEVICE_TO_DMA);
+	}*/
+	return 0;
+}
+
+
+
+int SetPacketSize(XAxiDma* AxiDma,u32 length){
+
+	UINTPTR Addr;
+	if(AxiDma == xAxiDma0Get())
+		Addr = PACKER_BASEADDR0;
+	else if(AxiDma == xAxiDma1Get())
+		Addr = PACKER_BASEADDR1;
+	else
+		Addr = PACKER_BASEADDR2;
+	xil_printf("addr %x .\n",Addr);
+	Xil_Out32(Addr,0);
+	xil_printf("PACKER_BASEADDR DATA %d .\n",Xil_In32(Addr));
+	Xil_Out32(Addr+4,length);
+	xil_printf("PACKER_BASEADDR +4 DATA %d .\n",Xil_In32(Addr + 4));
+	Xil_Out32(Addr,1);
+	xil_printf("PACKER_BASEADDR DATA %d .\n",Xil_In32(Addr));
+	return  0;
+}
+int DownloadWave(u8 * data){
+	u32 * buffer;
+	u64 addr;
+	int i;
+	buffer =  (u32 *) data;
+	addr = BRAM_BASEADDR;
+	for(i=0;i<WAVELENGTH;i++){
+		Xil_Out32(addr+i*4,* (buffer +i));
+//		Xil_Out32(addr+i*4,0x11223344);
+//		xil_printf("ADDR 0x%x DATA 0x%x.\r\n",(buffer +i), * (buffer +i));
+	}
+	addr = BRAM_BASEADDR_1;
+		for(i=0;i<WAVELENGTH;i++){
+			Xil_Out32(addr+i*4,* (buffer +i));
+//			Xil_Out32(addr+i*4,0x11223344);
+//			xil_printf("ADDR 0x%x DATA 0x%x.\r\n",(buffer +i), * (buffer +i));
+		}
+	return 0;
+}
+void dbg_printf( const char8 *ctrl1, ...){
+#ifdef DBGLOG
+	xil_printf( ctrl1 );
+#endif
+}
+void PackerRst(void){
+    GpioSetPinDir(0x03,GPIO_DIR_OUTPUT);
+    GpioWritePin(3,0x0);//dma_axis_rx_rstn
+    GpioWritePin(3,0x01);//dma_axis_rx_rstn
+    GpioSetPinDir(0x09,GPIO_DIR_OUTPUT);
+    GpioWritePin(9,0x01);//data_valid
+}
+int peripheral_test(void){
+u8 spi_test;
+u8 Gpio_test;
+u8 BRAM_test;
+u8 DDR_test;
+//	SPI TEST
+u8 rx_data;
+xil_printf("start spi test.\r\n");
+u8 spi_wr_buff[3]={0x87,0x82,0x5A};
+u8 spi_rd_buff[3]={0x07,0x82,0x00};
+SpiPs_write_read(spi_wr_buff,&rx_data);
+SpiPs_write_read(spi_rd_buff,&rx_data);
+if(rx_data==spi_wr_buff[2])
+{
+	xil_printf("spi test successful.\r\n");
+	spi_test = 1;
+}else
+{
+	xil_printf("spi test unsuccessful.\r\n");
+	spi_test = 0;
+}
+
+
+//BRAM TEST
+xil_printf("start bram test.\r\n");
+BRAM_test = 1;
+//for (int i=0;i<8192;i++){
+//	Xil_Out32(XPAR_BRAM_0_BASEADDR + 4*i,i);
+//	if(i != Xil_In32(XPAR_BRAM_0_BASEADDR + 4*i)){
+////		xil_printf("BRAM ERROR,ADDR %x DATA %d read back is %d.\r\n",XPAR_BRAM_0_BASEADDR + 4*i,i,Xil_In32(XPAR_BRAM_0_BASEADDR + 4*i));
+//		BRAM_test = 0;
+//	}
+////	else{
+////		xil_printf("BRAM PASS,ADDR %x DATA %d read back is %d.\r\n",XPAR_BRAM_0_BASEADDR + 4*i,i,Xil_In32(XPAR_BRAM_0_BASEADDR + 4*i));
+////	}
+//}
+
+//MIG TEST
+xil_printf("start mig test.\r\n");
+DDR_test = 1;
+for (int i=0;i<2048;i++){
+	Xil_Out32(TX_BUFFER_BASE + 4*i,i);
+	if(i != Xil_In32(TX_BUFFER_BASE + 4*i)){
+//		xil_printf("MIG ERROR,ADDR %x DATA %d read back is %d.\r\n",TX_BUFFER_BASE + 4*i,i,Xil_In32(TX_BUFFER_BASE + 4*i));
+		DDR_test = 0;
+	}
+//	else{
+//		xil_printf("BRAM11 PASS,ADDR %x DATA %d read back is %d.\r\n",TX_BUFFER_BASE + 4*i,i,Xil_In32(TX_BUFFER_BASE + 4*i));
+//	}
+}
+
+// GPIO TEST
+int Gpio_data;
+xil_printf("start gpio test.\r\n");
+GpioSetPinDir(NRST,GPIO_DIR_OUTPUT);
+GpioWritePin(NRST,0x00);
+GpioWritePin(NRST,0x01);
+GpioSetPinDir(rst,GPIO_DIR_OUTPUT);
+GpioWritePin(rst,0x01);
+GpioWritePin(rst,0x00);
+GpioSetPinDir(aresetn_0,GPIO_DIR_OUTPUT);
+GpioWritePin(aresetn_0,0x00);
+GpioWritePin(aresetn_0,0x01);
+GpioSetPinDir(aresetn_1,GPIO_DIR_OUTPUT);
+GpioWritePin(aresetn_1,0x00);
+GpioWritePin(aresetn_1,0x01);
+GpioSetPinDir(aresetn_2,GPIO_DIR_OUTPUT);
+GpioWritePin(aresetn_2,0x00);
+GpioWritePin(aresetn_2,0x01);
+GpioSetPinDir(debug_mode,GPIO_DIR_OUTPUT);
+GpioWritePin(debug_mode,0x00);
+GpioSetPinDir(cx3e04_rstn,GPIO_DIR_OUTPUT);
+GpioWritePin(cx3e04_rstn,0x01);
+GpioSetPinDir(spi_select,GPIO_DIR_OUTPUT);
+GpioWritePin(spi_select,spi_select_value&0xff);
+//GpioSetPinDir(test_temp,GPIO_DIR_INPUT);
+Gpio_data=GpioReadPin(aresetn_1);
+if(Gpio_data==1)
+{
+	xil_printf("GPIO test successful.\r\n");
+	Gpio_test = 1;
+}else
+{
+	xil_printf("GPIO test unsuccessful.\r\n");
+	Gpio_test = 0;
+}
+//GpioSetPinDir(test_temp,GPIO_DIR_OUTPUT);
+//GpioWritePin(test_temp,0x01);
+
+if((spi_test==1)&&(Gpio_test==1)&&(BRAM_test==1)&&(DDR_test==1))
+{
+	xil_printf("peripheral test successful.\r\n");
+	return 1;
+}else
+{
+	xil_printf("peripheral test unsuccessful.\r\n");
+	return 0;
+}
+
+}
+
+int spi_stack_in(u8 * data,struct spi_stack * spistack){
+	spistack->recv_buf[spistack->spi_write_num * 3 + 0] = *(data + 0);
+	spistack->recv_buf[spistack->spi_write_num * 3 + 1] = *(data + 1);
+	spistack->recv_buf[spistack->spi_write_num * 3 + 2] = *(data + 2);
+	spistack->spi_write_num = spistack->spi_write_num + 1;
+	if(spistack->spi_write_num >= SPI_STACK_LENGTH-1){
+		return 1;
+	}
+	else
+		return 0;
+}
+
+void spi_stack_out(struct spi_stack * spistack){
+
+	int i;
+	u8 rx_data;
+	for(i=0;i<spistack->spi_write_num;i++ ){
+	SpiPs_write_read((u8 *)&(spistack->recv_buf[i * 3]),&rx_data);
+	}
+	spistack->spi_write_num = 0;
+}
+
+int rom_read(u8 * data)
+{
+	int addr ;
+	addr = *(data + 0)*256+  *(data + 1);
+	return Xil_In32(BROM_BASEADDR+addr*4);
+}
+
+void trx_ch_pll_config(u8 pll_index)
+{
+	u8 rx_data;
+	u8 recv_buf[3]={0};
+	u32 trx_ch_pll_data;
+
+	if(pll_index==1){
+		trx_ch_pll_data = 0x00077DCF;
+	}else if(pll_index==2){
+		trx_ch_pll_data = 0x00077D0C;
+	}
+
+	recv_buf[0] =(trx_ch_pll_data>>16 & 0xff)|0x80 ;
+	recv_buf[1] = trx_ch_pll_data>>8 & 0xff;
+	recv_buf[2] = trx_ch_pll_data  & 0xff;
+	SpiPs_write_read(recv_buf,&rx_data);
+}
+
+u16 pll1_config_addr[] ={0x0620,0x061D,0x0B06,0x0B07,0x0B08,0x0B09,0x0B0A,0x061A,0x061B,0x061C,0x062A};
+u16 pll2_config_addr[] ={0x0642,0x063F,0x0B14,0x0B15,0x0B16,0x0B17,0x0B18,0x063C,0x063D,0x063E,0x064C};
+u16 pll3_config_addr[] ={0x0664,0x0661,0x0B22,0x0B23,0x0B24,0x0B25,0x0B26,0x065E,0x065F,0x0660,0x066E};
+u16 pll4_config_addr[] ={0x0686,0x0683,0x0B30,0x0B31,0x0B32,0x0B33,0x0B34,0x0680,0x0681,0x0682,0x0690};
+
+int PLL_config(u8 pll_index,double pll_frq)
+{
+
+	int i = 0,afc_cnt=0;
+	u16 pll_config_addr[11];
+	u16 afc_addr,lock_addr;
+	double ref=200;
+	u8 pllreg_buf[11];
+	u8 recv_buf[3];
+	u8 rx_data,pll_div;
+	u16 div_addr;
+
+	switch(pll_index){
+		case 1:for (i = 0; i < 11; i++){pll_config_addr[i] = pll1_config_addr[i];} afc_addr=0x0617;lock_addr=0x0635;break;
+		case 2:for (i = 0; i < 11; i++){pll_config_addr[i] = pll2_config_addr[i];} afc_addr=0x0639;lock_addr=0x0657;break;
+		case 3:for (i = 0; i < 11; i++){pll_config_addr[i] = pll3_config_addr[i];} afc_addr=0x065B;lock_addr=0x0679;break;
+		case 4:for (i = 0; i < 11; i++){pll_config_addr[i] = pll4_config_addr[i];} afc_addr=0x067D;lock_addr=0x069B;break;
+		default :;
+	}
+    //caculate pll frequence word
+	pll_frq_caculation_new(ref,pll_frq,(u8 *)&pllreg_buf);
+	for (i = 0; i < 11; i++)
+	{
+		recv_buf[0] = (pll_config_addr[i]>>8 & 0xff)|0x80 ;
+		recv_buf[1] =  pll_config_addr[i] & 0xff;
+		recv_buf[2] =  pllreg_buf[i] & 0xff;
+		SpiPs_write_read((u8 *)&recv_buf[0],&rx_data);
+	}
+    //afc pll
+	pll_div  = pllreg_buf[1];
+	div_addr = pll_config_addr[1];
+	recv_buf[0] = lock_addr>>8 & 0xff ;
+	recv_buf[1] = lock_addr & 0xff;
+	recv_buf[2] = 0x00;
+	rx_data = 0;
+	while(rx_data!=48){
+		PLL_afc(afc_addr,div_addr,pll_div);
+		SpiPs_write_read((u8 *)&recv_buf[0],&rx_data);
+		afc_cnt++;
+	}
+    return afc_cnt;
+	//xil_printf("afc lock count: %d.\r\n",afc_cnt);
+
+}
+
+void PLL_afc(u16 afc_addr,u16 div_addr,u8 pll_div){
+
+	u8 recv_buf[3];
+	u8 rx_data;
+	if(pll_div>=48){
+		recv_buf[0] = (div_addr>>8 & 0xff)|0x80 ;
+		recv_buf[1] =  div_addr & 0xff;
+		recv_buf[2] =  pll_div & 0x2f;
+		SpiPs_write_read((u8 *)&recv_buf[0],&rx_data);
+	}
+	recv_buf[0] = (afc_addr>>8 & 0xff)|0x80 ;
+	recv_buf[1] =  afc_addr & 0xff;
+	recv_buf[2] =  0x00;
+	SpiPs_write_read((u8 *)&recv_buf[0],&rx_data);
+	recv_buf[2] =  0x03;
+	SpiPs_write_read((u8 *)&recv_buf[0],&rx_data);
+	usleep(30);
+	if(pll_div>=48){
+		recv_buf[0] = (div_addr>>8 & 0xff)|0x80 ;
+		recv_buf[1] =  div_addr & 0xff;
+		recv_buf[2] =  pll_div & 0xff;
+		SpiPs_write_read((u8 *)&recv_buf[0],&rx_data);
+	}
+
+}
+
+int pll_frq_caculation(double ref,double pll_frq,u8 *reg_data){
+
+    u8 row,column;
+	int vco = pll_frq;
+	int div = 1;
+	while(vco < 7001){
+		vco = vco*2;
+	    div = div*2;
+	}
+	char  coreTable[7][4][3] =  {{{0x0C,0x30,0x08},{0x0B,0x30,0x09},{0x0C,0x30,0x05},{0x0D,0x30,0x08}},
+								 {{0x0C,0x30,0x0C},{0x0B,0x30,0x0E},{0x0C,0x30,0x08},{0x0D,0x30,0x0B}},
+								 {{0x0C,0x20,0x10},{0x0B,0x20,0x10},{0x0C,0x20,0x0A},{0x0D,0x20,0x0D}},
+								 {{0x0C,0x20,0x11},{0x0B,0x20,0x13},{0x0C,0x20,0x0C},{0x0D,0x20,0x0F}},
+								 {{0x0D,0x30,0x14},{0x0D,0x22,0x14},{0x0D,0x20,0x0D},{0x0D,0x15,0x0C}},
+								 {{0x0E,0x30,0x18},{0x0E,0x25,0x16},{0x0E,0x25,0x0F},{0x0E,0x18,0x0F}},
+								 {{0x0F,0x38,0x1A},{0x0F,0x32,0x1C},{0x0F,0x18,0x12},{0x0F,0x18,0x12}}};
+
+	    if (ref >= 28 && ref < 40){
+	        row = 0;
+	    }else if (ref >= 40 && ref < 60){
+	        row = 1;
+		}else if (ref >= 60 && ref < 90){
+	        row = 2;
+		}else if (ref >= 90 && ref < 110){
+	        row = 3;
+		}else if (ref >= 110 && ref < 140){
+	        row = 4;
+		}else if (ref >= 140 && ref < 180){
+	        row = 5;
+		}else if (ref >= 180 && ref <= 240){
+	        row = 6;
+		}
+
+	    if (vco >= 7001 && vco < 8400){
+	        column = 0;
+		}else if (vco >= 8400 && vco < 10500){
+	        column = 1;
+		}else if (vco >= 10500 && vco < 12000){
+	        column = 2;
+		}else if (vco >= 12000 && vco <= 14000){
+	        column = 3;
+		}
+
+		char cp   = coreTable[row][column][0];
+		char c1r3 = coreTable[row][column][1];
+		char r1   = coreTable[row][column][2];
+
+		char dither,nHigh,nLow,fHigh,fMiddle,fLow,outputDiv,core = 0x81;
+	    if(vco > 10500){
+	         core = core + 0x10;
+	    }
+	    if (div == 2){
+	        outputDiv = 0+7;
+	    }else if (div == 4){
+	        outputDiv = 32+7;
+	    }else{
+	        outputDiv = 48 + divBin(div);
+	    }
+
+	    double nf = 1.0*vco / ref;
+	    int n = nf;
+	    double f = nf - n;
+	    if(f > 1e-10){
+	        dither = 11;
+	    }else{
+	        dither = 0;
+	    }
+	    if(n >= 256){
+	        nHigh = 1;
+	    }else{
+	        nHigh = 0;
+	    }
+	    nLow = n & 0xff;
+	    int f1 = f * pow(2,24);
+	    fHigh   = f1>>16 & 0xff;
+	    fMiddle = f1>>8 & 0xff;
+	    fLow    = f1 & 0xff;
+	    reg_data[0]=core;
+	    reg_data[1]=outputDiv;
+	    reg_data[2]=nHigh;
+	    reg_data[3]=nLow;
+	    reg_data[4]=fHigh;
+	    reg_data[5]=fMiddle;
+	    reg_data[6]=fLow;
+	    reg_data[7]=cp;
+	    reg_data[8]=c1r3;
+	    reg_data[9]=r1;
+	    reg_data[10]=dither;
+	return 0;
+}
+int pll_frq_caculation_new(double ref,double pll_frq,u8 *reg_data){
+
+    u8 row,column;
+    double vco = pll_frq;
+	int div = 1;
+	while(vco < 6701){
+		vco = vco*2;
+	    div = div*2;
+	}
+	char  coreTable[7][4][3] =  {{{0x0C,0x30,0x08},{0x0B,0x30,0x09},{0x0C,0x30,0x05},{0x0D,0x30,0x08}},
+								 {{0x0C,0x30,0x0C},{0x0B,0x30,0x0E},{0x0C,0x30,0x08},{0x0D,0x30,0x0B}},
+								 {{0x0C,0x20,0x10},{0x0B,0x20,0x10},{0x0C,0x20,0x0A},{0x0D,0x20,0x0D}},
+								 {{0x0C,0x20,0x11},{0x0B,0x20,0x13},{0x0C,0x20,0x0C},{0x0D,0x20,0x0F}},
+								 {{0x0D,0x30,0x14},{0x0D,0x22,0x14},{0x0D,0x20,0x0D},{0x0D,0x15,0x0C}},
+								 {{0x0E,0x30,0x18},{0x0E,0x25,0x16},{0x0E,0x25,0x0F},{0x0E,0x18,0x0F}},
+								 {{0x0F,0x38,0x1A},{0x0F,0x32,0x1C},{0x0F,0x18,0x12},{0x0F,0x18,0x12}}};
+
+	    if (ref >= 28 && ref < 40){
+	        row = 0;
+	    }else if (ref >= 40 && ref < 60){
+	        row = 1;
+		}else if (ref >= 60 && ref < 90){
+	        row = 2;
+		}else if (ref >= 90 && ref < 110){
+	        row = 3;
+		}else if (ref >= 110 && ref < 140){
+	        row = 4;
+		}else if (ref >= 140 && ref < 180){
+	        row = 5;
+		}else if (ref >= 180 && ref <= 240){
+	        row = 6;
+		}
+
+	    if (vco < 8400){
+	        column = 0;
+		}else if (vco >= 8400 && vco < 10150){
+	        column = 1;
+		}else if (vco >= 10150 && vco < 12000){
+	        column = 2;
+		}else if (vco >= 12000 ){
+	        column = 3;
+		}
+
+		char cp   = coreTable[row][column][0];
+		char c1r3 = coreTable[row][column][1];
+		char r1   = coreTable[row][column][2];
+
+		char dither,nHigh,nLow,fHigh,fMiddle,fLow,outputDiv,core = 0x81;
+	    if(vco > 10150){
+	         core = core + 0x10;
+	    }
+	    if (div == 2){
+	        outputDiv = 0+7;
+	    }else if (div == 4){
+	        outputDiv = 32+7;
+	    }else{
+	        outputDiv = 48 + divBin(div);
+	    }
+
+	    double nf = 1.0*vco / ref;
+	    int n = nf;
+	    double f = nf - n;
+	    if(f > 1e-10){
+	        dither = 11;
+	    }else{
+	        dither = 0;
+	    }
+	    if(n >= 256){
+	        nHigh = 1;
+	    }else{
+	        nHigh = 0;
+	    }
+	    nLow = n & 0xff;
+	    int f1 = f * pow(2,24);
+	    fHigh   = f1>>16 & 0xff;
+	    fMiddle = f1>>8 & 0xff;
+	    fLow    = f1 & 0xff;
+	    reg_data[0]=core;
+	    reg_data[1]=outputDiv;
+	    reg_data[2]=nHigh;
+	    reg_data[3]=nLow;
+	    reg_data[4]=fHigh;
+	    reg_data[5]=fMiddle;
+	    reg_data[6]=fLow;
+	    reg_data[7]=cp;
+	    reg_data[8]=c1r3;
+	    reg_data[9]=r1;
+	    reg_data[10]=dither;
+	return 0;
+}
+char divBin(u16 div){
+
+	switch(div){
+		case   8:return 7;break;
+		case  16:return 6;break;
+		case  32:return 5;break;
+		case  64:return 4;break;
+		case 128:return 3;break;
+		case 256:return 2;break;
+		default :return 2;
+	}
+
+}
+
+void configTxNcoFreq(int freq, int fs) {
+	u8 rx_data;
+	double ratio = (double) freq < 0 ? (freq + fs) / fs : freq / fs;
+	double bin = ratio * pow(2,48);
+	int bin_low = (u32) bin & 0xFFFFFF;
+	int bin_high = (u32)(bin / pow(2,24)) & 0xFFFFFF;
+    SpiPs_write_read1(0x164, (bin_high >> 16) & 0xFF,&rx_data);
+    SpiPs_write_read1(0x165, (bin_high >> 8) & 0xFF,&rx_data);
+    SpiPs_write_read1(0x166,  bin_high & 0xFF,&rx_data);
+    SpiPs_write_read1(0x167, (bin_low >> 16) & 0xFF,&rx_data);
+    SpiPs_write_read1(0x168, (bin_low >> 8) & 0xFF,&rx_data);
+    SpiPs_write_read1(0x169,  bin_low & 0xFF,&rx_data);
+}
+void configRxNcoFreq(int freq, int fs) {
+	u8 rx_data;
+	double ratio = (double) freq < 0 ? (freq + fs) / fs : freq / fs;
+	double bin = ratio * pow(2,48);
+	int bin_low = (u32) bin & 0xFFFFFF;
+	int bin_high = (u32)(bin / pow(2,24)) & 0xFFFFFF;
+    SpiPs_write_read1(0xA16, (bin_high >> 16) & 0xFF,&rx_data);
+    SpiPs_write_read1(0xA17, (bin_high >> 8) & 0xFF,&rx_data);
+    SpiPs_write_read1(0xA18,  bin_high & 0xFF,&rx_data);
+    SpiPs_write_read1(0xA19, (bin_low >> 16) & 0xFF,&rx_data);
+    SpiPs_write_read1(0xA1A, (bin_low >> 8) & 0xFF,&rx_data);
+    SpiPs_write_read1(0xA1B,  bin_low & 0xFF,&rx_data);
+}
+

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_CX9261A_HOP/xilinx_io.h

@@ -0,0 +1,153 @@
+/*
+ * xilinx_io.h
+ *
+ *  Created on: 2021年9月6日
+ *      Author: cxlab
+ */
+
+#ifndef SRC_XILINX_IO_H_
+#define SRC_XILINX_IO_H_
+
+
+
+#endif /* SRC_XILINX_IO_H_ */
+#include "xspips.h"		/* SPI device driver */
+#include "xgpiops.h"
+#include "xgpio.h"
+#include "xaxidma.h"
+#include "xparameters.h"
+#include "xscugic.h"
+#include "xil_exception.h"
+
+//#define DBGLOG
+#define MAX_DATA		 100
+#define SPI_WRITE		 0x80
+#define SPI_READ		 0x00
+#define GPIO_DIR_INPUT   0x00
+#define GPIO_DIR_OUTPUT  0x01
+#define GPIO_EMIO_OFFSET 54
+
+#define TX_EN  0x08
+#define RX_EN  0x07
+#define GPIO_1  0x06
+#define GPIO_0  0x05
+
+#define NRST 0
+#define ENABLE_TRX1 1
+#define ENABLE_TRX2 2
+#define ENABLE_TRX3 3
+#define TXNRX_TRX1 4
+#define TXNRX_TRX2 5
+#define TXNRX_RX3 6
+
+#define aresetn_0 33
+#define rst 34
+#define tr_sel 35
+#define tdd_fdd_sel 36
+#define r1t1_r2t2_sel 37
+#define sp_dp_sel 38
+#define aresetn_1 39
+#define aresetn_2 40
+#define hop 41
+#define cx3e04_rstn 42
+#define spi_select 46
+#define debug_mode 63
+
+#define INTER_SIG3  0x03//dma_axis_rx_rstn
+#define INTER_SIG2  0x02//frame_pattern
+#define INTER_SIG1  0x01//mode_sel_async
+#define INTER_SIG0  0x00//rst_async
+
+#define SPI_DEVICE_ID XPAR_XSPIPS_0_DEVICE_ID
+#define GPIO_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
+
+#define AXI_DMA_DEVCIE_ID0 XPAR_AXI_DMA_0_DEVICE_ID
+#define AXI_DMA_DEVCIE_ID1 XPAR_AXI_DMA_1_DEVICE_ID
+#define AXI_DMA_DEVCIE_ID2 XPAR_AXI_DMA_2_DEVICE_ID
+
+#define BROM_BASEADDR XPAR_M08_AXI_0_BASEADDR
+
+#define AXI4_LITE0_SPI_BASEADDR XPAR_AXI4_LITE_SPI_0_BASEADDR
+#define AXI4_LITE1_SPI_BASEADDR XPAR_AXI4_LITE_SPI_1_BASEADDR
+#define BRAM_BASEADDR XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR
+#define BRAM_BASEADDR_1 XPAR_AXI_BRAM_CTRL_1_S_AXI_BASEADDR
+#define PACKER_BASEADDR0 XPAR_AXIS_ADC_DATA_PACKER_0_S00_AXI_BASEADDR
+#define PACKER_BASEADDR1 XPAR_AXIS_ADC_DATA_PACKER_1_S00_AXI_BASEADDR
+#define PACKER_BASEADDR2 XPAR_AXIS_ADC_DATA_PACKER_2_S00_AXI_BASEADDR
+#define WAVELENGTH 8192
+#define TX_BUFFER_BASE		XPAR_MIG_7SERIES_0_BASEADDR +0x2000
+#define WAVE_LENGTH 8192*4
+
+#define GPIO_INT_ID XPAR_FABRIC_GPIO_0_VEC_ID   //PL 端  AXI GPIO 中断 ID
+#define AXI_GPIO_ID XPAR_AXI_GPIO_0_DEVICE_ID   //PL 端  AXI GPIO 器件 ID
+#define SCUGIC_ID   XPAR_SCUGIC_0_DEVICE_ID     //中断控制器 ID
+
+#define KEY_MASK    XGPIO_IR_CH1_MASK           //通道 1 的位定义
+
+int cx3e04_write(int addr , int value);
+int cx3e04_read(int addr);
+int cx9261a_write(int addr , int value);
+int cx9261a_read(int addr);
+void cx3e04_config(void);
+void cx9261a_710_config(void);
+
+void AXIGpioInit(void);
+void ConfigAXIGPIOIntr(void);
+void axi_gpio_handler(void *CallbackRef);
+void XScuGicInit(void);
+void ExceptionInit(void);
+
+int SpiPsInit(u16 SpiDeviceId);
+//int SpiPs_write_read(u8 cmd, u16 addr,u8 data,u8 * rx_data);
+int SpiPs_write_read(u8 * data,u8 * rx_data);
+int SpiPs_write_read1(u16 addr,u8 data,u8 * rx_data);
+int SpiPs_write_read2(u16 addr,u8 data,u8 * rx_data);
+int GpioInit(u16 DeviceId);
+int GpioSetPinDir(u32 Pin,u32 Direction);
+int GpioWritePin(u32 Pin,u32 data);
+int GpioReadPin(u32 Pin);
+void DeviceRst(void);
+
+//校准
+void cx9261a_151_config(void);
+void cx9261a_076_config(void);
+void rxFFTCalib(int lo, int fs,int ref, int firLength,int chan);
+void configTxNcoFreq(int freq, int fs);
+void configRxNcoFreq(int freq, int fs);
+void configDcCalib(int dcCalibEnable,int dcCalibLength);
+void txBisectionQecCalib(int f0, int fs);
+void txBisectionDcCalib(int f0, int fs);
+
+extern XAxiDma* xAxiDma0Get(void);
+extern XAxiDma* xAxiDma1Get(void);
+extern XAxiDma* xAxiDma2Get(void);
+int XAxiDma_Init(XAxiDma* AxiDma,u16 DeviceId);
+int XAxiDmaCapture(XAxiDma* AxiDma,u32 data_length);
+int XAxiDmaCapture2(XAxiDma* AxiDma,u32 data_length);
+
+int DownloadWave(u8 * data);
+int SetPacketSize(XAxiDma* AxiDma,u32 length);
+void dbg_printf( const char8 *ctrl1, ...);
+void PackerRst(void);
+int peripheral_test(void);
+
+#define SPI_STACK_LENGTH 65536
+struct spi_stack {
+	int spi_write_num;
+	u8 recv_buf[SPI_STACK_LENGTH*3];
+};
+int spi_stack_in(u8 * data,struct spi_stack * spistack);
+
+void spi_stack_out(struct spi_stack * spistack);
+
+int rom_read(u8 * data);
+void download_bin(void);
+//跳频
+void frqhop_config(int hop_flag);
+void frqhop_flag(int frqhop_flag);
+int PLL_config(u8 pll_index,double pll_frq);
+void trx_ch_pll_config(u8 pll_index);
+int pll_frq_caculation(double ref,double pll_frq,u8 *reg_data);
+int pll_frq_caculation_new(double ref,double pll_frq,u8 *reg_data);
+void PLL_afc(u16 afc_addr,u16 div_addr,u8 pll_div);
+char divBin(u16 div);

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_cx9261a_api_1_9_0/cx9261adriver.h

@@ -0,0 +1,546 @@
+/**
+ * @file cx9261adriver.h
+ */
+
+#ifndef CX9261ADRIVER_CX9261ADRIVER_H
+#define CX9261ADRIVER_CX9261ADRIVER_H
+
+#define VERSION 1.9.0
+
+#include "defs.h"
+// 如果不需要输出日志内容，注释掉下面的宏定义
+#define USE_LOGGING
+
+#ifdef USE_LOGGING
+#    define LOGGING(x) logging(x);
+#else
+#    define LOGGING(x)
+#endif
+
+namespace CX9261A {
+#ifdef USE_LOGGING
+/**
+ * @brief 输出日志的函数
+ * @param msg 要输出的内容
+ */
+void logging(const std::string& msg);
+#endif
+/**
+ * @brief 需要实现的函数，实现SPI写入寄存器功能
+ * @param address 要写入的寄存器地址
+ * @param value 要写入的寄存器值
+ */
+void writeSpi(int address, int value);
+/**
+ * @brief 需要实现的函数，实现SPI读取寄存器功能
+ * @param address 要读取的寄存器地址
+ * @return 返回的寄存器值
+ */
+int readSpi(int address);
+/**
+ * @brief 需要实现的函数，实现等待功能
+ * @param ms 等待时间，单位毫秒
+ */
+void pause(double ms);
+/**
+ * @brief 需要实现的函数，实现配置FPGA对应寄存器功能
+ * @param pin 寄存器地址
+ * @param value 寄存器值
+ */
+void setPin(int pin, int value);
+/**
+ * @brief 初始化芯片状态，写入与具体配置无关的寄存器值
+ */
+void initialChip();
+/**
+ * @brief 初始化电源配置，如果只自定义配置部分模式下的电源管理，在自定义配置之前需要先调用此函数
+ */
+void initialPowerConfig(const CX9261AConfiguration& config);
+/**
+ * @brief 初始化BBPLL相关寄存器，如果调用了initialChip，则无需单独调用此函数
+ */
+void initialBBPLL();
+/**
+ * @brief 初始化PLL1相关寄存器，如果调用了initialChip，则无需单独调用此函数
+ */
+void initialPLL1();
+/**
+ * @brief 初始化PLL2相关寄存器，如果调用了initialChip，则无需单独调用此函数
+ */
+void initialPLL2();
+/**
+ * @brief 初始化PLL3相关寄存器，如果调用了initialChip，则无需单独调用此函数
+ */
+void initialPLL3();
+/**
+ * @brief 初始化PLL4相关寄存器，如果调用了initialChip，则无需单独调用此函数
+ */
+void initialPLL4();
+/**
+ * @brief 初始化PLL5相关寄存器，如果调用了initialChip，则无需单独调用此函数
+ */
+void initialPLL5();
+/**
+ * @brief 配置受参考时钟频率影响的寄存器
+ * @param ref 参考时钟频率，单位MHz
+ */
+void configRef(double ref);
+/**
+ * @brief 配置时钟相关寄存器，包括ADC和BBPLL
+ * @param config CX9261A参数结构体
+ */
+void configBBPLL(const CX9261AConfiguration& config);
+/**
+ * @brief BBPLL AFC
+ * @return 是否锁定
+ */
+bool afcBBPll();
+/**
+ * @brief 配置PLL1频率
+ * @param lo 目标频率
+ * @param clock 时钟结构体，使用其中的ref和refDoubler属性
+ */
+void configPll1(double lo, const Clock& clock);
+/**
+ * @brief Pll1 AFC
+ * @return 是否锁定
+ */
+bool afcPll1();
+/**
+ * @brief 配置PLL2频率
+ * @param lo 目标频率
+ * @param clock 时钟结构体，使用其中的ref和refDoubler属性
+ */
+void configPll2(double lo, const Clock& clock);
+/**
+ * @brief Pll2 AFC
+ * @return 是否锁定
+ */
+bool afcPll2();
+/**
+ * @brief 配置PLL3频率
+ * @param lo 目标频率
+ * @param clock 时钟结构体，使用其中的ref和refDoubler属性
+ */
+void configPll3(double lo, const Clock& clock);
+/**
+ * @brief Pll3 AFC
+ * @return 是否锁定
+ */
+bool afcPll3();
+/**
+ * @brief 配置PLL4频率
+ * @param lo 目标频率
+ * @param clock 时钟结构体，使用其中的ref和refDoubler属性
+ */
+void configPll4(double lo, const Clock& clock);
+/**
+ * @brief Pll4 AFC
+ * @return 是否锁定
+ */
+bool afcPll4();
+/**
+ * @brief 配置PLL5频率
+ * @param lo 目标频率
+ * @param clock 时钟结构体，使用其中的ref和refDoubler属性
+ */
+void configPll5(double lo, const Clock& clock);
+/**
+ * @brief Pll5 AFC
+ * @return 是否锁定
+ */
+bool afcPll5();
+/**
+ * @brief 配置AGC模式
+ * @param mode 模式0~13
+ */
+void configAGCMode(int mode);
+/**
+ * @brief 配置AGC PDT
+ * @param pdt AGCPDT结构体
+ */
+void configAGCPDT(const AGCPDT& pdt);
+/**
+ * @brief 配置AGC LMT
+ * @param lmt AGCLMT结构体
+ */
+void configAGCLMT(const AGCLMT& lmt);
+/**
+ * @brief 配置AGC DIG
+ * @param dig AGCDIG结构体
+ */
+void configAGCDIG(const AGCDIG& dig);
+/**
+ * @brief 配置AGC
+ * @param agc AGC结构体
+ */
+void configAGC(const AGC& agc);
+/**
+ * @brief 配置片内处理器，仅在使用需要处理器辅助的校准方法时需要开启处理器
+ * @param on 开启/关闭
+ */
+void configRISCV(bool on);
+/**
+ * @brief 配置温补
+ * @param mode 温补模式 DAC/Band
+ */
+void configTemperatureCompensation(TemperatureComp mode);
+/**
+ * @brief ADC校准
+ * @param adc ADC速率
+ */
+void configADCCalib(double adc);
+/**
+ * @brief Flash校准
+ */
+void configFlashCalib();
+/**
+ * @brief QEC校准会改变部分寄存器配置，在进行校准之前需要保存这部分寄存器，校准后恢复
+ * @return 包含寄存器地址和值的map
+ */
+std::map<int, int> beforeQecState();
+/**
+ * @brief 恢复QEC校准过程中改变的寄存器
+ * @param state beforeQecState函数返回的map
+ */
+void restoreQecState(const std::map<int, int>& state);
+/**
+ * @brief 根据pll来源配置校准模式下的电源管理
+ * @param pllSource PllSource结构体
+ */
+void preparePowerForRxCalib(const PllSource& pllSource);
+/**
+ * @brief 调整校准时Pll的配置
+ * @param config CX9261A配置结构体
+ * @param chan 要进行校准的通道
+ */
+void preparePllForRxCalib(const CX9261AConfiguration& config, RxChannel chan);
+/**
+ * @brief 等待RxTST窄带校准结束，可重写
+ * @return 校准是否结束
+ */
+bool waitRxTSTFinished();
+/**
+ * @brief RX时域统计校准
+ * @param chan 校准的RX通道
+ */
+void rxTSTCalib(RxChannel chan);
+/**
+ * @brief RX延时线校准
+ * @param fs ADC采样率
+ * @param chan 校准的RX通道
+ */
+void rxDelayCalib(double fs, RxChannel chan);
+/**
+ * @brief DC Tracking
+ * @param config CX9261A配置结构体
+ */
+void configDcCalib(const Calib& config);
+void configDcCalibMethod(DCCalibMethod method);
+void configDcTrackingLength(int length);
+void configDcHighPassFactor(int factor);
+/**
+ * @brief Rx校准
+ * @param config CX9261A配置结构体
+ * @param chan 要进行校准的通道
+ */
+void rxCalib(const CX9261AConfiguration& config, RxChannel chan);
+/**
+ * @brief 选择校准方法
+ * @param calib 校准结构体
+ */
+void configCalibMethod(const Calib& calib);
+/**
+ * @brief 读取当前Rx chan通道的校准值
+ * @param chan Rx通道
+ * @return 校准值结构体
+ */
+CalibPredis readRxCalibPredis(RxChannel chan);
+/**
+ * @brief 储存校准值
+ * @param index 第index组校准值
+ * @param chan 接收通道
+ * @param pll 使用的PLL
+ */
+void saveRxCalibPredis(unsigned char index, RxChannel chan, LoSource pll);
+/**
+ * @brief 加载保存的校准值
+ * @param index 第index组校准值
+ * @param chan 指定加载校准值的通道
+ * @param pll 使用的PLL
+ */
+void loadRxCalibPredis(unsigned char index, RxChannel chan, LoSource pll);
+/**
+ * @brief Rx窄带多点校准
+ * @param config CX9261A配置结构体
+ * @param points 校准点
+ * @param chan 接收通道
+ */
+void configRxMultiPointsQec(const CX9261AConfiguration& config, const std::vector<double>& points, RxChannel chan);
+/**
+ * @brief 根据pll来源配置校准模式下的电源管理
+ * @param pllSource PllSource结构体
+ */
+void preparePowerForTxCalib(const PllSource& pllSource);
+/**
+ * @brief 调整校准时Pll的配置
+ * @param config CX9261A配置结构体
+ */
+void preparePllForTxCalib(const CX9261AConfiguration& config);
+/**
+ * @brief TX二分法QEC校准
+ * @param f0 校准音频率
+ * @param fs adc频率
+ */
+void txBisectionQecCalib(double f0, double fs);
+/**
+ * @brief TX时域统计法校准
+ * @param config CX9261A配置结构体
+ * @param chan 要校准的通道
+ */
+void txTSTCalib(const CX9261AConfiguration& config, TxChannel chan);
+/**
+ * @brief TX二分法DC校准
+ * @param f0 校准音频率
+ * @param fs adc频率
+ */
+void txBisectionDcCalib(double f0, double fs);
+/**
+ * @brief Tx多点校准
+ * @param config CX9261A配置结构体
+ * @param points 校准点
+ */
+void configTxMultiPointsQec(const CX9261AConfiguration& config, const std::vector<double>& points);
+/**
+ * @brief Tx通道校准
+ * @param config CX9261A配置结构体
+ */
+void txCalib(const CX9261AConfiguration& config);
+/**
+ * @brief 储存校准值
+ * @param index 第index组校准值
+ * @param chan 发射通道
+ * @param pll pll
+ */
+void saveTxCalibPredis(unsigned char index, TxChannel chan, LoSource pll);
+/**
+ * @brief 加载保存的校准值
+ * @param index 第index组校准值
+ * @param chan 指定加载校准值的通道
+ * @param pll 指定加载校准值对应的PLL
+ */
+void loadTxCalibPredis(unsigned char index, TxChannel chan, LoSource pll);
+/**
+ * @brief Qec校准顶层函数，内部根据配置选择使用对应方法进行校准
+ * @param config CX9261A配置结构体
+ */
+void configQecCalib(const CX9261AConfiguration& config);
+/**
+ * @brief 配置TX NCO相关寄存器
+ * @param nco TX NCO配置结构体
+ * @param fs adc速率
+ */
+void configTxNco(const TxNCO& nco, double fs);
+/**
+ * @brief 配置TX NCO BIST模式
+ * @param bist 开启/关闭BIST
+ */
+void configTxBIST(bool bist);
+/**
+ * @brief 配置TX NCO频率
+ * @param freq 混频频率
+ * @param fs adc抽取后速率
+ */
+void configTxNcoFreq(double freq, double fs);
+/**
+ * @brief 配置RX NCO相关寄存器
+ * @param nco RX NCO配置结构体
+ * @param fs adc速率
+ */
+void configRxNco(const RxNCO& nco, double fs);
+/**
+ * @brief 配置Rx NCO模式
+ * @param mode NCO模式：Bypass/BIST/Up/Down
+ */
+void configRxNcoMode(NCOMode mode);
+/**
+ * @brief 配置Rx NCO模式
+ * @param mode NCO模式：Master/Slaver
+ */
+void configRxNcoMS(NCOMode mode);
+/**
+ * @brief 配置Rx NCO频率
+ * @param freq 混频频率
+ * @param fs adc速率
+ */
+void configRxNcoFreq(double freq, double fs);
+/**
+ * @brief 配置接口相关寄存器
+ * @param interface Interface配置结构体
+ */
+void configInterface(const Interface& interface);
+/**
+ * @brief 配置PLL来源
+ * @param pllSource PLlSource结构体
+ */
+void configPllSource(const PllSource& pllSource);
+/**
+ * @brief 切换电源模式
+ * @param pm 电源模式
+ */
+void configPowerMode(PowerMode pm);
+/**
+ * @brief 配置电源管理
+ * @param power 电源配置结构体
+ * @param pm 电源模式
+ */
+void configPowerPins(const Power& power, PowerMode pm);
+/**
+ * @brief 配置参考倍频器
+ * @param doubler 倍频器开关
+ * @param ref 参考时钟频率，单位MHz
+ */
+void configRefDoubler(bool doubler, double ref);
+/**
+ * @brief 初始化通道，调用initialChip函数会初始化RX1，RX2，RX3三个通道
+ * @param chan 通道 RX1/RX2/RX3
+ */
+void initialRxChannel(RxChannel chan);
+/**
+ * @brief 配置Rx带宽
+ * @note 只改变Rx带宽会导致通道增益改变，建议使用configRxChannel函数进行带宽调整
+ * @param bandwidth 带宽，单位(MHz)
+ * @param chan 通道 Rx1/Rx2/Rx3
+ */
+void configRxBandwidth(double bandwidth, RxChannel chan);
+/**
+ * @brief 配置Rx TIA
+ * @note 只改变TIA会导致通道带宽改变，建议使用configRxChannel函数进行TIA调整
+ * @param tia tia档位
+ * @param chan 通道 Rx1/Rx2/Rx3
+ */
+void configRxTIA(int tia, RxChannel chan);
+/**
+ * @brief 配置Rx Mixer
+ * @param mixer mixer档位
+ */
+void configRxMixer(int mixer);
+/**
+ * @brief 配置Rx通道，包含TIA，Mixer以及Bandwidth
+ * @param config RxConfig结构体
+ * @param chan Rx1/Rx2/Rx3
+ */
+void configRxChannel(const RxConfig& config, RxChannel chan);
+/**
+ * @brief 配置Rx FIR滤波器抽取倍数
+ * @param fir 抽取倍数 0(Bypass)/1/2/3/4/8
+ */
+void configRxFIR(int fir);
+/**
+ * @brief 配置Rx HBF1滤波器抽取倍数
+ * @param hbf 抽取倍数 0(Bypass)/2
+ */
+void configRxHBF1(int hbf);
+/**
+ * @brief 配置Rx HBF2滤波器抽取倍数
+ * @param hbf 抽取倍数 0(Bypass)/2
+ */
+void configRxHBF2(int hbf);
+/**
+ * @brief 配置Rx HBF3滤波器抽取倍数
+ * @param hbf 抽取倍数 0(Bypass)/2/3
+ */
+void configRxHBF3(int hbf);
+/**
+ * @brief 配置Rx CIC滤波器
+ * @param cic 抽取倍数 0(Bypass)/20
+ */
+void configRxCIC(int cic);
+/**
+ * @brief 配置Rx滤波器
+ * @param filters Filters结构体
+ */
+void configRxFilters(const Filters& filters);
+/**
+ * @brief 配置Rx FIR滤波器系数
+ * @param coe 滤波器系数，长度为16的整倍数，最大128
+ */
+void configRxFIRCoe(const std::vector<double>& coe);
+/**
+ * @brief 配置Tx带宽
+ * @param bandwidth 带宽，单位(MHz)
+ * @param chan 通道 TX1/TX2
+ */
+void configTxBandwidth(double bandwidth, TxChannel chan);
+/**
+ * @brief 配置Tx Mixer
+ * @param mixer 混频器值
+ * @param chan TX1/TX2
+ */
+void configTxMixer(int mixer, TxChannel chan);
+/**
+ * @brief 初始化Tx通道
+ * @param chan 通道 TX1/TX2
+ */
+void initialTxChannel(TxChannel chan);
+/**
+ * @brief 根据Tx通道的本振频率，配置对应的参数
+ * @param lo 本振频率，单位(MHz)
+ * @param chan 通道(Tx1/Tx2)
+ */
+void configTxChannelFrequency(double lo, TxChannel chan);
+/**
+ * @brief 配置Tx通道，Mixer以及Bandwidth
+ * @param config TxConfig结构体
+ * @param chan Tx1/Tx2
+ */
+void configTxChannel(const TxConfig& config, TxChannel chan);
+/**
+ * @brief 配置Tx FIR滤波器插值倍数
+ * @param fir 插值倍数 0(Bypass)/1/2/3/4/8
+ */
+void configTxFIR(int fir);
+/**
+ * @brief 配置Tx HBF1滤波器插值倍数
+ * @param hbf 插值倍数 0(Bypass)/2
+ */
+void configTxHBF1(int hbf);
+/**
+ * @brief 配置Tx HBF2滤波器插值倍数
+ * @param hbf 插值倍数 0(Bypass)/2
+ */
+void configTxHBF2(int hbf);
+/**
+ * @brief 配置Tx HBF3滤波器插值倍数
+ * @param hbf 插值倍数 0(Bypass)/2/3
+ */
+void configTxHBF3(int hbf);
+/**
+ * @brief 配置Tx CIC滤波器
+ * @param cic 插值倍数 0(Bypass)/8/20/32/80
+ */
+void configTxCIC(int cic);
+/**
+ * @brief 配置Tx滤波器
+ * @param filters Filters结构体
+ */
+void configTxFilters(const Filters& filters);
+/**
+ * @brief 配置Tx FIR滤波器系数
+ * @param coe 滤波器系数，长度为16的整倍数，最大128
+ */
+void configTxFIRCoe(const std::vector<double>& coe);
+/**
+ * @brief 读取当前Tx chan通道的校准值
+ * @param chan Tx通道
+ * @return 校准值结构体
+ */
+CalibPredis readTxCalibPredis(TxChannel chan);
+/**
+ * @brief 此函数为Demo板配套配置函数，用于配置FPGA接口，用户开发自己的程序时应重写对应功能
+ * @param interface Interface结构体
+ */
+void configFPGA(const Interface& interface);
+}  // namespace CX9261A
+
+#endif  // CX9261ADRIVER_CX9261ADRIVER_H

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_cx9261a_api_1_9_0/defs.h

@@ -0,0 +1,424 @@
+/**
+ * @file defs.h
+ */
+
+#ifndef CX9261ADRIVER_DEFS_H
+#define CX9261ADRIVER_DEFS_H
+
+#include <bitset>
+#include <map>
+#include <vector>
+
+#ifdef interface
+#    undef interface
+#endif
+
+namespace CX9261A {
+/**
+ * @brief 芯片工作模式
+ */
+enum class WorkMode : std::uint8_t { Rx, Tx, FDD };
+/**
+ * @brief 收发数据通道数量
+ * @note 此模式并不代表使用几个通道进行收发
+ */
+enum class TrMode : std::uint8_t { R1T1, R2T2 };
+/**
+ * @brief 收发接口通道数量
+ */
+enum class PortMode : std::uint8_t { Single, Dual };
+/**
+ * @brief 接口模式：
+ * CMOS CMOS接口模式，
+ * LVDS_S LVDS顺序模式，
+ * LVDS_E LVDS奇偶模式
+ */
+enum class IOMode : std::uint8_t { CMOS, LVDS_S, LVDS_E };
+/**
+ * @brief 本振来源
+ */
+enum class LoSource : std::uint8_t {
+    Pll1 = 0b00001,
+    Pll2 = 0b00010,
+    Pll3 = 0b00100,
+    Pll4 = 0b01000,
+    Pll5 = 0b10000,
+    Off = 0
+};
+
+inline std::string toString(const LoSource source)
+{
+    switch (source) {
+    case LoSource::Pll1:
+        return "Pll1";
+    case LoSource::Pll2:
+        return "Pll2";
+    case LoSource::Pll3:
+        return "Pll3";
+    case LoSource::Pll4:
+        return "Pll4";
+    case LoSource::Pll5:
+        return "Pll5";
+    default:
+        return "Off";
+    }
+}
+/**
+ * @brief 接收通道
+ */
+enum class RxChannel : std::uint8_t { Rx1 = 1, Rx2, Rx3 };
+
+inline std::string toString(const RxChannel chan)
+{
+    switch (chan) {
+    case RxChannel::Rx1:
+        return "Rx1";
+    case RxChannel::Rx2:
+        return "Rx2";
+    case RxChannel::Rx3:
+        return "Rx3";
+    default:
+        return "Unknown Channel";
+    }
+}
+/**
+ * @brief 发射通道
+ */
+enum class TxChannel : std::uint8_t { Tx1 = 1, Tx2 };
+
+inline std::string toString(const TxChannel chan)
+{
+    switch (chan) {
+    case TxChannel::Tx1:
+        return "Tx1";
+    case TxChannel::Tx2:
+        return "Tx2";
+    default:
+        return "Unknown Channel";
+    }
+}
+/**
+ * @brief 电源模式
+ */
+enum class PowerMode : std::uint8_t { Shutdown = 0, Sleep, Alert, Calib, Receive, Transmit, Duplex, Obs };
+/**
+ * @brief NCO模式
+ */
+enum class NCOMode : std::uint8_t { Bypass = 0, Up, Down, BIST, Master, Slaver };
+/**
+ * @brief 温补模式 DAC: DAC模式 Band: 跳子带模式
+ */
+enum class TemperatureComp : std::uint8_t { DAC = 0, Band };
+/**
+ * @brief 校准方法 TST: 时域统计 Rx通道使用, Bisec: 二分法 Tx通道使用, MultiPoints: 多点校准
+ */
+enum class CalibMethod : std::uint8_t { TST = 0, Bisec, MultiPoints, Tracking };
+/**
+ * @brief DC校准方法 Tracking: 跟踪校准 HighPass: 高通滤波器滤掉直流
+ */
+enum class DCCalibMethod : std::uint8_t { Tracking = 0, HighPass };
+/**
+ * @brief AFC等待延时，单位ms
+ */
+constexpr double delay = 100;
+/**
+ * @brief QEC等待延时，单位ms
+ */
+constexpr double qecDelay = 500;
+/**
+ * @brief 接收通道本振来源映射表
+ */
+static const std::map<std::pair<LoSource, LoSource>, std::bitset<7>> rxSrcMap = {
+    { { LoSource::Pll2, LoSource::Pll2 }, 0b0010000 }, { { LoSource::Pll1, LoSource::Pll1 }, 0b1101000 },
+    { { LoSource::Pll2, LoSource::Pll1 }, 0b0100000 }, { { LoSource::Pll1, LoSource::Pll2 }, 0b1000000 },
+    { { LoSource::Off, LoSource::Pll1 }, 0b0101010 },  { { LoSource::Off, LoSource::Pll2 }, 0b1010010 },
+    { { LoSource::Pll1, LoSource::Off }, 0b1001001 },  { { LoSource::Pll2, LoSource::Off }, 0b0110001 },
+    { { LoSource::Off, LoSource::Off }, 0b0011011 }
+};
+/**
+ * @brief 发射通道本振来源映射表
+ */
+static const std::map<std::pair<LoSource, LoSource>, std::bitset<11>> txSrcMap = {
+    { { LoSource::Pll4, LoSource::Pll4 }, 16 },   { { LoSource::Pll3, LoSource::Pll3 }, 104 },
+    { { LoSource::Pll4, LoSource::Pll3 }, 32 },   { { LoSource::Pll3, LoSource::Pll4 }, 64 },
+    { { LoSource::Pll2, LoSource::Pll2 }, 1560 }, { { LoSource::Pll1, LoSource::Pll1 }, 1944 },
+    { { LoSource::Pll2, LoSource::Pll1 }, 1688 }, { { LoSource::Pll1, LoSource::Pll2 }, 1816 },
+    { { LoSource::Off, LoSource::Pll3 }, 42 },    { { LoSource::Off, LoSource::Pll4 }, 82 },
+    { { LoSource::Off, LoSource::Pll2 }, 794 },   { { LoSource::Off, LoSource::Pll1 }, 666 },
+    { { LoSource::Pll3, LoSource::Off }, 73 },    { { LoSource::Pll4, LoSource::Off }, 49 },
+    { { LoSource::Pll2, LoSource::Off }, 1177 },  { { LoSource::Pll1, LoSource::Off }, 1305 },
+    { { LoSource::Off, LoSource::Off }, 27 },     { { LoSource::Pll1, LoSource::Pll3 }, 1320 },
+    { { LoSource::Pll1, LoSource::Pll4 }, 1360 }, { { LoSource::Pll2, LoSource::Pll3 }, 1064 },
+    { { LoSource::Pll2, LoSource::Pll4 }, 1104 }, { { LoSource::Pll3, LoSource::Pll1 }, 712 },
+    { { LoSource::Pll4, LoSource::Pll1 }, 688 },  { { LoSource::Pll3, LoSource::Pll2 }, 584 },
+    { { LoSource::Pll4, LoSource::Pll2 }, 560 }
+};
+/**
+ * @brief 环路参数选择表
+ */
+static const std::vector<std::vector<std::vector<int>>> coreTable = {
+    { { 0x0C, 0x30, 0x08 }, { 0x0B, 0x30, 0x09 }, { 0x0C, 0x30, 0x05 }, { 0x0D, 0x30, 0x08 } },
+    { { 0x0C, 0x30, 0x0C }, { 0x0B, 0x30, 0x0E }, { 0x0C, 0x30, 0x08 }, { 0x0D, 0x30, 0x0B } },
+    { { 0x0C, 0x20, 0x10 }, { 0x0B, 0x20, 0x10 }, { 0x0C, 0x20, 0x0A }, { 0x0D, 0x20, 0x0D } },
+    { { 0x0C, 0x20, 0x11 }, { 0x0B, 0x20, 0x13 }, { 0x0C, 0x20, 0x0C }, { 0x0D, 0x20, 0x0F } },
+    { { 0x0D, 0x30, 0x14 }, { 0x0D, 0x22, 0x14 }, { 0x0D, 0x20, 0x0D }, { 0x0D, 0x15, 0x0C } },
+    { { 0x0E, 0x30, 0x18 }, { 0x0E, 0x25, 0x16 }, { 0x0E, 0x25, 0x0F }, { 0x0E, 0x18, 0x0F } },
+    { { 0x0F, 0x38, 0x1A }, { 0x0F, 0x32, 0x1C }, { 0x0F, 0x18, 0x12 }, { 0x0F, 0x18, 0x12 } }
+};
+
+/**
+ * @brief AGC PDT模式的结构体
+ */
+struct AGCPDT
+{
+    int pdtN;
+    int pdtM;
+};
+
+/**
+ * @brief AGC LMT模式的结构体
+ */
+struct AGCLMT
+{
+    int count; /**< LMT统计次数阈值*/
+    int threshold1; /**< LMT阈值第一档*/
+    int threshold2; /**< LMT阈值第二档*/
+    int threshold3; /**< LMT阈值第三档*/
+    int threshold4; /**< LMT阈值第四档*/
+};
+
+/**
+ * @brief AGC DIG模式的结构体
+ */
+struct AGCDIG
+{
+    int count; /**< DIG统计次数阈值*/
+    int threshold1; /**< DIG阈值第一档*/
+    int threshold2; /**< DIG阈值第二档*/
+    int threshold3; /**< DIG阈值第三档*/
+    int threshold4; /**< DIG阈值第四档*/
+};
+
+/**
+ * @brief AGC模式的结构体
+ */
+struct AGC
+{
+    int mode; /**< AGC模式选择*/
+    AGCPDT pdt; /**< AGC PDT模式的结构体*/
+    AGCLMT lmt; /**< AGC LMT模式的结构体*/
+    AGCDIG dig; /**< AGC DIG模式的结构体*/
+};
+
+/**
+ * @brief 时钟相关参数结构体
+ */
+struct Clock
+{
+    double ref; /**< 参考时钟频率，单位MHz*/
+    double adc; /**< ADC频率，单位MHz*/
+    int refDiv; /**< 参考时钟分频比*/
+    bool bbUseIntDiv; /**< 是否使用整数分频模式*/
+    bool refDoubler; /**< 是否使用参考时钟倍频器*/
+};
+
+/**
+ * @brief 校准相关参数结构体
+ */
+struct Calib
+{
+    bool calibDC; /**< 是否开启DC Tracking*/
+    DCCalibMethod dcCalibMethod;
+    int dcTrackingLength; /**< DC Tracking长度*/
+    int dcHighPassFactor; /**< DC高通滤波系数，越大代表滤波器阶数越高，滤波范围越窄*/
+    std::uint8_t rx1CalibPll; /**< rx1校准的pll选择，Pll1 | Pll2*/
+    std::uint8_t rx2CalibPll; /**< rx2校准的pll选择，Pll1 | Pll2*/
+    std::uint8_t rx3CalibPll; /**< rx3校准的pll选择，Pll5*/
+    std::uint8_t tx1CalibPll; /**< tx1校准的pll选择，Pll1 | Pll2 | Pll3 | Pll4*/
+    std::uint8_t tx2CalibPll; /**< tx2校准的pll选择，Pll1 | Pll2 | Pll3 | Pll4*/
+    CalibMethod rxMethod;
+    CalibMethod txMethod;
+    double f0; /**< 校准音频率*/
+    std::vector<double> rxMultiPoints; /**< Rx多点校准的频率*/
+    std::vector<double> txMultiPoints; /**< Tx多点校准的频率*/
+};
+
+/**
+ * @brief 配置PLL来源相关参数结构体
+ */
+struct PllSource
+{
+    bool rxUseExt; /**< 接收通道是否使用外本振*/
+    bool txUseExt; /**< 发射通道是否使用外本振*/
+    LoSource rx1Source; /**< Rx1通道本振来源*/
+    LoSource rx2Source; /**< Rx2通道本振来源*/
+    LoSource rx3Source; /**< Rx3通道本振来源*/
+    LoSource tx1Source; /**< Tx1通道本振来源*/
+    LoSource tx2Source; /**< Tx2通道本振来源*/
+};
+
+/**
+ * @brief 配置PLL频率相关参数结构体
+ */
+struct PllFreq
+{
+    double pll1Freq; /**< PLL1本振时钟，单位MHz*/
+    double pll2Freq; /**< PLL2本振时钟，单位MHz*/
+    double pll3Freq; /**< PLL3本振时钟，单位MHz*/
+    double pll4Freq; /**< PLL4本振时钟，单位MHz*/
+    double pll5Freq; /**< PLL5本振时钟，单位MHz*/
+    double rxExtFreq; /**< 接收通道使用外本振时，外本振频率，单位MHz*/
+    double txExtFreq; /**< 发射通道使用外本振时，外本振频率，单位MHz*/
+};
+
+/**
+ * @brief 配置接口相关参数结构体
+ */
+struct Interface
+{
+    WorkMode workMode; /**< 芯片工作模式*/
+    TrMode trMode; /**< 收发数据通道模式*/
+    PortMode portMode; /**< 收发接口通道模式*/
+    IOMode ioMode; /**< 接口电平模式*/
+};
+
+/**
+ * @brief 配置TX NCO相关参数结构体
+ */
+struct TxNCO
+{
+    bool txUseBist; /**< 是否开启BIST模式*/
+    double txNCOFreq; /**< NCO频率*/
+};
+
+/**
+ * @brief 配置RX NCO相关参数结构体
+ */
+struct RxNCO
+{
+    bool rxUseBist; /**< 是否开启BIST模式*/
+    bool rxNCOBypass; /**< 是否Bypass NCO*/
+    bool rxNCOUpward; /**< 开启上/下混频模式*/
+    bool rxNCOMaster; /**< 使用Master/Slaver模式*/
+    double rxNCOFreq; /**< NCO频率*/
+};
+
+/**
+ * @brief 配置接收通道相关参数结构体
+ */
+struct RxConfig
+{
+    double bandwidth; /**< 接收通道1dB带宽，单位MHz*/
+    int tia; /**< 接收通道TIA增益配置，推荐配置6*/
+    int mixer; /**< 接收通道Mixer增益配置*/
+};
+
+/**
+ * @brief 配置发射通道相关参数结构体
+ */
+struct TxConfig
+{
+    double bandwidth; /**< 发射通道1dB带宽，单位MHz*/
+    int mixer; /**< 发射通道Mixer增益配置*/
+};
+
+/**
+ * @brief 配置滤波器相关参数结构体，0代表bypass
+ */
+struct Filters
+{
+    int fir; /**< FIR滤波器抽取/插值倍数*/
+    int hbf1; /**< HBF1滤波器抽取/插值倍数*/
+    int hbf2; /**< HBF2滤波器抽取/插值倍数*/
+    int hbf3; /**< HBF3滤波器抽取/插值倍数*/
+    int cic; /**< CIC滤波器抽取/插值倍数*/
+};
+
+/**
+ * @brief 配置电源模式结构体，1代表该模块上电
+ */
+struct Power
+{
+    bool dig_tx2;
+    bool dig_tx1;
+    bool dig_rx3;
+    bool dig_rx2;
+    bool dig_rx1;
+    bool fref1_rx;
+    bool auxadc2;
+    bool auxadc1;
+    bool auxdac;
+    bool temp_sensor;
+    bool bgr;
+    bool exlo;
+    bool tx2;
+    bool tx1;
+    bool rx3;
+    bool rx2;
+    bool rx1;
+    bool pll5_ldo;
+    bool pll5;
+    bool pll4_ldo;
+    bool pll4;
+    bool pll3_ldo;
+    bool pll3;
+    bool pll2_ldo;
+    bool pll2;
+    bool pll1_ldo;
+    bool pll1;
+    bool bbpll;
+};
+
+/**
+ * @brief 配置电源模式管理，包含模式选择，接收模式，发射模式，FDD模式
+ */
+struct PowerManagement
+{
+    PowerMode powerMode;
+    Power rxPower;
+    Power txPower;
+    Power fddPower;
+};
+
+/**
+ * @brief 储存窄带校准结果的结构体
+ */
+struct CalibPredis
+{
+    int bHigh;
+    int bLow;
+    int cHigh;
+    int cLow;
+    int dciHigh;
+    int dciLow;
+    int dcqHigh;
+    int dcqLow;
+};
+
+/**
+ * @brief CX9261A结构体
+ */
+struct CX9261AConfiguration
+{
+    TemperatureComp tempComp; /**< 温度补偿*/
+    AGC agc; /**< AGC结构体*/
+    Interface interface; /**< Interface结构体*/
+    Clock clock; /**< Clock结构体*/
+    PllSource pllSource; /**< PllSource结构体*/
+    Calib calib; /**< Calib结构体*/
+    PllFreq pllFreq; /**< PllFreq结构体*/
+    TxNCO txNco; /**< TxNCO结构体*/
+    RxNCO rxNco; /**< RxNCO结构体*/
+    RxConfig rx1Config; /**< RxConfig结构体*/
+    RxConfig rx2Config; /**< RxConfig结构体*/
+    RxConfig rx3Config; /**< RxConfig结构体*/
+    TxConfig tx1Config; /**< TxConfig结构体*/
+    TxConfig tx2Config; /**< TxConfig结构体*/
+    Filters rxFilters; /**< Filters结构体*/
+    Filters txFilters; /**< Filters结构体*/
+    PowerManagement powerManagement; /**< PowerManagement结构体*/
+    std::vector<double> rxFIRCoe; /**< Rx FIR滤波器系数*/
+    std::vector<double> txFIRCoe; /**< Tx FIR滤波器系数*/
+};
+} // namespace CX9261A
+#endif // CX9261ADRIVER_DEFS_H

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_cx9261a_api_1_9_0/main.cpp

@@ -0,0 +1,138 @@
+#include "cx9261adriver.h"
+#include "defs.h"
+
+int main() {
+
+    // 芯片配置结构体
+    CX9261A::CX9261AConfiguration configuration;
+    // 电源管理
+    // 接收模式电源管理
+    configuration.powerManagement.rxPower = {0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0,
+                                             0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1};
+    // 发射模式电源管理
+    configuration.powerManagement.txPower = {1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 1, 1,
+                                             0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1};
+    // FDD模式电源管理
+    configuration.powerManagement.fddPower = {1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 1, 1,
+                                              0, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 1};
+    // 电源模式 即配置结束后的电源模式
+    configuration.powerManagement.powerMode = CX9261A::PowerMode::Receive;
+    // 接口模式
+    configuration.interface = {.workMode = CX9261A::WorkMode::Rx,
+                               .trMode = CX9261A::TrMode::R1T1,
+                               .portMode = CX9261A::PortMode::Single,
+                               .ioMode = CX9261A::IOMode::CMOS};
+    // 时钟相关
+    configuration.clock = {.ref = 125, .adc = 64, .refDiv = 2, .bbUseIntDiv = false, .refDoubler = false};
+    // 本振相关
+    using LoSource = CX9261A::LoSource;
+    // 本振来源
+    configuration.pllSource = {.rxUseExt = false,
+                               .txUseExt = false,
+                               .rx1Source = LoSource::Pll1,
+                               .rx2Source = LoSource::Pll1,
+                               .rx3Source = LoSource::Off,
+                               .tx1Source = LoSource::Off,
+                               .tx2Source = LoSource::Off};
+    // 本振频率 注意：使用的所有PLL，频率必须设为正数
+    configuration.pllFreq = {
+        .pll1Freq = 5800, .pll2Freq = 5800, .pll3Freq = 800, .pll4Freq = 900, .pll5Freq = 1000};
+    // Rx通道 注意：tia推荐配置为6 Mixer为三个通道共用同一个寄存器
+    configuration.rx1Config = {.bandwidth = 32, .tia = 6, .mixer = 31};
+    configuration.rx2Config = {.bandwidth = 32, .tia = 6, .mixer = 31};
+    configuration.rx3Config = {.bandwidth = 32, .tia = 6, .mixer = 31};
+    // Tx通道
+    configuration.tx1Config = {.bandwidth = 20, .mixer = 63};
+    configuration.tx2Config = {.bandwidth = 20, .mixer = 63};
+    // 接收滤波器
+    configuration.rxFilters = {.fir = 0, .hbf1 = 0, .hbf2 = 0, .hbf3 = 0, .cic = 0};
+    // 发射滤波器
+    configuration.txFilters = {.fir = 0, .hbf1 = 2, .hbf2 = 2, .hbf3 = 0, .cic = 0};
+    // Rx NCO
+    configuration.rxNco = {
+        .rxUseBist = false, .rxNCOBypass = true, .rxNCOUpward = true, .rxNCOMaster = true, .rxNCOFreq = 0};
+    // Tx NCO
+    configuration.txNco = {.txUseBist = false, .txNCOFreq = 0};
+    // AGC 注意：mode = 0表示关闭AGC，此时其他的参数可以不配置
+    configuration.calib = {
+        .calibDC = true,
+        .dcCalibMethod = CX9261A::DCCalibMethod::Tracking,
+        .dcTrackingLength = 16384,
+        .dcHighPassFactor = 8191,
+        .rx1CalibPll = int(LoSource::Pll1) | int(LoSource::Pll2),
+        .rx2CalibPll = int(LoSource::Pll1) | int(LoSource::Pll2),
+        .rx3CalibPll = int(LoSource::Pll5),
+        .tx1CalibPll = 0,
+        .tx2CalibPll = 0,
+        .rxMethod = CX9261A::CalibMethod::MultiPoints,
+        .txMethod = CX9261A::CalibMethod::Bisec,
+        .f0 = 4
+    };
+    configuration.agc = {.mode = 0};
+    // 校准
+    configuration.calib.rxMultiPoints = {2200, 2400, 2600, 2800, 3000, 3200, 3400, 3600, 3800, 4000, 4200,
+                                         4400, 4600, 4800, 5000, 5200, 5400, 5600, 5800, 6000};
+    // 配置温补模式为跳子带温补
+    configuration.tempComp = CX9261A::TemperatureComp::Band;
+
+    // 开始配置芯片
+    CX9261A::initialChip(); // 最开始需要调用此函数
+    CX9261A::initialPowerConfig(configuration);
+    // 配置温补
+    configTemperatureCompensation(configuration.tempComp);
+    using PowerMode = CX9261A::PowerMode;
+    // 不需要自定义电源管理时，这部分代码可以省略
+    CX9261A::configPowerPins(configuration.powerManagement.rxPower, PowerMode::Receive);
+    CX9261A::configPowerPins(configuration.powerManagement.txPower, PowerMode::Transmit);
+    CX9261A::configPowerPins(configuration.powerManagement.fddPower, PowerMode::Duplex);
+    // 配置pll
+    CX9261A::configBBPLL(configuration);
+    CX9261A::configPllSource(configuration.pllSource);
+    CX9261A::configPll1(configuration.pllFreq.pll1Freq, configuration.clock);
+    CX9261A::configPll2(configuration.pllFreq.pll2Freq, configuration.clock);
+    // 配置Rx通道
+    CX9261A::configRxChannel(configuration.rx1Config, CX9261A::RxChannel::Rx1);
+    CX9261A::configRxChannel(configuration.rx2Config, CX9261A::RxChannel::Rx2);
+    CX9261A::configRxChannel(configuration.rx3Config, CX9261A::RxChannel::Rx3);
+    // 配置Tx通道
+    using TxChannel = CX9261A::TxChannel;
+    CX9261A::configTxChannelFrequency(configuration.pllFreq.pll1Freq, TxChannel::Tx1);
+    CX9261A::configTxChannelFrequency(configuration.pllFreq.pll2Freq, TxChannel::Tx2);
+    CX9261A::configTxChannel(configuration.tx1Config, TxChannel::Tx1);
+    CX9261A::configTxChannel(configuration.tx2Config, TxChannel::Tx2);
+    // 配置滤波器
+    CX9261A::configRxFilters(configuration.rxFilters);
+    CX9261A::configTxFilters(configuration.txFilters);
+    // 配置NCO
+    CX9261A::configRxNco(configuration.rxNco, configuration.clock.adc);
+    const int filters = std::max(configuration.rxFilters.fir, 1) * std::max(configuration.rxFilters.hbf3, 1) *
+                        std::max(configuration.rxFilters.hbf2, 1) *
+                        std::max(configuration.rxFilters.hbf1, 1) * std::max(configuration.rxFilters.cic, 1);
+    CX9261A::configTxNco(configuration.txNco, configuration.clock.adc / filters);
+    // 配置AGC
+    CX9261A::configAGC(configuration.agc);
+    // 切换到休眠模式
+    CX9261A::configPowerMode(PowerMode::Sleep);
+    CX9261A::pause(1000);
+    // 切换到校准模式
+    CX9261A::configPowerMode(PowerMode::Calib);
+    CX9261A::pause(100);
+    // 锁定BBPLL
+    CX9261A::afcBBPll();
+    // 配置校准
+    CX9261A::configADCCalib(configuration.clock.adc);
+    CX9261A::configFlashCalib();
+    configDcCalib(configuration.calib);
+    configQecCalib(configuration);
+    CX9261A::loadRxCalibPredis(0, CX9261A::RxChannel::Rx1, LoSource::Pll1);
+    CX9261A::loadRxCalibPredis(0, CX9261A::RxChannel::Rx2, LoSource::Pll1);
+    // 配置接口
+    CX9261A::configInterface(configuration.interface);
+    // 配置FPGA接口相关 此为示例，仅适用于Demo工程，用户应根据实际情况进行配置
+    CX9261A::configFPGA(configuration.interface);
+    // 锁定PLL1
+    CX9261A::afcPll1();
+    // 锁定PLL2
+    CX9261A::afcPll2();
+    return 0;
+}

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_cx9261a_api_1_9_0/utils.h

@@ -0,0 +1,99 @@
+/**
+ * @file utils.h
+ */
+
+#ifndef CX9261ADRIVER_UTILS_H
+#define CX9261ADRIVER_UTILS_H
+#include <algorithm>
+#include <bitset>
+#include <cmath>
+#include <string>
+namespace CX9261A {
+#if __cplusplus >= 201703L
+template <typename T>
+constexpr const T& clamp(const T& v, const T& lo, const T& hi) {
+    return std::clamp(v, lo, hi);
+}
+#else
+template <typename T>
+constexpr const T& clamp(const T& v, const T& lo, const T& hi) {
+    return std::max(std::min(hi, v), lo);
+}
+#endif
+
+template <typename Float>
+int round(Float f) {
+    return static_cast<int>(std::round(f));
+}
+
+template <typename Float>
+long long round64(Float f) {
+    return static_cast<long long>(std::round(f));
+}
+
+template <typename Float>
+int floor(Float f) {
+    return static_cast<int>(std::floor(f));
+}
+
+template <typename Float>
+long long floor64(Float f) {
+    return static_cast<long long>(std::floor(f));
+}
+
+template <typename Float>
+int ceil(Float f) {
+    return static_cast<int>(std::ceil(f));
+}
+
+template <typename Float>
+long long ceil64(Float f) {
+    return static_cast<long long>(std::ceil(f));
+}
+/**
+* @brief Register类，提供方便的位操作函数
+*/
+class Register {
+public:
+    template <typename T = int>
+    constexpr Register(const T value = 0) {
+        static_assert(std::is_integral_v<T>, "Register value must be integral!");
+        m_value = static_cast<unsigned long long>(value);
+    }
+    /**
+    * 以十进制返回寄存器值
+    */
+    unsigned char value() const { return static_cast<unsigned char>(m_value.to_ulong()); }
+    /**
+    * 对寄存器值进行部分值的替换操作
+    * 例：replace(7, 4, 0b1111); 使寄存器的高四位为1
+    * @param start 起始位
+    * @param end 中止位
+    * @param after 要替换的值
+    */
+    void replace(const unsigned int start, const unsigned int end, unsigned char after) {
+        for (auto i = end; i <= start; ++i) {
+            m_value[i] = (after >> (i - end)) & 0b1;
+        }
+    }
+
+    auto operator[](const size_t position) { return m_value[position]; }
+
+    template <typename Type>
+    operator Type() const {
+        static_assert(std::is_integral_v<Type>, "Type must be an integral");
+        return static_cast<Type>(m_value.to_ulong());
+    }
+
+private:
+    std::bitset<8> m_value{};
+};
+
+template <int N>
+std::string frac2bin(const double frac) {
+    const long double num = frac * (pow(2.0, N));
+    std::string ret = std::bitset<N>(std::floor(num)).to_string();
+    return ret;
+}
+}  // namespace CX9261A
+#endif  // CX9261ADRIVER_UTILS_H

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_cx9261a_api_lib_c/config/app_config.h

@@ -0,0 +1,331 @@
+/*****************************************************************************/
+/**
+ * Description: Global configurations.
+ *
+ * Date: 2021-04-28 13:19
+ * Last Editors: Fan Hao
+ * Last Edit Time: [2022-05-23 20:32]
+ *
+ * Revisions: Rev 0.0
+ * History:
+ * [2021-04-28]: Initial edition.
+ *
+ * Copyright(c) 2024 Beijing Institute of Technology.
+ * Lab of Communication and Networking
+ *
+ ******************************************************************************/
+
+#ifndef __APP_CONFIG_H_
+#define __APP_CONFIG_H_
+
+#define XILINX_PLATFORM
+
+#include "xparameters.h"
+
+/******** Software Version ********/
+#define _APP_VER 0x00010008
+
+#define _APP_VER_MAIN ((_APP_VER & 0xFF000000) >> 24)
+#define _APP_VER_MINOR ((_APP_VER & 0x00FF0000) >> 16)
+#define _APP_VER_PATCH (_APP_VER & 0x0000FFFF)
+
+/*********** Debug Info Level ************/
+//  #define _DEBUG_LEVEL 1
+// 3 - print all debug info
+// 2 - print warnings and errors
+// 1 - print only errors
+// other - print nothing
+
+#define DATALINK_ENABLE_AUTORECONNECT
+#define DATALINK_ENABLE_AUTOTIMESYNC
+// #define DATALINK_ENABLE_BERTEST
+
+/************ Hardware Configs ************/
+#ifdef __aarch64__ // Zynq MPSoC (Zynq UltraScale+)
+#define CPU_CLK_HZ XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
+#define FCLK_CLK0_HZ 100000000
+#define APP_TIMER_CLK_HZ FCLK_CLK0_HZ
+#else // Zynq-7000
+#define CPU_CLK_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#define APP_TIMER_CLK_HZ (CPU_CLK_HZ / 2)
+#define FCLK_CLK0_HZ 100000000
+#endif
+/********* Zynq Platform Configs **********/
+// APP Timer (for logging)
+#ifdef __aarch64__ // Zynq MPSoC (Zynq UltraScale+)
+#define APPTIMER_DEVICE_ID XPAR_AXI_TIMER_DEVICE_ID
+#define APPTIMER_INTR_ID XPAR_FABRIC_AXI_TIMER_INTERRUPT_INTR
+#else
+#define APPTIMER_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
+#define APPTIMER_INTR_ID XPAR_SCUTIMER_INTR
+#endif
+// Physical Layer Configs
+#define PHY_DEVICE_ID (0x01 | 0x00)
+#define PHY_BASEADDR XPAR_PHYC_BASEADDR
+#define PHY_BEAM_FORMING_ENABLE
+// -- Antenna Bram Configs
+#define PHY_ANTCONFIG_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_ANT_CONFIG_BRAM_CTRL_DEVICE_ID
+#define PHY_ANTINFO_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_ANT_BEAM_BRAM_CTRL_DEVICE_ID
+// -- Buffers
+#define PHY_TXBUFF_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_TX_FRAME_BRAM_CTRL_DEVICE_ID
+#define PHY_RXBUFF_BRAM_DEVICE_ID XPAR_PHY_DATA_INTERFACE_RX_FRAME_BRAM_CTRL_DEVICE_ID
+// -- Xadc
+#define PHY_HW_SYSMON_DEVICE_ID XPAR_SYSTEM_MANAGEMENT_DEVICE_ID
+// -- Interrupt id
+#define PHY_INTR_ID XPAR_FABRIC_PHY_IRQ_INTR
+#define PERIODIC_5MS_INTR_ID XPAR_FABRIC_PHY_5MS_DELAY_2MS_INTR
+
+// Time Controller Configs
+#define TIME_CONTROLLER_BASEADDR XPAR_TMC_BASEADDR
+
+// System Bus Configs
+#define SYSBUS_BASE_ADDR XPAR_SYSTEMBUS_BASEADDR
+#define SYSBUS_TX_INTR_ID XPAR_FABRIC_SYSTEMBUS_TX_DONE_INTR
+#define SYSBUS_RX_INTR_ID XPAR_FABRIC_SYSTEMBUS_RX_DONE_INTR
+
+// INTC configis
+#define INTC_DEVICE_ID XPAR_SCUGIC_0_DEVICE_ID
+
+/********* Hardware Configurations **********/
+
+// Clock Management Configuration
+//#define HMC7044
+//#define AD9528
+//#define LMK04828
+//#define LMX2594_ADC
+//#define LMX2594_DAC
+
+// RF Transceiver Configuration
+//#define AD9361_REG
+//#define AD9361_API
+//#define RFSOC
+#define CX9261A
+
+// ADC Configuration
+//#define AD9653
+//#define AD9694
+
+// RFSoC Configuration
+#ifdef RFSOC
+#define RFDC_DEVICE_ID 	XPAR_XRFDC_0_DEVICE_ID
+#endif
+
+// AD9361 Configuration
+#define SPI_INTERFACE_SPI_ENGINE
+#define HAVE_SPLIT_GAIN_TABLE 1 /* only set to 0 in case split_gain_table_mode_enable = 0*/
+#define HAVE_TDD_SYNTH_TABLE 1	/* only set to 0 in case split_gain_table_mode_enable = 0*/
+#define AD9361_DEVICE 1			/* set it 1 if AD9361 device is used, 0 otherwise */
+#define AD9364_DEVICE 0			/* set it 1 if AD9364 device is used, 0 otherwise */
+#define AD9363A_DEVICE 0		/* set it 1 if AD9363A device is used, 0 otherwise */
+#define HAVE_VERBOSE_MESSAGES	/* Recommended during development prints errors and warnings */
+// #define HAVE_DEBUG_MESSAGES /* For Debug purposes only */
+//  -- AD9361 SPI Engine Configuration
+#define AD9361_SPI_DEVICE_ID 0
+#define AD9361_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
+#define AD9361_SPI_ENGINE_MAX_SPEED 5000000
+//#define AD9361_SPI_ENGINE_BASEADDR 0
+#define AD9361_SPI_ENGINE_BASEADDR 0
+#define AD9361_SPI_ENGINE_DATA_WIDTH 8
+#define AD9361_SPI_ENGINE_CS_DELAY 3
+#define AD9361_1_SPI_CS 0x01
+#define AD9361_2_SPI_CS 0x02
+#define AD9361_TIMEOUT_TH 2000
+// -- AD9361 GPIO Configurations
+#define AD9361_GPIO_DEVICE_ID 0
+#define AD9361_GPIO_OFFSET 54
+#define AD9361_GPIO_INPUT 0
+#define AD9361_GPIO_OUTPUT 1
+#define AD9361_GPIO_DISABLE 0
+#define AD9361_GPIO_ENABLE 1
+// -- AD9361-1
+#define AD9361_1_TXNRX (AD9361_GPIO_OFFSET + 6)
+#define AD9361_1_ENABLE (AD9361_GPIO_OFFSET + 7)
+#define AD9361_1_EN_AGC (AD9361_GPIO_OFFSET + 8)
+#define AD9361_1_RESET_B (AD9361_GPIO_OFFSET + 9)
+#define AD9361_1_CTRL_OUT0 (AD9361_GPIO_OFFSET + 10)
+#define AD9361_1_CTRL_OUT1 (AD9361_GPIO_OFFSET + 11)
+#define AD9361_1_CTRL_OUT2 (AD9361_GPIO_OFFSET + 12)
+#define AD9361_1_CTRL_OUT3 (AD9361_GPIO_OFFSET + 13)
+#define AD9361_1_CTRL_OUT4 (AD9361_GPIO_OFFSET + 14)
+#define AD9361_1_CTRL_OUT5 (AD9361_GPIO_OFFSET + 15)
+#define AD9361_1_CTRL_OUT6 (AD9361_GPIO_OFFSET + 16)
+#define AD9361_1_CTRL_OUT7 (AD9361_GPIO_OFFSET + 17)
+#define AD9361_1_CTRL_IN0 (AD9361_GPIO_OFFSET + 18)
+#define AD9361_1_CTRL_IN1 (AD9361_GPIO_OFFSET + 19)
+#define AD9361_1_CTRL_IN2 (AD9361_GPIO_OFFSET + 20)
+#define AD9361_1_CTRL_IN3 (AD9361_GPIO_OFFSET + 21)
+// AD9361-2
+#define AD9361_2_TXNRX (AD9361_GPIO_OFFSET + 22)
+#define AD9361_2_ENABLE (AD9361_GPIO_OFFSET + 23)
+#define AD9361_2_EN_AGC (AD9361_GPIO_OFFSET + 24)
+#define AD9361_2_RESET_B (AD9361_GPIO_OFFSET + 25)
+#define AD9361_2_CTRL_OUT0 (AD9361_GPIO_OFFSET + 26)
+#define AD9361_2_CTRL_OUT1 (AD9361_GPIO_OFFSET + 27)
+#define AD9361_2_CTRL_OUT2 (AD9361_GPIO_OFFSET + 28)
+#define AD9361_2_CTRL_OUT3 (AD9361_GPIO_OFFSET + 29)
+#define AD9361_2_CTRL_OUT4 (AD9361_GPIO_OFFSET + 30)
+#define AD9361_2_CTRL_OUT5 (AD9361_GPIO_OFFSET + 31)
+#define AD9361_2_CTRL_OUT6 (AD9361_GPIO_OFFSET + 32)
+#define AD9361_2_CTRL_OUT7 (AD9361_GPIO_OFFSET + 33)
+#define AD9361_2_CTRL_IN0 (AD9361_GPIO_OFFSET + 34)
+#define AD9361_2_CTRL_IN1 (AD9361_GPIO_OFFSET + 35)
+#define AD9361_2_CTRL_IN2 (AD9361_GPIO_OFFSET + 36)
+#define AD9361_2_CTRL_IN3 (AD9361_GPIO_OFFSET + 37)
+// AD9361-Status Code
+#define AD9361_SYNC (AD9361_GPIO_OFFSET + 38)
+#define AD9361_RX_FIFO_RST (AD9361_GPIO_OFFSET + 39)
+#define AD9361_1_CAL_START (AD9361_GPIO_OFFSET + 40)
+#define AD9361_2_CAL_START (AD9361_GPIO_OFFSET + 41)
+#define AD9361_RECAL (AD9361_GPIO_OFFSET + 42)
+#define AD9361_TX_SWITCH (AD9361_GPIO_OFFSET + 43)
+#define AD9361_1_CAL_DONE (AD9361_GPIO_OFFSET + 44)
+#define AD9361_2_CAL_DONE (AD9361_GPIO_OFFSET + 45)
+#define AD9361_CAL_RESULT (AD9361_GPIO_OFFSET + 46)
+
+typedef enum
+{
+	TX_FREQ_125,
+	TX_FREQ_126,
+	TX_FREQ_4125
+} ad9361TxFreq;
+
+// CX9261A Configurations
+#define CX9261A_GPIO_DEVICE_ID 0
+#define CX9261A_GPIO_OFFSET 54
+#define CX9261A_NRST (CX9261A_GPIO_OFFSET+0)
+#define CX9261A_TXNRX_TRX1 (CX9261A_GPIO_OFFSET+1)
+#define CX9261A_TXNRX_TRX2 (CX9261A_GPIO_OFFSET+2)
+#define CX9261A_TXNRX_RXFB (CX9261A_GPIO_OFFSET+3)
+#define CX9261A_ENABLE_TRX1 (CX9261A_GPIO_OFFSET+4)
+#define CX9261A_ENABLE_TRX2 (CX9261A_GPIO_OFFSET+5)
+#define CX9261A_ENABLE_RXFB (CX9261A_GPIO_OFFSET+6)
+#define CX9261A_PL_RST (CX9261A_GPIO_OFFSET+7)
+#define CX9261A_TR_SEL (CX9261A_GPIO_OFFSET+8)
+#define CX9261A_TDD_FDD_SEL (CX9261A_GPIO_OFFSET+9)
+#define CX9261A_R1T1_R2T2_SEL (CX9261A_GPIO_OFFSET+10)
+#define CX9261A_SP_DP_SEL (CX9261A_GPIO_OFFSET+11)
+#define CX9261A_MCLK_DELAY_CTRL0 (CX9261A_GPIO_OFFSET+12)
+#define CX9261A_MCLK_DELAY_CTRL1 (CX9261A_GPIO_OFFSET+13)
+#define CX9261A_MCLK_DELAY_CTRL2 (CX9261A_GPIO_OFFSET+14)
+#define CX9261A_HOP_FLAG (CX9261A_GPIO_OFFSET+15)
+// -- CX9261A SPI Engine Configuration
+#define CX9261A_SPI_DEVICE_ID 0
+#define CX9261A_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
+#define CX9261A_SPI_ENGINE_MAX_SPEED 5000000
+//#define CX9261A_SPI_ENGINE_BASEADDR 0
+#define CX9261A_SPI_ENGINE_BASEADDR 0
+#define CX9261A_SPI_ENGINE_DATA_WIDTH 8
+#define CX9261A_SPI_ENGINE_CS_DELAY 3
+#define CX9261A_SPI_CS 0x00
+
+// HMC7044 Configurations
+#define HMC7044_GPIO_DEVICE_ID 0
+#define HMC7044_GPIO_OFFSET 54
+#define HMC7044_RESET (HMC7044_GPIO_OFFSET + 0)
+#define HMC7044_SYNC (HMC7044_GPIO_OFFSET + 1)
+#define HMC7044_GPIO_0 (HMC7044_GPIO_OFFSET + 2)
+#define HMC7044_GPIO_1 (HMC7044_GPIO_OFFSET + 3)
+#define HMC7044_GPIO_2 (HMC7044_GPIO_OFFSET + 4)
+#define HMC7044_GPIO_3 (HMC7044_GPIO_OFFSET + 5)
+// -- HMC7044 SPI Engine Configuration
+#define HMC7044_SPI_DEVICE_ID 0
+#define HMC7044_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
+#define HMC7044_SPI_ENGINE_MAX_SPEED 5000000
+#define HMC7044_SPI_ENGINE_BASEADDR 0
+#define HMC7044_SPI_ENGINE_DATA_WIDTH 8
+#define HMC7044_SPI_ENGINE_CS_DELAY 3
+#define HMC7044_SPI_CS 0x00
+
+// AD9528 Configurations
+#define AD9528_GPIO_DEVICE_ID 0
+#define AD9528_GPIO_OFFSET 54
+#define AD9528_RESETB (AD9528_GPIO_OFFSET+0)
+#define AD9528_SYSREF_REQ (AD9528_GPIO_OFFSET+1)
+#define AD9528_STATUS_0 (AD9528_GPIO_OFFSET+2)
+#define AD9528_STATUS_1 (AD9528_GPIO_OFFSET+3)
+// -- AD9528 SPI Engine Configuration
+#define AD9528_SPI_DEVICE_ID 0
+#define AD9528_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
+#define AD9528_SPI_ENGINE_MAX_SPEED 5000000
+//#define AD9528_SPI_ENGINE_BASEADDR 0
+#define AD9528_SPI_ENGINE_BASEADDR 0
+#define AD9528_SPI_ENGINE_DATA_WIDTH 8
+#define AD9528_SPI_ENGINE_CS_DELAY 3
+#define AD9528_SPI_CS 0x00
+
+// LMK04828 Configurations
+#define LMK04828_GPIO_DEVICE_ID 0
+#define LMK04828_GPIO_OFFSET 54
+// -- LMK04828 SPI Engine Configuration
+#define LMK04828_SPI_DEVICE_ID 0
+#define LMK04828_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
+#define LMK04828_SPI_ENGINE_MAX_SPEED 5000000
+#define LMK04828_SPI_ENGINE_BASEADDR 0
+#define LMK04828_SPI_ENGINE_DATA_WIDTH 8
+#define LMK04828_SPI_ENGINE_CS_DELAY 3
+#define LMK04828_SPI_CS 0x00
+
+// LMX2594_ADC Configurations
+#define LMX2594_ADC_GPIO_DEVICE_ID 0
+#define LMX2594_ADC_GPIO_OFFSET 54
+// -- LMX2594_ADC SPI Engine Configuration
+#define LMX2594_ADC_SPI_DEVICE_ID 0
+#define LMX2594_ADC_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
+#define LMX2594_ADC_SPI_ENGINE_MAX_SPEED 5000000
+#define LMX2594_ADC_SPI_ENGINE_BASEADDR 0
+#define LMX2594_ADC_SPI_ENGINE_DATA_WIDTH 8
+#define LMX2594_ADC_SPI_ENGINE_CS_DELAY 3
+#define LMX2594_ADC_SPI_CS 0x01
+
+// LMX2594_DAC Configurations
+#define LMX2594_DAC_GPIO_DEVICE_ID 0
+#define LMX2594_DAC_GPIO_OFFSET 54
+// -- LMX2594_DAC SPI Engine Configuration
+#define LMX2594_DAC_SPI_DEVICE_ID 0
+#define LMX2594_DAC_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
+#define LMX2594_DAC_SPI_ENGINE_MAX_SPEED 5000000
+#define LMX2594_DAC_SPI_ENGINE_BASEADDR 0
+#define LMX2594_DAC_SPI_ENGINE_DATA_WIDTH 8
+#define LMX2594_DAC_SPI_ENGINE_CS_DELAY 3
+#define LMX2594_DAC_SPI_CS 0x02
+
+// AD9653 Configurations
+#define AD9653_GPIO_DEVICE_ID 0
+#define AD9653_GPIO_OFFSET 54
+#define AD9653_POWR_DOWN (AD9653_GPIO_OFFSET+0)
+// -- AD9653 SPI Engine Configuration
+#define AD9653_SPI_DEVICE_ID 0
+#define AD9653_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
+#define AD9653_SPI_ENGINE_MAX_SPEED 5000000
+//#define AD9653_SPI_ENGINE_BASEADDR 0
+#define AD9653_SPI_ENGINE_BASEADDR 0
+#define AD9653_SPI_ENGINE_DATA_WIDTH 8
+#define AD9653_SPI_ENGINE_CS_DELAY 3
+#define AD9653_SPI_CS 0x03
+
+// AD9694 Configurations
+#define AD9694_GPIO_DEVICE_ID 0
+#define AD9694_GPIO_OFFSET 54
+// -- AD9694 SPI Engine Configuration
+#define AD9694_SPI_DEVICE_ID 0
+#define AD9694_SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
+#define AD9694_SPI_ENGINE_MAX_SPEED 5000000
+//#define AD9694_SPI_ENGINE_BASEADDR 0
+#define AD9694_SPI_ENGINE_BASEADDR 0
+#define AD9694_SPI_ENGINE_DATA_WIDTH 8
+#define AD9694_SPI_ENGINE_CS_DELAY 3
+#define AD9694_SPI_CS 0x03
+
+// Configuration Check
+#if defined(PHY_BEAM_SET_PRESET) && !defined(PHY_BEAM_FORMING_ENABLE)
+#define PHY_BEAM_FORMING_ENABLE
+#warning To impliment beam scan must enable beam forming...
+#endif
+
+#if defined(DATALINK_ENABLE_BERTEST)
+#if !defined(DATALINK_ENABLE_AUTOTIMESYNC)
+#warning To enbale bit error rate test, auto time-sync should be enabled...
+#endif
+#endif
+
+#endif //__APP_CONFIG_H_

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_cx9261a_api_lib_c/dev_profile/ad9361_profile.c

@@ -0,0 +1,340 @@
+#include "dev_profile.h"
+#include "../config/app_config.h"
+#include "../drivers/rf-transceiver/ad9361/ad9361_api.h"
+#include "../drivers/axi_core/spi_engine/spi_engine.h"
+#include "../drivers/platform/xilinx_gpio.h"
+
+struct spi_engine_init_param spi_engine_param = {
+	.ref_clk_hz = AD9361_SPI_ENGINE_REF_CLK,
+	.type = SPI_ENGINE,
+	.spi_engine_baseaddr = AD9361_SPI_ENGINE_BASEADDR,
+	.cs_delay = AD9361_SPI_ENGINE_CS_DELAY,
+	.data_width = AD9361_SPI_ENGINE_DATA_WIDTH
+};
+
+struct xil_gpio_init_param xil_gpio_param = {
+	.type = GPIO_PS,
+	.device_id = AD9361_GPIO_DEVICE_ID
+};
+
+AD9361_InitParam ad9361_default_init_param = {
+	/* Device selection */
+	ID_AD9361,	// dev_sel
+	/* Reference Clock */
+	48000000UL,	//reference_clk_rate
+	/* Base Configuration */
+	1,		//two_rx_two_tx_mode_enable *** adi,2rx-2tx-mode-enable
+	1,		//one_rx_one_tx_mode_use_rx_num *** adi,1rx-1tx-mode-use-rx-num
+	1,		//one_rx_one_tx_mode_use_tx_num *** adi,1rx-1tx-mode-use-tx-num
+	1,		//frequency_division_duplex_mode_enable *** adi,frequency-division-duplex-mode-enable
+	0,		//frequency_division_duplex_independent_mode_enable *** adi,frequency-division-duplex-independent-mode-enable
+	0,		//tdd_use_dual_synth_mode_enable *** adi,tdd-use-dual-synth-mode-enable
+	0,		//tdd_skip_vco_cal_enable *** adi,tdd-skip-vco-cal-enable
+	0,		//tx_fastlock_delay_ns *** adi,tx-fastlock-delay-ns
+	0,		//rx_fastlock_delay_ns *** adi,rx-fastlock-delay-ns
+	0,		//rx_fastlock_pincontrol_enable *** adi,rx-fastlock-pincontrol-enable
+	0,		//tx_fastlock_pincontrol_enable *** adi,tx-fastlock-pincontrol-enable
+	0,		//external_rx_lo_enable *** adi,external-rx-lo-enable
+	0,		//external_tx_lo_enable *** adi,external-tx-lo-enable
+	5,		//dc_offset_tracking_update_event_mask *** adi,dc-offset-tracking-update-event-mask
+	6,		//dc_offset_attenuation_high_range *** adi,dc-offset-attenuation-high-range
+	5,		//dc_offset_attenuation_low_range *** adi,dc-offset-attenuation-low-range
+	0x28,	//dc_offset_count_high_range *** adi,dc-offset-count-high-range
+	0x32,	//dc_offset_count_low_range *** adi,dc-offset-count-low-range
+	0,		//split_gain_table_mode_enable *** adi,split-gain-table-mode-enable
+	MAX_SYNTH_FREF,	//trx_synthesizer_target_fref_overwrite_hz *** adi,trx-synthesizer-target-fref-overwrite-hz
+	0,		// qec_tracking_slow_mode_enable *** adi,qec-tracking-slow-mode-enable
+	/* ENSM Control */
+	0,		//ensm_enable_pin_pulse_mode_enable *** adi,ensm-enable-pin-pulse-mode-enable
+	0,		//ensm_enable_txnrx_control_enable *** adi,ensm-enable-txnrx-control-enable
+	/* LO Control */
+	4125000000UL,	//rx_synthesizer_frequency_hz *** adi,rx-synthesizer-frequency-hz
+	4126000000UL,	//tx_synthesizer_frequency_hz *** adi,tx-synthesizer-frequency-hz
+	1,				//tx_lo_powerdown_managed_enable *** adi,tx-lo-powerdown-managed-enable
+	/* Rate & BW Control */
+	{768000000, 192000000, 96000000, 48000000, 24000000, 24000000},// rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies
+	{768000000, 192000000, 96000000, 48000000, 24000000, 24000000},// tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies
+	18000000,//rf_rx_bandwidth_hz *** adi,rf-rx-bandwidth-hz
+	18000000,//rf_tx_bandwidth_hz *** adi,rf-tx-bandwidth-hz
+	/* RF Port Control */
+	0,		//rx_rf_port_input_select *** adi,rx-rf-port-input-select
+	0,		//tx_rf_port_input_select *** adi,tx-rf-port-input-select
+	/* TX Attenuation Control */
+	10000,	//tx_attenuation_mdB *** adi,tx-attenuation-mdB
+	0,		//update_tx_gain_in_alert_enable *** adi,update-tx-gain-in-alert-enable
+	/* Reference Clock Control */
+	0,		//xo_disable_use_ext_refclk_enable *** adi,xo-disable-use-ext-refclk-enable
+	{8, 5920},	//dcxo_coarse_and_fine_tune[2] *** adi,dcxo-coarse-and-fine-tune
+	CLKOUT_DISABLE,	//clk_output_mode_select *** adi,clk-output-mode-select
+	/* Gain Control */
+	2,		//gc_rx1_mode *** adi,gc-rx1-mode
+	2,		//gc_rx2_mode *** adi,gc-rx2-mode
+	58,		//gc_adc_large_overload_thresh *** adi,gc-adc-large-overload-thresh
+	4,		//gc_adc_ovr_sample_size *** adi,gc-adc-ovr-sample-size
+	47,		//gc_adc_small_overload_thresh *** adi,gc-adc-small-overload-thresh
+	8192,	//gc_dec_pow_measurement_duration *** adi,gc-dec-pow-measurement-duration
+	0,		//gc_dig_gain_enable *** adi,gc-dig-gain-enable
+	800,	//gc_lmt_overload_high_thresh *** adi,gc-lmt-overload-high-thresh
+	704,	//gc_lmt_overload_low_thresh *** adi,gc-lmt-overload-low-thresh
+	24,		//gc_low_power_thresh *** adi,gc-low-power-thresh
+	15,		//gc_max_dig_gain *** adi,gc-max-dig-gain
+	0,		//gc_use_rx_fir_out_for_dec_pwr_meas_enable *** adi,gc-use-rx-fir-out-for-dec-pwr-meas-enable
+	/* Gain MGC Control */
+	2,		//mgc_dec_gain_step *** adi,mgc-dec-gain-step
+	2,		//mgc_inc_gain_step *** adi,mgc-inc-gain-step
+	0,		//mgc_rx1_ctrl_inp_enable *** adi,mgc-rx1-ctrl-inp-enable
+	0,		//mgc_rx2_ctrl_inp_enable *** adi,mgc-rx2-ctrl-inp-enable
+	0,		//mgc_split_table_ctrl_inp_gain_mode *** adi,mgc-split-table-ctrl-inp-gain-mode
+	/* Gain AGC Control */
+	10,		//agc_adc_large_overload_exceed_counter *** adi,agc-adc-large-overload-exceed-counter
+	2,		//agc_adc_large_overload_inc_steps *** adi,agc-adc-large-overload-inc-steps
+	0,		//agc_adc_lmt_small_overload_prevent_gain_inc_enable *** adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable
+	10,		//agc_adc_small_overload_exceed_counter *** adi,agc-adc-small-overload-exceed-counter
+	4,		//agc_dig_gain_step_size *** adi,agc-dig-gain-step-size
+	3,		//agc_dig_saturation_exceed_counter *** adi,agc-dig-saturation-exceed-counter
+	1000,	// agc_gain_update_interval_us *** adi,agc-gain-update-interval-us
+	0,		//agc_immed_gain_change_if_large_adc_overload_enable *** adi,agc-immed-gain-change-if-large-adc-overload-enable
+	0,		//agc_immed_gain_change_if_large_lmt_overload_enable *** adi,agc-immed-gain-change-if-large-lmt-overload-enable
+	10,		//agc_inner_thresh_high *** adi,agc-inner-thresh-high
+	1,		//agc_inner_thresh_high_dec_steps *** adi,agc-inner-thresh-high-dec-steps
+	12,		//agc_inner_thresh_low *** adi,agc-inner-thresh-low
+	1,		//agc_inner_thresh_low_inc_steps *** adi,agc-inner-thresh-low-inc-steps
+	10,		//agc_lmt_overload_large_exceed_counter *** adi,agc-lmt-overload-large-exceed-counter
+	2,		//agc_lmt_overload_large_inc_steps *** adi,agc-lmt-overload-large-inc-steps
+	10,		//agc_lmt_overload_small_exceed_counter *** adi,agc-lmt-overload-small-exceed-counter
+	5,		//agc_outer_thresh_high *** adi,agc-outer-thresh-high
+	2,		//agc_outer_thresh_high_dec_steps *** adi,agc-outer-thresh-high-dec-steps
+	18,		//agc_outer_thresh_low *** adi,agc-outer-thresh-low
+	2,		//agc_outer_thresh_low_inc_steps *** adi,agc-outer-thresh-low-inc-steps
+	1,		//agc_attack_delay_extra_margin_us; *** adi,agc-attack-delay-extra-margin-us
+	0,		//agc_sync_for_gain_counter_enable *** adi,agc-sync-for-gain-counter-enable
+	/* Fast AGC */
+	64,		//fagc_dec_pow_measuremnt_duration ***  adi,fagc-dec-pow-measurement-duration
+	260,	//fagc_state_wait_time_ns ***  adi,fagc-state-wait-time-ns
+	/* Fast AGC - Low Power */
+	0,		//fagc_allow_agc_gain_increase ***  adi,fagc-allow-agc-gain-increase-enable
+	5,		//fagc_lp_thresh_increment_time ***  adi,fagc-lp-thresh-increment-time
+	1,		//fagc_lp_thresh_increment_steps ***  adi,fagc-lp-thresh-increment-steps
+	/* Fast AGC - Lock Level (Lock Level is set via slow AGC inner high threshold) */
+	1,		//fagc_lock_level_lmt_gain_increase_en ***  adi,fagc-lock-level-lmt-gain-increase-enable
+	5,		//fagc_lock_level_gain_increase_upper_limit ***  adi,fagc-lock-level-gain-increase-upper-limit
+	/* Fast AGC - Peak Detectors and Final Settling */
+	1,		//fagc_lpf_final_settling_steps ***  adi,fagc-lpf-final-settling-steps
+	1,		//fagc_lmt_final_settling_steps ***  adi,fagc-lmt-final-settling-steps
+	3,		//fagc_final_overrange_count ***  adi,fagc-final-overrange-count
+	/* Fast AGC - Final Power Test */
+	0,		//fagc_gain_increase_after_gain_lock_en ***  adi,fagc-gain-increase-after-gain-lock-enable
+	/* Fast AGC - Unlocking the Gain */
+	0,		//fagc_gain_index_type_after_exit_rx_mode ***  adi,fagc-gain-index-type-after-exit-rx-mode
+	1,		//fagc_use_last_lock_level_for_set_gain_en ***  adi,fagc-use-last-lock-level-for-set-gain-enable
+	1,		//fagc_rst_gla_stronger_sig_thresh_exceeded_en ***  adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable
+	5,		//fagc_optimized_gain_offset ***  adi,fagc-optimized-gain-offset
+	10,		//fagc_rst_gla_stronger_sig_thresh_above_ll ***  adi,fagc-rst-gla-stronger-sig-thresh-above-ll
+	1,		//fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en ***  adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable
+	1,		//fagc_rst_gla_engergy_lost_goto_optim_gain_en ***  adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable
+	10,		//fagc_rst_gla_engergy_lost_sig_thresh_below_ll ***  adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll
+	8,		//fagc_energy_lost_stronger_sig_gain_lock_exit_cnt ***  adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt
+	1,		//fagc_rst_gla_large_adc_overload_en ***  adi,fagc-rst-gla-large-adc-overload-enable
+	1,		//fagc_rst_gla_large_lmt_overload_en ***  adi,fagc-rst-gla-large-lmt-overload-enable
+	0,		//fagc_rst_gla_en_agc_pulled_high_en ***  adi,fagc-rst-gla-en-agc-pulled-high-enable
+	0,		//fagc_rst_gla_if_en_agc_pulled_high_mode ***  adi,fagc-rst-gla-if-en-agc-pulled-high-mode
+	64,		//fagc_power_measurement_duration_in_state5 ***  adi,fagc-power-measurement-duration-in-state5
+	2,		//fagc_large_overload_inc_steps *** adi,fagc-adc-large-overload-inc-steps
+	/* RSSI Control */
+	1,		//rssi_delay *** adi,rssi-delay
+	1000,	//rssi_duration *** adi,rssi-duration
+	3,		//rssi_restart_mode *** adi,rssi-restart-mode
+	0,		//rssi_unit_is_rx_samples_enable *** adi,rssi-unit-is-rx-samples-enable
+	1,		//rssi_wait *** adi,rssi-wait
+	/* Aux ADC Control */
+	256,	//aux_adc_decimation *** adi,aux-adc-decimation
+	48000000UL,	//aux_adc_rate *** adi,aux-adc-rate
+	/* AuxDAC Control */
+	1,		//aux_dac_manual_mode_enable ***  adi,aux-dac-manual-mode-enable
+	0,		//aux_dac1_default_value_mV ***  adi,aux-dac1-default-value-mV
+	0,		//aux_dac1_active_in_rx_enable ***  adi,aux-dac1-active-in-rx-enable
+	0,		//aux_dac1_active_in_tx_enable ***  adi,aux-dac1-active-in-tx-enable
+	0,		//aux_dac1_active_in_alert_enable ***  adi,aux-dac1-active-in-alert-enable
+	0,		//aux_dac1_rx_delay_us ***  adi,aux-dac1-rx-delay-us
+	0,		//aux_dac1_tx_delay_us ***  adi,aux-dac1-tx-delay-us
+	0,		//aux_dac2_default_value_mV ***  adi,aux-dac2-default-value-mV
+	0,		//aux_dac2_active_in_rx_enable ***  adi,aux-dac2-active-in-rx-enable
+	0,		//aux_dac2_active_in_tx_enable ***  adi,aux-dac2-active-in-tx-enable
+	0,		//aux_dac2_active_in_alert_enable ***  adi,aux-dac2-active-in-alert-enable
+	0,		//aux_dac2_rx_delay_us ***  adi,aux-dac2-rx-delay-us
+	0,		//aux_dac2_tx_delay_us ***  adi,aux-dac2-tx-delay-us
+	/* Temperature Sensor Control */
+	256,	//temp_sense_decimation *** adi,temp-sense-decimation
+	1000,	//temp_sense_measurement_interval_ms *** adi,temp-sense-measurement-interval-ms
+	0xCE,	//temp_sense_offset_signed *** adi,temp-sense-offset-signed
+	1,		//temp_sense_periodic_measurement_enable *** adi,temp-sense-periodic-measurement-enable
+	/* Control Out Setup */
+	0xFF,	//ctrl_outs_enable_mask *** adi,ctrl-outs-enable-mask
+	0,		//ctrl_outs_index *** adi,ctrl-outs-index
+	/* External LNA Control */
+	0,		//elna_settling_delay_ns *** adi,elna-settling-delay-ns
+	0,		//elna_gain_mdB *** adi,elna-gain-mdB
+	0,		//elna_bypass_loss_mdB *** adi,elna-bypass-loss-mdB
+	0,		//elna_rx1_gpo0_control_enable *** adi,elna-rx1-gpo0-control-enable
+	0,		//elna_rx2_gpo1_control_enable *** adi,elna-rx2-gpo1-control-enable
+	0,		//elna_gaintable_all_index_enable *** adi,elna-gaintable-all-index-enable
+	/* Digital Interface Control */
+	0,		//digital_interface_tune_skip_mode *** adi,digital-interface-tune-skip-mode
+	0,		//digital_interface_tune_fir_disable *** adi,digital-interface-tune-fir-disable
+	1,		//pp_tx_swap_enable *** adi,pp-tx-swap-enable
+	1,		//pp_rx_swap_enable *** adi,pp-rx-swap-enable
+	0,		//tx_channel_swap_enable *** adi,tx-channel-swap-enable
+	0,		//rx_channel_swap_enable *** adi,rx-channel-swap-enable
+	1,		//rx_frame_pulse_mode_enable *** adi,rx-frame-pulse-mode-enable
+	0,		//two_t_two_r_timing_enable *** adi,2t2r-timing-enable
+	0,		//invert_data_bus_enable *** adi,invert-data-bus-enable
+	0,		//invert_data_clk_enable *** adi,invert-data-clk-enable
+	0,		//fdd_alt_word_order_enable *** adi,fdd-alt-word-order-enable
+	0,		//invert_rx_frame_enable *** adi,invert-rx-frame-enable
+	0,		//fdd_rx_rate_2tx_enable *** adi,fdd-rx-rate-2tx-enable
+	0,		//swap_ports_enable *** adi,swap-ports-enable
+	0,		//single_data_rate_enable *** adi,single-data-rate-enable
+	1,		//lvds_mode_enable *** adi,lvds-mode-enable
+	0,		//half_duplex_mode_enable *** adi,half-duplex-mode-enable
+	0,		//single_port_mode_enable *** adi,single-port-mode-enable
+	0,		//full_port_enable *** adi,full-port-enable
+	0,		//full_duplex_swap_bits_enable *** adi,full-duplex-swap-bits-enable
+	0,		//delay_rx_data *** adi,delay-rx-data
+	0,		//rx_data_clock_delay *** adi,rx-data-clock-delay
+	4,		//rx_data_delay *** adi,rx-data-delay
+	7,		//tx_fb_clock_delay *** adi,tx-fb-clock-delay
+	0,		//tx_data_delay *** adi,tx-data-delay
+	150,	//lvds_bias_mV *** adi,lvds-bias-mV
+	1,		//lvds_rx_onchip_termination_enable *** adi,lvds-rx-onchip-termination-enable
+	0,		//rx1rx2_phase_inversion_en *** adi,rx1-rx2-phase-inversion-enable
+	0xFF,	//lvds_invert1_control *** adi,lvds-invert1-control
+	0x0F,	//lvds_invert2_control *** adi,lvds-invert2-control
+	/* GPO Control */
+	0,		//gpo_manual_mode_enable *** adi,gpo-manual-mode-enable
+	0,		//gpo_manual_mode_enable_mask *** adi,gpo-manual-mode-enable-mask
+	0,		//gpo0_inactive_state_high_enable *** adi,gpo0-inactive-state-high-enable
+	0,		//gpo1_inactive_state_high_enable *** adi,gpo1-inactive-state-high-enable
+	0,		//gpo2_inactive_state_high_enable *** adi,gpo2-inactive-state-high-enable
+	0,		//gpo3_inactive_state_high_enable *** adi,gpo3-inactive-state-high-enable
+	0,		//gpo0_slave_rx_enable *** adi,gpo0-slave-rx-enable
+	0,		//gpo0_slave_tx_enable *** adi,gpo0-slave-tx-enable
+	0,		//gpo1_slave_rx_enable *** adi,gpo1-slave-rx-enable
+	0,		//gpo1_slave_tx_enable *** adi,gpo1-slave-tx-enable
+	0,		//gpo2_slave_rx_enable *** adi,gpo2-slave-rx-enable
+	0,		//gpo2_slave_tx_enable *** adi,gpo2-slave-tx-enable
+	0,		//gpo3_slave_rx_enable *** adi,gpo3-slave-rx-enable
+	0,		//gpo3_slave_tx_enable *** adi,gpo3-slave-tx-enable
+	0,		//gpo0_rx_delay_us *** adi,gpo0-rx-delay-us
+	0,		//gpo0_tx_delay_us *** adi,gpo0-tx-delay-us
+	0,		//gpo1_rx_delay_us *** adi,gpo1-rx-delay-us
+	0,		//gpo1_tx_delay_us *** adi,gpo1-tx-delay-us
+	0,		//gpo2_rx_delay_us *** adi,gpo2-rx-delay-us
+	0,		//gpo2_tx_delay_us *** adi,gpo2-tx-delay-us
+	0,		//gpo3_rx_delay_us *** adi,gpo3-rx-delay-us
+	0,		//gpo3_tx_delay_us *** adi,gpo3-tx-delay-us
+	/* Tx Monitor Control */
+	37000,	//low_high_gain_threshold_mdB *** adi,txmon-low-high-thresh
+	0,		//low_gain_dB *** adi,txmon-low-gain
+	24,		//high_gain_dB *** adi,txmon-high-gain
+	0,		//tx_mon_track_en *** adi,txmon-dc-tracking-enable
+	0,		//one_shot_mode_en *** adi,txmon-one-shot-mode-enable
+	511,	//tx_mon_delay *** adi,txmon-delay
+	8192,	//tx_mon_duration *** adi,txmon-duration
+	2,		//tx1_mon_front_end_gain *** adi,txmon-1-front-end-gain
+	2,		//tx2_mon_front_end_gain *** adi,txmon-2-front-end-gain
+	48,		//tx1_mon_lo_cm *** adi,txmon-1-lo-cm
+	48,		//tx2_mon_lo_cm *** adi,txmon-2-lo-cm
+	/* GPIO definitions */
+	/* Reset_b */
+	{
+		.number = AD9361_1_RESET_B,
+		.platform_ops = &xil_gpio_ops,
+		.extra = &xil_gpio_param
+	},		//gpio_resetb *** reset-gpios
+	/* MCS Sync */
+	{
+		.number = -1,
+		.platform_ops = &xil_gpio_ops,
+		.extra = &xil_gpio_param
+	},		//gpio_sync *** sync-gpios
+	/* Cal-SW1 */
+	{
+		.number = -1,
+		.platform_ops = &xil_gpio_ops,
+		.extra = &xil_gpio_param
+	},		//gpio_cal_sw1 *** cal-sw1-gpios
+	/* Cal-SW2 */
+	{
+		.number = -1,
+		.platform_ops = &xil_gpio_ops,
+		.extra = &xil_gpio_param
+	},		//gpio_cal_sw2 *** cal-sw2-gpios
+
+	{
+		.device_id = AD9361_SPI_DEVICE_ID,
+		.mode = SPI_MODE_1,
+		.chip_select = AD9361_1_SPI_CS,
+		.platform_ops = &spi_eng_platform_ops,
+		.extra = &spi_engine_param
+	},
+
+	/* External LO clocks */
+	NULL,	//(*ad9361_rfpll_ext_recalc_rate)()
+	NULL,	//(*ad9361_rfpll_ext_round_rate)()
+	NULL,	//(*ad9361_rfpll_ext_set_rate)()
+};
+
+AD9361_RXFIRConfig rx_fir_config = {	// BPF PASSBAND 3/20 fs to 1/4 fs
+	3, // rx
+	0, // rx_gain
+	1, // rx_dec
+	{
+		-4, -6, -37, 35, 186, 86, -284, -315,
+		107, 219, -4, 271, 558, -307, -1182, -356,
+		658, 157, 207, 1648, 790, -2525, -2553, 748,
+		865, -476, 3737, 6560, -3583, -14731, -5278, 14819,
+		14819, -5278, -14731, -3583, 6560, 3737, -476, 865,
+		748, -2553, -2525, 790, 1648, 207, 157, 658,
+		-356, -1182, -307, 558, 271, -4, 219, 107,
+		-315, -284, 86, 186, 35, -37, -6, -4,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0
+	}, // rx_coef[128]
+	64, // rx_coef_size
+	{0, 0, 0, 0, 0, 0}, //rx_path_clks[6]
+	0 // rx_bandwidth
+};
+
+AD9361_TXFIRConfig tx_fir_config = {	// BPF PASSBAND 3/20 fs to 1/4 fs
+	3, // tx
+	-6, // tx_gain
+	1, // tx_int
+	{
+		-4, -6, -37, 35, 186, 86, -284, -315,
+		107, 219, -4, 271, 558, -307, -1182, -356,
+		658, 157, 207, 1648, 790, -2525, -2553, 748,
+		865, -476, 3737, 6560, -3583, -14731, -5278, 14819,
+		14819, -5278, -14731, -3583, 6560, 3737, -476, 865,
+		748, -2553, -2525, 790, 1648, 207, 157, 658,
+		-356, -1182, -307, 558, 271, -4, 219, 107,
+		-315, -284, 86, 186, 35, -37, -6, -4,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0
+	}, // tx_coef[128]
+	64, // tx_coef_size
+	{0, 0, 0, 0, 0, 0}, // tx_path_clks[6]
+	0 // tx_bandwidth
+};
+

cx9261a_demo_cmos_20240513/vitis_classic_autobuild/source_cx9261a_api_lib_c/dev_profile/ad9528_profile.c

@@ -0,0 +1,134 @@
+#include "dev_profile.h"
+#include "../config/app_config.h"
+#include "../drivers/platform/xilinx_gpio.h"
+#include "../drivers/axi_core/spi_engine/spi_engine.h"
+#include "../drivers/frequency/ad9528/ad9528.h"
+
+static struct spi_engine_init_param spi_engine_param = {
+	.ref_clk_hz = AD9528_SPI_ENGINE_REF_CLK,
+	.type = SPI_ENGINE,
+	.spi_engine_baseaddr = AD9528_SPI_ENGINE_BASEADDR,
+	.cs_delay = AD9528_SPI_ENGINE_CS_DELAY,
+	.data_width = AD9528_SPI_ENGINE_DATA_WIDTH
+};
+
+static struct xil_gpio_init_param xil_gpio_param = {
+	.type = GPIO_PS,
+	.device_id = AD9528_GPIO_DEVICE_ID
+};
+
+static struct spi_init_param ad9528_spi_init = {
+	.device_id = AD9528_SPI_DEVICE_ID,
+    .max_speed_hz = AD9528_SPI_ENGINE_MAX_SPEED,
+	.mode = SPI_MODE_0,
+	.chip_select = AD9528_SPI_CS,
+	.platform_ops = &spi_eng_platform_ops,
+	.extra = &spi_engine_param
+};
+
+static struct gpio_init_param ad9528_gpio_resetb_init = {
+	.number = AD9528_RESETB,
+	.platform_ops = &xil_gpio_ops,
+	.extra = &xil_gpio_param
+};
+
+static struct gpio_init_param ad9528_gpio_sysref_req_init = {
+	.number = AD9528_SYSREF_REQ,
+	.platform_ops = &xil_gpio_ops,
+	.extra = &xil_gpio_param
+};
+
+static ad9528pll1Settings_t clockPll1Settings = {
+    .refA_Frequency_Hz  = 50000000,
+    .refA_Divider       = 1,
+    .refA_bufferCtrl    = SINGLE_ENDED,
+    .refB_Frequency_Hz  = 0,
+    .refB_Divider       = 1,
+    .refB_bufferCtrl    = DISABLED,
+    .vcxo_Frequency_Hz  = 50000000,
+    .vcxoBufferCtrl     = SINGLE_ENDED,
+    .nDivider           = 1
+};
+
+static ad9528pll2Settings_t clockPll2Settings = {
+    .rfDivider = 4,
+    .n2Divider = 20,
+    .totalNdiv = 80
+};
+
+/*******************************************************************
+ * Output Distribution Settings
+ * 9369CE02A uses the following clock outputs
+ * OUT 1: FPGA REFCLK
+ * OUT 3: FPGA SYSREF
+ * OUT 12: DUT SYSREF
+ * OUT 13: DUT REFCLK
+ *******************************************************************
+ */
+static ad9528outputSettings_t clockOutputSettings = {
+    .outPowerDown = 0xE001,
+    .outSource = {
+            AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV,
+			AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV,
+			AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV, AD9528_CHANNEL_DIV
+    },
+    .outBufferCtrl = {
+    		0,0,0,0,0,
+    		0,0,0,0,0,
+			0,0,0,0
+    },
+    .outAnalogDelay = {
+    		0,0,0,0,0,
+    		0,0,0,0,0,
+			0,0,0,0
+    },
+    .outDigitalDelay = {
+    		0,0,0,0,0,
+    		0,0,0,0,0,
+			0,0,0,0
+    },
+    .outChannelDiv = {
+    		5,25,25,5,5,
+			5,5,5,5,5,
+			5,5,10,5
+    },
+    .outFrequency_Hz    = {
+            200e6, 40e6, 40e6, 200e6, 200e6,
+			200e6, 200e6, 200e6, 200e6, 200e6,
+			200e6, 200e6, 100e6, 200e6
+    }
+};
+
+static ad9528sysrefSettings_t clockSysrefSettings = {
+    .sysrefRequestMethod    = PIN,
+    .sysrefSource           = INTERNAL,
+    .sysrefPinEdgeMode      = LEVEL_ACTIVE_HIGH,
+    .sysrefPinBufferMode    = DISABLED,
+    .sysrefPatternMode      = CONTINUOUS,
+    .sysrefNshotMode        = FOUR_PULSES,
+    .sysrefDivide           = 256
+};
+
+static ad9528spiSettings_t clockSpiSettings = {
+    .chipSelectIndex        = AD9528_SPI_CS, //chip select Index, not used
+    .writeBitPolarity       = 0, //Write bit polarity
+    .longInstructionWord    = 1, //16bit instruction word
+    .MSBFirst               = 1, //MSB first
+    .CPHA                   = 0, //Clock phase
+    .CPOL                   = 0, //Clock polarity
+    .enSpiStreaming         = 0, //uint8_t enSpiStreaming;
+    .autoIncAddrUp          = 1, //uint8_t autoIncAddrUp;
+    .fourWireMode           = 1  //uint8_t fourWireMode;
+};
+
+ad9528Init_t ad9528_default_init_param = {
+	/* SPI */
+	.spi_init = &ad9528_spi_init,
+	.gpio_init_resetb = &ad9528_gpio_resetb_init,
+	.gpio_init_sysref_req = &ad9528_gpio_sysref_req_init,
+    .spiSettings = &clockSpiSettings,
+    .pll1Settings = &clockPll1Settings,
+    .pll2Settings = &clockPll2Settings,
+    .outputSettings = &clockOutputSettings,
+    .sysrefSettings = &clockSysrefSettings
+};