josh 197ee19bef add cx9261a_demo vitis classic project, some projects need further revision due to bsp version upgrade

2024-11-02 00:57:31 +08:00

board_file

add board files

2024-10-31 10:03:59 +08:00

cx9261a_demo_cmos_20240513

add cx9261a_demo vitis classic project, some projects need further revision due to bsp version upgrade

2024-11-02 00:57:31 +08:00

scripts @ eec2f030d8

update zc706_cx9261a_demo vitis project, add api to help debug

2024-10-31 12:03:03 +08:00

zc706_cx9261a_demo

add cx9261_demo vivado project

2024-10-31 19:28:02 +08:00

.gitattributes

add board files

2024-10-31 10:03:59 +08:00

.gitmodules

initial commit for zc706_cx9261a_demo

2024-10-31 00:22:43 +08:00

S

Description

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3.5 GiB

Languages

VHDL 87.2%

Verilog 4%

SystemVerilog 3.3%

Coq 2.3%

C 1.4%

Other 1.7%