add multirate qpsk transmitter, modify frequency hopping procedure

add cx9261a_demo vitis classic project, some projects need further revision due to bsp version upgrade
add cx9261_demo vivado project
2024-11-02 01:00:01 +08:00 · 2024-11-02 00:57:31 +08:00 · 2024-10-31 19:28:02 +08:00 · 2024-10-31 18:45:37 +08:00
1441 changed files with 6569877 additions and 20735 deletions
@@ -0,0 +1,20 @@
+# System generated files
+# -- macOS
+.DS_Store
+.AppleDouble
+.LSOverride
+._*
+
+# -- Windows
+Thumbs.db
+ehthumbs.db
+Desktop.ini
+
+# -- Linux
+*~
+
+# IDEs and editors' files
+*.idea
+*.vscode
+*.sublime-workspace
+*.sublime-project
@@ -0,0 +1,130 @@
+################################################################################
+############################### Project Specific ###############################
+################################################################################
+# everything
+*
+
+# git related
+!/.gitignore
+!/.gitattributes
+
+# project documents
+!/*.md
+!/*.txt
+
+################################################################################
+############################### Vivado Specific ################################
+################################################################################
+
+# xpr: needed for recreating design
+!/*.xpr
+
+# source: include everything
+!/*.srcs/
+!/*.srcs/**/*
+
+# runs: exclude everything but design run results
+!/*.runs/
+!/*.runs/impl_*/
+!/*.runs/impl_*/*.bit
+!/*.runs/impl_*/*.ltx
+
+# xsa (Xilinx support archive): include for ps
+!/*.xsa
+
+################################################################################
+################################ Vitis Specific ################################
+################################################################################
+
+# include sdk directory and everything in it
+!/vitis*/
+!/vitis*/**
+/vitis*/**.log
+/vitis*/.analytics
+
+# exclude some obscure hidden SDK folders
+/vitis*/.metadata/
+/vitis*/.sdk/
+/vitis*/RemoteSystemsTempFiles/
+/vitis*/webtalk/
+
+# hw_platform: exclude the entire hw_platform folder, as everything can be
+# generated from the .hdf file. Make sure to include the bitstream in the .hdf
+# file when exporting from Vivado!
+/vitis*/*_hw_platform_*/
+
+# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
+# Makefile, ps lib files are regenerated automatically
+/vitis*/*_bsp/*
+!/vitis*/*_bsp/*.cproject
+!/vitis*/*_bsp/*.project
+!/vitis*/*_bsp/*.sdkproject
+!/vitis*/*_bsp/system.mss
+!/vitis*/*_bsp/Makefile
+
+# Application: ignored file patterns, exclude Debug & Release folders
+/vitis*/**/*.o
+/vitis*/**/*.d
+/vitis*/**/*.a
+/vitis*/*/Debug/
+/vitis*/*/Release/
+
+################################################################################
+############################ Vivado & Vitis Common #############################
+################################################################################
+
+# file patterns that should always be ignored (journal files, log files, dump
+# files that are created upon Vivado/SDK errors)
+*.jou
+*.log
+*.backup.jou
+*.backup.log
+*.upgrade_log
+*.dmp
+*.debug
+vivado_pid*
+
+# vivado workspace files
+xsim.dir/
+xvlog.pb
+
+# Xilinx tools generated files
+.metadata/
+.settings/
+.wsdata/
+.Xil/
+logs/
+Packages/
+*.log*
+
+# System generated files
+# -- macOS
+.DS_Store
+.AppleDouble
+.LSOverride
+._*
+
+# -- Windows
+Thumbs.db
+ehthumbs.db
+Desktop.ini
+
+# -- Linux
+*~
+
+# IDEs and editors' files
+*.idea
+*.vscode
+*.sublime-workspace
+*.sublime-project
+
+################################################################################
+############################### Project Specific ###############################
+################################################################################
+
+!/bootimage/
+!/bootimage/**/*
+!/ip_repo/
+!/ip_repo/**/*
+!/rom_data/
+!/rom_data/**/*
@@ -0,0 +1,7 @@
+//arch = zynq; split = false; format = BIN
+the_ROM_image:
+{
+	[bootloader]C:\Users\cxlab\Desktop\fpga_project\01_CX7045_demo\cmos\CX9261A_FPGA_DEMO240318\project_fix_dac.sdk\FSBL\Debug\FSBL.elf
+	C:\Users\cxlab\Desktop\fpga_project\01_CX7045_demo\cmos\CX9261A_FPGA_DEMO240318\project_fix_dac.runs\impl_2\CX9261A_ZC706.bit
+	C:\Users\cxlab\Desktop\fpga_project\01_CX7045_demo\cmos\CX9261A_FPGA_DEMO240318\project_fix_dac.sdk\CX9261A_DEMO\Debug\CX9261A_DEMO.elf
+}
@@ -0,0 +1,7 @@
+//arch = zynq; split = false; format = BIN
+the_ROM_image:
+{
+	[bootloader]C:\Users\cxlab\Desktop\fpga_project\01_CX7045_demo\cmos\CX9261A_FPGA_DEMO240318\project_fix_dac.sdk\FSBL\Debug\FSBL.elf
+	C:\Users\cxlab\Desktop\fpga_project\01_CX7045_demo\cmos\CX9261A_FPGA_DEMO240318\project_fix_dac.runs\impl_1\CX9261A_ZC706.bit
+	C:\Users\cxlab\Desktop\fpga_project\01_CX7045_demo\cmos\CX9261A_FPGA_DEMO240318\project_fix_dac.sdk\CX9261A_DEMO\Debug\CX9261A_DEMO.elf
+}
@@ -0,0 +1,86 @@
+
+proc init { cellpath otherInfo } {                                                                   
+                                                                                                             
+	set cell_handle [get_bd_cells $cellpath]                                                                 
+	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
+	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+	set full_sbusif_list [list  ]
+			                                                                                                 
+	foreach busif $all_busif {                                                                               
+		if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {                            
+			set busif_param_list [list]                                                                      
+			set busif_name [get_property NAME $busif]					                                     
+			if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {					         
+			    continue                                                                                     
+			}                                                                                                
+			foreach tparam $axi_standard_param_list {                                                        
+				lappend busif_param_list "C_${busif_name}_${tparam}"                                       
+			}                                                                                                
+			bd::mark_propagate_only $cell_handle $busif_param_list			                                 
+		}		                                                                                             
+	}                                                                                                        
+}
+
+
+proc pre_propagate {cellpath otherInfo } {                                                           
+                                                                                                             
+	set cell_handle [get_bd_cells $cellpath]                                                                 
+	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
+	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+	                                                                                                         
+	foreach busif $all_busif {	                                                                             
+		if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {                  
+			continue                                                                                         
+		}                                                                                                    
+		if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {                           
+			continue                                                                                         
+		}			                                                                                         
+		                                                                                                     
+		set busif_name [get_property NAME $busif]			                                                 
+		foreach tparam $axi_standard_param_list {		                                                     
+			set busif_param_name "C_${busif_name}_${tparam}"			                                     
+			                                                                                                 
+			set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]                                  
+			set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]                           
+			                                                                                                 
+			if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {                          
+				if { $val_on_cell != "" } {                                                                  
+					set_property CONFIG.${tparam} $val_on_cell $busif                                        
+				}                                                                                            
+			}			                                                                                     
+		}		                                                                                             
+	}                                                                                                        
+}
+
+
+proc propagate {cellpath otherInfo } {                                                               
+                                                                                                             
+	set cell_handle [get_bd_cells $cellpath]                                                                 
+	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
+	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+	                                                                                                         
+	foreach busif $all_busif {                                                                               
+		if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {                  
+			continue                                                                                         
+		}                                                                                                    
+		if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {                            
+			continue                                                                                         
+		}			                                                                                         
+	                                                                                                         
+		set busif_name [get_property NAME $busif]		                                                     
+		foreach tparam $axi_standard_param_list {			                                                 
+			set busif_param_name "C_${busif_name}_${tparam}"			                                     
+                                                                                                             
+			set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]                                  
+			set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]                           
+			                                                                                                 
+			if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {                          
+				#override property of bd_interface_net to bd_cell -- only for slaves.  May check for supported values..
+				if { $val_on_cell_intf_pin != "" } {                                                         
+					set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle               
+				}                                                                                            
+			}                                                                                                
+		}		                                                                                             
+	}                                                                                                        
+}
+
@@ -0,0 +1,10 @@
+
+
+OPTION psf_version = 2.1;
+
+BEGIN DRIVER Axis_adc_data_packer
+	OPTION supported_peripherals = (Axis_adc_data_packer);
+	OPTION copyfiles = all;
+	OPTION VERSION = 1.0;
+	OPTION NAME = Axis_adc_data_packer;
+END DRIVER
@@ -0,0 +1,5 @@
+
+
+proc generate {drv_handle} {
+	xdefine_include_file $drv_handle "xparameters.h" "Axis_adc_data_packer" "NUM_INSTANCES" "DEVICE_ID"  "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
+}
@@ -0,0 +1,6 @@
+
+
+/***************************** Include Files *******************************/
+#include "Axis_adc_data_packer.h"
+
+/************************** Function Definitions ***************************/
@@ -0,0 +1,79 @@
+
+#ifndef AXIS_ADC_DATA_PACKER_H
+#define AXIS_ADC_DATA_PACKER_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG0_OFFSET 0
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG1_OFFSET 4
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG2_OFFSET 8
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG3_OFFSET 12
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a AXIS_ADC_DATA_PACKER register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param   BaseAddress is the base address of the AXIS_ADC_DATA_PACKERdevice.
+ * @param   RegOffset is the register offset from the base to write to.
+ * @param   Data is the data written to the register.
+ *
+ * @return  None.
+ *
+ * @note
+ * C-style signature:
+ * 	void AXIS_ADC_DATA_PACKER_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define AXIS_ADC_DATA_PACKER_mWriteReg(BaseAddress, RegOffset, Data) \
+  	Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a AXIS_ADC_DATA_PACKER register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param   BaseAddress is the base address of the AXIS_ADC_DATA_PACKER device.
+ * @param   RegOffset is the register offset from the base to write to.
+ *
+ * @return  Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * 	u32 AXIS_ADC_DATA_PACKER_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define AXIS_ADC_DATA_PACKER_mReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the AXIS_ADC_DATA_PACKER instance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus AXIS_ADC_DATA_PACKER_Reg_SelfTest(void * baseaddr_p);
+
+#endif // AXIS_ADC_DATA_PACKER_H
@@ -0,0 +1,60 @@
+
+/***************************** Include Files *******************************/
+#include "Axis_adc_data_packer.h"
+#include "xparameters.h"
+#include "stdio.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+#define READ_WRITE_MUL_FACTOR 0x10
+
+/************************** Function Definitions ***************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the AXIS_ADC_DATA_PACKERinstance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus AXIS_ADC_DATA_PACKER_Reg_SelfTest(void * baseaddr_p)
+{
+	u32 baseaddr;
+	int write_loop_index;
+	int read_loop_index;
+	int Index;
+
+	baseaddr = (u32) baseaddr_p;
+
+	xil_printf("******************************\n\r");
+	xil_printf("* User Peripheral Self Test\n\r");
+	xil_printf("******************************\n\n\r");
+
+	/*
+	 * Write to user logic slave module register(s) and read back
+	 */
+	xil_printf("User logic slave module test...\n\r");
+
+	for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
+	  AXIS_ADC_DATA_PACKER_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
+	for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
+	  if ( AXIS_ADC_DATA_PACKER_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
+	    xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
+	    return XST_FAILURE;
+	  }
+
+	xil_printf("   - slave register write/read passed\n\n\r");
+
+	return XST_SUCCESS;
+}
@@ -0,0 +1,26 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+	echo "Compiling Axis_adc_data_packer..."
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+	make clean
+
+include:
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}
@@ -0,0 +1,197 @@
+
+`timescale 1ns / 1ps
+`include "Axis_adc_data_packer_v1_0_tb_include.svh"
+
+import axi_vip_pkg::*;
+import Axis_adc_data_packer_v1_0_bfm_1_master_0_0_pkg::*;
+
+module Axis_adc_data_packer_v1_0_tb();
+
+
+xil_axi_uint                            error_cnt = 0;
+xil_axi_uint                            comparison_cnt = 0;
+axi_transaction                         wr_transaction;   
+axi_transaction                         rd_transaction;   
+axi_monitor_transaction                 mst_monitor_transaction;  
+axi_monitor_transaction                 master_moniter_transaction_queue[$];  
+xil_axi_uint                            master_moniter_transaction_queue_size =0;  
+axi_monitor_transaction                 mst_scb_transaction;  
+axi_monitor_transaction                 passthrough_monitor_transaction;  
+axi_monitor_transaction                 passthrough_master_moniter_transaction_queue[$];  
+xil_axi_uint                            passthrough_master_moniter_transaction_queue_size =0;  
+axi_monitor_transaction                 passthrough_mst_scb_transaction;  
+axi_monitor_transaction                 passthrough_slave_moniter_transaction_queue[$];  
+xil_axi_uint                            passthrough_slave_moniter_transaction_queue_size =0;  
+axi_monitor_transaction                 passthrough_slv_scb_transaction;  
+axi_monitor_transaction                 slv_monitor_transaction;  
+axi_monitor_transaction                 slave_moniter_transaction_queue[$];  
+xil_axi_uint                            slave_moniter_transaction_queue_size =0;  
+axi_monitor_transaction                 slv_scb_transaction;  
+xil_axi_uint                           mst_agent_verbosity = 0;  
+xil_axi_uint                           slv_agent_verbosity = 0;  
+xil_axi_uint                           passthrough_agent_verbosity = 0;  
+bit                                     clock;
+bit                                     reset;
+integer result_slave;  
+bit [31:0] S00_AXI_test_data[3:0]; 
+ localparam LC_AXI_BURST_LENGTH = 8; 
+ localparam LC_AXI_DATA_WIDTH = 32; 
+task automatic COMPARE_DATA; 
+  input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]expected; 
+  input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]actual; 
+  begin 
+    if (expected === 'hx || actual === 'hx) begin 
+      $display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!"); 
+ result_slave = 0;    $stop; 
+  end 
+  if (actual != expected) begin 
+    $display("TESTBENCH ERROR! Data expected is not equal to actual.",     " expected = 0x%h",expected,     " actual   = 0x%h",actual); 
+    result_slave = 0; 
+    $stop; 
+  end 
+  else  
+    begin 
+     $display("TESTBENCH Passed! Data expected is equal to actual.", 
+              " expected = 0x%h",expected,               " actual   = 0x%h",actual); 
+    end 
+  end 
+endtask 
+integer                                 i; 
+integer                                 j;  
+xil_axi_uint                            trans_cnt_before_switch = 48;  
+xil_axi_uint                            passthrough_cmd_switch_cnt = 0;  
+event                                   passthrough_mastermode_start_event;  
+event                                   passthrough_mastermode_end_event;  
+event                                   passthrough_slavemode_end_event;  
+xil_axi_uint                            mtestID;  
+xil_axi_ulong                           mtestADDR;  
+xil_axi_len_t                           mtestBurstLength;  
+xil_axi_size_t                          mtestDataSize;   
+xil_axi_burst_t                         mtestBurstType;   
+xil_axi_lock_t                          mtestLOCK;  
+xil_axi_cache_t                         mtestCacheType = 0;  
+xil_axi_prot_t                          mtestProtectionType = 3'b000;  
+xil_axi_region_t                        mtestRegion = 4'b000;  
+xil_axi_qos_t                           mtestQOS = 4'b000;  
+xil_axi_data_beat                       dbeat;  
+xil_axi_data_beat [255:0]               mtestWUSER;   
+xil_axi_data_beat                       mtestAWUSER = 'h0;  
+xil_axi_data_beat                       mtestARUSER = 0;  
+xil_axi_data_beat [255:0]               mtestRUSER;      
+xil_axi_uint                            mtestBUSER = 0;  
+xil_axi_resp_t                          mtestBresp;  
+xil_axi_resp_t[255:0]                   mtestRresp;  
+bit [63:0]                              mtestWDataL; 
+bit [63:0]                              mtestRDataL; 
+axi_transaction                         pss_wr_transaction;   
+axi_transaction                         pss_rd_transaction;   
+axi_transaction                         reactive_transaction;   
+axi_transaction                         rd_payload_transaction;  
+axi_transaction                         wr_rand;  
+axi_transaction                         rd_rand;  
+axi_transaction                         wr_reactive;  
+axi_transaction                         rd_reactive;  
+axi_transaction                         wr_reactive2;   
+axi_transaction                         rd_reactive2;  
+axi_ready_gen                           bready_gen;  
+axi_ready_gen                           rready_gen;  
+axi_ready_gen                           awready_gen;  
+axi_ready_gen                           wready_gen;  
+axi_ready_gen                           arready_gen;  
+axi_ready_gen                           bready_gen2;  
+axi_ready_gen                           rready_gen2;  
+axi_ready_gen                           awready_gen2;  
+axi_ready_gen                           wready_gen2;  
+axi_ready_gen                           arready_gen2;  
+xil_axi_payload_byte                    data_mem[xil_axi_ulong];  
+Axis_adc_data_packer_v1_0_bfm_1_master_0_0_mst_t          mst_agent_0;
+
+  `BD_WRAPPER DUT(
+      .ARESETN(reset), 
+      .ACLK(clock) 
+    ); 
+  
+initial begin
+     mst_agent_0 = new("master vip agent",DUT.`BD_INST_NAME.master_0.inst.IF);//ms  
+   mst_agent_0.vif_proxy.set_dummy_drive_type(XIL_AXI_VIF_DRIVE_NONE); 
+   mst_agent_0.set_agent_tag("Master VIP"); 
+   mst_agent_0.set_verbosity(mst_agent_verbosity); 
+   mst_agent_0.start_master(); 
+     $timeformat (-12, 1, " ps", 1);
+  end
+  initial begin
+    reset <= 1'b0;
+    #200ns;
+    reset <= 1'b1;
+    repeat (5) @(negedge clock); 
+  end
+  always #5 clock <= ~clock;
+  initial begin
+      S_AXI_TEST ( );
+
+      #1ns;
+      $finish;
+  end
+task automatic S_AXI_TEST;  
+begin   
+#1; 
+   $display("Sequential write transfers example similar to  AXI BFM WRITE_BURST method starts"); 
+   mtestID = 0; 
+   mtestADDR = 64'h00000000; 
+   mtestBurstLength = 0; 
+   mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); 
+   mtestBurstType = XIL_AXI_BURST_TYPE_INCR;  
+   mtestLOCK = XIL_AXI_ALOCK_NOLOCK;  
+   mtestCacheType = 0;  
+   mtestProtectionType = 0;  
+   mtestRegion = 0; 
+   mtestQOS = 0; 
+   result_slave = 1; 
+  mtestWDataL[31:0] = 32'h00000001; 
+  for(int i = 0; i < 4;i++) begin 
+  S00_AXI_test_data[i] <= mtestWDataL[31:0];   
+  mst_agent_0.AXI4LITE_WRITE_BURST( 
+  mtestADDR, 
+  mtestProtectionType, 
+  mtestWDataL, 
+  mtestBresp 
+  );   
+  mtestWDataL[31:0] = mtestWDataL[31:0] + 1; 
+  mtestADDR = mtestADDR + 64'h4; 
+  end 
+     $display("Sequential write transfers example similar to  AXI BFM WRITE_BURST method completes"); 
+     $display("Sequential read transfers example similar to  AXI BFM READ_BURST method starts"); 
+     mtestID = 0; 
+     mtestADDR = 64'h00000000; 
+     mtestBurstLength = 0; 
+     mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); 
+     mtestBurstType = XIL_AXI_BURST_TYPE_INCR;  
+     mtestLOCK = XIL_AXI_ALOCK_NOLOCK;  
+     mtestCacheType = 0;  
+     mtestProtectionType = 0;  
+     mtestRegion = 0; 
+     mtestQOS = 0; 
+ for(int i = 0; i < 4;i++) begin 
+   mst_agent_0.AXI4LITE_READ_BURST( 
+        mtestADDR, 
+        mtestProtectionType, 
+        mtestRDataL, 
+        mtestRresp 
+      ); 
+   mtestADDR = mtestADDR + 64'h4; 
+   COMPARE_DATA(S00_AXI_test_data[i],mtestRDataL); 
+ end 
+     $display("Sequential read transfers example similar to  AXI BFM READ_BURST method completes"); 
+     $display("Sequential read transfers example similar to  AXI VIP READ_BURST method completes"); 
+     $display("---------------------------------------------------------"); 
+     $display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!"); 
+     if ( result_slave ) begin                    
+       $display("PTGEN_TEST: PASSED!");                  
+     end    else begin                                       
+       $display("PTGEN_TEST: FAILED!");                  
+     end                                
+     $display("---------------------------------------------------------"); 
+  end 
+endtask  
+
+endmodule
@@ -0,0 +1,88 @@
+proc create_ipi_design { offsetfile design_name } {
+	create_bd_design $design_name
+	open_bd_design $design_name
+
+	# Create Clock and Reset Ports
+	set ACLK [ create_bd_port -dir I -type clk ACLK ]
+	set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
+	set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
+	set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}  ] $ARESETN
+	set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
+
+	# Create instance: Axis_adc_data_packer_0, and set properties
+	set Axis_adc_data_packer_0 [ create_bd_cell -type ip -vlnv labnet.com:user:Axis_adc_data_packer:1.0 Axis_adc_data_packer_0]
+
+	# Create instance: master_0, and set properties
+	set master_0 [ create_bd_cell -type ip -vlnv  xilinx.com:ip:axi_vip master_0]
+	set_property -dict [ list CONFIG.PROTOCOL {AXI4LITE} CONFIG.INTERFACE_MODE {MASTER} ] $master_0
+
+	# Create interface connections
+	connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI ] [get_bd_intf_pins Axis_adc_data_packer_0/S00_AXI]
+
+	# Create port connections
+	connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/ACLK] [get_bd_pins Axis_adc_data_packer_0/S00_AXI_ACLK]
+	connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/ARESETN] [get_bd_pins Axis_adc_data_packer_0/S00_AXI_ARESETN]
+set_property target_simulator XSim [current_project]
+set_property -name {xsim.simulate.runtime} -value {100ms} -objects [get_filesets sim_1]
+
+	# Auto assign address
+	assign_bd_address
+
+	# Copy all address to interface_address.vh file
+	set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
+	upvar 1 $offsetfile offset_file
+	set offset_file "${bd_path}/Axis_adc_data_packer_v1_0_tb_include.svh"
+	set fp [open $offset_file "w"]
+	puts $fp "`ifndef Axis_adc_data_packer_v1_0_tb_include_vh_"
+	puts $fp "`define Axis_adc_data_packer_v1_0_tb_include_vh_\n"
+	puts $fp "//Configuration current bd names"
+	puts $fp "`define BD_NAME ${design_name}"
+	puts $fp "`define BD_INST_NAME ${design_name}_i"
+	puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
+	puts $fp "//Configuration address parameters"
+
+	puts $fp "`endif"
+	close $fp
+}
+
+set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores labnet.com:user:Axis_adc_data_packer:1.0]]]]
+set test_bench_file ${ip_path}/example_designs/bfm_design/Axis_adc_data_packer_v1_0_tb.sv
+set interface_address_vh_file ""
+
+# Set IP Repository and Update IP Catalogue 
+set repo_paths [get_property ip_repo_paths [current_fileset]] 
+if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
+	set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
+	update_ip_catalog
+}
+
+set design_name ""
+set all_bd {}
+set all_bd_files [get_files *.bd -quiet]
+foreach file $all_bd_files {
+set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
+set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
+lappend all_bd $bd_name
+}
+
+for { set i 1 } { 1 } { incr i } {
+	set design_name "Axis_adc_data_packer_v1_0_bfm_${i}"
+	if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
+		break
+	}
+}
+
+create_ipi_design interface_address_vh_file ${design_name}
+validate_bd_design
+
+set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
+import_files -force -norecurse $wrapper_file
+
+set_property SOURCE_SET sources_1 [get_filesets sim_1]
+import_files -fileset sim_1 -norecurse -force $test_bench_file
+remove_files -quiet -fileset sim_1 Axis_adc_data_packer_v1_0_tb_include.vh
+import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
+set_property top Axis_adc_data_packer_v1_0_tb [get_filesets sim_1]
+set_property top_lib {} [get_filesets sim_1]
+set_property top_file {} [get_filesets sim_1]
+launch_simulation -simset sim_1 -mode behavioral
@@ -0,0 +1,45 @@
+# Runtime Tcl commands to interact with - Axis_adc_data_packer_v1_0
+
+# Sourcing design address info tcl
+set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
+source ${bd_path}/Axis_adc_data_packer_v1_0_include.tcl
+
+# jtag axi master interface hardware name, change as per your design.
+set jtag_axi_master hw_axi_1
+set ec 0
+
+# hw test script
+# Delete all previous axis transactions
+if { [llength [get_hw_axi_txns -quiet]] } {
+	delete_hw_axi_txn [get_hw_axi_txns -quiet]
+}
+
+
+# Test all lite slaves.
+set wdata_1 abcd1234
+
+# Test: S00_AXI
+# Create a write transaction at s00_axi_addr address
+create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1
+# Create a read transaction at s00_axi_addr address
+create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr
+# Initiate transactions
+run_hw_axi r_s00_axi_addr
+run_hw_axi w_s00_axi_addr
+run_hw_axi r_s00_axi_addr
+set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]]
+# Compare read data
+if { $rdata_tmp == $wdata_1 } {
+	puts "Data comparison test pass for - S00_AXI"
+} else {
+	puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp"
+	inc ec
+}
+
+# Check error flag
+if { $ec == 0 } {
+	 puts "PTGEN_TEST: PASSED!" 
+} else {
+	 puts "PTGEN_TEST: FAILED!" 
+}
+
@@ -0,0 +1,118 @@
+
+proc create_ipi_design { offsetfile design_name } {
+
+	create_bd_design $design_name
+	open_bd_design $design_name
+
+	# Create and configure Clock/Reset
+	create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
+	create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
+
+	#Constraints will be provided manually while pin planning.
+		create_bd_port -dir I -type rst reset_rtl
+		set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
+		connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
+		connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
+		set external_reset_port reset_rtl
+		create_bd_port -dir I -type clk clock_rtl
+		connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
+		set external_clock_port clock_rtl
+	
+	#Avoid IPI DRC, make clock port synchronous to reset
+	if { $external_clock_port ne "" && $external_reset_port ne "" } {
+		set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
+	}
+
+	# Connect other sys_reset pins
+	connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
+
+	# Create instance: Axis_adc_data_packer_0, and set properties
+	set Axis_adc_data_packer_0 [ create_bd_cell -type ip -vlnv labnet.com:user:Axis_adc_data_packer:1.0 Axis_adc_data_packer_0 ]
+
+	# Create instance: jtag_axi_0, and set properties
+	set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
+	set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
+	connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+	# Create instance: axi_peri_interconnect, and set properties
+	set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
+	connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
+	set_property -dict [ list CONFIG.NUM_SI {1}  ] $axi_peri_interconnect
+	connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
+	connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
+
+	set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect
+	connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+	# Connect all clock & reset of Axis_adc_data_packer_0 slave interfaces..
+	connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins Axis_adc_data_packer_0/S00_AXI]
+	connect_bd_net [get_bd_pins Axis_adc_data_packer_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins Axis_adc_data_packer_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+
+	# Auto assign address
+	assign_bd_address
+
+	# Copy all address to Axis_adc_data_packer_v1_0_include.tcl file
+	set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
+	upvar 1 $offsetfile offset_file
+	set offset_file "${bd_path}/Axis_adc_data_packer_v1_0_include.tcl"
+	set fp [open $offset_file "w"]
+	puts $fp "# Configuration address parameters"
+
+	set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_Axis_adc_data_packer_0_S00_AXI_* ]]
+	puts $fp "set s00_axi_addr ${offset}"
+
+	close $fp
+}
+
+# Set IP Repository and Update IP Catalogue 
+set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores labnet.com:user:Axis_adc_data_packer:1.0]]]]
+set hw_test_file ${ip_path}/example_designs/debug_hw_design/Axis_adc_data_packer_v1_0_hw_test.tcl
+
+set repo_paths [get_property ip_repo_paths [current_fileset]] 
+if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
+	set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
+	update_ip_catalog
+}
+
+set design_name ""
+set all_bd {}
+set all_bd_files [get_files *.bd -quiet]
+foreach file $all_bd_files {
+set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
+set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
+lappend all_bd $bd_name
+}
+
+for { set i 1 } { 1 } { incr i } {
+	set design_name "Axis_adc_data_packer_v1_0_hw_${i}"
+	if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
+		break
+	}
+}
+
+set intf_address_include_file ""
+create_ipi_design intf_address_include_file ${design_name}
+save_bd_design
+validate_bd_design
+
+set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
+import_files -force -norecurse $wrapper_file
+
+puts "-------------------------------------------------------------------------------------------------"
+puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
+puts "   please perform following steps to test design in targeted board."
+puts "1. Generate bitstream"
+puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
+puts "3. Download generated bitstream"
+puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
+puts "   to every interface present in the peripheral : xilinx.com:user:myip:1.0"
+puts "   : source -notrace ${hw_test_file}"
+puts "-------------------------------------------------------------------------------------------------"
+
@@ -0,0 +1,98 @@
+`timescale 1 ns / 1 ps
+
+	module Axis_adc_data_packer_v1_0 #
+	(
+		// Users to add parameters here
+
+		// User parameters ends
+		// Do not modify the parameters beyond this line
+
+
+		// Parameters of Axi Slave Bus Interface S00_AXI
+		parameter integer C_S00_AXI_DATA_WIDTH	= 32,
+		parameter integer C_S00_AXI_ADDR_WIDTH	= 4
+	)
+	(
+		// Users to add ports here
+    input wire aclk,		
+    input wire aresetn,
+    input wire  axis_tvalid,
+    input wire axis_tlast,
+    output wire axis_ready,
+    input  wire [63:0] axis_tdata,
+      
+    output wire m_axis_tvalid,
+    output wire m_axis_tlast,
+    input wire m_axis_ready,
+    output wire [63:0] m_axis_tdata,
+		// User ports ends
+		
+		// Do not modify the ports beyond this line
+
+
+		// Ports of Axi Slave Bus Interface S00_AXI
+		input wire  s00_axi_aclk,
+		input wire  s00_axi_aresetn,
+		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
+		input wire [2 : 0] s00_axi_awprot,
+		input wire  s00_axi_awvalid,
+		output wire  s00_axi_awready,
+		input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
+		input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
+		input wire  s00_axi_wvalid,
+		output wire  s00_axi_wready,
+		output wire [1 : 0] s00_axi_bresp,
+		output wire  s00_axi_bvalid,
+		input wire  s00_axi_bready,
+		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
+		input wire [2 : 0] s00_axi_arprot,
+		input wire  s00_axi_arvalid,
+		output wire  s00_axi_arready,
+		output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
+		output wire [1 : 0] s00_axi_rresp,
+		output wire  s00_axi_rvalid,
+		input wire  s00_axi_rready
+	);
+// Instantiation of Axi Bus Interface S00_AXI
+	Axis_adc_data_packer_v1_0_S00_AXI # ( 
+		.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
+		.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
+	) Axis_adc_data_packer_v1_0_S00_AXI_inst (
+		.S_AXI_ACLK(s00_axi_aclk),
+		.S_AXI_ARESETN(s00_axi_aresetn),
+		.S_AXI_AWADDR(s00_axi_awaddr),
+		.S_AXI_AWPROT(s00_axi_awprot),
+		.S_AXI_AWVALID(s00_axi_awvalid),
+		.S_AXI_AWREADY(s00_axi_awready),
+		.S_AXI_WDATA(s00_axi_wdata),
+		.S_AXI_WSTRB(s00_axi_wstrb),
+		.S_AXI_WVALID(s00_axi_wvalid),
+		.S_AXI_WREADY(s00_axi_wready),
+		.S_AXI_BRESP(s00_axi_bresp),
+		.S_AXI_BVALID(s00_axi_bvalid),
+		.S_AXI_BREADY(s00_axi_bready),
+		.S_AXI_ARADDR(s00_axi_araddr),
+		.S_AXI_ARPROT(s00_axi_arprot),
+		.S_AXI_ARVALID(s00_axi_arvalid),
+		.S_AXI_ARREADY(s00_axi_arready),
+		.S_AXI_RDATA(s00_axi_rdata),
+		.S_AXI_RRESP(s00_axi_rresp),
+		.S_AXI_RVALID(s00_axi_rvalid),
+		.S_AXI_RREADY(s00_axi_rready),
+    .axis_tvalid(axis_tvalid),
+    .axis_ready(axis_ready),
+    .axis_tdata(axis_tdata),
+    
+    .aclk(aclk),
+    .aresetn(aresetn),
+    .m_axis_tvalid(m_axis_tvalid),
+    .m_axis_tlast(m_axis_tlast),
+    .m_axis_ready(m_axis_ready),
+    .m_axis_tdata(m_axis_tdata)   
+	);
+
+	// Add user logic here
+
+	// User logic ends
+
+	endmodule
@@ -0,0 +1,469 @@
+`timescale 1 ns / 1 ps
+
+	module Axis_adc_data_packer_v1_0_S00_AXI #
+	(
+		// Users to add parameters here
+
+		// User parameters ends
+		// Do not modify the parameters beyond this line
+
+		// Width of S_AXI data bus
+		parameter integer C_S_AXI_DATA_WIDTH	= 32,
+		// Width of S_AXI address bus
+		parameter integer C_S_AXI_ADDR_WIDTH	= 4
+	)
+	(
+		// Users to add ports here
+	input wire aclk,
+    input wire aresetn,
+    input wire axis_tvalid,
+    output wire  axis_ready,
+    input wire [63:0] axis_tdata,
+      
+    output wire m_axis_tvalid,
+    output wire m_axis_tlast,
+    input wire m_axis_ready,
+    output wire [63:0] m_axis_tdata,
+
+		// User ports ends
+		// Do not modify the ports beyond this line
+
+		// Global Clock Signal
+		input wire  S_AXI_ACLK,
+		// Global Reset Signal. This Signal is Active LOW
+		input wire  S_AXI_ARESETN,
+		// Write address (issued by master, acceped by Slave)
+		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
+		// Write channel Protection type. This signal indicates the
+    		// privilege and security level of the transaction, and whether
+    		// the transaction is a data access or an instruction access.
+		input wire [2 : 0] S_AXI_AWPROT,
+		// Write address valid. This signal indicates that the master signaling
+    		// valid write address and control information.
+		input wire  S_AXI_AWVALID,
+		// Write address ready. This signal indicates that the slave is ready
+    		// to accept an address and associated control signals.
+		output wire  S_AXI_AWREADY,
+		// Write data (issued by master, acceped by Slave) 
+		input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
+		// Write strobes. This signal indicates which byte lanes hold
+    		// valid data. There is one write strobe bit for each eight
+    		// bits of the write data bus.    
+		input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
+		// Write valid. This signal indicates that valid write
+    		// data and strobes are available.
+		input wire  S_AXI_WVALID,
+		// Write ready. This signal indicates that the slave
+    		// can accept the write data.
+		output wire  S_AXI_WREADY,
+		// Write response. This signal indicates the status
+    		// of the write transaction.
+		output wire [1 : 0] S_AXI_BRESP,
+		// Write response valid. This signal indicates that the channel
+    		// is signaling a valid write response.
+		output wire  S_AXI_BVALID,
+		// Response ready. This signal indicates that the master
+    		// can accept a write response.
+		input wire  S_AXI_BREADY,
+		// Read address (issued by master, acceped by Slave)
+		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
+		// Protection type. This signal indicates the privilege
+    		// and security level of the transaction, and whether the
+    		// transaction is a data access or an instruction access.
+		input wire [2 : 0] S_AXI_ARPROT,
+		// Read address valid. This signal indicates that the channel
+    		// is signaling valid read address and control information.
+		input wire  S_AXI_ARVALID,
+		// Read address ready. This signal indicates that the slave is
+    		// ready to accept an address and associated control signals.
+		output wire  S_AXI_ARREADY,
+		// Read data (issued by slave)
+		output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
+		// Read response. This signal indicates the status of the
+    		// read transfer.
+		output wire [1 : 0] S_AXI_RRESP,
+		// Read valid. This signal indicates that the channel is
+    		// signaling the required read data.
+		output wire  S_AXI_RVALID,
+		// Read ready. This signal indicates that the master can
+    		// accept the read data and response information.
+		input wire  S_AXI_RREADY
+	);
+
+	// AXI4LITE signals
+	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
+	reg  	axi_awready;
+	reg  	axi_wready;
+	reg [1 : 0] 	axi_bresp;
+	reg  	axi_bvalid;
+	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
+	reg  	axi_arready;
+	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
+	reg [1 : 0] 	axi_rresp;
+	reg  	axi_rvalid;
+
+	// Example-specific design signals
+	// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
+	// ADDR_LSB is used for addressing 32/64 bit registers/memories
+	// ADDR_LSB = 2 for 32 bits (n downto 2)
+	// ADDR_LSB = 3 for 64 bits (n downto 3)
+	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
+	localparam integer OPT_MEM_ADDR_BITS = 1;
+	//----------------------------------------------
+	//-- Signals for user logic register space example
+	//------------------------------------------------
+	//-- Number of Slave Registers 4
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg0;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg1;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg2;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg3;
+	wire	 slv_reg_rden;
+	wire	 slv_reg_wren;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
+	integer	 byte_index;
+	reg	 aw_en;
+
+	// I/O Connections assignments
+
+	assign S_AXI_AWREADY	= axi_awready;
+	assign S_AXI_WREADY	= axi_wready;
+	assign S_AXI_BRESP	= axi_bresp;
+	assign S_AXI_BVALID	= axi_bvalid;
+	assign S_AXI_ARREADY	= axi_arready;
+	assign S_AXI_RDATA	= axi_rdata;
+	assign S_AXI_RRESP	= axi_rresp;
+	assign S_AXI_RVALID	= axi_rvalid;
+	// Implement axi_awready generation
+	// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
+	// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
+	// de-asserted when reset is low.
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_awready <= 1'b0;
+	      aw_en <= 1'b1;
+	    end 
+	  else
+	    begin    
+	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
+	        begin
+	          // slave is ready to accept write address when 
+	          // there is a valid write address and write data
+	          // on the write address and data bus. This design 
+	          // expects no outstanding transactions. 
+	          axi_awready <= 1'b1;
+	          aw_en <= 1'b0;
+	        end
+	        else if (S_AXI_BREADY && axi_bvalid)
+	            begin
+	              aw_en <= 1'b1;
+	              axi_awready <= 1'b0;
+	            end
+	      else           
+	        begin
+	          axi_awready <= 1'b0;
+	        end
+	    end 
+	end       
+
+	// Implement axi_awaddr latching
+	// This process is used to latch the address when both 
+	// S_AXI_AWVALID and S_AXI_WVALID are valid. 
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_awaddr <= 0;
+	    end 
+	  else
+	    begin    
+	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
+	        begin
+	          // Write Address latching 
+	          axi_awaddr <= S_AXI_AWADDR;
+	        end
+	    end 
+	end       
+
+	// Implement axi_wready generation
+	// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
+	// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is 
+	// de-asserted when reset is low. 
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_wready <= 1'b0;
+	    end 
+	  else
+	    begin    
+	      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
+	        begin
+	          // slave is ready to accept write data when 
+	          // there is a valid write address and write data
+	          // on the write address and data bus. This design 
+	          // expects no outstanding transactions. 
+	          axi_wready <= 1'b1;
+	        end
+	      else
+	        begin
+	          axi_wready <= 1'b0;
+	        end
+	    end 
+	end       
+
+	// Implement memory mapped register select and write logic generation
+	// The write data is accepted and written to memory mapped registers when
+	// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
+	// select byte enables of slave registers while writing.
+	// These registers are cleared when reset (active low) is applied.
+	// Slave register write enable is asserted when valid address and data are available
+	// and the slave is ready to accept the write address and write data.
+	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      slv_reg0 <= 0;
+	      slv_reg1 <= 0;
+	      slv_reg2 <= 0;
+	      slv_reg3 <= 0;
+	    end 
+	  else begin
+	    if (slv_reg_wren)
+	      begin
+	        case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
+	          2'h0:
+	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+	                // Respective byte enables are asserted as per write strobes 
+	                // Slave register 0
+	                slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+	              end  
+	          2'h1:
+	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+	                // Respective byte enables are asserted as per write strobes 
+	                // Slave register 1
+	                slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+	              end  
+	          2'h2:
+	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+	                // Respective byte enables are asserted as per write strobes 
+	                // Slave register 2
+	                slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+	              end  
+	          2'h3:
+	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+	                // Respective byte enables are asserted as per write strobes 
+	                // Slave register 3
+	                slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+	              end  
+	          default : begin
+	                      slv_reg0 <= slv_reg0;
+	                      slv_reg1 <= slv_reg1;
+	                      slv_reg2 <= slv_reg2;
+	                      slv_reg3 <= slv_reg3;
+	                    end
+	        endcase
+	      end
+	  end
+	end    
+
+	// Implement write response logic generation
+	// The write response and response valid signals are asserted by the slave 
+	// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.  
+	// This marks the acceptance of address and indicates the status of 
+	// write transaction.
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_bvalid  <= 0;
+	      axi_bresp   <= 2'b0;
+	    end 
+	  else
+	    begin    
+	      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
+	        begin
+	          // indicates a valid write response is available
+	          axi_bvalid <= 1'b1;
+	          axi_bresp  <= 2'b0; // 'OKAY' response 
+	        end                   // work error responses in future
+	      else
+	        begin
+	          if (S_AXI_BREADY && axi_bvalid) 
+	            //check if bready is asserted while bvalid is high) 
+	            //(there is a possibility that bready is always asserted high)   
+	            begin
+	              axi_bvalid <= 1'b0; 
+	            end  
+	        end
+	    end
+	end   
+
+	// Implement axi_arready generation
+	// axi_arready is asserted for one S_AXI_ACLK clock cycle when
+	// S_AXI_ARVALID is asserted. axi_awready is 
+	// de-asserted when reset (active low) is asserted. 
+	// The read address is also latched when S_AXI_ARVALID is 
+	// asserted. axi_araddr is reset to zero on reset assertion.
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_arready <= 1'b0;
+	      axi_araddr  <= 32'b0;
+	    end 
+	  else
+	    begin    
+	      if (~axi_arready && S_AXI_ARVALID)
+	        begin
+	          // indicates that the slave has acceped the valid read address
+	          axi_arready <= 1'b1;
+	          // Read address latching
+	          axi_araddr  <= S_AXI_ARADDR;
+	        end
+	      else
+	        begin
+	          axi_arready <= 1'b0;
+	        end
+	    end 
+	end       
+
+	// Implement axi_arvalid generation
+	// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both 
+	// S_AXI_ARVALID and axi_arready are asserted. The slave registers 
+	// data are available on the axi_rdata bus at this instance. The 
+	// assertion of axi_rvalid marks the validity of read data on the 
+	// bus and axi_rresp indicates the status of read transaction.axi_rvalid 
+	// is deasserted on reset (active low). axi_rresp and axi_rdata are 
+	// cleared to zero on reset (active low).  
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_rvalid <= 0;
+	      axi_rresp  <= 0;
+	    end 
+	  else
+	    begin    
+	      if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
+	        begin
+	          // Valid read data is available at the read data bus
+	          axi_rvalid <= 1'b1;
+	          axi_rresp  <= 2'b0; // 'OKAY' response
+	        end   
+	      else if (axi_rvalid && S_AXI_RREADY)
+	        begin
+	          // Read data is accepted by the master
+	          axi_rvalid <= 1'b0;
+	        end                
+	    end
+	end    
+
+	// Implement memory mapped register select and read logic generation
+	// Slave register read enable is asserted when valid address is available
+	// and the slave is ready to accept the read address.
+	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
+	always @(*)
+	begin
+	      // Address decoding for reading registers
+	      case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
+	        2'h0   : reg_data_out <= slv_reg0;
+	        2'h1   : reg_data_out <= slv_reg1;
+	        2'h2   : reg_data_out <= slv_reg2;
+	        2'h3   : reg_data_out <= slv_reg3;
+	        default : reg_data_out <= 0;
+	      endcase
+	end
+
+	// Output register or memory read data
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_rdata  <= 0;
+	    end 
+	  else
+	    begin    
+	      // When there is a valid read address (S_AXI_ARVALID) with 
+	      // acceptance of read address by the slave (axi_arready), 
+	      // output the read dada 
+	      if (slv_reg_rden)
+	        begin
+	          axi_rdata <= reg_data_out;     // register read data
+	        end   
+	    end
+	end    
+	
+	wire capture_cdc;
+	wire [25:0] length_cdc;
+	
+	   xpm_cdc_array_single #(
+      .DEST_SYNC_FF(4),   // DECIMAL; range: 2-10
+      .INIT_SYNC_FF(0),   // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
+      .SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      .SRC_INPUT_REG(1),  // DECIMAL; 0=do not register input, 1=register input
+      .WIDTH(1)           // DECIMAL; range: 1-1024
+   )
+   xpm_cdc_array_single_inst0 (
+      .dest_out(capture_cdc), // WIDTH-bit output: src_in synchronized to the destination clock domain. This
+                           // output is registered.
+
+      .dest_clk(aclk), // 1-bit input: Clock signal for the destination clock domain.
+      .src_clk(S_AXI_ACLK),   // 1-bit input: optional; required when SRC_INPUT_REG = 1
+      .src_in(slv_reg0[0])      // WIDTH-bit input: Input single-bit array to be synchronized to destination clock
+                           // domain. It is assumed that each bit of the array is unrelated to the others. This
+                           // is reflected in the constraints applied to this macro. To transfer a binary value
+                           // losslessly across the two clock domains, use the XPM_CDC_GRAY macro instead.
+
+   );
+   
+   	   xpm_cdc_array_single #(
+      .DEST_SYNC_FF(4),   // DECIMAL; range: 2-10
+      .INIT_SYNC_FF(0),   // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
+      .SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      .SRC_INPUT_REG(1),  // DECIMAL; 0=do not register input, 1=register input
+      .WIDTH(26)           // DECIMAL; range: 1-1024
+   )
+   xpm_cdc_array_single_inst1 (
+      .dest_out(length_cdc), // WIDTH-bit output: src_in synchronized to the destination clock domain. This
+                           // output is registered.
+
+      .dest_clk(aclk), // 1-bit input: Clock signal for the destination clock domain.
+      .src_clk(S_AXI_ACLK),   // 1-bit input: optional; required when SRC_INPUT_REG = 1
+      .src_in(slv_reg1[25:0])      // WIDTH-bit input: Input single-bit array to be synchronized to destination clock
+                           // domain. It is assumed that each bit of the array is unrelated to the others. This
+                           // is reflected in the constraints applied to this macro. To transfer a binary value
+                           // losslessly across the two clock domains, use the XPM_CDC_GRAY macro instead.
+
+   );
+   
+	
+	// Add user logic here
+    axis_adc_data_packer axis_adc_data_packer(
+    .aclk(aclk),
+    .aresetn(aresetn),
+    .axis_tvalid(axis_tvalid),
+    .axis_ready(axis_ready),
+    .axis_tdata(axis_tdata),
+    .capture(capture_cdc),
+    .length(length_cdc),
+    .m_axis_tvalid(m_axis_tvalid),
+    .m_axis_tlast(m_axis_tlast),
+    .m_axis_ready(m_axis_ready),
+    .m_axis_tdata(m_axis_tdata)     
+    );
+	// User logic ends
+
+	endmodule
@@ -0,0 +1,104 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2021/09/07 14:33:53
+// Design Name: 
+// Module Name: axis_adc_data_packer
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module axis_adc_data_packer(
+aclk,aresetn,axis_tvalid,axis_ready,axis_tdata,
+capture,length,
+m_axis_tvalid,m_axis_tlast,m_axis_ready,m_axis_tdata
+    );
+    input wire aclk;
+    input wire aresetn;
+    input wire axis_tvalid;
+    output reg axis_ready;
+    input wire [63:0] axis_tdata;
+    
+    input capture;
+    input [25:0] length; 
+   
+    output reg m_axis_tvalid;
+    output reg m_axis_tlast;
+    input wire m_axis_ready;
+    output reg [63:0] m_axis_tdata;
+    
+    reg [7:0]capture_d;
+    always@(posedge aclk)begin
+        if(~aresetn)begin
+            capture_d<='d0;
+        end
+        begin
+            capture_d<={capture_d[6:0],capture};
+        end
+    end
+    
+       (* keep="true" *)reg [25:0] cnt;
+       (* keep="true" *)reg [7:0] state;
+    always@(posedge aclk)begin
+        if(~aresetn)begin
+            cnt<='d0;
+            axis_ready<='d0;
+            m_axis_tvalid<='d0;
+            m_axis_tlast<='d0;
+            m_axis_tdata<='d0;      
+            state  <='d0;   
+        end
+        else begin
+            case(state)
+            0:begin
+            m_axis_tlast<=1'b0;
+            m_axis_tvalid<=1'b0;
+			m_axis_tdata<=m_axis_tdata;
+			cnt<='d0;
+                if(capture_d == 8'b01111111)begin
+                    state<=1;
+                end
+				else state<=0;
+            end
+            1:begin
+              if(axis_tvalid)begin
+                m_axis_tdata<=axis_tdata;
+                m_axis_tvalid<=axis_tvalid;
+                if(cnt >= (length-1))begin
+                    cnt<='d0;
+                    state<='d0;
+                    m_axis_tlast<=1'b1;
+                end
+                else begin
+                    cnt<=cnt+1'b1;
+                    m_axis_tlast<=1'b0;
+                end
+              end
+              else begin
+                m_axis_tdata<=m_axis_tdata;
+                m_axis_tvalid<=1'b0;
+                m_axis_tlast<=1'b0;              
+              end  
+            end
+			default:begin
+				state<='d0;
+			end
+            endcase
+        
+        
+        end
+        
+    end     
+    endmodule
@@ -0,0 +1,62 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  set C_S00_AXI_DATA_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox]
+  set_property tooltip {Width of S_AXI data bus} ${C_S00_AXI_DATA_WIDTH}
+  set C_S00_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}]
+  set_property tooltip {Width of S_AXI address bus} ${C_S00_AXI_ADDR_WIDTH}
+  ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+	# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+	# Procedure called to validate C_S00_AXI_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+	# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+	# Procedure called to validate C_S00_AXI_ADDR_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
+	# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
+	# Procedure called to validate C_S00_AXI_BASEADDR
+	return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
+	# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
+	# Procedure called to validate C_S00_AXI_HIGHADDR
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
+}
+
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+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Fri Dec 24 10:35:31 2021">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="8b6833958267472dad005008c4feb711" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+<item name="Java Command Handlers">
+<property name="AddBusInterfaceHandler" value="2" type="JavaHandler"/>
+<property name="EditUndo" value="7" type="JavaHandler"/>
+<property name="FlipToViewTaskSynthesis" value="1" type="JavaHandler"/>
+<property name="IPPackagerHandler" value="6" type="JavaHandler"/>
+<property name="ReportClockInteraction" value="1" type="JavaHandler"/>
+<property name="RunSchematic" value="7" type="JavaHandler"/>
+<property name="RunSynthesis" value="2" type="JavaHandler"/>
+<property name="SaveFileProxyHandler" value="1" type="JavaHandler"/>
+<property name="TimingConstraintsWizard" value="1" type="JavaHandler"/>
+<property name="ToolsSettings" value="1" type="JavaHandler"/>
+<property name="ToolsTemplates" value="2" type="JavaHandler"/>
+<property name="ViewTaskProjectManager" value="1" type="JavaHandler"/>
+<property name="ViewTaskSynthesis" value="1" type="JavaHandler"/>
+</item>
+<item name="Gui Handlers">
+<property name="AbstractSearchablePanel_SHOW_SEARCH" value="2" type="GuiHandlerData"/>
+<property name="BaseDialog_CANCEL" value="24" type="GuiHandlerData"/>
+<property name="BaseDialog_OK" value="26" type="GuiHandlerData"/>
+<property name="ConstraintsChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
+<property name="ConstraintsChooserPanel_FILE_TABLE" value="1" type="GuiHandlerData"/>
+<property name="CreateConstraintsFilePanel_FILE_NAME" value="1" type="GuiHandlerData"/>
+<property name="EditInterfaceDialog_TABBED_PANE" value="10" type="GuiHandlerData"/>
+<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="25" type="GuiHandlerData"/>
+<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="11" type="GuiHandlerData"/>
+<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="12" type="GuiHandlerData"/>
+<property name="InterfaceConfigurationPanel_NAME" value="3" type="GuiHandlerData"/>
+<property name="InterfaceDefinitionChooser_INTERFACE_DEFINITION_CHOOSER" value="1" type="GuiHandlerData"/>
+<property name="InterfaceDefinitionTreeTable_INTERFACES_TREE_TABLE" value="1" type="GuiHandlerData"/>
+<property name="InterfacePortMappingPanel_INTERFACES_LOGICAL_PORTS" value="4" type="GuiHandlerData"/>
+<property name="InterfacePortMappingPanel_IPS_PHYSICAL_PORTS" value="3" type="GuiHandlerData"/>
+<property name="InterfacePortMappingPanel_MAP_PORTS" value="1" type="GuiHandlerData"/>
+<property name="LanguageTemplatesDialog_TEMPLATES_TREE" value="6" type="GuiHandlerData"/>
+<property name="MessageBanner_CHANGES_DETECTED_IN_IP_THAT_REQUIRE" value="1" type="GuiHandlerData"/>
+<property name="MessageBanner_CHANGES_DETECTED_IN_VIVADO_PROJECT_THAT" value="4" type="GuiHandlerData"/>
+<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="7" type="GuiHandlerData"/>
+<property name="MsgView_CLEAR_MESSAGES_RESULTING_FROM_USER_EXECUTED" value="1" type="GuiHandlerData"/>
+<property name="NetlistTreeView_NETLIST_TREE" value="12" type="GuiHandlerData"/>
+<property name="PACommandNames_GOTO_NETLIST_DESIGN" value="1" type="GuiHandlerData"/>
+<property name="PACommandNames_PACKAGER_ADD_BUS_INTERFACE" value="2" type="GuiHandlerData"/>
+<property name="PAViews_PACKAGE" value="1" type="GuiHandlerData"/>
+<property name="PAViews_PACKAGE_IP" value="2" type="GuiHandlerData"/>
+<property name="PAViews_PROJECT_SUMMARY" value="2" type="GuiHandlerData"/>
+<property name="PAViews_SCHEMATIC" value="2" type="GuiHandlerData"/>
+<property name="PackagerStepContentPanel_MESSAGES" value="5" type="GuiHandlerData"/>
+<property name="PackagerStepsPanel_PACKAGER_STEPS_LIST" value="34" type="GuiHandlerData"/>
+<property name="PortAndInterfaceContentPanel_REFRESH" value="21" type="GuiHandlerData"/>
+<property name="PortAndInterfaceFacetTable_ASSOCIATE_CLOCKS" value="43" type="GuiHandlerData"/>
+<property name="PortAndInterfaceFacetTable_EDIT_INTERFACE" value="3" type="GuiHandlerData"/>
+<property name="PortAndInterfaceFacetTable_PORT_AND_INTERFACE_FACET_TABLE" value="218" type="GuiHandlerData"/>
+<property name="PortAndInterfaceFacetTable_REMOVE_INTERFACE" value="1" type="GuiHandlerData"/>
+<property name="ReviewContentPanel_EDIT_PACKAGING_SETTINGS" value="1" type="GuiHandlerData"/>
+<property name="ReviewContentPanel_RE_PACKAGE_IP" value="2" type="GuiHandlerData"/>
+<property name="SaveProjectUtils_DONT_SAVE" value="1" type="GuiHandlerData"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="242" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="185" type="TclMode"/>
+</item>
+</section>
+</application>
+</document>
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2018.3 (64-bit)                     -->
+<!--                                                              -->
+<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0"/>
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
@@ -0,0 +1,8 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
@@ -0,0 +1,8 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command="vivado.bat" Owner="swang" Host="HPZ240A" Pid="8716">
+    </Process>
+</ProcessHandle>
@@ -0,0 +1,67 @@
+# 
+# Synthesis run script generated by Vivado
+# 
+
+set TIME_start [clock seconds] 
+proc create_report { reportName command } {
+  set status "."
+  append status $reportName ".fail"
+  if { [file exists $status] } {
+    eval file delete [glob $status]
+  }
+  send_msg_id runtcl-4 info "Executing : $command"
+  set retval [eval catch { $command } msg]
+  if { $retval != 0 } {
+    set fp [open $status w]
+    close $fp
+    send_msg_id runtcl-5 warning "$msg"
+  }
+}
+set_param power.BramSDPPropagationFix 1
+set_param power.enableUnconnectedCarry8PinPower 1
+set_param power.enableCarry8RouteBelPower 1
+set_param power.enableLutRouteBelPower 1
+set_msg_config -id {HDL-1065} -limit 10000
+create_project -in_memory -part xczu7ev-ffvc1156-2-e
+
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_property webtalk.parent_dir C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.cache/wt [current_project]
+set_property parent.project_path C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.xpr [current_project]
+set_property XPM_LIBRARIES XPM_CDC [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language Verilog [current_project]
+set_property board_part xilinx.com:zcu106:part0:2.3 [current_project]
+set_property ip_repo_paths c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work [current_project]
+update_ip_catalog
+set_property ip_output_repo c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.cache/ip [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+read_verilog -library "" {
+  C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v
+  C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v
+}
+read_verilog -library xil_defaultlib C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v
+# Mark all dcp files as not used in implementation to prevent them from being
+# stitched into the results of this synthesis run. Any black boxes in the
+# design are intentionally left as such for best results. Dcp files will be
+# stitched into the design at a later time, either when this synthesis run is
+# opened, or when it is stitched into a dependent implementation run.
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
+  set_property used_in_implementation false $dcp
+}
+read_xdc C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.srcs/constrs_1/new/constrains.xdc
+set_property used_in_implementation false [get_files C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.srcs/constrs_1/new/constrains.xdc]
+
+set_param ips.enableIPCacheLiteLoad 1
+close [open __synthesis_is_running__ w]
+
+synth_design -top Axis_adc_data_packer_v1_0 -part xczu7ev-ffvc1156-2-e
+
+
+# disable binary constraint mode for synth run checkpoints
+set_param constraints.enableBinaryConstraints false
+write_checkpoint -force -noxdef Axis_adc_data_packer_v1_0.dcp
+create_report "synth_1_synth_report_utilization_0" "report_utilization -file Axis_adc_data_packer_v1_0_utilization_synth.rpt -pb Axis_adc_data_packer_v1_0_utilization_synth.pb"
+file delete __synthesis_is_running__
+close [open __synthesis_is_complete__ w]
@@ -0,0 +1,410 @@
+#-----------------------------------------------------------
+# Vivado v2018.3 (64-bit)
+# SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
+# IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
+# Start of session at: Thu Dec 23 15:59:40 2021
+# Process ID: 9796
+# Current directory: C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1
+# Command line: vivado.exe -log Axis_adc_data_packer_v1_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Axis_adc_data_packer_v1_0.tcl
+# Log file: C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1/Axis_adc_data_packer_v1_0.vds
+# Journal file: C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1\vivado.jou
+#-----------------------------------------------------------
+source Axis_adc_data_packer_v1_0.tcl -notrace
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work'.
+WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1'.)
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/xilinx/Vivado/2018.3/data/ip'.
+WARNING: [IP_Flow 19-4995] The host OS only allows 260 characters in a normal path. The IP cache path is more than 80 characters. If you experience issues with IP caching, please consider changing the IP cache to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. 
+Current IP cache path is c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.cache/ip 
+WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:]
+WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v:]
+Command: synth_design -top Axis_adc_data_packer_v1_0 -part xczu7ev-ffvc1156-2-e
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xczu7ev'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu7ev'
+INFO: Launching helper process for spawning children vivado processes
+INFO: Helper process launched with PID 1944 
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 465.340 ; gain = 103.711
+---------------------------------------------------------------------------------
+INFO: [Synth 8-6157] synthesizing module 'Axis_adc_data_packer_v1_0' [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v:3]
+	Parameter C_S00_AXI_DATA_WIDTH bound to: 32 - type: integer 
+	Parameter C_S00_AXI_ADDR_WIDTH bound to: 4 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'Axis_adc_data_packer_v1_0_S00_AXI' [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:3]
+	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
+	Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer 
+	Parameter ADDR_LSB bound to: 2 - type: integer 
+	Parameter OPT_MEM_ADDR_BITS bound to: 1 - type: integer 
+INFO: [Synth 8-226] default block is never used [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:240]
+INFO: [Synth 8-226] default block is never used [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:381]
+INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_array_single' [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
+	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
+	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
+	Parameter SRC_INPUT_REG bound to: 1 - type: integer 
+	Parameter VERSION bound to: 0 - type: integer 
+	Parameter WIDTH bound to: 1 - type: integer 
+INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:958]
+INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_array_single' (1#1) [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_array_single__parameterized0' [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
+	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
+	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
+	Parameter SRC_INPUT_REG bound to: 1 - type: integer 
+	Parameter VERSION bound to: 0 - type: integer 
+	Parameter WIDTH bound to: 26 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_array_single__parameterized0' (1#1) [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+INFO: [Synth 8-6157] synthesizing module 'axis_adc_data_packer' [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:23]
+INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:52]
+INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:53]
+INFO: [Synth 8-6155] done synthesizing module 'axis_adc_data_packer' (2#1) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:23]
+INFO: [Synth 8-6155] done synthesizing module 'Axis_adc_data_packer_v1_0_S00_AXI' (3#1) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:3]
+INFO: [Synth 8-6155] done synthesizing module 'Axis_adc_data_packer_v1_0' (4#1) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v:3]
+WARNING: [Synth 8-3331] design axis_adc_data_packer has unconnected port m_axis_ready
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_AWPROT[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_AWPROT[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_AWPROT[0]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_ARPROT[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_ARPROT[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_ARPROT[0]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port axis_tlast
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 515.703 ; gain = 154.074
+---------------------------------------------------------------------------------
+
+Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
+|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
+|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 515.703 ; gain = 154.074
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 515.703 ; gain = 154.074
+---------------------------------------------------------------------------------
+INFO: [Device 21-403] Loading part xczu7ev-ffvc1156-2-e
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.srcs/constrs_1/new/constrains.xdc]
+Finished Parsing XDC File [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.srcs/constrs_1/new/constrains.xdc]
+Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst0'
+Finished Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst0'
+Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst1'
+Finished Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst1'
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/Axis_adc_data_packer_v1_0_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/Axis_adc_data_packer_v1_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1584.711 ; gain = 0.000
+WARNING: [Constraints 18-5210] No constraints selected for write.
+Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1584.711 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1584.711 ; gain = 0.000
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1584.711 ; gain = 0.000
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xczu7ev-ffvc1156-2-e
+INFO: [Synth 8-6742] Reading net delay rules and data
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property DONT_TOUCH = true for Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst0. (constraint file  auto generated constraint, line ).
+Applied set_property DONT_TOUCH = true for Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst1. (constraint file  auto generated constraint, line ).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axis_adc_data_packer'
+INFO: [Synth 8-5546] ROM "cnt" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-6159] Found Keep on FSM register 'state_reg' in module 'axis_adc_data_packer', re-encoding will not be performed
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+*
+                  iSTATE |                         00000000 |                         00000000
+                 iSTATE0 |                         00000001 |                         00000001
+---------------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
+-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start RTL Component Statistics 
+---------------------------------------------------------------------------------
+Detailed RTL Component Info : 
+---Adders : 
+	   2 Input     32 Bit       Adders := 1     
+	   2 Input     26 Bit       Adders := 1     
+---Registers : 
+	               64 Bit    Registers := 1     
+	               32 Bit    Registers := 5     
+	               26 Bit    Registers := 6     
+	                8 Bit    Registers := 1     
+	                4 Bit    Registers := 2     
+	                2 Bit    Registers := 2     
+	                1 Bit    Registers := 14    
+---Muxes : 
+	   2 Input     32 Bit        Muxes := 4     
+	   4 Input     32 Bit        Muxes := 5     
+	   2 Input     26 Bit        Muxes := 4     
+	   3 Input      8 Bit        Muxes := 1     
+	   2 Input      8 Bit        Muxes := 2     
+	   2 Input      1 Bit        Muxes := 14    
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics 
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Hierarchical Component Statistics 
+---------------------------------------------------------------------------------
+Hierarchical RTL Component report 
+Module xpm_cdc_array_single 
+Detailed RTL Component Info : 
+---Registers : 
+	                1 Bit    Registers := 5     
+Module xpm_cdc_array_single__parameterized0 
+Detailed RTL Component Info : 
+---Registers : 
+	               26 Bit    Registers := 5     
+Module axis_adc_data_packer 
+Detailed RTL Component Info : 
+---Adders : 
+	   2 Input     32 Bit       Adders := 1     
+	   2 Input     26 Bit       Adders := 1     
+---Registers : 
+	               64 Bit    Registers := 1     
+	               26 Bit    Registers := 1     
+	                8 Bit    Registers := 1     
+	                1 Bit    Registers := 3     
+---Muxes : 
+	   2 Input     26 Bit        Muxes := 4     
+	   3 Input      8 Bit        Muxes := 1     
+	   2 Input      8 Bit        Muxes := 2     
+	   2 Input      1 Bit        Muxes := 9     
+Module Axis_adc_data_packer_v1_0_S00_AXI 
+Detailed RTL Component Info : 
+---Registers : 
+	               32 Bit    Registers := 5     
+	                4 Bit    Registers := 2     
+	                2 Bit    Registers := 2     
+	                1 Bit    Registers := 6     
+---Muxes : 
+	   2 Input     32 Bit        Muxes := 4     
+	   4 Input     32 Bit        Muxes := 5     
+	   2 Input      1 Bit        Muxes := 5     
+---------------------------------------------------------------------------------
+Finished RTL Hierarchical Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 1728 (col length:144)
+BRAMs: 624 (col length: RAMB18 144 RAMB36 72)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+Warning: Parallel synthesis criteria is not met 
+INFO: [Synth 8-5546] ROM "Axis_adc_data_packer_v1_0_S00_AXI_inst/axis_adc_data_packer/state" won't be mapped to RAM because it is too sparse
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port axis_tlast
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port m_axis_ready
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_awprot[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_awprot[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_awprot[0]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_arprot[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_arprot[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_arprot[0]
+INFO: [Synth 8-3886] merging instance 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_rresp_reg[0]' (FDRE) to 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_rresp_reg[1]'
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_rresp_reg[1] )
+INFO: [Synth 8-3886] merging instance 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_bresp_reg[0]' (FDRE) to 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_bresp_reg[1]'
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_bresp_reg[1] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Axis_adc_data_packer_v1_0_S00_AXI_inst/axis_adc_data_packer/axis_ready_reg )
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
+-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1995.184 ; gain = 1633.555
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1995.496 ; gain = 1633.867
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
+-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
+-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+
+Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
+|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
+|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
+-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes: 
+-+--------------+----------+
+| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
+
+Report Cell Usage: 
+------+-------+------+
+|      |Cell   |Count |
+------+-------+------+
+|1     |BUFG   |     2|
+|2     |CARRY8 |    10|
+|3     |LUT1   |    27|
+|4     |LUT2   |     3|
+|5     |LUT3   |     2|
+|6     |LUT4   |    49|
+|7     |LUT5   |    25|
+|8     |LUT6   |    38|
+|9     |FDRE   |   412|
+|10    |FDSE   |     1|
+|11    |IBUF   |   114|
+|12    |OBUF   |   108|
+------+-------+------+
+
+Report Instance Areas: 
+------+-----------------------------------------+-------------------------------------+------+
+|      |Instance                                 |Module                               |Cells |
+------+-----------------------------------------+-------------------------------------+------+
+|1     |top                                      |                                     |   791|
+|2     |  Axis_adc_data_packer_v1_0_S00_AXI_inst |Axis_adc_data_packer_v1_0_S00_AXI    |   567|
+|3     |    xpm_cdc_array_single_inst0           |xpm_cdc_array_single                 |     5|
+|4     |    xpm_cdc_array_single_inst1           |xpm_cdc_array_single__parameterized0 |   130|
+|5     |    axis_adc_data_packer                 |axis_adc_data_packer                 |   205|
+------+-----------------------------------------+-------------------------------------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 8 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 2007.641 ; gain = 577.004
+Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+INFO: [Project 1-571] Translating synthesized netlist
+INFO: [Netlist 29-17] Analyzing 126 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2043.539 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 116 instances were transformed.
+  BUFG => BUFGCE: 2 instances
+  IBUF => IBUF (IBUFCTRL, INBUF): 114 instances
+
+INFO: [Common 17-83] Releasing license: Synthesis
+41 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2043.539 ; gain = 1693.754
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2043.539 ; gain = 0.000
+WARNING: [Constraints 18-5210] No constraints selected for write.
+Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
+INFO: [Common 17-1381] The checkpoint 'C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1/Axis_adc_data_packer_v1_0.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_utilization -file Axis_adc_data_packer_v1_0_utilization_synth.rpt -pb Axis_adc_data_packer_v1_0_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Thu Dec 23 16:00:12 2021...
@@ -0,0 +1,189 @@
+Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
+| Date         : Thu Dec 23 16:00:12 2021
+| Host         : HPZ240A running 64-bit Service Pack 1  (build 7601)
+| Command      : report_utilization -file Axis_adc_data_packer_v1_0_utilization_synth.rpt -pb Axis_adc_data_packer_v1_0_utilization_synth.pb
+| Design       : Axis_adc_data_packer_v1_0
+| Device       : xczu7evffvc1156-2
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. CLB Logic
+1.1 Summary of Registers by Type
+2. BLOCKRAM
+3. ARITHMETIC
+4. I/O
+5. CLOCK
+6. ADVANCED
+7. CONFIGURATION
+8. Primitives
+9. Black Boxes
+10. Instantiated Netlists
+
+1. CLB Logic
+------------
+
+-------------------------+------+-------+-----------+-------+
+|        Site Type        | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
+| CLB LUTs*               |  130 |     0 |    230400 |  0.06 |
+|   LUT as Logic          |  130 |     0 |    230400 |  0.06 |
+|   LUT as Memory         |    0 |     0 |    101760 |  0.00 |
+| CLB Registers           |  413 |     0 |    460800 |  0.09 |
+|   Register as Flip Flop |  413 |     0 |    460800 |  0.09 |
+|   Register as Latch     |    0 |     0 |    460800 |  0.00 |
+| CARRY8                  |   10 |     0 |     28800 |  0.03 |
+| F7 Muxes                |    0 |     0 |    115200 |  0.00 |
+| F8 Muxes                |    0 |     0 |     57600 |  0.00 |
+| F9 Muxes                |    0 |     0 |     28800 |  0.00 |
+-------------------------+------+-------+-----------+-------+
+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
+-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
+| 0     |            _ |           - |            - |
+| 0     |            _ |           - |          Set |
+| 0     |            _ |           - |        Reset |
+| 0     |            _ |         Set |            - |
+| 0     |            _ |       Reset |            - |
+| 0     |          Yes |           - |            - |
+| 0     |          Yes |           - |          Set |
+| 0     |          Yes |           - |        Reset |
+| 1     |          Yes |         Set |            - |
+| 412   |          Yes |       Reset |            - |
+-------+--------------+-------------+--------------+
+
+
+2. BLOCKRAM
+-----------
+
+----------------+------+-------+-----------+-------+
+|    Site Type   | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
+| Block RAM Tile |    0 |     0 |       312 |  0.00 |
+|   RAMB36/FIFO* |    0 |     0 |       312 |  0.00 |
+|   RAMB18       |    0 |     0 |       624 |  0.00 |
+| URAM           |    0 |     0 |        96 |  0.00 |
+----------------+------+-------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2
+
+
+3. ARITHMETIC
+-------------
+
+-----------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
+| DSPs      |    0 |     0 |      1728 |  0.00 |
+-----------+------+-------+-----------+-------+
+
+
+4. I/O
+------
+
+------------+------+-------+-----------+-------+
+|  Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
+| Bonded IOB |  222 |     0 |       360 | 61.67 |
+------------+------+-------+-----------+-------+
+
+
+5. CLOCK
+--------
+
+----------------------+------+-------+-----------+-------+
+|       Site Type      | Used | Fixed | Available | Util% |
+----------------------+------+-------+-----------+-------+
+| GLOBAL CLOCK BUFFERs |    2 |     0 |       544 |  0.37 |
+|   BUFGCE             |    2 |     0 |       208 |  0.96 |
+|   BUFGCE_DIV         |    0 |     0 |        32 |  0.00 |
+|   BUFG_GT            |    0 |     0 |       144 |  0.00 |
+|   BUFG_PS            |    0 |     0 |        96 |  0.00 |
+|   BUFGCTRL*          |    0 |     0 |        64 |  0.00 |
+| PLL                  |    0 |     0 |        16 |  0.00 |
+| MMCM                 |    0 |     0 |         8 |  0.00 |
+----------------------+------+-------+-----------+-------+
+* Note: Each used BUFGCTRL counts as two global buffer resources. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.
+
+
+6. ADVANCED
+-----------
+
+-----------------+------+-------+-----------+-------+
+|    Site Type    | Used | Fixed | Available | Util% |
+-----------------+------+-------+-----------+-------+
+| GTHE4_CHANNEL   |    0 |     0 |        20 |  0.00 |
+| GTHE4_COMMON    |    0 |     0 |         5 |  0.00 |
+| OBUFDS_GTE4     |    0 |     0 |        10 |  0.00 |
+| OBUFDS_GTE4_ADV |    0 |     0 |        10 |  0.00 |
+| PCIE40E4        |    0 |     0 |         2 |  0.00 |
+| PS8             |    0 |     0 |         1 |  0.00 |
+| SYSMONE4        |    0 |     0 |         1 |  0.00 |
+| VCU             |    0 |     0 |         1 |  0.00 |
+-----------------+------+-------+-----------+-------+
+
+
+7. CONFIGURATION
+----------------
+
+-------------+------+-------+-----------+-------+
+|  Site Type  | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
+| BSCANE2     |    0 |     0 |         4 |  0.00 |
+| DNA_PORTE2  |    0 |     0 |         1 |  0.00 |
+| EFUSE_USR   |    0 |     0 |         1 |  0.00 |
+| FRAME_ECCE4 |    0 |     0 |         1 |  0.00 |
+| ICAPE3      |    0 |     0 |         2 |  0.00 |
+| MASTER_JTAG |    0 |     0 |         1 |  0.00 |
+| STARTUPE3   |    0 |     0 |         1 |  0.00 |
+-------------+------+-------+-----------+-------+
+
+
+8. Primitives
+-------------
+
+----------+------+---------------------+
+| Ref Name | Used | Functional Category |
+----------+------+---------------------+
+| FDRE     |  412 |            Register |
+| INBUF    |  114 |                 I/O |
+| IBUFCTRL |  114 |              Others |
+| OBUF     |  108 |                 I/O |
+| LUT4     |   49 |                 CLB |
+| LUT6     |   38 |                 CLB |
+| LUT1     |   27 |                 CLB |
+| LUT5     |   25 |                 CLB |
+| CARRY8   |   10 |                 CLB |
+| LUT2     |    3 |                 CLB |
+| LUT3     |    2 |                 CLB |
+| BUFGCE   |    2 |               Clock |
+| FDSE     |    1 |            Register |
+----------+------+---------------------+
+
+
+9. Black Boxes
+--------------
+
+----------+------+
+| Ref Name | Used |
+----------+------+
+
+
+10. Instantiated Netlists
+-------------------------
+
+----------+------+
+| Ref Name | Used |
+----------+------+
+
+
@@ -0,0 +1,244 @@
+//
+//  Vivado(TM)
+//  ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+//  Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. 
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+  // 1. RUN DIR setup
+  var ISEScrFP = WScript.ScriptFullName;
+  var ISEScrN = WScript.ScriptName;
+  ISERunDir = 
+    ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+  // 2. LOG file setup
+  ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  // 3. LOG echo?
+  var ISEScriptArgs = WScript.Arguments;
+  for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+    if ( ISEScriptArgs(loopi) == "-quiet" ) {
+      ISELogEcho = false;
+      break;
+    }
+  }
+
+  // 4. WSH version check
+  var ISEOptimalVersionWSH = 5.6;
+  var ISECurrentVersionWSH = WScript.Version;
+  if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+    ISEStdErr( "" );
+    ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+	       ISEOptimalVersionWSH + " or higher. Downloads" );
+    ISEStdErr( "         for upgrading your Windows Scripting Host can be found here: " );
+    ISEStdErr( "             http://msdn.microsoft.com/downloads/list/webdev.asp" );
+    ISEStdErr( "" );
+
+    ISEOldVersionWSH = true;
+  }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+  // CHECK for a STOP FILE
+  if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+    ISEStdErr( "" );
+    ISEStdErr( "*** Halting run - EA reset detected ***" );
+    ISEStdErr( "" );
+    WScript.Quit( 1 );
+  }
+
+  // WRITE STEP HEADER to LOG
+  ISEStdOut( "" );
+  ISEStdOut( "*** Running " + ISEProg );
+  ISEStdOut( "    with args " + ISEArgs );
+  ISEStdOut( "" );
+
+  // LAUNCH!
+  var ISEExitCode = ISEExec( ISEProg, ISEArgs );  
+  if ( ISEExitCode != 0 ) {
+    WScript.Quit( ISEExitCode );
+  }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+  var ISEStep = ISEProg;
+  if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+    ISEProg += ".bat";
+  }
+
+  var ISECmdLine = ISEProg + " " + ISEArgs;
+  var ISEExitCode = 1;
+
+  if ( ISEOldVersionWSH ) { // WSH 5.1
+
+    // BEGIN file creation
+    ISETouchFile( ISEStep, "begin" );
+
+    // LAUNCH!
+    ISELogFileStr.Close();
+    ISECmdLine = 
+      "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+    ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+    ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  } else {  // WSH 5.6
+
+    // LAUNCH!
+    ISEShell.CurrentDirectory = ISERunDir;
+
+    // Redirect STDERR to STDOUT
+    ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+    var ISEProcess = ISEShell.Exec( ISECmdLine );
+    
+    // BEGIN file creation
+    var ISENetwork = WScript.CreateObject( "WScript.Network" );
+    var ISEHost = ISENetwork.ComputerName;
+    var ISEUser = ISENetwork.UserName;
+    var ISEPid = ISEProcess.ProcessID;
+    var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+    ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+    ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+    ISEBeginFile.WriteLine( "    <Process Command=\"" + ISEProg + 
+			    "\" Owner=\"" + ISEUser + 
+			    "\" Host=\"" + ISEHost + 
+			    "\" Pid=\"" + ISEPid +
+			    "\">" );
+    ISEBeginFile.WriteLine( "    </Process>" );
+    ISEBeginFile.WriteLine( "</ProcessHandle>" );
+    ISEBeginFile.Close();
+    
+    var ISEOutStr = ISEProcess.StdOut;
+    var ISEErrStr = ISEProcess.StdErr;
+    
+    // WAIT for ISEStep to finish
+    while ( ISEProcess.Status == 0 ) {
+      
+      // dump stdout then stderr - feels a little arbitrary
+      while ( !ISEOutStr.AtEndOfStream ) {
+        ISEStdOut( ISEOutStr.ReadLine() );
+      }  
+      
+      WScript.Sleep( 100 );
+    }
+
+    ISEExitCode = ISEProcess.ExitCode;
+  }
+
+  ISELogFileStr.Close();
+
+  // END/ERROR file creation
+  if ( ISEExitCode != 0 ) {    
+    ISETouchFile( ISEStep, "error" );
+    
+  } else {
+    ISETouchFile( ISEStep, "end" );
+  }
+
+  return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+  ISELogFileStr.WriteLine( ISELine );
+  
+  if ( ISELogEcho ) {
+    WScript.StdOut.WriteLine( ISELine );
+  }
+}
+
+function ISEStdErr( ISELine ) {
+  
+  ISELogFileStr.WriteLine( ISELine );
+
+  if ( ISELogEcho ) {
+    WScript.StdErr.WriteLine( ISELine );
+  }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+  var ISETFile = 
+    ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+  ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+  // This function has been updated to deal with a problem seen in CR #870871.
+  // In that case the user runs a script that runs impl_1, and then turns around
+  // and runs impl_1 -to_step write_bitstream. That second run takes place in
+  // the same directory, which means we may hit some of the same files, and in
+  // particular, we will open the runme.log file. Even though this script closes
+  // the file (now), we see cases where a subsequent attempt to open the file
+  // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+  // play? In any case, we try to work around this by first waiting if the file
+  // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+  // and try to open the file 10 times with a one second delay after each attempt.
+  // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+  // If there is an unrecognized exception when trying to open the file, we output
+  // an error message and write details to an exception.log file.
+  var ISEFullPath = ISERunDir + "/" + ISEFilename;
+  if (ISEFileSys.FileExists(ISEFullPath)) {
+    // File is already there. This could be a problem. Wait in case it is still in use.
+    WScript.Sleep(5000);
+  }
+  var i;
+  for (i = 0; i < 10; ++i) {
+    try {
+      return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+    } catch (exception) {
+      var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+      if (error_code == 52) { // 52 is bad file name or number.
+        // Wait a second and try again.
+        WScript.Sleep(1000);
+        continue;
+      } else {
+        WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+        var exceptionFilePath = ISERunDir + "/exception.log";
+        if (!ISEFileSys.FileExists(exceptionFilePath)) {
+          WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+          var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+          exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+          exceptionFile.WriteLine("\tException name: " + exception.name);
+          exceptionFile.WriteLine("\tException error code: " + error_code);
+          exceptionFile.WriteLine("\tException message: " + exception.message);
+          exceptionFile.Close();
+        }
+        throw exception;
+      }
+    }
+  }
+  // If we reached this point, we failed to open the file after 10 attempts.
+  // We need to error out.
+  WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+  WScript.Quit(1);
+}
@@ -0,0 +1,63 @@
+#!/bin/sh
+
+#
+#  Vivado(TM)
+#  ISEWrap.sh: Vivado Runs Script for UNIX
+#  Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. 
+#
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo ""                                        >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo ""                                        >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo ""                      >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo "    with args $@"      >> $HD_LOG
+echo ""                      >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+if [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST     #csh
+fi
+ISE_USER=$USER
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>"                                                                     >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">"                                                   >> $ISE_BEGINFILE
+echo "    <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\">" >> $ISE_BEGINFILE
+echo "    </Process>"                                                                              >> $ISE_BEGINFILE
+echo "</ProcessHandle>"                                                                            >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+    /bin/touch .$ISE_STEP.end.rst
+else
+    /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
@@ -0,0 +1,66 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="synth_1" LaunchPart="xczu7ev-ffvc1156-2-e" LaunchTime="1640246379">
+  <File Type="PA-TCL" Name="Axis_adc_data_packer_v1_0.tcl"/>
+  <File Type="REPORTS-TCL" Name="Axis_adc_data_packer_v1_0_reports.tcl"/>
+  <File Type="RDS-RDS" Name="Axis_adc_data_packer_v1_0.vds"/>
+  <File Type="RDS-UTIL" Name="Axis_adc_data_packer_v1_0_utilization_synth.rpt"/>
+  <File Type="RDS-UTIL-PB" Name="Axis_adc_data_packer_v1_0_utilization_synth.pb"/>
+  <File Type="RDS-DCP" Name="Axis_adc_data_packer_v1_0.dcp"/>
+  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+    <Filter Type="Srcs"/>
+    <File Path="$PPRDIR/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v">
+      <FileInfo>
+        <Attr Name="Library" Val=""/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v">
+      <FileInfo>
+        <Attr Name="Library" Val=""/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/Axis_adc_data_packer_1.0/component.xml">
+      <FileInfo SFType="IPXACT"/>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopModule" Val="Axis_adc_data_packer_v1_0"/>
+      <Option Name="TopRTLFile" Val="$PPRDIR/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PSRCDIR/constrs_1/new/constrains.xdc">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/constrains.xdc"/>
+      <Option Name="ConstrsType" Val="XDC"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+    <Filter Type="Utils"/>
+    <Config>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <Strategy Version="1" Minor="2">
+    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
+    <Step Id="synth_design"/>
+  </Strategy>
+</GenRun>
@@ -0,0 +1,9 @@
+REM
+REM Vivado(TM)
+REM htr.txt: a Vivado-generated description of how-to-repeat the
+REM          the basic steps of a run.  Note that runme.bat/sh needs
+REM          to be invoked for Vivado to track run status.
+REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+REM
+
+vivado -log Axis_adc_data_packer_v1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Axis_adc_data_packer_v1_0.tcl
@@ -0,0 +1,31 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:34:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
+5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6335643931336632613664323462303262616164333333346666633564313432:506172656e742050412070726f6a656374204944:00
+eof:7738646
@@ -0,0 +1,36 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+//
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+  PathVal = "D:/xilinx/SDK/2018.3/bin;D:/xilinx/Vivado/2018.3/ids_lite/ISE/bin/nt64;D:/xilinx/Vivado/2018.3/ids_lite/ISE/lib/nt64;D:/xilinx/Vivado/2018.3/bin;";
+} else {
+  PathVal = "D:/xilinx/SDK/2018.3/bin;D:/xilinx/Vivado/2018.3/ids_lite/ISE/bin/nt64;D:/xilinx/Vivado/2018.3/ids_lite/ISE/lib/nt64;D:/xilinx/Vivado/2018.3/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+ISEStep( "vivado",
+         "-log Axis_adc_data_packer_v1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Axis_adc_data_packer_v1_0.tcl" );
+
+
+
+function EAInclude( EAInclFilename ) {
+  var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+  var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+  var EAIFContents = EAInclFile.ReadAll();
+  EAInclFile.Close();
+  return EAIFContents;
+}
@@ -0,0 +1,10 @@
+@echo off
+
+rem  Vivado (TM)
+rem  runme.bat: a Vivado-generated Script
+rem  Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
@@ -0,0 +1,417 @@
+
+*** Running vivado
+    with args -log Axis_adc_data_packer_v1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Axis_adc_data_packer_v1_0.tcl
+
+
+****** Vivado v2018.3 (64-bit)
+  **** SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
+  **** IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
+    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+
+source Axis_adc_data_packer_v1_0.tcl -notrace
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work'.
+WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1'.)
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/xilinx/Vivado/2018.3/data/ip'.
+WARNING: [IP_Flow 19-4995] The host OS only allows 260 characters in a normal path. The IP cache path is more than 80 characters. If you experience issues with IP caching, please consider changing the IP cache to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. 
+Current IP cache path is c:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.cache/ip 
+WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:]
+WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v:]
+Command: synth_design -top Axis_adc_data_packer_v1_0 -part xczu7ev-ffvc1156-2-e
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xczu7ev'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu7ev'
+INFO: Launching helper process for spawning children vivado processes
+INFO: Helper process launched with PID 1944 
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 465.340 ; gain = 103.711
+---------------------------------------------------------------------------------
+INFO: [Synth 8-6157] synthesizing module 'Axis_adc_data_packer_v1_0' [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v:3]
+	Parameter C_S00_AXI_DATA_WIDTH bound to: 32 - type: integer 
+	Parameter C_S00_AXI_ADDR_WIDTH bound to: 4 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'Axis_adc_data_packer_v1_0_S00_AXI' [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:3]
+	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
+	Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer 
+	Parameter ADDR_LSB bound to: 2 - type: integer 
+	Parameter OPT_MEM_ADDR_BITS bound to: 1 - type: integer 
+INFO: [Synth 8-226] default block is never used [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:240]
+INFO: [Synth 8-226] default block is never used [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:381]
+INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_array_single' [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
+	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
+	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
+	Parameter SRC_INPUT_REG bound to: 1 - type: integer 
+	Parameter VERSION bound to: 0 - type: integer 
+	Parameter WIDTH bound to: 1 - type: integer 
+INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:958]
+INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_array_single' (1#1) [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_array_single__parameterized0' [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+	Parameter DEST_SYNC_FF bound to: 4 - type: integer 
+	Parameter INIT_SYNC_FF bound to: 0 - type: integer 
+	Parameter SIM_ASSERT_CHK bound to: 0 - type: integer 
+	Parameter SRC_INPUT_REG bound to: 1 - type: integer 
+	Parameter VERSION bound to: 0 - type: integer 
+	Parameter WIDTH bound to: 26 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_array_single__parameterized0' (1#1) [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:903]
+INFO: [Synth 8-6157] synthesizing module 'axis_adc_data_packer' [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:23]
+INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:52]
+INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:53]
+INFO: [Synth 8-6155] done synthesizing module 'axis_adc_data_packer' (2#1) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v:23]
+INFO: [Synth 8-6155] done synthesizing module 'Axis_adc_data_packer_v1_0_S00_AXI' (3#1) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v:3]
+INFO: [Synth 8-6155] done synthesizing module 'Axis_adc_data_packer_v1_0' (4#1) [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v:3]
+WARNING: [Synth 8-3331] design axis_adc_data_packer has unconnected port m_axis_ready
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_AWPROT[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_AWPROT[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_AWPROT[0]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_ARPROT[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_ARPROT[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0_S00_AXI has unconnected port S_AXI_ARPROT[0]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port axis_tlast
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 515.703 ; gain = 154.074
+---------------------------------------------------------------------------------
+
+Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
+|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
+|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 515.703 ; gain = 154.074
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 515.703 ; gain = 154.074
+---------------------------------------------------------------------------------
+INFO: [Device 21-403] Loading part xczu7ev-ffvc1156-2-e
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.srcs/constrs_1/new/constrains.xdc]
+Finished Parsing XDC File [C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.srcs/constrs_1/new/constrains.xdc]
+Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst0'
+Finished Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst0'
+Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst1'
+Finished Sourcing Tcl File [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst1'
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/Axis_adc_data_packer_v1_0_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/Axis_adc_data_packer_v1_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1584.711 ; gain = 0.000
+WARNING: [Constraints 18-5210] No constraints selected for write.
+Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1584.711 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1584.711 ; gain = 0.000
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1584.711 ; gain = 0.000
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xczu7ev-ffvc1156-2-e
+INFO: [Synth 8-6742] Reading net delay rules and data
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property DONT_TOUCH = true for Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst0. (constraint file  auto generated constraint, line ).
+Applied set_property DONT_TOUCH = true for Axis_adc_data_packer_v1_0_S00_AXI_inst/xpm_cdc_array_single_inst1. (constraint file  auto generated constraint, line ).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+.p 4
+.s 3
+.r iSTATE
+	 Default iSTATE 
+	 iSTATE iSTATE0 
+	 iSTATE iSTATE 
+	 iSTATE0 iSTATE 
+.e
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axis_adc_data_packer'
+INFO: [Synth 8-5546] ROM "cnt" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-6159] Found Keep on FSM register 'state_reg' in module 'axis_adc_data_packer', re-encoding will not be performed
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+*
+                  iSTATE |                         00000000 |                         00000000
+                 iSTATE0 |                         00000001 |                         00000001
+---------------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
+-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start RTL Component Statistics 
+---------------------------------------------------------------------------------
+Detailed RTL Component Info : 
+---Adders : 
+	   2 Input     32 Bit       Adders := 1     
+	   2 Input     26 Bit       Adders := 1     
+---Registers : 
+	               64 Bit    Registers := 1     
+	               32 Bit    Registers := 5     
+	               26 Bit    Registers := 6     
+	                8 Bit    Registers := 1     
+	                4 Bit    Registers := 2     
+	                2 Bit    Registers := 2     
+	                1 Bit    Registers := 14    
+---Muxes : 
+	   2 Input     32 Bit        Muxes := 4     
+	   4 Input     32 Bit        Muxes := 5     
+	   2 Input     26 Bit        Muxes := 4     
+	   3 Input      8 Bit        Muxes := 1     
+	   2 Input      8 Bit        Muxes := 2     
+	   2 Input      1 Bit        Muxes := 14    
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics 
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Hierarchical Component Statistics 
+---------------------------------------------------------------------------------
+Hierarchical RTL Component report 
+Module xpm_cdc_array_single 
+Detailed RTL Component Info : 
+---Registers : 
+	                1 Bit    Registers := 5     
+Module xpm_cdc_array_single__parameterized0 
+Detailed RTL Component Info : 
+---Registers : 
+	               26 Bit    Registers := 5     
+Module axis_adc_data_packer 
+Detailed RTL Component Info : 
+---Adders : 
+	   2 Input     32 Bit       Adders := 1     
+	   2 Input     26 Bit       Adders := 1     
+---Registers : 
+	               64 Bit    Registers := 1     
+	               26 Bit    Registers := 1     
+	                8 Bit    Registers := 1     
+	                1 Bit    Registers := 3     
+---Muxes : 
+	   2 Input     26 Bit        Muxes := 4     
+	   3 Input      8 Bit        Muxes := 1     
+	   2 Input      8 Bit        Muxes := 2     
+	   2 Input      1 Bit        Muxes := 9     
+Module Axis_adc_data_packer_v1_0_S00_AXI 
+Detailed RTL Component Info : 
+---Registers : 
+	               32 Bit    Registers := 5     
+	                4 Bit    Registers := 2     
+	                2 Bit    Registers := 2     
+	                1 Bit    Registers := 6     
+---Muxes : 
+	   2 Input     32 Bit        Muxes := 4     
+	   4 Input     32 Bit        Muxes := 5     
+	   2 Input      1 Bit        Muxes := 5     
+---------------------------------------------------------------------------------
+Finished RTL Hierarchical Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 1728 (col length:144)
+BRAMs: 624 (col length: RAMB18 144 RAMB36 72)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+Warning: Parallel synthesis criteria is not met 
+INFO: [Synth 8-5546] ROM "Axis_adc_data_packer_v1_0_S00_AXI_inst/axis_adc_data_packer/state" won't be mapped to RAM because it is too sparse
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port axis_tlast
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port m_axis_ready
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_awprot[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_awprot[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_awprot[0]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_arprot[2]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_arprot[1]
+WARNING: [Synth 8-3331] design Axis_adc_data_packer_v1_0 has unconnected port s00_axi_arprot[0]
+INFO: [Synth 8-3886] merging instance 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_rresp_reg[0]' (FDRE) to 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_rresp_reg[1]'
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_rresp_reg[1] )
+INFO: [Synth 8-3886] merging instance 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_bresp_reg[0]' (FDRE) to 'Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_bresp_reg[1]'
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Axis_adc_data_packer_v1_0_S00_AXI_inst/axi_bresp_reg[1] )
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Axis_adc_data_packer_v1_0_S00_AXI_inst/axis_adc_data_packer/axis_ready_reg )
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1584.711 ; gain = 1223.082
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
+-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1995.184 ; gain = 1633.555
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1995.496 ; gain = 1633.867
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
+-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
+-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+
+Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
+|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
+|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
+-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes: 
+-+--------------+----------+
+| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
+
+Report Cell Usage: 
+------+-------+------+
+|      |Cell   |Count |
+------+-------+------+
+|1     |BUFG   |     2|
+|2     |CARRY8 |    10|
+|3     |LUT1   |    27|
+|4     |LUT2   |     3|
+|5     |LUT3   |     2|
+|6     |LUT4   |    49|
+|7     |LUT5   |    25|
+|8     |LUT6   |    38|
+|9     |FDRE   |   412|
+|10    |FDSE   |     1|
+|11    |IBUF   |   114|
+|12    |OBUF   |   108|
+------+-------+------+
+
+Report Instance Areas: 
+------+-----------------------------------------+-------------------------------------+------+
+|      |Instance                                 |Module                               |Cells |
+------+-----------------------------------------+-------------------------------------+------+
+|1     |top                                      |                                     |   791|
+|2     |  Axis_adc_data_packer_v1_0_S00_AXI_inst |Axis_adc_data_packer_v1_0_S00_AXI    |   567|
+|3     |    xpm_cdc_array_single_inst0           |xpm_cdc_array_single                 |     5|
+|4     |    xpm_cdc_array_single_inst1           |xpm_cdc_array_single__parameterized0 |   130|
+|5     |    axis_adc_data_packer                 |axis_adc_data_packer                 |   205|
+------+-----------------------------------------+-------------------------------------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 8 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 2007.641 ; gain = 577.004
+Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2007.641 ; gain = 1646.012
+INFO: [Project 1-571] Translating synthesized netlist
+INFO: [Netlist 29-17] Analyzing 126 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2043.539 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 116 instances were transformed.
+  BUFG => BUFGCE: 2 instances
+  IBUF => IBUF (IBUFCTRL, INBUF): 114 instances
+
+INFO: [Common 17-83] Releasing license: Synthesis
+41 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2043.539 ; gain = 1693.754
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2043.539 ; gain = 0.000
+WARNING: [Constraints 18-5210] No constraints selected for write.
+Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
+INFO: [Common 17-1381] The checkpoint 'C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1/Axis_adc_data_packer_v1_0.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_utilization -file Axis_adc_data_packer_v1_0_utilization_synth.rpt -pb Axis_adc_data_packer_v1_0_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Thu Dec 23 16:00:12 2021...
@@ -0,0 +1,43 @@
+#!/bin/sh
+
+# 
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+# 
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
+exit
+
+if [ -z "$PATH" ]; then
+  PATH=D:/xilinx/SDK/2018.3/bin;D:/xilinx/Vivado/2018.3/ids_lite/ISE/bin/nt64;D:/xilinx/Vivado/2018.3/ids_lite/ISE/lib/nt64:D:/xilinx/Vivado/2018.3/bin
+else
+  PATH=D:/xilinx/SDK/2018.3/bin;D:/xilinx/Vivado/2018.3/ids_lite/ISE/bin/nt64;D:/xilinx/Vivado/2018.3/ids_lite/ISE/lib/nt64:D:/xilinx/Vivado/2018.3/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+  LD_LIBRARY_PATH=
+else
+  LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+     $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+     if [ $? -ne 0 ]
+     then
+         exit
+     fi
+}
+
+EAStep vivado -log Axis_adc_data_packer_v1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Axis_adc_data_packer_v1_0.tcl
@@ -0,0 +1,12 @@
+#-----------------------------------------------------------
+# Vivado v2018.3 (64-bit)
+# SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
+# IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
+# Start of session at: Thu Dec 23 15:59:40 2021
+# Process ID: 9796
+# Current directory: C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1
+# Command line: vivado.exe -log Axis_adc_data_packer_v1_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Axis_adc_data_packer_v1_0.tcl
+# Log file: C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1/Axis_adc_data_packer_v1_0.vds
+# Journal file: C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.runs/synth_1\vivado.jou
+#-----------------------------------------------------------
+source Axis_adc_data_packer_v1_0.tcl -notrace
@@ -0,0 +1,200 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2018.3 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="39" Path="C:/Users/swang/Desktop/cx91e1/zcu106/ip_repo/work/edit_Axis_adc_data_packer_v1_0.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="c5d913f2a6d24b02baad3334ffc5d142"/>
+    <Option Name="Part" Val="xczu7ev-ffvc1156-2-e"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="BoardPart" Val="xilinx.com:zcu106:part0:2.3"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPRepoPath" Val="$PPRDIR/."/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSAVendor" Val="xilinx"/>
+    <Option Name="DSABoardId" Val="zcu106"/>
+    <Option Name="DSANumComputeUnits" Val="60"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v">
+        <FileInfo>
+          <Attr Name="Library" Val=""/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/Axis_adc_data_packer_1.0/hdl/axis_adc_data_packer.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v">
+        <FileInfo>
+          <Attr Name="Library" Val=""/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/Axis_adc_data_packer_1.0/component.xml">
+        <FileInfo SFType="IPXACT"/>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="Axis_adc_data_packer_v1_0"/>
+        <Option Name="TopRTLFile" Val="$PPRDIR/Axis_adc_data_packer_1.0/hdl/Axis_adc_data_packer_v1_0.v"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="Axis_adc_data_packer_v1_0"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="10">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xczu7ev-ffvc1156-2-e" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xczu7ev-ffvc1156-2-e" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+  </Runs>
+  <Board>
+    <Jumpers/>
+  </Board>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+  <BootPmcSettings Version="1" Minor="0">
+    <Parameters/>
+  </BootPmcSettings>
+</Project>
@@ -0,0 +1,143 @@
+################ 1 #CX9261A Interface PACKAGE_PIN and IOStandard constraints####################
+############CX9261A SPI and Control pin Interface##############
+set_property PACKAGE_PIN V28 [get_ports SCLK       ]
+set_property PACKAGE_PIN V29 [get_ports CSB        ]
+set_property PACKAGE_PIN T28 [get_ports SDO        ]
+set_property PACKAGE_PIN R28 [get_ports SDIO       ]
+set_property PACKAGE_PIN N27 [get_ports NRST       ]
+set_property PACKAGE_PIN U26 [get_ports OSC_OUT    ]
+set_property PACKAGE_PIN P26 [get_ports ENABLE_TRX2]
+set_property PACKAGE_PIN P25 [get_ports ENABLE_TRX1]
+set_property PACKAGE_PIN N26 [get_ports ENABLE_RXFB]
+set_property PACKAGE_PIN P29 [get_ports TXNRX_TRX1 ]
+set_property PACKAGE_PIN N29 [get_ports TXNRX_TRX2 ]
+set_property PACKAGE_PIN U27 [get_ports TXNRX_RXFB ]
+set_property IOSTANDARD LVCMOS25 [get_ports SCLK       ]
+set_property IOSTANDARD LVCMOS25 [get_ports CSB        ]
+set_property IOSTANDARD LVCMOS25 [get_ports SDO        ]
+set_property IOSTANDARD LVCMOS25 [get_ports SDIO       ]
+set_property IOSTANDARD LVCMOS25 [get_ports NRST       ]
+set_property IOSTANDARD LVCMOS25 [get_ports OSC_OUT    ]
+set_property IOSTANDARD LVCMOS25 [get_ports ENABLE_TRX1]
+set_property IOSTANDARD LVCMOS25 [get_ports ENABLE_TRX2]
+set_property IOSTANDARD LVCMOS25 [get_ports ENABLE_RXFB]
+set_property IOSTANDARD LVCMOS25 [get_ports TXNRX_TRX1 ]
+set_property IOSTANDARD LVCMOS25 [get_ports TXNRX_TRX2 ]
+set_property IOSTANDARD LVCMOS25 [get_ports TXNRX_RXFB ]
+###############################################################
+####################CX9261A data Interface#####################
+set_property PACKAGE_PIN W25  [get_ports RXFB_MCLK_IN     ]
+set_property PACKAGE_PIN W26  [get_ports RXFB_FRAME_IN    ]
+set_property PACKAGE_PIN AF22 [get_ports RX1_MCLK_IN_N    ]
+set_property PACKAGE_PIN AE22 [get_ports RX2_MCLK_IN_P    ]
+set_property PACKAGE_PIN AH24 [get_ports RX1_FRAME_IN_N   ]
+set_property PACKAGE_PIN AH23 [get_ports RX2_FRAME_IN_P   ]
+set_property PACKAGE_PIN R26  [get_ports TX1_FCLK_OUT_N   ]
+set_property PACKAGE_PIN R25  [get_ports TX2_FCLK_OUT_P   ]
+set_property PACKAGE_PIN T25  [get_ports TX1_FRAME_OUT_N  ]
+set_property PACKAGE_PIN T24  [get_ports TX2_FRAME_OUT_P  ]
+set_property PACKAGE_PIN P30  [get_ports {RXFB_RX_DATA[7]}]
+set_property PACKAGE_PIN R30  [get_ports {RXFB_RX_DATA[6]}]
+set_property PACKAGE_PIN P23  [get_ports {RXFB_RX_DATA[5]}]
+set_property PACKAGE_PIN P24  [get_ports {RXFB_RX_DATA[4]}]
+set_property PACKAGE_PIN P21  [get_ports {RXFB_RX_DATA[3]}]
+set_property PACKAGE_PIN R21  [get_ports {RXFB_RX_DATA[2]}]
+set_property PACKAGE_PIN W29  [get_ports {RXFB_RX_DATA[1]}]
+set_property PACKAGE_PIN W30  [get_ports {RXFB_RX_DATA[0]}]
+set_property PACKAGE_PIN U25  [get_ports {RXFB_TX_DATA[7]}]
+set_property PACKAGE_PIN V26  [get_ports {RXFB_TX_DATA[6]}]
+set_property PACKAGE_PIN V27  [get_ports {RXFB_TX_DATA[5]}]
+set_property PACKAGE_PIN W28  [get_ports {RXFB_TX_DATA[4]}]
+set_property PACKAGE_PIN T29  [get_ports {RXFB_TX_DATA[3]}]
+set_property PACKAGE_PIN U29  [get_ports {RXFB_TX_DATA[2]}]
+set_property PACKAGE_PIN T30  [get_ports {RXFB_TX_DATA[1]}]
+set_property PACKAGE_PIN U30  [get_ports {RXFB_TX_DATA[0]}]
+set_property PACKAGE_PIN AH19 [get_ports {RX1_FDD_DATA[7]}]
+set_property PACKAGE_PIN AJ19 [get_ports {RX1_FDD_DATA[6]}]
+set_property PACKAGE_PIN AF19 [get_ports {RX1_FDD_DATA[5]}]
+set_property PACKAGE_PIN AG19 [get_ports {RX1_FDD_DATA[4]}]
+set_property PACKAGE_PIN AF23 [get_ports {RX1_FDD_DATA[3]}]
+set_property PACKAGE_PIN AF24 [get_ports {RX1_FDD_DATA[2]}]
+set_property PACKAGE_PIN AA24 [get_ports {RX1_FDD_DATA[1]}]
+set_property PACKAGE_PIN AB24 [get_ports {RX1_FDD_DATA[0]}]
+set_property PACKAGE_PIN Y22  [get_ports {RX2_FDD_DATA[7]}]
+set_property PACKAGE_PIN Y23  [get_ports {RX2_FDD_DATA[6]}]
+set_property PACKAGE_PIN AC24 [get_ports {RX2_FDD_DATA[5]}]
+set_property PACKAGE_PIN AD24 [get_ports {RX2_FDD_DATA[4]}]
+set_property PACKAGE_PIN AG24 [get_ports {RX2_FDD_DATA[3]}]
+set_property PACKAGE_PIN AG25 [get_ports {RX2_FDD_DATA[2]}]
+set_property PACKAGE_PIN AF20 [get_ports {RX2_FDD_DATA[1]}]
+set_property PACKAGE_PIN AG20 [get_ports {RX2_FDD_DATA[0]}]
+set_property PACKAGE_PIN AG22 [get_ports {TX1_FDD_DATA[7]}]
+set_property PACKAGE_PIN AH22 [get_ports {TX1_FDD_DATA[6]}]
+set_property PACKAGE_PIN AA22 [get_ports {TX1_FDD_DATA[5]}]
+set_property PACKAGE_PIN AA23 [get_ports {TX1_FDD_DATA[4]}]
+set_property PACKAGE_PIN AG21 [get_ports {TX1_FDD_DATA[3]}]
+set_property PACKAGE_PIN AH21 [get_ports {TX1_FDD_DATA[2]}]
+set_property PACKAGE_PIN AD21 [get_ports {TX1_FDD_DATA[1]}]
+set_property PACKAGE_PIN AE21 [get_ports {TX1_FDD_DATA[0]}]
+set_property PACKAGE_PIN AK17 [get_ports {TX2_FDD_DATA[7]}]
+set_property PACKAGE_PIN AK18 [get_ports {TX2_FDD_DATA[6]}]
+set_property PACKAGE_PIN AJ20 [get_ports {TX2_FDD_DATA[5]}]
+set_property PACKAGE_PIN AK20 [get_ports {TX2_FDD_DATA[4]}]
+set_property PACKAGE_PIN AJ23 [get_ports {TX2_FDD_DATA[3]}]
+set_property PACKAGE_PIN AJ24 [get_ports {TX2_FDD_DATA[2]}]
+set_property PACKAGE_PIN AD23 [get_ports {TX2_FDD_DATA[1]}]
+set_property PACKAGE_PIN AE23 [get_ports {TX2_FDD_DATA[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports RXFB_MCLK_IN     ]
+set_property IOSTANDARD LVCMOS25 [get_ports RXFB_FRAME_IN    ]
+set_property IOSTANDARD LVCMOS25 [get_ports RX1_MCLK_IN_N    ]
+set_property IOSTANDARD LVCMOS25 [get_ports RX2_MCLK_IN_P    ]
+set_property IOSTANDARD LVCMOS25 [get_ports RX1_FRAME_IN_N   ]
+set_property IOSTANDARD LVCMOS25 [get_ports RX2_FRAME_IN_P   ]
+set_property IOSTANDARD LVCMOS25 [get_ports TX1_FCLK_OUT_N   ]
+set_property IOSTANDARD LVCMOS25 [get_ports TX2_FCLK_OUT_P   ]
+set_property IOSTANDARD LVCMOS25 [get_ports TX1_FRAME_OUT_N  ]
+set_property IOSTANDARD LVCMOS25 [get_ports TX2_FRAME_OUT_P  ]
+set_property IOSTANDARD LVCMOS25 [get_ports {RXFB_RX_DATA[*]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {RXFB_TX_DATA[*]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {RX1_FDD_DATA[*]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {RX2_FDD_DATA[*]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {TX1_FDD_DATA[*]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {TX2_FDD_DATA[*]}]
+###############################################################
+################################################################################################
+########### 2 #CX3E04 and Debug Interface PACKAGE_PIN and IOStandard constraints################
+######################CX3E04 Interface#########################
+set_property PACKAGE_PIN W23  [get_ports CX3E04_NRST  ]
+set_property PACKAGE_PIN AJ25 [get_ports CX3E04_CSB   ]
+set_property PACKAGE_PIN AK25 [get_ports CX3E04_SDIO  ]
+set_property PACKAGE_PIN AK22 [get_ports CX3E04_SCLK  ]
+set_property IOSTANDARD LVCMOS25 [get_ports CX3E04_NRST ]
+set_property IOSTANDARD LVCMOS25 [get_ports CX3E04_CSB  ]
+set_property IOSTANDARD LVCMOS25 [get_ports CX3E04_SDIO ]
+set_property IOSTANDARD LVCMOS25 [get_ports CX3E04_SCLK ]
+
+set_property PACKAGE_PIN AE28 [get_ports CX3E04_CLK_P ]
+set_property PACKAGE_PIN AF28 [get_ports CX3E04_CLK_N ]
+set_property PACKAGE_PIN AC29 [get_ports CX3E04_SYNC_P]
+set_property PACKAGE_PIN AD29 [get_ports CX3E04_SYNC_N]
+set_property IOSTANDARD LVDS_25 [get_ports CX3E04_CLK_P ]
+set_property IOSTANDARD LVDS_25 [get_ports CX3E04_CLK_N ]
+set_property IOSTANDARD LVDS_25 [get_ports CX3E04_SYNC_P]
+set_property IOSTANDARD LVDS_25 [get_ports CX3E04_SYNC_N]
+###############################################################
+######################Debug Interface##########################
+#set_property PACKAGE_PIN AD18 [get_ports power_on_trigger]
+#set_property IOSTANDARD LVCMOS25 [get_ports power_on_trigger]
+###############################################################
+################################################################################################
+################# 3 #clock Period/Route and hardcore Position constraints#######################
+create_clock -period 6.25 -name RX1_MCLK_IN_N -waveform {0.000 3.125} [get_ports RX1_MCLK_IN_N]
+create_clock -period 6.25 -name RX2_MCLK_IN_P -waveform {0.000 3.125} [get_ports RX2_MCLK_IN_P]
+create_clock -period 6.25 -name RXFB_MCLK_IN  -waveform {0.000 3.125} [get_ports RXFB_MCLK_IN ]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_mclk_delay/MCLK1]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_mclk_delay/MCLK2]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_mclk_delay/MCLK3]
+
+set_property LOC IDELAYCTRL_X0Y2 [get_cells u_mclk_delay/IDELAYCTRL_RX12]
+set_property LOC IDELAYCTRL_X0Y4 [get_cells u_mclk_delay/IDELAYCTRL_RX3]
+################################################################################################
+
+set_clock_groups -asynchronous -group [get_clocks RXFB_MCLK_IN] -group [get_clocks RX1_MCLK_IN_N] -group [get_clocks RX2_MCLK_IN_P] -group [get_clocks clk_fpga_0]
@@ -0,0 +1,49 @@
+##################################### 1 #set false path########################################
+set_false_path -from [get_pins {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/SAFETY_CKT_GEN.RSTB_SHFT_REG_reg[3]_srl3/CLK}] -to [get_pins {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/SAFETY_CKT_GEN.RSTB_SHFT_REG_reg[4]/D}]
+set_false_path -from [get_pins {system_top_i/fifo_generator_0/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/SAFETY_CKT_GEN.RSTA_SHFT_REG_reg[3]_srl3/CLK}] -to [get_pins {system_top_i/fifo_generator_0/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/SAFETY_CKT_GEN.RSTA_SHFT_REG_reg[4]/D}]
+
+set_false_path -from [get_clocks RX1_MCLK_IN_N] -to [get_clocks -of_objects [get_pins system_top_i/mig_7series_0/u_system_top_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT]]
+set_false_path -from [get_clocks RX2_MCLK_IN_P] -to [get_clocks -of_objects [get_pins system_top_i/mig_7series_0/u_system_top_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT]]
+
+set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks RX2_MCLK_IN_P]
+################################################################################################
+#################################### 2 #CX9261A data ila########################################
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list system_top_i/processing_system7_0/inst/FCLK_CLK0]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 24 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {hop_intr/r_hop_cnt[0]} {hop_intr/r_hop_cnt[1]} {hop_intr/r_hop_cnt[2]} {hop_intr/r_hop_cnt[3]} {hop_intr/r_hop_cnt[4]} {hop_intr/r_hop_cnt[5]} {hop_intr/r_hop_cnt[6]} {hop_intr/r_hop_cnt[7]} {hop_intr/r_hop_cnt[8]} {hop_intr/r_hop_cnt[9]} {hop_intr/r_hop_cnt[10]} {hop_intr/r_hop_cnt[11]} {hop_intr/r_hop_cnt[12]} {hop_intr/r_hop_cnt[13]} {hop_intr/r_hop_cnt[14]} {hop_intr/r_hop_cnt[15]} {hop_intr/r_hop_cnt[16]} {hop_intr/r_hop_cnt[17]} {hop_intr/r_hop_cnt[18]} {hop_intr/r_hop_cnt[19]} {hop_intr/r_hop_cnt[20]} {hop_intr/r_hop_cnt[21]} {hop_intr/r_hop_cnt[22]} {hop_intr/r_hop_cnt[23]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 1 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list hop_intr/hop_flag]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 1 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list hop_intr/spi_pose_flag]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 1 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list hop_intr/r_hop_cnt_flag]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 1 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list hop_intr/hop_neg_flag]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 1 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list hop_intr/hop_signal]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets MCLK2]
+################################################################################################
@@ -0,0 +1,163 @@
+set_false_path -from [get_pins {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/SAFETY_CKT_GEN.RSTB_SHFT_REG_reg[3]_srl3/CLK}] -to [get_pins {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/SAFETY_CKT_GEN.RSTB_SHFT_REG_reg[4]/D}]
+set_false_path -from [get_pins {system_top_i/fifo_generator_0/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/SAFETY_CKT_GEN.RSTA_SHFT_REG_reg[3]_srl3/CLK}] -to [get_pins {system_top_i/fifo_generator_0/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/SAFETY_CKT_GEN.RSTA_SHFT_REG_reg[4]/D}]
+
+
+
+
+
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/mclk_g1]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 8 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 8 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 8 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_pos_o[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 8 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_neg_o[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 8 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX1_DATA_pos_o[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 8 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX1_DATA_neg_o[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 16 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_i_data[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+set_property port_width 16 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_q_data[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+set_property port_width 16 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_i_data[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+set_property port_width 16 [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_q_data[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+set_property port_width 1 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx1_data_valid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+set_property port_width 1 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_data_ready]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+set_property port_width 1 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_frame_neg]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+set_property port_width 1 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx1_frame_pos]]
+create_debug_core u_ila_1 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
+set_property port_width 1 [get_debug_ports u_ila_1/clk]
+connect_debug_port u_ila_1/clk [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/data_clk2]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
+set_property port_width 2 [get_debug_ports u_ila_1/probe0]
+connect_debug_port u_ila_1/probe0 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX_FRAME_N[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX_FRAME_N[1]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
+set_property port_width 8 [get_debug_ports u_ila_1/probe1]
+connect_debug_port u_ila_1/probe1 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_neg_o[7]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
+set_property port_width 8 [get_debug_ports u_ila_1/probe2]
+connect_debug_port u_ila_1/probe2 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA[7]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
+set_property port_width 8 [get_debug_ports u_ila_1/probe3]
+connect_debug_port u_ila_1/probe3 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_neg_o[7]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4]
+set_property port_width 8 [get_debug_ports u_ila_1/probe4]
+connect_debug_port u_ila_1/probe4 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/TX2_DATA_pos_o[7]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5]
+set_property port_width 8 [get_debug_ports u_ila_1/probe5]
+connect_debug_port u_ila_1/probe5 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA_pos_o[7]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6]
+set_property port_width 8 [get_debug_ports u_ila_1/probe6]
+connect_debug_port u_ila_1/probe6 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/RX2_DATA[7]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7]
+set_property port_width 16 [get_debug_ports u_ila_1/probe7]
+connect_debug_port u_ila_1/probe7 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_q_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8]
+set_property port_width 16 [get_debug_ports u_ila_1/probe8]
+connect_debug_port u_ila_1/probe8 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_i_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9]
+set_property port_width 16 [get_debug_ports u_ila_1/probe9]
+connect_debug_port u_ila_1/probe9 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_i_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe10]
+set_property port_width 16 [get_debug_ports u_ila_1/probe10]
+connect_debug_port u_ila_1/probe10 [get_nets [list {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[0]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[1]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[2]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[3]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[4]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[5]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[6]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[7]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[8]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[9]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[10]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[11]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[12]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[13]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[14]} {cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_q_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe11]
+set_property port_width 1 [get_debug_ports u_ila_1/probe11]
+connect_debug_port u_ila_1/probe11 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/r1t1_r2t2_sel]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe12]
+set_property port_width 1 [get_debug_ports u_ila_1/probe12]
+connect_debug_port u_ila_1/probe12 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/rx2_data_valid]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe13]
+set_property port_width 1 [get_debug_ports u_ila_1/probe13]
+connect_debug_port u_ila_1/probe13 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/sp_dp_sel]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe14]
+set_property port_width 1 [get_debug_ports u_ila_1/probe14]
+connect_debug_port u_ila_1/probe14 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tdd_fdd_sel]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe15]
+set_property port_width 1 [get_debug_ports u_ila_1/probe15]
+connect_debug_port u_ila_1/probe15 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tr_sel]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe16]
+set_property port_width 1 [get_debug_ports u_ila_1/probe16]
+connect_debug_port u_ila_1/probe16 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_data_ready]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe17]
+set_property port_width 1 [get_debug_ports u_ila_1/probe17]
+connect_debug_port u_ila_1/probe17 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_frame_neg]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe18]
+set_property port_width 1 [get_debug_ports u_ila_1/probe18]
+connect_debug_port u_ila_1/probe18 [get_nets [list cx9261a_if_cmos/u_cx9261a_if_cmos_port/tx2_frame_pos]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets data_clk2]
@@ -0,0 +1,763 @@
+set_property MARK_DEBUG true [get_nets {data_i[10]}]
+set_property MARK_DEBUG true [get_nets {data_i[1]}]
+set_property MARK_DEBUG true [get_nets {data_i[4]}]
+set_property MARK_DEBUG true [get_nets {data_i[6]}]
+set_property MARK_DEBUG true [get_nets {data_i[13]}]
+set_property MARK_DEBUG true [get_nets {data_q[2]}]
+set_property MARK_DEBUG true [get_nets {data_q[6]}]
+set_property MARK_DEBUG true [get_nets {data_q[10]}]
+set_property MARK_DEBUG true [get_nets {data_q[15]}]
+set_property MARK_DEBUG true [get_nets {data_i[0]}]
+set_property MARK_DEBUG true [get_nets {data_i[5]}]
+set_property MARK_DEBUG true [get_nets {data_i[8]}]
+set_property MARK_DEBUG true [get_nets {data_i[15]}]
+set_property MARK_DEBUG true [get_nets {data_q[1]}]
+set_property MARK_DEBUG true [get_nets {data_q[5]}]
+set_property MARK_DEBUG true [get_nets {data_q[8]}]
+set_property MARK_DEBUG true [get_nets {data_q[12]}]
+set_property MARK_DEBUG true [get_nets {data_i[3]}]
+set_property MARK_DEBUG true [get_nets {data_i[7]}]
+set_property MARK_DEBUG true [get_nets {data_i[12]}]
+set_property MARK_DEBUG true [get_nets {data_q[0]}]
+set_property MARK_DEBUG true [get_nets {data_q[4]}]
+set_property MARK_DEBUG true [get_nets {data_q[7]}]
+set_property MARK_DEBUG true [get_nets {data_q[13]}]
+set_property MARK_DEBUG true [get_nets {data_i[2]}]
+set_property MARK_DEBUG true [get_nets {data_i[9]}]
+set_property MARK_DEBUG true [get_nets {data_i[11]}]
+set_property MARK_DEBUG true [get_nets {data_i[14]}]
+set_property MARK_DEBUG true [get_nets {data_q[3]}]
+set_property MARK_DEBUG true [get_nets {data_q[9]}]
+set_property MARK_DEBUG true [get_nets {data_q[11]}]
+set_property MARK_DEBUG true [get_nets {data_q[14]}]
+
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[0]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[2]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[4]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[6]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[7]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[10]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[12]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[14]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[1]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[3]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[5]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[8]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[9]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[11]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_1_Q[13]}]
+
+set_property MARK_DEBUG true [get_nets system_top_i/CE]
+set_property MARK_DEBUG true [get_nets NRST_OBUF]
+
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[13]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[29]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[54]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[12]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[42]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[17]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[34]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[37]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[35]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[41]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[61]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[24]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[39]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[45]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[23]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[56]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[21]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[35]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[54]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[56]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[42]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[10]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[53]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[63]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[1]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[6]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[58]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[9]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[21]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[23]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[38]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[14]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[12]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[50]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[55]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[57]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[61]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[5]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[50]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[31]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[43]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[55]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[10]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[12]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[39]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[32]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[16]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[63]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[49]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[40]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[58]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[4]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[27]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[13]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[22]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[44]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[15]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[58]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[4]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[7]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[49]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[5]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[59]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[19]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[28]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[3]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[27]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[30]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[9]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[26]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[1]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[6]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[27]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[46]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[3]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[53]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[56]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[8]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[25]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[26]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[47]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[59]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[11]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[29]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[52]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[18]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[24]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[7]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[50]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[33]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[41]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[61]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[1]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[15]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[18]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[0]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[16]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[19]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[51]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[55]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[2]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[20]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[31]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[13]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[49]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[3]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[51]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[7]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[14]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[15]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[32]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[53]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[17]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[23]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[4]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[14]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[45]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[24]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[22]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[59]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[62]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[11]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[22]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[37]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[45]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[60]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[18]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[28]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[0]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[17]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[36]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[39]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[43]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[63]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[2]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[30]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[42]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[60]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[52]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[54]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[26]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[9]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[20]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[33]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[44]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[48]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[60]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[21]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[41]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[48]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[38]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[47]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[29]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[36]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[38]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[44]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[51]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[43]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[48]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[11]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[16]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[35]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[10]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[34]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[40]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[46]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[62]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[0]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[25]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[32]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[8]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[19]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[37]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[57]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[62]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[6]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[52]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[8]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[31]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[20]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[25]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[34]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[40]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[46]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[2]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[57]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[5]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_i[28]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[47]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[33]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_t[36]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/GPIO_0_0_tri_o[30]}]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io0_t]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io1_t]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_sck_o]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_ss_i]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io0_i]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_sck_i]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_sck_t]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_ss1_o]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_ss2_o]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io0_o]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io1_i]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_io1_o]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_ss_o]
+set_property MARK_DEBUG true [get_nets system_top_i/SPI_0_0_ss_t]
+
+
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[3]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[5]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[7]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[10]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[11]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[12]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[14]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[2]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[4]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[6]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[8]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[9]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/addrb[13]}]
+set_property MARK_DEBUG true [get_nets system_top_i/blk_mem_gen_0/U0/rstb_busy]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[1]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[3]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[6]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[10]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[4]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[0]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[2]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[5]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[8]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[12]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[9]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[11]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[7]}]
+
+set_property MARK_DEBUG true [get_nets system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/capture_cdc]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[3]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[8]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[24]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[25]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[9]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[0]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[2]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[5]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[18]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[19]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[20]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[21]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[6]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[10]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[17]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[22]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[23]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[12]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[16]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[1]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[4]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[7]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[11]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[13]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[14]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[15]}]
+#connect_debug_port dbg_hub/clk [get_nets data_clk]
+
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[3]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[0]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[1]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[2]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[4]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[5]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[6]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[7]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[0]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[1]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[2]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[3]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[4]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[5]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[6]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[7]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[4]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[5]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[7]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[2]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[3]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[6]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[0]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[1]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[0]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[1]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[2]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[3]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[4]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[5]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[6]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[7]}]
+set_property MARK_DEBUG true [get_nets cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FRAME_neg]
+set_property MARK_DEBUG true [get_nets cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FRAME_pos]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[2]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[0]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[6]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[1]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[5]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[0]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[4]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[2]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[3]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[7]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[1]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[2]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[6]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[1]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[7]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[3]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[0]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[4]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[4]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[7]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[3]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[2]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[5]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[6]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[1]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[5]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[5]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[0]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[4]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[7]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[3]}]
+set_property MARK_DEBUG true [get_nets {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[6]}]
+set_property MARK_DEBUG true [get_nets cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FRAME_neg]
+set_property MARK_DEBUG true [get_nets cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FRAME_pos]
+
+set_property MARK_DEBUG true [get_nets {rx1_q_data[1]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[1]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[8]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[8]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[8]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[1]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[1]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[8]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[4]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[12]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[4]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[12]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[12]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[4]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[4]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[12]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[11]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[3]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[11]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[3]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[3]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[11]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[3]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[11]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[9]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[14]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[6]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[14]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[6]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[14]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[6]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[14]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[5]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[13]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[5]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[13]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[5]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[13]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[5]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[13]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[7]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[0]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[6]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[0]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[7]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[0]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[0]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[7]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[7]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[15]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[9]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[15]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[15]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[9]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[9]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[15]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[2]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[2]}]
+set_property MARK_DEBUG true [get_nets {rx1_i_data[10]}]
+set_property MARK_DEBUG true [get_nets {rx1_q_data[10]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[2]}]
+set_property MARK_DEBUG true [get_nets {rx2_i_data[10]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[2]}]
+set_property MARK_DEBUG true [get_nets {rx2_q_data[10]}]
+
+set_property MARK_DEBUG true [get_nets {tx1_i_data[4]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[12]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[4]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[12]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[12]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[4]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[4]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[12]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[1]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[1]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[8]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[8]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[1]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[8]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[1]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[8]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[2]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[10]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[2]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[10]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[2]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[10]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[2]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[10]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[15]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[9]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[9]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[15]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[9]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[15]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[9]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[15]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[7]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[7]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[0]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[0]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[0]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[7]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[0]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[7]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[5]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[13]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[5]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[13]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[13]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[5]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[5]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[13]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[14]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[6]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[6]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[14]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[6]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[14]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[6]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[14]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[3]}]
+set_property MARK_DEBUG true [get_nets {tx1_i_data[11]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[3]}]
+set_property MARK_DEBUG true [get_nets {tx1_q_data[11]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[11]}]
+set_property MARK_DEBUG true [get_nets {tx2_i_data[3]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[3]}]
+set_property MARK_DEBUG true [get_nets {tx2_q_data[11]}]
+
+set_property MARK_DEBUG true [get_nets system_top_i/CE_1]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[1]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[4]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[15]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[16]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[17]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[19]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[24]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[31]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[3]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[5]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[6]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[7]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[10]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[18]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[22]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[2]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[0]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[8]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[29]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[9]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[12]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[30]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[13]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[20]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[21]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[27]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[11]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[14]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[23]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[25]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[26]}]
+set_property MARK_DEBUG true [get_nets {system_top_i/c_counter_binary_2_Q[28]}]
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list system_top_i/mig_7series_0/u_system_top_mig_7series_0_0_mig/u_ddr3_infrastructure/CLK]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 26 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[0]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[1]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[2]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[3]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[4]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[5]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[6]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[7]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[8]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[9]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[10]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[11]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[12]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[13]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[14]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[15]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[16]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[17]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[18]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[19]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[20]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[21]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[22]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[23]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[24]} {system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/length_cdc[25]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 64 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {system_top_i/GPIO_0_0_tri_o[0]} {system_top_i/GPIO_0_0_tri_o[1]} {system_top_i/GPIO_0_0_tri_o[2]} {system_top_i/GPIO_0_0_tri_o[3]} {system_top_i/GPIO_0_0_tri_o[4]} {system_top_i/GPIO_0_0_tri_o[5]} {system_top_i/GPIO_0_0_tri_o[6]} {system_top_i/GPIO_0_0_tri_o[7]} {system_top_i/GPIO_0_0_tri_o[8]} {system_top_i/GPIO_0_0_tri_o[9]} {system_top_i/GPIO_0_0_tri_o[10]} {system_top_i/GPIO_0_0_tri_o[11]} {system_top_i/GPIO_0_0_tri_o[12]} {system_top_i/GPIO_0_0_tri_o[13]} {system_top_i/GPIO_0_0_tri_o[14]} {system_top_i/GPIO_0_0_tri_o[15]} {system_top_i/GPIO_0_0_tri_o[16]} {system_top_i/GPIO_0_0_tri_o[17]} {system_top_i/GPIO_0_0_tri_o[18]} {system_top_i/GPIO_0_0_tri_o[19]} {system_top_i/GPIO_0_0_tri_o[20]} {system_top_i/GPIO_0_0_tri_o[21]} {system_top_i/GPIO_0_0_tri_o[22]} {system_top_i/GPIO_0_0_tri_o[23]} {system_top_i/GPIO_0_0_tri_o[24]} {system_top_i/GPIO_0_0_tri_o[25]} {system_top_i/GPIO_0_0_tri_o[26]} {system_top_i/GPIO_0_0_tri_o[27]} {system_top_i/GPIO_0_0_tri_o[28]} {system_top_i/GPIO_0_0_tri_o[29]} {system_top_i/GPIO_0_0_tri_o[30]} {system_top_i/GPIO_0_0_tri_o[31]} {system_top_i/GPIO_0_0_tri_o[32]} {system_top_i/GPIO_0_0_tri_o[33]} {system_top_i/GPIO_0_0_tri_o[34]} {system_top_i/GPIO_0_0_tri_o[35]} {system_top_i/GPIO_0_0_tri_o[36]} {system_top_i/GPIO_0_0_tri_o[37]} {system_top_i/GPIO_0_0_tri_o[38]} {system_top_i/GPIO_0_0_tri_o[39]} {system_top_i/GPIO_0_0_tri_o[40]} {system_top_i/GPIO_0_0_tri_o[41]} {system_top_i/GPIO_0_0_tri_o[42]} {system_top_i/GPIO_0_0_tri_o[43]} {system_top_i/GPIO_0_0_tri_o[44]} {system_top_i/GPIO_0_0_tri_o[45]} {system_top_i/GPIO_0_0_tri_o[46]} {system_top_i/GPIO_0_0_tri_o[47]} {system_top_i/GPIO_0_0_tri_o[48]} {system_top_i/GPIO_0_0_tri_o[49]} {system_top_i/GPIO_0_0_tri_o[50]} {system_top_i/GPIO_0_0_tri_o[51]} {system_top_i/GPIO_0_0_tri_o[52]} {system_top_i/GPIO_0_0_tri_o[53]} {system_top_i/GPIO_0_0_tri_o[54]} {system_top_i/GPIO_0_0_tri_o[55]} {system_top_i/GPIO_0_0_tri_o[56]} {system_top_i/GPIO_0_0_tri_o[57]} {system_top_i/GPIO_0_0_tri_o[58]} {system_top_i/GPIO_0_0_tri_o[59]} {system_top_i/GPIO_0_0_tri_o[60]} {system_top_i/GPIO_0_0_tri_o[61]} {system_top_i/GPIO_0_0_tri_o[62]} {system_top_i/GPIO_0_0_tri_o[63]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 64 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {system_top_i/GPIO_0_0_tri_t[0]} {system_top_i/GPIO_0_0_tri_t[1]} {system_top_i/GPIO_0_0_tri_t[2]} {system_top_i/GPIO_0_0_tri_t[3]} {system_top_i/GPIO_0_0_tri_t[4]} {system_top_i/GPIO_0_0_tri_t[5]} {system_top_i/GPIO_0_0_tri_t[6]} {system_top_i/GPIO_0_0_tri_t[7]} {system_top_i/GPIO_0_0_tri_t[8]} {system_top_i/GPIO_0_0_tri_t[9]} {system_top_i/GPIO_0_0_tri_t[10]} {system_top_i/GPIO_0_0_tri_t[11]} {system_top_i/GPIO_0_0_tri_t[12]} {system_top_i/GPIO_0_0_tri_t[13]} {system_top_i/GPIO_0_0_tri_t[14]} {system_top_i/GPIO_0_0_tri_t[15]} {system_top_i/GPIO_0_0_tri_t[16]} {system_top_i/GPIO_0_0_tri_t[17]} {system_top_i/GPIO_0_0_tri_t[18]} {system_top_i/GPIO_0_0_tri_t[19]} {system_top_i/GPIO_0_0_tri_t[20]} {system_top_i/GPIO_0_0_tri_t[21]} {system_top_i/GPIO_0_0_tri_t[22]} {system_top_i/GPIO_0_0_tri_t[23]} {system_top_i/GPIO_0_0_tri_t[24]} {system_top_i/GPIO_0_0_tri_t[25]} {system_top_i/GPIO_0_0_tri_t[26]} {system_top_i/GPIO_0_0_tri_t[27]} {system_top_i/GPIO_0_0_tri_t[28]} {system_top_i/GPIO_0_0_tri_t[29]} {system_top_i/GPIO_0_0_tri_t[30]} {system_top_i/GPIO_0_0_tri_t[31]} {system_top_i/GPIO_0_0_tri_t[32]} {system_top_i/GPIO_0_0_tri_t[33]} {system_top_i/GPIO_0_0_tri_t[34]} {system_top_i/GPIO_0_0_tri_t[35]} {system_top_i/GPIO_0_0_tri_t[36]} {system_top_i/GPIO_0_0_tri_t[37]} {system_top_i/GPIO_0_0_tri_t[38]} {system_top_i/GPIO_0_0_tri_t[39]} {system_top_i/GPIO_0_0_tri_t[40]} {system_top_i/GPIO_0_0_tri_t[41]} {system_top_i/GPIO_0_0_tri_t[42]} {system_top_i/GPIO_0_0_tri_t[43]} {system_top_i/GPIO_0_0_tri_t[44]} {system_top_i/GPIO_0_0_tri_t[45]} {system_top_i/GPIO_0_0_tri_t[46]} {system_top_i/GPIO_0_0_tri_t[47]} {system_top_i/GPIO_0_0_tri_t[48]} {system_top_i/GPIO_0_0_tri_t[49]} {system_top_i/GPIO_0_0_tri_t[50]} {system_top_i/GPIO_0_0_tri_t[51]} {system_top_i/GPIO_0_0_tri_t[52]} {system_top_i/GPIO_0_0_tri_t[53]} {system_top_i/GPIO_0_0_tri_t[54]} {system_top_i/GPIO_0_0_tri_t[55]} {system_top_i/GPIO_0_0_tri_t[56]} {system_top_i/GPIO_0_0_tri_t[57]} {system_top_i/GPIO_0_0_tri_t[58]} {system_top_i/GPIO_0_0_tri_t[59]} {system_top_i/GPIO_0_0_tri_t[60]} {system_top_i/GPIO_0_0_tri_t[61]} {system_top_i/GPIO_0_0_tri_t[62]} {system_top_i/GPIO_0_0_tri_t[63]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 13 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[0]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[1]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[2]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[3]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[4]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[5]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[6]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[7]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[8]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[9]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[10]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[11]} {system_top_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/addrb[12]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 1 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list system_top_i/Axis_adc_data_packer_0/inst/Axis_adc_data_packer_v1_0_S00_AXI_inst/capture_cdc]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 1 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list NRST_OBUF]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 1 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list system_top_i/blk_mem_gen_0/U0/rstb_busy]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+set_property port_width 1 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list system_top_i/SPI_0_0_io0_i]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+set_property port_width 1 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list system_top_i/SPI_0_0_io0_o]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+set_property port_width 1 [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list system_top_i/SPI_0_0_io0_t]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+set_property port_width 1 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list system_top_i/SPI_0_0_io1_i]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+set_property port_width 1 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list system_top_i/SPI_0_0_io1_o]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+set_property port_width 1 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list system_top_i/SPI_0_0_io1_t]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+set_property port_width 1 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list system_top_i/SPI_0_0_sck_i]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
+set_property port_width 1 [get_debug_ports u_ila_0/probe14]
+connect_debug_port u_ila_0/probe14 [get_nets [list system_top_i/SPI_0_0_sck_o]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
+set_property port_width 1 [get_debug_ports u_ila_0/probe15]
+connect_debug_port u_ila_0/probe15 [get_nets [list system_top_i/SPI_0_0_sck_t]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
+set_property port_width 1 [get_debug_ports u_ila_0/probe16]
+connect_debug_port u_ila_0/probe16 [get_nets [list system_top_i/SPI_0_0_ss1_o]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
+set_property port_width 1 [get_debug_ports u_ila_0/probe17]
+connect_debug_port u_ila_0/probe17 [get_nets [list system_top_i/SPI_0_0_ss2_o]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
+set_property port_width 1 [get_debug_ports u_ila_0/probe18]
+connect_debug_port u_ila_0/probe18 [get_nets [list system_top_i/SPI_0_0_ss_i]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
+set_property port_width 1 [get_debug_ports u_ila_0/probe19]
+connect_debug_port u_ila_0/probe19 [get_nets [list system_top_i/SPI_0_0_ss_o]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
+set_property port_width 1 [get_debug_ports u_ila_0/probe20]
+connect_debug_port u_ila_0/probe20 [get_nets [list system_top_i/SPI_0_0_ss_t]]
+create_debug_core u_ila_1 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
+set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_1]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
+set_property port_width 1 [get_debug_ports u_ila_1/clk]
+connect_debug_port u_ila_1/clk [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/CLK]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
+set_property port_width 8 [get_debug_ports u_ila_1/probe0]
+connect_debug_port u_ila_1/probe0 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_neg[7]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
+set_property port_width 16 [get_debug_ports u_ila_1/probe1]
+connect_debug_port u_ila_1/probe1 [get_nets [list {rx1_i_data[0]} {rx1_i_data[1]} {rx1_i_data[2]} {rx1_i_data[3]} {rx1_i_data[4]} {rx1_i_data[5]} {rx1_i_data[6]} {rx1_i_data[7]} {rx1_i_data[8]} {rx1_i_data[9]} {rx1_i_data[10]} {rx1_i_data[11]} {rx1_i_data[12]} {rx1_i_data[13]} {rx1_i_data[14]} {rx1_i_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
+set_property port_width 8 [get_debug_ports u_ila_1/probe2]
+connect_debug_port u_ila_1/probe2 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FDD_DATA_pos[7]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
+set_property port_width 8 [get_debug_ports u_ila_1/probe3]
+connect_debug_port u_ila_1/probe3 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_pos[7]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4]
+set_property port_width 16 [get_debug_ports u_ila_1/probe4]
+connect_debug_port u_ila_1/probe4 [get_nets [list {tx1_i_data[0]} {tx1_i_data[1]} {tx1_i_data[2]} {tx1_i_data[3]} {tx1_i_data[4]} {tx1_i_data[5]} {tx1_i_data[6]} {tx1_i_data[7]} {tx1_i_data[8]} {tx1_i_data[9]} {tx1_i_data[10]} {tx1_i_data[11]} {tx1_i_data[12]} {tx1_i_data[13]} {tx1_i_data[14]} {tx1_i_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5]
+set_property port_width 16 [get_debug_ports u_ila_1/probe5]
+connect_debug_port u_ila_1/probe5 [get_nets [list {tx1_q_data[0]} {tx1_q_data[1]} {tx1_q_data[2]} {tx1_q_data[3]} {tx1_q_data[4]} {tx1_q_data[5]} {tx1_q_data[6]} {tx1_q_data[7]} {tx1_q_data[8]} {tx1_q_data[9]} {tx1_q_data[10]} {tx1_q_data[11]} {tx1_q_data[12]} {tx1_q_data[13]} {tx1_q_data[14]} {tx1_q_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6]
+set_property port_width 16 [get_debug_ports u_ila_1/probe6]
+connect_debug_port u_ila_1/probe6 [get_nets [list {rx1_q_data[0]} {rx1_q_data[1]} {rx1_q_data[2]} {rx1_q_data[3]} {rx1_q_data[4]} {rx1_q_data[5]} {rx1_q_data[6]} {rx1_q_data[7]} {rx1_q_data[8]} {rx1_q_data[9]} {rx1_q_data[10]} {rx1_q_data[11]} {rx1_q_data[12]} {rx1_q_data[13]} {rx1_q_data[14]} {rx1_q_data[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7]
+set_property port_width 8 [get_debug_ports u_ila_1/probe7]
+connect_debug_port u_ila_1/probe7 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/TX_FDD_DATA_neg[7]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8]
+set_property port_width 32 [get_debug_ports u_ila_1/probe8]
+connect_debug_port u_ila_1/probe8 [get_nets [list {system_top_i/c_counter_binary_1_Q[0]} {system_top_i/c_counter_binary_1_Q[1]} {system_top_i/c_counter_binary_1_Q[2]} {system_top_i/c_counter_binary_1_Q[3]} {system_top_i/c_counter_binary_1_Q[4]} {system_top_i/c_counter_binary_1_Q[5]} {system_top_i/c_counter_binary_1_Q[6]} {system_top_i/c_counter_binary_1_Q[7]} {system_top_i/c_counter_binary_1_Q[8]} {system_top_i/c_counter_binary_1_Q[9]} {system_top_i/c_counter_binary_1_Q[10]} {system_top_i/c_counter_binary_1_Q[11]} {system_top_i/c_counter_binary_1_Q[12]} {system_top_i/c_counter_binary_1_Q[13]} {system_top_i/c_counter_binary_1_Q[14]} {system_top_i/c_counter_binary_1_Q[15]} {system_top_i/c_counter_binary_1_Q[16]} {system_top_i/c_counter_binary_1_Q[17]} {system_top_i/c_counter_binary_1_Q[18]} {system_top_i/c_counter_binary_1_Q[19]} {system_top_i/c_counter_binary_1_Q[20]} {system_top_i/c_counter_binary_1_Q[21]} {system_top_i/c_counter_binary_1_Q[22]} {system_top_i/c_counter_binary_1_Q[23]} {system_top_i/c_counter_binary_1_Q[24]} {system_top_i/c_counter_binary_1_Q[25]} {system_top_i/c_counter_binary_1_Q[26]} {system_top_i/c_counter_binary_1_Q[27]} {system_top_i/c_counter_binary_1_Q[28]} {system_top_i/c_counter_binary_1_Q[29]} {system_top_i/c_counter_binary_1_Q[30]} {system_top_i/c_counter_binary_1_Q[31]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9]
+set_property port_width 1 [get_debug_ports u_ila_1/probe9]
+connect_debug_port u_ila_1/probe9 [get_nets [list system_top_i/CE]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe10]
+set_property port_width 1 [get_debug_ports u_ila_1/probe10]
+connect_debug_port u_ila_1/probe10 [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FRAME_neg]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe11]
+set_property port_width 1 [get_debug_ports u_ila_1/probe11]
+connect_debug_port u_ila_1/probe11 [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX1.cx9261a_if_cmos_TRX1/RX_FRAME_pos]]
+create_debug_core u_ila_2 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2]
+set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_2]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_2]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2]
+set_property port_width 1 [get_debug_ports u_ila_2/clk]
+connect_debug_port u_ila_2/clk [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/CLK]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0]
+set_property port_width 16 [get_debug_ports u_ila_2/probe0]
+connect_debug_port u_ila_2/probe0 [get_nets [list {rx2_i_data[0]} {rx2_i_data[1]} {rx2_i_data[2]} {rx2_i_data[3]} {rx2_i_data[4]} {rx2_i_data[5]} {rx2_i_data[6]} {rx2_i_data[7]} {rx2_i_data[8]} {rx2_i_data[9]} {rx2_i_data[10]} {rx2_i_data[11]} {rx2_i_data[12]} {rx2_i_data[13]} {rx2_i_data[14]} {rx2_i_data[15]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1]
+set_property port_width 8 [get_debug_ports u_ila_2/probe1]
+connect_debug_port u_ila_2/probe1 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_neg[7]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe2]
+set_property port_width 8 [get_debug_ports u_ila_2/probe2]
+connect_debug_port u_ila_2/probe2 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_neg[7]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe3]
+set_property port_width 16 [get_debug_ports u_ila_2/probe3]
+connect_debug_port u_ila_2/probe3 [get_nets [list {tx2_i_data[0]} {tx2_i_data[1]} {tx2_i_data[2]} {tx2_i_data[3]} {tx2_i_data[4]} {tx2_i_data[5]} {tx2_i_data[6]} {tx2_i_data[7]} {tx2_i_data[8]} {tx2_i_data[9]} {tx2_i_data[10]} {tx2_i_data[11]} {tx2_i_data[12]} {tx2_i_data[13]} {tx2_i_data[14]} {tx2_i_data[15]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe4]
+set_property port_width 32 [get_debug_ports u_ila_2/probe4]
+connect_debug_port u_ila_2/probe4 [get_nets [list {system_top_i/c_counter_binary_2_Q[0]} {system_top_i/c_counter_binary_2_Q[1]} {system_top_i/c_counter_binary_2_Q[2]} {system_top_i/c_counter_binary_2_Q[3]} {system_top_i/c_counter_binary_2_Q[4]} {system_top_i/c_counter_binary_2_Q[5]} {system_top_i/c_counter_binary_2_Q[6]} {system_top_i/c_counter_binary_2_Q[7]} {system_top_i/c_counter_binary_2_Q[8]} {system_top_i/c_counter_binary_2_Q[9]} {system_top_i/c_counter_binary_2_Q[10]} {system_top_i/c_counter_binary_2_Q[11]} {system_top_i/c_counter_binary_2_Q[12]} {system_top_i/c_counter_binary_2_Q[13]} {system_top_i/c_counter_binary_2_Q[14]} {system_top_i/c_counter_binary_2_Q[15]} {system_top_i/c_counter_binary_2_Q[16]} {system_top_i/c_counter_binary_2_Q[17]} {system_top_i/c_counter_binary_2_Q[18]} {system_top_i/c_counter_binary_2_Q[19]} {system_top_i/c_counter_binary_2_Q[20]} {system_top_i/c_counter_binary_2_Q[21]} {system_top_i/c_counter_binary_2_Q[22]} {system_top_i/c_counter_binary_2_Q[23]} {system_top_i/c_counter_binary_2_Q[24]} {system_top_i/c_counter_binary_2_Q[25]} {system_top_i/c_counter_binary_2_Q[26]} {system_top_i/c_counter_binary_2_Q[27]} {system_top_i/c_counter_binary_2_Q[28]} {system_top_i/c_counter_binary_2_Q[29]} {system_top_i/c_counter_binary_2_Q[30]} {system_top_i/c_counter_binary_2_Q[31]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe5]
+set_property port_width 16 [get_debug_ports u_ila_2/probe5]
+connect_debug_port u_ila_2/probe5 [get_nets [list {tx2_q_data[0]} {tx2_q_data[1]} {tx2_q_data[2]} {tx2_q_data[3]} {tx2_q_data[4]} {tx2_q_data[5]} {tx2_q_data[6]} {tx2_q_data[7]} {tx2_q_data[8]} {tx2_q_data[9]} {tx2_q_data[10]} {tx2_q_data[11]} {tx2_q_data[12]} {tx2_q_data[13]} {tx2_q_data[14]} {tx2_q_data[15]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe6]
+set_property port_width 16 [get_debug_ports u_ila_2/probe6]
+connect_debug_port u_ila_2/probe6 [get_nets [list {rx2_q_data[0]} {rx2_q_data[1]} {rx2_q_data[2]} {rx2_q_data[3]} {rx2_q_data[4]} {rx2_q_data[5]} {rx2_q_data[6]} {rx2_q_data[7]} {rx2_q_data[8]} {rx2_q_data[9]} {rx2_q_data[10]} {rx2_q_data[11]} {rx2_q_data[12]} {rx2_q_data[13]} {rx2_q_data[14]} {rx2_q_data[15]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe7]
+set_property port_width 8 [get_debug_ports u_ila_2/probe7]
+connect_debug_port u_ila_2/probe7 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/TX_FDD_DATA_pos[7]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe8]
+set_property port_width 8 [get_debug_ports u_ila_2/probe8]
+connect_debug_port u_ila_2/probe8 [get_nets [list {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[0]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[1]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[2]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[3]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[4]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[5]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[6]} {cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FDD_DATA_pos[7]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe9]
+set_property port_width 1 [get_debug_ports u_ila_2/probe9]
+connect_debug_port u_ila_2/probe9 [get_nets [list system_top_i/CE_1]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe10]
+set_property port_width 1 [get_debug_ports u_ila_2/probe10]
+connect_debug_port u_ila_2/probe10 [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FRAME_neg]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe11]
+set_property port_width 1 [get_debug_ports u_ila_2/probe11]
+connect_debug_port u_ila_2/probe11 [get_nets [list cx9261a_if_cmos/GEN_SINGLE_PORT.GEN_SINGLE_PORT_TRX2.cx9261a_if_cmos_TRX2/RX_FRAME_pos]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets ui_clk]
@@ -0,0 +1,86 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2022/05/19 13:23:50
+// Design Name: 
+// Module Name: tb
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb(
+
+    );
+    reg aclk,S_AXI_ACLK;
+    
+    reg[31:0] slv_reg0,slv_reg1;
+    
+    
+    initial begin
+    aclk = 0;
+    S_AXI_ACLK = 0;
+        #100 slv_reg0 = 0;
+        #100 slv_reg1 = 8192;
+        #100 slv_reg0 = 1;
+    end
+    
+    always #2 aclk=~aclk;
+    always #1 S_AXI_ACLK=~S_AXI_ACLK;
+    
+    
+    wire capture_cdc;
+	wire [25:0] length_cdc;
+    
+    xpm_cdc_array_single #(
+      .DEST_SYNC_FF(4),   // DECIMAL; range: 2-10
+      .INIT_SYNC_FF(0),   // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
+      .SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      .SRC_INPUT_REG(1),  // DECIMAL; 0=do not register input, 1=register input
+      .WIDTH(1)           // DECIMAL; range: 1-1024
+   )
+       xpm_cdc_array_single_inst0 (
+      .dest_out(capture_cdc), // WIDTH-bit output: src_in synchronized to the destination clock domain. This
+                           // output is registered.
+
+      .dest_clk(aclk), // 1-bit input: Clock signal for the destination clock domain.
+      .src_clk(S_AXI_ACLK),   // 1-bit input: optional; required when SRC_INPUT_REG = 1
+      .src_in(slv_reg0[0])      // WIDTH-bit input: Input single-bit array to be synchronized to destination clock
+                           // domain. It is assumed that each bit of the array is unrelated to the others. This
+                           // is reflected in the constraints applied to this macro. To transfer a binary value
+                           // losslessly across the two clock domains, use the XPM_CDC_GRAY macro instead.
+
+   );
+   
+   	   xpm_cdc_array_single #(
+      .DEST_SYNC_FF(4),   // DECIMAL; range: 2-10
+      .INIT_SYNC_FF(0),   // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
+      .SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      .SRC_INPUT_REG(1),  // DECIMAL; 0=do not register input, 1=register input
+      .WIDTH(26)           // DECIMAL; range: 1-1024
+   )
+   xpm_cdc_array_single_inst1 (
+      .dest_out(length_cdc), // WIDTH-bit output: src_in synchronized to the destination clock domain. This
+                           // output is registered.
+
+      .dest_clk(aclk), // 1-bit input: Clock signal for the destination clock domain.
+      .src_clk(S_AXI_ACLK),   // 1-bit input: optional; required when SRC_INPUT_REG = 1
+      .src_in(slv_reg1[25:0])      // WIDTH-bit input: Input single-bit array to be synchronized to destination clock
+                           // domain. It is assumed that each bit of the array is unrelated to the others. This
+                           // is reflected in the constraints applied to this macro. To transfer a binary value
+                           // losslessly across the two clock domains, use the XPM_CDC_GRAY macro instead.
+
+   );
+   
+endmodule
@@ -0,0 +1,11 @@
+{
+  "design": {
+    "design_info": {
+      "boundary_crc": "0x0",
+      "name": "bin_rom",
+      "synth_flow_mode": "Hierarchical",
+      "tool_version": "2018.3"
+    },
+    "design_tree": {}
+  }
+}
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Root MajorVersion="0" MinorVersion="36">
+  <CompositeFile CompositeFileTopName="bin_rom" CanBeSetAsTop="false" CanDisplayChildGraph="true">
+    <Description>Composite Fileset</Description>
+    <Generation Name="SYNTHESIS" State="STALE" Timestamp="1700708194"/>
+    <Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1700708194"/>
+    <Generation Name="SIMULATION" State="STALE" Timestamp="1700708194"/>
+    <Generation Name="HW_HANDOFF" State="STALE" Timestamp="1700708194"/>
+    <FileCollection Name="SOURCES" Type="SOURCES"/>
+  </CompositeFile>
+</Root>
@@ -0,0 +1,10 @@
+
+
+OPTION psf_version = 2.1;
+
+BEGIN DRIVER Axis_adc_data_packer
+	OPTION supported_peripherals = (Axis_adc_data_packer);
+	OPTION copyfiles = all;
+	OPTION VERSION = 1.0;
+	OPTION NAME = Axis_adc_data_packer;
+END DRIVER
@@ -0,0 +1,5 @@
+
+
+proc generate {drv_handle} {
+	xdefine_include_file $drv_handle "xparameters.h" "Axis_adc_data_packer" "NUM_INSTANCES" "DEVICE_ID"  "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
+}
@@ -0,0 +1,6 @@
+
+
+/***************************** Include Files *******************************/
+#include "Axis_adc_data_packer.h"
+
+/************************** Function Definitions ***************************/
@@ -0,0 +1,79 @@
+
+#ifndef AXIS_ADC_DATA_PACKER_H
+#define AXIS_ADC_DATA_PACKER_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG0_OFFSET 0
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG1_OFFSET 4
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG2_OFFSET 8
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG3_OFFSET 12
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a AXIS_ADC_DATA_PACKER register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param   BaseAddress is the base address of the AXIS_ADC_DATA_PACKERdevice.
+ * @param   RegOffset is the register offset from the base to write to.
+ * @param   Data is the data written to the register.
+ *
+ * @return  None.
+ *
+ * @note
+ * C-style signature:
+ * 	void AXIS_ADC_DATA_PACKER_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define AXIS_ADC_DATA_PACKER_mWriteReg(BaseAddress, RegOffset, Data) \
+  	Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a AXIS_ADC_DATA_PACKER register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param   BaseAddress is the base address of the AXIS_ADC_DATA_PACKER device.
+ * @param   RegOffset is the register offset from the base to write to.
+ *
+ * @return  Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * 	u32 AXIS_ADC_DATA_PACKER_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define AXIS_ADC_DATA_PACKER_mReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the AXIS_ADC_DATA_PACKER instance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus AXIS_ADC_DATA_PACKER_Reg_SelfTest(void * baseaddr_p);
+
+#endif // AXIS_ADC_DATA_PACKER_H
@@ -0,0 +1,60 @@
+
+/***************************** Include Files *******************************/
+#include "Axis_adc_data_packer.h"
+#include "xparameters.h"
+#include "stdio.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+#define READ_WRITE_MUL_FACTOR 0x10
+
+/************************** Function Definitions ***************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the AXIS_ADC_DATA_PACKERinstance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus AXIS_ADC_DATA_PACKER_Reg_SelfTest(void * baseaddr_p)
+{
+	u32 baseaddr;
+	int write_loop_index;
+	int read_loop_index;
+	int Index;
+
+	baseaddr = (u32) baseaddr_p;
+
+	xil_printf("******************************\n\r");
+	xil_printf("* User Peripheral Self Test\n\r");
+	xil_printf("******************************\n\n\r");
+
+	/*
+	 * Write to user logic slave module register(s) and read back
+	 */
+	xil_printf("User logic slave module test...\n\r");
+
+	for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
+	  AXIS_ADC_DATA_PACKER_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
+	for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
+	  if ( AXIS_ADC_DATA_PACKER_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
+	    xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
+	    return XST_FAILURE;
+	  }
+
+	xil_printf("   - slave register write/read passed\n\n\r");
+
+	return XST_SUCCESS;
+}
@@ -0,0 +1,26 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+	echo "Compiling Axis_adc_data_packer..."
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+	make clean
+
+include:
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}
@@ -0,0 +1,197 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: labnet.com:user:Axis_adc_data_packer:1.0
+// IP Revision: 9
+
+(* X_CORE_INFO = "Axis_adc_data_packer_v1_0,Vivado 2024.1" *)
+(* CHECK_LICENSE_TYPE = "system_top_Axis_adc_data_packer_0_0,Axis_adc_data_packer_v1_0,{}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module system_top_Axis_adc_data_packer_0_0 (
+  aclk,
+  aresetn,
+  axis_tvalid,
+  axis_tlast,
+  axis_ready,
+  axis_tdata,
+  m_axis_tvalid,
+  m_axis_tlast,
+  m_axis_ready,
+  m_axis_tdata,
+  s00_axi_awaddr,
+  s00_axi_awprot,
+  s00_axi_awvalid,
+  s00_axi_awready,
+  s00_axi_wdata,
+  s00_axi_wstrb,
+  s00_axi_wvalid,
+  s00_axi_wready,
+  s00_axi_bresp,
+  s00_axi_bvalid,
+  s00_axi_bready,
+  s00_axi_araddr,
+  s00_axi_arprot,
+  s00_axi_arvalid,
+  s00_axi_arready,
+  s00_axi_rdata,
+  s00_axi_rresp,
+  s00_axi_rvalid,
+  s00_axi_rready,
+  s00_axi_aclk,
+  s00_axi_aresetn
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF axis:m_axis, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
+input wire aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
+input wire aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TVALID" *)
+input wire axis_tvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TLAST" *)
+input wire axis_tlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TREADY" *)
+output wire axis_ready;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk, LAYERED_METADATA undef, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TDATA" *)
+input wire [63 : 0] axis_tdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TVALID" *)
+output wire m_axis_tvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TLAST" *)
+output wire m_axis_tlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TREADY" *)
+input wire m_axis_ready;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk, LAYERED_METADATA undef, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TDATA" *)
+output wire [63 : 0] m_axis_tdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
+input wire [3 : 0] s00_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
+input wire [2 : 0] s00_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
+input wire s00_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
+output wire s00_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
+input wire [31 : 0] s00_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
+input wire [3 : 0] s00_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
+input wire s00_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
+output wire s00_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
+output wire [1 : 0] s00_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
+output wire s00_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
+input wire s00_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
+input wire [3 : 0] s00_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
+input wire [2 : 0] s00_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
+input wire s00_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
+output wire s00_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
+output wire [31 : 0] s00_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
+output wire [1 : 0] s00_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
+output wire s00_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_syste\
+m7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
+input wire s00_axi_rready;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK" *)
+input wire s00_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST" *)
+input wire s00_axi_aresetn;
+
+  Axis_adc_data_packer_v1_0 #(
+    .C_S00_AXI_DATA_WIDTH(32),  // Width of S_AXI data bus
+    .C_S00_AXI_ADDR_WIDTH(4)  // Width of S_AXI address bus
+  ) inst (
+    .aclk(aclk),
+    .aresetn(aresetn),
+    .axis_tvalid(axis_tvalid),
+    .axis_tlast(axis_tlast),
+    .axis_ready(axis_ready),
+    .axis_tdata(axis_tdata),
+    .m_axis_tvalid(m_axis_tvalid),
+    .m_axis_tlast(m_axis_tlast),
+    .m_axis_ready(m_axis_ready),
+    .m_axis_tdata(m_axis_tdata),
+    .s00_axi_awaddr(s00_axi_awaddr),
+    .s00_axi_awprot(s00_axi_awprot),
+    .s00_axi_awvalid(s00_axi_awvalid),
+    .s00_axi_awready(s00_axi_awready),
+    .s00_axi_wdata(s00_axi_wdata),
+    .s00_axi_wstrb(s00_axi_wstrb),
+    .s00_axi_wvalid(s00_axi_wvalid),
+    .s00_axi_wready(s00_axi_wready),
+    .s00_axi_bresp(s00_axi_bresp),
+    .s00_axi_bvalid(s00_axi_bvalid),
+    .s00_axi_bready(s00_axi_bready),
+    .s00_axi_araddr(s00_axi_araddr),
+    .s00_axi_arprot(s00_axi_arprot),
+    .s00_axi_arvalid(s00_axi_arvalid),
+    .s00_axi_arready(s00_axi_arready),
+    .s00_axi_rdata(s00_axi_rdata),
+    .s00_axi_rresp(s00_axi_rresp),
+    .s00_axi_rvalid(s00_axi_rvalid),
+    .s00_axi_rready(s00_axi_rready),
+    .s00_axi_aclk(s00_axi_aclk),
+    .s00_axi_aresetn(s00_axi_aresetn)
+  );
+endmodule
@@ -0,0 +1,269 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_Axis_adc_data_packer_0_0",
+    "cell_name": "Axis_adc_data_packer_0",
+    "component_reference": "labnet.com:user:Axis_adc_data_packer:1.0",
+    "ip_revision": "9",
+    "gen_directory": ".",
+    "parameters": {
+      "component_parameters": {
+        "C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S00_AXI_BASEADDR": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_S00_AXI_HIGHADDR": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "Component_Name": [ { "value": "system_top_Axis_adc_data_packer_0_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "9" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "." } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "aclk": [ { "direction": "in" } ],
+        "aresetn": [ { "direction": "in" } ],
+        "axis_tvalid": [ { "direction": "in" } ],
+        "axis_tlast": [ { "direction": "in", "driver_value": "0" } ],
+        "axis_ready": [ { "direction": "out" } ],
+        "axis_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
+        "m_axis_tvalid": [ { "direction": "out" } ],
+        "m_axis_tlast": [ { "direction": "out" } ],
+        "m_axis_ready": [ { "direction": "in" } ],
+        "m_axis_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
+        "s00_axi_awaddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
+        "s00_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
+        "s00_axi_awvalid": [ { "direction": "in" } ],
+        "s00_axi_awready": [ { "direction": "out" } ],
+        "s00_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
+        "s00_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
+        "s00_axi_wvalid": [ { "direction": "in" } ],
+        "s00_axi_wready": [ { "direction": "out" } ],
+        "s00_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s00_axi_bvalid": [ { "direction": "out" } ],
+        "s00_axi_bready": [ { "direction": "in" } ],
+        "s00_axi_araddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
+        "s00_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
+        "s00_axi_arvalid": [ { "direction": "in" } ],
+        "s00_axi_arready": [ { "direction": "out" } ],
+        "s00_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "s00_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s00_axi_rvalid": [ { "direction": "out" } ],
+        "s00_axi_rready": [ { "direction": "in" } ],
+        "s00_axi_aclk": [ { "direction": "in" } ],
+        "s00_axi_aresetn": [ { "direction": "in" } ]
+      },
+      "interfaces": {
+        "S00_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "memory_map_ref": "S00_AXI",
+          "parameters": {
+            "WIZ_DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "WIZ_NUM_REG": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "s00_axi_awaddr" } ],
+            "AWPROT": [ { "physical_name": "s00_axi_awprot" } ],
+            "AWVALID": [ { "physical_name": "s00_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "s00_axi_awready" } ],
+            "WDATA": [ { "physical_name": "s00_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "s00_axi_wstrb" } ],
+            "WVALID": [ { "physical_name": "s00_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "s00_axi_wready" } ],
+            "BRESP": [ { "physical_name": "s00_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s00_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "s00_axi_bready" } ],
+            "ARADDR": [ { "physical_name": "s00_axi_araddr" } ],
+            "ARPROT": [ { "physical_name": "s00_axi_arprot" } ],
+            "ARVALID": [ { "physical_name": "s00_axi_arvalid" } ],
+            "ARREADY": [ { "physical_name": "s00_axi_arready" } ],
+            "RDATA": [ { "physical_name": "s00_axi_rdata" } ],
+            "RRESP": [ { "physical_name": "s00_axi_rresp" } ],
+            "RVALID": [ { "physical_name": "s00_axi_rvalid" } ],
+            "RREADY": [ { "physical_name": "s00_axi_rready" } ]
+          }
+        },
+        "S00_AXI_RST": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s00_axi_aresetn" } ]
+          }
+        },
+        "S00_AXI_CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S00_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s00_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s00_axi_aclk" } ]
+          }
+        },
+        "m_axis": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_tdata" } ],
+            "TLAST": [ { "physical_name": "m_axis_tlast" } ],
+            "TVALID": [ { "physical_name": "m_axis_tvalid" } ],
+            "TREADY": [ { "physical_name": "m_axis_ready" } ]
+          }
+        },
+        "aclk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "axis:m_axis", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "aresetn": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "aresetn" } ]
+          }
+        },
+        "axis": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "axis_tdata" } ],
+            "TLAST": [ { "physical_name": "axis_tlast" } ],
+            "TVALID": [ { "physical_name": "axis_tvalid" } ],
+            "TREADY": [ { "physical_name": "axis_ready" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "S00_AXI": {
+          "address_blocks": {
+            "S00_AXI_reg": {
+              "base_address": "0",
+              "range": "4096",
+              "usage": "register",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_S00_AXI_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_S00_AXI_HIGHADDR" } ]
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}
@@ -0,0 +1,10 @@
+
+
+OPTION psf_version = 2.1;
+
+BEGIN DRIVER Axis_adc_data_packer
+	OPTION supported_peripherals = (Axis_adc_data_packer);
+	OPTION copyfiles = all;
+	OPTION VERSION = 1.0;
+	OPTION NAME = Axis_adc_data_packer;
+END DRIVER
@@ -0,0 +1,5 @@
+
+
+proc generate {drv_handle} {
+	xdefine_include_file $drv_handle "xparameters.h" "Axis_adc_data_packer" "NUM_INSTANCES" "DEVICE_ID"  "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
+}
@@ -0,0 +1,6 @@
+
+
+/***************************** Include Files *******************************/
+#include "Axis_adc_data_packer.h"
+
+/************************** Function Definitions ***************************/
@@ -0,0 +1,79 @@
+
+#ifndef AXIS_ADC_DATA_PACKER_H
+#define AXIS_ADC_DATA_PACKER_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG0_OFFSET 0
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG1_OFFSET 4
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG2_OFFSET 8
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG3_OFFSET 12
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a AXIS_ADC_DATA_PACKER register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param   BaseAddress is the base address of the AXIS_ADC_DATA_PACKERdevice.
+ * @param   RegOffset is the register offset from the base to write to.
+ * @param   Data is the data written to the register.
+ *
+ * @return  None.
+ *
+ * @note
+ * C-style signature:
+ * 	void AXIS_ADC_DATA_PACKER_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define AXIS_ADC_DATA_PACKER_mWriteReg(BaseAddress, RegOffset, Data) \
+  	Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a AXIS_ADC_DATA_PACKER register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param   BaseAddress is the base address of the AXIS_ADC_DATA_PACKER device.
+ * @param   RegOffset is the register offset from the base to write to.
+ *
+ * @return  Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * 	u32 AXIS_ADC_DATA_PACKER_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define AXIS_ADC_DATA_PACKER_mReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the AXIS_ADC_DATA_PACKER instance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus AXIS_ADC_DATA_PACKER_Reg_SelfTest(void * baseaddr_p);
+
+#endif // AXIS_ADC_DATA_PACKER_H
@@ -0,0 +1,60 @@
+
+/***************************** Include Files *******************************/
+#include "Axis_adc_data_packer.h"
+#include "xparameters.h"
+#include "stdio.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+#define READ_WRITE_MUL_FACTOR 0x10
+
+/************************** Function Definitions ***************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the AXIS_ADC_DATA_PACKERinstance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus AXIS_ADC_DATA_PACKER_Reg_SelfTest(void * baseaddr_p)
+{
+	u32 baseaddr;
+	int write_loop_index;
+	int read_loop_index;
+	int Index;
+
+	baseaddr = (u32) baseaddr_p;
+
+	xil_printf("******************************\n\r");
+	xil_printf("* User Peripheral Self Test\n\r");
+	xil_printf("******************************\n\n\r");
+
+	/*
+	 * Write to user logic slave module register(s) and read back
+	 */
+	xil_printf("User logic slave module test...\n\r");
+
+	for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
+	  AXIS_ADC_DATA_PACKER_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
+	for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
+	  if ( AXIS_ADC_DATA_PACKER_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
+	    xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
+	    return XST_FAILURE;
+	  }
+
+	xil_printf("   - slave register write/read passed\n\n\r");
+
+	return XST_SUCCESS;
+}
@@ -0,0 +1,26 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+	echo "Compiling Axis_adc_data_packer..."
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+	make clean
+
+include:
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}
@@ -0,0 +1,197 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: labnet.com:user:Axis_adc_data_packer:1.0
+// IP Revision: 9
+
+(* X_CORE_INFO = "Axis_adc_data_packer_v1_0,Vivado 2024.1" *)
+(* CHECK_LICENSE_TYPE = "system_top_Axis_adc_data_packer_1_0,Axis_adc_data_packer_v1_0,{}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module system_top_Axis_adc_data_packer_1_0 (
+  aclk,
+  aresetn,
+  axis_tvalid,
+  axis_tlast,
+  axis_ready,
+  axis_tdata,
+  m_axis_tvalid,
+  m_axis_tlast,
+  m_axis_ready,
+  m_axis_tdata,
+  s00_axi_awaddr,
+  s00_axi_awprot,
+  s00_axi_awvalid,
+  s00_axi_awready,
+  s00_axi_wdata,
+  s00_axi_wstrb,
+  s00_axi_wvalid,
+  s00_axi_wready,
+  s00_axi_bresp,
+  s00_axi_bvalid,
+  s00_axi_bready,
+  s00_axi_araddr,
+  s00_axi_arprot,
+  s00_axi_arvalid,
+  s00_axi_arready,
+  s00_axi_rdata,
+  s00_axi_rresp,
+  s00_axi_rvalid,
+  s00_axi_rready,
+  s00_axi_aclk,
+  s00_axi_aresetn
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF axis:m_axis, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_1, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
+input wire aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
+input wire aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TVALID" *)
+input wire axis_tvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TLAST" *)
+input wire axis_tlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TREADY" *)
+output wire axis_ready;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_1, LAYERED_METADATA undef, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TDATA" *)
+input wire [63 : 0] axis_tdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TVALID" *)
+output wire m_axis_tvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TLAST" *)
+output wire m_axis_tlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TREADY" *)
+input wire m_axis_ready;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_1, LAYERED_METADATA undef, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TDATA" *)
+output wire [63 : 0] m_axis_tdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
+input wire [3 : 0] s00_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
+input wire [2 : 0] s00_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
+input wire s00_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
+output wire s00_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
+input wire [31 : 0] s00_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
+input wire [3 : 0] s00_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
+input wire s00_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
+output wire s00_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
+output wire [1 : 0] s00_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
+output wire s00_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
+input wire s00_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
+input wire [3 : 0] s00_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
+input wire [2 : 0] s00_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
+input wire s00_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
+output wire s00_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
+output wire [31 : 0] s00_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
+output wire [1 : 0] s00_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
+output wire s00_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_syste\
+m7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
+input wire s00_axi_rready;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK" *)
+input wire s00_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST" *)
+input wire s00_axi_aresetn;
+
+  Axis_adc_data_packer_v1_0 #(
+    .C_S00_AXI_DATA_WIDTH(32),  // Width of S_AXI data bus
+    .C_S00_AXI_ADDR_WIDTH(4)  // Width of S_AXI address bus
+  ) inst (
+    .aclk(aclk),
+    .aresetn(aresetn),
+    .axis_tvalid(axis_tvalid),
+    .axis_tlast(axis_tlast),
+    .axis_ready(axis_ready),
+    .axis_tdata(axis_tdata),
+    .m_axis_tvalid(m_axis_tvalid),
+    .m_axis_tlast(m_axis_tlast),
+    .m_axis_ready(m_axis_ready),
+    .m_axis_tdata(m_axis_tdata),
+    .s00_axi_awaddr(s00_axi_awaddr),
+    .s00_axi_awprot(s00_axi_awprot),
+    .s00_axi_awvalid(s00_axi_awvalid),
+    .s00_axi_awready(s00_axi_awready),
+    .s00_axi_wdata(s00_axi_wdata),
+    .s00_axi_wstrb(s00_axi_wstrb),
+    .s00_axi_wvalid(s00_axi_wvalid),
+    .s00_axi_wready(s00_axi_wready),
+    .s00_axi_bresp(s00_axi_bresp),
+    .s00_axi_bvalid(s00_axi_bvalid),
+    .s00_axi_bready(s00_axi_bready),
+    .s00_axi_araddr(s00_axi_araddr),
+    .s00_axi_arprot(s00_axi_arprot),
+    .s00_axi_arvalid(s00_axi_arvalid),
+    .s00_axi_arready(s00_axi_arready),
+    .s00_axi_rdata(s00_axi_rdata),
+    .s00_axi_rresp(s00_axi_rresp),
+    .s00_axi_rvalid(s00_axi_rvalid),
+    .s00_axi_rready(s00_axi_rready),
+    .s00_axi_aclk(s00_axi_aclk),
+    .s00_axi_aresetn(s00_axi_aresetn)
+  );
+endmodule
@@ -0,0 +1,269 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_Axis_adc_data_packer_1_0",
+    "cell_name": "Axis_adc_data_packer_1",
+    "component_reference": "labnet.com:user:Axis_adc_data_packer:1.0",
+    "ip_revision": "9",
+    "gen_directory": ".",
+    "parameters": {
+      "component_parameters": {
+        "C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S00_AXI_BASEADDR": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_S00_AXI_HIGHADDR": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "Component_Name": [ { "value": "system_top_Axis_adc_data_packer_1_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "9" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "." } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "aclk": [ { "direction": "in" } ],
+        "aresetn": [ { "direction": "in" } ],
+        "axis_tvalid": [ { "direction": "in" } ],
+        "axis_tlast": [ { "direction": "in", "driver_value": "0" } ],
+        "axis_ready": [ { "direction": "out" } ],
+        "axis_tdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
+        "m_axis_tvalid": [ { "direction": "out" } ],
+        "m_axis_tlast": [ { "direction": "out" } ],
+        "m_axis_ready": [ { "direction": "in" } ],
+        "m_axis_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
+        "s00_axi_awaddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
+        "s00_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
+        "s00_axi_awvalid": [ { "direction": "in" } ],
+        "s00_axi_awready": [ { "direction": "out" } ],
+        "s00_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
+        "s00_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
+        "s00_axi_wvalid": [ { "direction": "in" } ],
+        "s00_axi_wready": [ { "direction": "out" } ],
+        "s00_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s00_axi_bvalid": [ { "direction": "out" } ],
+        "s00_axi_bready": [ { "direction": "in" } ],
+        "s00_axi_araddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
+        "s00_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
+        "s00_axi_arvalid": [ { "direction": "in" } ],
+        "s00_axi_arready": [ { "direction": "out" } ],
+        "s00_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "s00_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s00_axi_rvalid": [ { "direction": "out" } ],
+        "s00_axi_rready": [ { "direction": "in" } ],
+        "s00_axi_aclk": [ { "direction": "in" } ],
+        "s00_axi_aresetn": [ { "direction": "in" } ]
+      },
+      "interfaces": {
+        "S00_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "memory_map_ref": "S00_AXI",
+          "parameters": {
+            "WIZ_DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "WIZ_NUM_REG": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "s00_axi_awaddr" } ],
+            "AWPROT": [ { "physical_name": "s00_axi_awprot" } ],
+            "AWVALID": [ { "physical_name": "s00_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "s00_axi_awready" } ],
+            "WDATA": [ { "physical_name": "s00_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "s00_axi_wstrb" } ],
+            "WVALID": [ { "physical_name": "s00_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "s00_axi_wready" } ],
+            "BRESP": [ { "physical_name": "s00_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s00_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "s00_axi_bready" } ],
+            "ARADDR": [ { "physical_name": "s00_axi_araddr" } ],
+            "ARPROT": [ { "physical_name": "s00_axi_arprot" } ],
+            "ARVALID": [ { "physical_name": "s00_axi_arvalid" } ],
+            "ARREADY": [ { "physical_name": "s00_axi_arready" } ],
+            "RDATA": [ { "physical_name": "s00_axi_rdata" } ],
+            "RRESP": [ { "physical_name": "s00_axi_rresp" } ],
+            "RVALID": [ { "physical_name": "s00_axi_rvalid" } ],
+            "RREADY": [ { "physical_name": "s00_axi_rready" } ]
+          }
+        },
+        "S00_AXI_RST": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s00_axi_aresetn" } ]
+          }
+        },
+        "S00_AXI_CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S00_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s00_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s00_axi_aclk" } ]
+          }
+        },
+        "m_axis": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk_1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_tdata" } ],
+            "TLAST": [ { "physical_name": "m_axis_tlast" } ],
+            "TVALID": [ { "physical_name": "m_axis_tvalid" } ],
+            "TREADY": [ { "physical_name": "m_axis_ready" } ]
+          }
+        },
+        "aclk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "axis:m_axis", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk_1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "aresetn": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "aresetn" } ]
+          }
+        },
+        "axis": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk_1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "axis_tdata" } ],
+            "TLAST": [ { "physical_name": "axis_tlast" } ],
+            "TVALID": [ { "physical_name": "axis_tvalid" } ],
+            "TREADY": [ { "physical_name": "axis_ready" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "S00_AXI": {
+          "address_blocks": {
+            "S00_AXI_reg": {
+              "base_address": "0",
+              "range": "4096",
+              "usage": "register",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_S00_AXI_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_S00_AXI_HIGHADDR" } ]
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}
@@ -0,0 +1,10 @@
+
+
+OPTION psf_version = 2.1;
+
+BEGIN DRIVER Axis_adc_data_packer
+	OPTION supported_peripherals = (Axis_adc_data_packer);
+	OPTION copyfiles = all;
+	OPTION VERSION = 1.0;
+	OPTION NAME = Axis_adc_data_packer;
+END DRIVER
@@ -0,0 +1,5 @@
+
+
+proc generate {drv_handle} {
+	xdefine_include_file $drv_handle "xparameters.h" "Axis_adc_data_packer" "NUM_INSTANCES" "DEVICE_ID"  "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
+}
@@ -0,0 +1,6 @@
+
+
+/***************************** Include Files *******************************/
+#include "Axis_adc_data_packer.h"
+
+/************************** Function Definitions ***************************/
@@ -0,0 +1,79 @@
+
+#ifndef AXIS_ADC_DATA_PACKER_H
+#define AXIS_ADC_DATA_PACKER_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG0_OFFSET 0
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG1_OFFSET 4
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG2_OFFSET 8
+#define AXIS_ADC_DATA_PACKER_S00_AXI_SLV_REG3_OFFSET 12
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a AXIS_ADC_DATA_PACKER register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param   BaseAddress is the base address of the AXIS_ADC_DATA_PACKERdevice.
+ * @param   RegOffset is the register offset from the base to write to.
+ * @param   Data is the data written to the register.
+ *
+ * @return  None.
+ *
+ * @note
+ * C-style signature:
+ * 	void AXIS_ADC_DATA_PACKER_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define AXIS_ADC_DATA_PACKER_mWriteReg(BaseAddress, RegOffset, Data) \
+  	Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a AXIS_ADC_DATA_PACKER register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param   BaseAddress is the base address of the AXIS_ADC_DATA_PACKER device.
+ * @param   RegOffset is the register offset from the base to write to.
+ *
+ * @return  Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * 	u32 AXIS_ADC_DATA_PACKER_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define AXIS_ADC_DATA_PACKER_mReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the AXIS_ADC_DATA_PACKER instance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus AXIS_ADC_DATA_PACKER_Reg_SelfTest(void * baseaddr_p);
+
+#endif // AXIS_ADC_DATA_PACKER_H
@@ -0,0 +1,60 @@
+
+/***************************** Include Files *******************************/
+#include "Axis_adc_data_packer.h"
+#include "xparameters.h"
+#include "stdio.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+#define READ_WRITE_MUL_FACTOR 0x10
+
+/************************** Function Definitions ***************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the AXIS_ADC_DATA_PACKERinstance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus AXIS_ADC_DATA_PACKER_Reg_SelfTest(void * baseaddr_p)
+{
+	u32 baseaddr;
+	int write_loop_index;
+	int read_loop_index;
+	int Index;
+
+	baseaddr = (u32) baseaddr_p;
+
+	xil_printf("******************************\n\r");
+	xil_printf("* User Peripheral Self Test\n\r");
+	xil_printf("******************************\n\n\r");
+
+	/*
+	 * Write to user logic slave module register(s) and read back
+	 */
+	xil_printf("User logic slave module test...\n\r");
+
+	for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
+	  AXIS_ADC_DATA_PACKER_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
+	for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
+	  if ( AXIS_ADC_DATA_PACKER_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
+	    xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
+	    return XST_FAILURE;
+	  }
+
+	xil_printf("   - slave register write/read passed\n\n\r");
+
+	return XST_SUCCESS;
+}
@@ -0,0 +1,26 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+	echo "Compiling Axis_adc_data_packer..."
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+	make clean
+
+include:
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}
@@ -0,0 +1,197 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: labnet.com:user:Axis_adc_data_packer:1.0
+// IP Revision: 9
+
+(* X_CORE_INFO = "Axis_adc_data_packer_v1_0,Vivado 2024.1" *)
+(* CHECK_LICENSE_TYPE = "system_top_Axis_adc_data_packer_2_0,Axis_adc_data_packer_v1_0,{}" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module system_top_Axis_adc_data_packer_2_0 (
+  aclk,
+  aresetn,
+  axis_tvalid,
+  axis_tlast,
+  axis_ready,
+  axis_tdata,
+  m_axis_tvalid,
+  m_axis_tlast,
+  m_axis_ready,
+  m_axis_tdata,
+  s00_axi_awaddr,
+  s00_axi_awprot,
+  s00_axi_awvalid,
+  s00_axi_awready,
+  s00_axi_wdata,
+  s00_axi_wstrb,
+  s00_axi_wvalid,
+  s00_axi_wready,
+  s00_axi_bresp,
+  s00_axi_bvalid,
+  s00_axi_bready,
+  s00_axi_araddr,
+  s00_axi_arprot,
+  s00_axi_arvalid,
+  s00_axi_arready,
+  s00_axi_rdata,
+  s00_axi_rresp,
+  s00_axi_rvalid,
+  s00_axi_rready,
+  s00_axi_aclk,
+  s00_axi_aresetn
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF axis:m_axis, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_2, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
+input wire aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
+input wire aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TVALID" *)
+input wire axis_tvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TLAST" *)
+input wire axis_tlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TREADY" *)
+output wire axis_ready;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_2, LAYERED_METADATA undef, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TDATA" *)
+input wire [63 : 0] axis_tdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TVALID" *)
+output wire m_axis_tvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TLAST" *)
+output wire m_axis_tlast;
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TREADY" *)
+input wire m_axis_ready;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_2, LAYERED_METADATA undef, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TDATA" *)
+output wire [63 : 0] m_axis_tdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
+input wire [3 : 0] s00_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
+input wire [2 : 0] s00_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
+input wire s00_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
+output wire s00_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
+input wire [31 : 0] s00_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
+input wire [3 : 0] s00_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
+input wire s00_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
+output wire s00_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
+output wire [1 : 0] s00_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
+output wire s00_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
+input wire s00_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
+input wire [3 : 0] s00_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
+input wire [2 : 0] s00_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
+input wire s00_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
+output wire s00_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
+output wire [31 : 0] s00_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
+output wire [1 : 0] s00_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
+output wire s00_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_syste\
+m7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
+input wire s00_axi_rready;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK" *)
+input wire s00_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST" *)
+input wire s00_axi_aresetn;
+
+  Axis_adc_data_packer_v1_0 #(
+    .C_S00_AXI_DATA_WIDTH(32),  // Width of S_AXI data bus
+    .C_S00_AXI_ADDR_WIDTH(4)  // Width of S_AXI address bus
+  ) inst (
+    .aclk(aclk),
+    .aresetn(aresetn),
+    .axis_tvalid(axis_tvalid),
+    .axis_tlast(axis_tlast),
+    .axis_ready(axis_ready),
+    .axis_tdata(axis_tdata),
+    .m_axis_tvalid(m_axis_tvalid),
+    .m_axis_tlast(m_axis_tlast),
+    .m_axis_ready(m_axis_ready),
+    .m_axis_tdata(m_axis_tdata),
+    .s00_axi_awaddr(s00_axi_awaddr),
+    .s00_axi_awprot(s00_axi_awprot),
+    .s00_axi_awvalid(s00_axi_awvalid),
+    .s00_axi_awready(s00_axi_awready),
+    .s00_axi_wdata(s00_axi_wdata),
+    .s00_axi_wstrb(s00_axi_wstrb),
+    .s00_axi_wvalid(s00_axi_wvalid),
+    .s00_axi_wready(s00_axi_wready),
+    .s00_axi_bresp(s00_axi_bresp),
+    .s00_axi_bvalid(s00_axi_bvalid),
+    .s00_axi_bready(s00_axi_bready),
+    .s00_axi_araddr(s00_axi_araddr),
+    .s00_axi_arprot(s00_axi_arprot),
+    .s00_axi_arvalid(s00_axi_arvalid),
+    .s00_axi_arready(s00_axi_arready),
+    .s00_axi_rdata(s00_axi_rdata),
+    .s00_axi_rresp(s00_axi_rresp),
+    .s00_axi_rvalid(s00_axi_rvalid),
+    .s00_axi_rready(s00_axi_rready),
+    .s00_axi_aclk(s00_axi_aclk),
+    .s00_axi_aresetn(s00_axi_aresetn)
+  );
+endmodule
@@ -0,0 +1,269 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_Axis_adc_data_packer_2_0",
+    "cell_name": "Axis_adc_data_packer_2",
+    "component_reference": "labnet.com:user:Axis_adc_data_packer:1.0",
+    "ip_revision": "9",
+    "gen_directory": ".",
+    "parameters": {
+      "component_parameters": {
+        "C_S00_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S00_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S00_AXI_BASEADDR": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_S00_AXI_HIGHADDR": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "Component_Name": [ { "value": "system_top_Axis_adc_data_packer_2_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
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+            "ARREADY": [ { "physical_name": "s00_axi_arready" } ],
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+            "RREADY": [ { "physical_name": "s00_axi_rready" } ]
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+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s00_axi_aclk" } ]
+          }
+        },
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+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
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+            "CLK_DOMAIN": [ { "value": "system_top_data_clk_2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
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+            "TLAST": [ { "physical_name": "m_axis_tlast" } ],
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+            "TREADY": [ { "physical_name": "m_axis_ready" } ]
+          }
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+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
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+            "CLK_DOMAIN": [ { "value": "system_top_data_clk_2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
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+          },
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+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
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+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
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+            "PHASE": [ { "value": "0.000", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_data_clk_2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "axis_tdata" } ],
+            "TLAST": [ { "physical_name": "axis_tlast" } ],
+            "TVALID": [ { "physical_name": "axis_tvalid" } ],
+            "TREADY": [ { "physical_name": "axis_ready" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "S00_AXI": {
+          "address_blocks": {
+            "S00_AXI_reg": {
+              "base_address": "0",
+              "range": "4096",
+              "usage": "register",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_S00_AXI_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_S00_AXI_HIGHADDR" } ]
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}
@@ -0,0 +1,167 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: cxkj.com:user:axi4_lite_spi:1.0
+// IP Revision: 2
+
+(* X_CORE_INFO = "axi4_lite_spi,Vivado 2024.1" *)
+(* CHECK_LICENSE_TYPE = "system_top_axi4_lite_spi_0_0,axi4_lite_spi,{}" *)
+(* IP_DEFINITION_SOURCE = "package_project" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module system_top_axi4_lite_spi_0_0 (
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_awaddr,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  s_axi_araddr,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rvalid,
+  s_axi_rready,
+  sclk_o,
+  ssn_o,
+  miso_i,
+  mosi_o,
+  sdio
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK" *)
+input wire s_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST" *)
+input wire s_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *)
+input wire [31 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *)
+input wire [31 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *)
+input wire [3 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *)
+input wire [31 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *)
+output wire [31 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS \
+1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *)
+input wire s_axi_rready;
+output wire sclk_o;
+output wire ssn_o;
+input wire miso_i;
+output wire mosi_o;
+inout wire sdio;
+
+  axi4_lite_spi #(
+    .C_S_AXI_ADDR_WIDTH(32),
+    .C_S_AXI_DATA_WIDTH(32),
+    .REGS_SIZE(24),
+    .SPI_CONFIG(7'B1011101),
+    .BAUD_RATE(16'H0002),
+    .REG_WIDTH(8),
+    .CHIP_ADDR_WIDTH(12),
+    .FOUR_WIRE_SPI("false")
+  ) inst (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .sclk_o(sclk_o),
+    .ssn_o(ssn_o),
+    .miso_i(miso_i),
+    .mosi_o(mosi_o),
+    .sdio(sdio)
+  );
+endmodule
@@ -0,0 +1,184 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_axi4_lite_spi_0_0",
+    "cell_name": "axi4_lite_spi_0",
+    "component_reference": "cxkj.com:user:axi4_lite_spi:1.0",
+    "ip_revision": "2",
+    "gen_directory": ".",
+    "parameters": {
+      "component_parameters": {
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "REGS_SIZE": [ { "value": "24", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SPI_CONFIG": [ { "value": "\"1011101\"", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "BAUD_RATE": [ { "value": "0x0002", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "REG_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CHIP_ADDR_WIDTH": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "FOUR_WIRE_SPI": [ { "value": "false", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_top_axi4_lite_spi_0_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "REGS_SIZE": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SPI_CONFIG": [ { "value": "\"1011101\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "BAUD_RATE": [ { "value": "0x0002", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "REG_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "CHIP_ADDR_WIDTH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "FOUR_WIRE_SPI": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "2" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "." } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "s_axi_aclk": [ { "direction": "in" } ],
+        "s_axi_aresetn": [ { "direction": "in" } ],
+        "s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_awready": [ { "direction": "out" } ],
+        "s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
+        "s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_wready": [ { "direction": "out" } ],
+        "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_bvalid": [ { "direction": "out" } ],
+        "s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_arready": [ { "direction": "out" } ],
+        "s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_rvalid": [ { "direction": "out" } ],
+        "s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
+        "sclk_o": [ { "direction": "out" } ],
+        "ssn_o": [ { "direction": "out" } ],
+        "miso_i": [ { "direction": "in" } ],
+        "mosi_o": [ { "direction": "out" } ],
+        "sdio": [ { "direction": "inout" } ]
+      },
+      "interfaces": {
+        "s_axi": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "memory_map_ref": "s_axi",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready" } ],
+            "ARADDR": [ { "physical_name": "s_axi_araddr" } ],
+            "ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
+            "ARREADY": [ { "physical_name": "s_axi_arready" } ],
+            "RDATA": [ { "physical_name": "s_axi_rdata" } ],
+            "RRESP": [ { "physical_name": "s_axi_rresp" } ],
+            "RVALID": [ { "physical_name": "s_axi_rvalid" } ],
+            "RREADY": [ { "physical_name": "s_axi_rready" } ]
+          }
+        },
+        "s_axi_aresetn": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s_axi_aresetn" } ]
+          }
+        },
+        "s_axi_aclk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_axi_aclk" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "s_axi": {
+          "address_blocks": {
+            "reg0": {
+              "base_address": "0",
+              "range": "4294967296",
+              "usage": "register"
+            }
+          }
+        }
+      }
+    }
+  }
+}
@@ -0,0 +1,167 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: cxkj.com:user:axi4_lite_spi:1.0
+// IP Revision: 2
+
+(* X_CORE_INFO = "axi4_lite_spi,Vivado 2024.1" *)
+(* CHECK_LICENSE_TYPE = "system_top_axi4_lite_spi_0_1,axi4_lite_spi,{}" *)
+(* IP_DEFINITION_SOURCE = "package_project" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module system_top_axi4_lite_spi_0_1 (
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_awaddr,
+  s_axi_awvalid,
+  s_axi_awready,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wvalid,
+  s_axi_wready,
+  s_axi_bresp,
+  s_axi_bvalid,
+  s_axi_bready,
+  s_axi_araddr,
+  s_axi_arvalid,
+  s_axi_arready,
+  s_axi_rdata,
+  s_axi_rresp,
+  s_axi_rvalid,
+  s_axi_rready,
+  sclk_o,
+  ssn_o,
+  miso_i,
+  mosi_o,
+  sdio
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK" *)
+input wire s_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST" *)
+input wire s_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *)
+input wire [31 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *)
+input wire [31 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *)
+input wire [3 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *)
+input wire [31 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *)
+output wire [31 : 0] s_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS \
+1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *)
+input wire s_axi_rready;
+output wire sclk_o;
+output wire ssn_o;
+input wire miso_i;
+output wire mosi_o;
+inout wire sdio;
+
+  axi4_lite_spi #(
+    .C_S_AXI_ADDR_WIDTH(32),
+    .C_S_AXI_DATA_WIDTH(32),
+    .REGS_SIZE(24),
+    .SPI_CONFIG(7'B1011101),
+    .BAUD_RATE(16'H0002),
+    .REG_WIDTH(8),
+    .CHIP_ADDR_WIDTH(13),
+    .FOUR_WIRE_SPI("true")
+  ) inst (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .sclk_o(sclk_o),
+    .ssn_o(ssn_o),
+    .miso_i(miso_i),
+    .mosi_o(mosi_o),
+    .sdio(sdio)
+  );
+endmodule
@@ -0,0 +1,184 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_top_axi4_lite_spi_0_1",
+    "cell_name": "axi4_lite_spi_1",
+    "component_reference": "cxkj.com:user:axi4_lite_spi:1.0",
+    "ip_revision": "2",
+    "gen_directory": ".",
+    "parameters": {
+      "component_parameters": {
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "REGS_SIZE": [ { "value": "24", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SPI_CONFIG": [ { "value": "\"1011101\"", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "BAUD_RATE": [ { "value": "0x0002", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "REG_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CHIP_ADDR_WIDTH": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "FOUR_WIRE_SPI": [ { "value": "true", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_top_axi4_lite_spi_0_1", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "REGS_SIZE": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SPI_CONFIG": [ { "value": "\"1011101\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "BAUD_RATE": [ { "value": "0x0002", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "REG_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "CHIP_ADDR_WIDTH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "FOUR_WIRE_SPI": [ { "value": "true", "resolve_type": "generated", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7z045" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "2" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "." } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "s_axi_aclk": [ { "direction": "in" } ],
+        "s_axi_aresetn": [ { "direction": "in" } ],
+        "s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_awready": [ { "direction": "out" } ],
+        "s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
+        "s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_wready": [ { "direction": "out" } ],
+        "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_bvalid": [ { "direction": "out" } ],
+        "s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_arready": [ { "direction": "out" } ],
+        "s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_rvalid": [ { "direction": "out" } ],
+        "s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
+        "sclk_o": [ { "direction": "out" } ],
+        "ssn_o": [ { "direction": "out" } ],
+        "miso_i": [ { "direction": "in" } ],
+        "mosi_o": [ { "direction": "out" } ],
+        "sdio": [ { "direction": "inout" } ]
+      },
+      "interfaces": {
+        "s_axi": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "memory_map_ref": "s_axi",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready" } ],
+            "ARADDR": [ { "physical_name": "s_axi_araddr" } ],
+            "ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
+            "ARREADY": [ { "physical_name": "s_axi_arready" } ],
+            "RDATA": [ { "physical_name": "s_axi_rdata" } ],
+            "RRESP": [ { "physical_name": "s_axi_rresp" } ],
+            "RVALID": [ { "physical_name": "s_axi_rvalid" } ],
+            "RREADY": [ { "physical_name": "s_axi_rready" } ]
+          }
+        },
+        "s_axi_aresetn": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s_axi_aresetn" } ]
+          }
+        },
+        "s_axi_aclk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "1e+08", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_top_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_axi_aclk" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "s_axi": {
+          "address_blocks": {
+            "reg0": {
+              "base_address": "0",
+              "range": "4294967296",
+              "usage": "register"
+            }
+          }
+        }
+      }
+    }
+  }
+}
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
josh	60e2dd6cb5	add multirate qpsk transmitter, modify frequency hopping procedure	2024-11-02 01:00:01 +08:00
josh	197ee19bef	add cx9261a_demo vitis classic project, some projects need further revision due to bsp version upgrade	2024-11-02 00:57:31 +08:00
josh	ba69738c48	add cx9261_demo vivado project	2024-10-31 19:28:02 +08:00
josh	425331337e	add missing libs	2024-10-31 18:45:37 +08:00
				`@@ -0,0 +1 @@`
				`The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.`