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0269bb9d4d
| Author | SHA1 | Date | |
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 josh
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0269bb9d4d | ||
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josh
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694b74f2e2 | ||
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josh
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b04b8ee4cc | ||
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josh
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decfa6f93e | ||
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josh
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27ff8f2354 |
+7
-8
@@ -1,20 +1,19 @@
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||||
# Xilinx files
|
||||
*.xsa filter=lfs diff=lfs merge=lfs -text
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||||
*.XSA filter=lfs diff=lfs merge=lfs -text
|
||||
*.bit filter=lfs diff=lfs merge=lfs -text
|
||||
*.BIT filter=lfs diff=lfs merge=lfs -text
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||||
*.bin filter=lfs diff=lfs merge=lfs -text
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||||
*.BIN filter=lfs diff=lfs merge=lfs -text
|
||||
*.dcp filter=lfs diff=lfs merge=lfs -text
|
||||
*.DCP filter=lfs diff=lfs merge=lfs -text
|
||||
# data files
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||||
*.csv filter=lfs diff=lfs merge=lfs -text
|
||||
*.CSV filter=lfs diff=lfs merge=lfs -text
|
||||
# board files
|
||||
*.brd filter=lfs diff=lfs merge=lfs -text
|
||||
*.BRD filter=lfs diff=lfs merge=lfs -text
|
||||
*.dsn filter=lfs diff=lfs merge=lfs -text
|
||||
*.DSN filter=lfs diff=lfs merge=lfs -text
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||||
# archive files
|
||||
*.zip filter=lfs diff=lfs merge=lfs -text
|
||||
*.rar filter=lfs diff=lfs merge=lfs -text
|
||||
*.tar filter=lfs diff=lfs merge=lfs -text
|
||||
*.gz filter=lfs diff=lfs merge=lfs -text
|
||||
*.xz filter=lfs diff=lfs merge=lfs -text
|
||||
*.7z filter=lfs diff=lfs merge=lfs -text
|
||||
# others
|
||||
*.pdf filter=lfs diff=lfs merge=lfs -text
|
||||
*.PDF filter=lfs diff=lfs merge=lfs -text
|
||||
|
||||
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@@ -0,0 +1,3 @@
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||||
DEMO_FPAG:适配cx9261a单芯片demo板，fpga开发板适配ZC706和cx7045
|
||||
dual_cp_sync:适配cx9261a双芯片demo板，fpga开发板适配ZC706，处理器硬核开发，同步功能matlab&lwip实现
|
||||
dual_cp_sync_softcore：适配cx9261a双芯片demo板，fpga开发板适配ZC706，microblaze软核开发，同步功能c语言实现
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||||
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||||
CX9261A ver 2.30.0.rar：CX9261A的上位机评估软件压缩包；
|
||||
CX9261A API ver 1.9.0.rar：CX9261A的API函数压缩包；
|
||||
matlab_scriptI.rar：CX9261A的部分功能寄存器脚本matlab程序压缩包；
|
||||
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||||
DEMO_FPAG:适配cx9261a单芯片demo板，fpga开发板适配ZC706和cx7045
|
||||
dual_cp_sync:适配cx9261a双芯片demo板，fpga开发板适配ZC706，处理器硬核开发，同步功能matlab&lwip实现
|
||||
dual_cp_sync_softcore：适配cx9261a双芯片demo板，fpga开发板适配ZC706，microblaze软核开发，同步功能c语言实现
|
||||
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|
||||
CX9261A ver 2.31.0.rar：CX9261A的上位机评估软件压缩包；
|
||||
CX9261A API ver 1.10.0.rar：CX9261A的API函数压缩包；
|
||||
matlab_script.rar：CX9261A的部分功能寄存器脚本matlab程序压缩包；
|
||||
@@ -0,0 +1,26 @@
|
||||
CX9261A技术支持包_20240702:
|
||||
1.添加了双芯片同步fpga工程和双芯片同步MATLAB脚本（适配zc706开发板）；
|
||||
2.增加了《12_CX9261A_*》《13_CX9261A_*》《14_CX9261A_*》文档；
|
||||
3.更新了评估软件 V2.27.0；
|
||||
4.增加了CX9261A API V1.5.0；
|
||||
5.更新了同步MATLAB脚本。
|
||||
CX9261A技术支持包_20240712:
|
||||
1.更新了评估软件 V2.28.1；
|
||||
CX9261A技术支持包_20240716:
|
||||
1.修改了matlab中setpll_hop函数的bug，分频比的小数部分计算由向下取整（floor）改为4舍5入取整（round）；
|
||||
CX9261A技术支持包_20240719:
|
||||
1.修改了04_客用评估软件的评估软件的bug，V2.28.1更新到了V2.28.2，选择tx二分法校准时，并未进行任一tx通道校准行为；
|
||||
CX9261A技术支持包_20240722:
|
||||
1.增加了lvds的sdk工程（适配zc706开发板）；
|
||||
2.增加了评估软件使用说明；
|
||||
CX9261A技术支持包_20240726:
|
||||
1.增加了microblaze软核开发的fpga工程（适配zc706开发板，用于cx9261a双芯片）；
|
||||
2.更新了评估软件CX9261A ver 2.28.3和API驱动函数CX9261A API ver 1.7.0，修复了pll频率码字计算精度问题；
|
||||
3.更新了matlab_script里的setpll，修复了pll频率码字计算精度问题；
|
||||
CX9261A技术支持包_20240823:
|
||||
1.更新了评估软件CX9261A ver 2.30.0和API驱动函数CX9261A API ver 1.9.0，修复了tx多点校准pll索引错误的bug；
|
||||
CX9261A技术支持包_20241025:
|
||||
1.更新了评估软件CX9261A ver 2.31.0和API驱动函数CX9261A API ver 1.10.0，修复了外本振校准和接口IO标准的bug；
|
||||
2.更新了fpga demo工程，添加了相关注释，更新了rom的coe，更新为最新多点校准的coe。
|
||||
3.添加了技术支持文档，跳频使用说明、同步使用说明、demo板使用说明。
|
||||
4.更新了script_to_client,添加了接收数据的fft。
|
||||
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+24
-14
@@ -5,22 +5,32 @@ COMPILER_FLAGS=
|
||||
EXTRA_COMPILER_FLAGS=
|
||||
LIB=libxil.a
|
||||
|
||||
RELEASEDIR=../../../lib
|
||||
INCLUDEDIR=../../../include
|
||||
INCLUDES=-I./. -I${INCLUDEDIR}
|
||||
CC_FLAGS = $(COMPILER_FLAGS)
|
||||
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
|
||||
|
||||
INCLUDEFILES=*.h
|
||||
LIBSOURCES=*.c
|
||||
OUTS = *.o
|
||||
RELEASEDIR=../../../lib/
|
||||
INCLUDEDIR=../../../include/
|
||||
INCLUDES=-I./. -I$(INCLUDEDIR)
|
||||
|
||||
libs:
|
||||
echo "Compiling Axis_adc_data_packer..."
|
||||
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
|
||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
|
||||
make clean
|
||||
SRCFILES:=$(wildcard *.c)
|
||||
|
||||
include:
|
||||
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
|
||||
OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
|
||||
|
||||
libs: $(OBJECTS)
|
||||
|
||||
include $(wildcard $(DEPFILES))
|
||||
|
||||
include $(wildcard ../../../../dep.mk)
|
||||
|
||||
$(RELEASEDIR)%.o: %.c
|
||||
${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $< -o $@
|
||||
|
||||
.PHONY: include
|
||||
include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
|
||||
|
||||
$(INCLUDEDIR)%.h: %.h
|
||||
$(CP) $< $@
|
||||
|
||||
clean:
|
||||
rm -rf ${OUTS}
|
||||
rm -rf ${OBJECTS}
|
||||
rm -rf $(DEPFILES)
|
||||
|
||||
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Load Diff
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Load Diff
@@ -140,4 +140,4 @@ set_property LOC IDELAYCTRL_X0Y2 [get_cells u_mclk_delay/IDELAYCTRL_RX12]
|
||||
set_property LOC IDELAYCTRL_X0Y4 [get_cells u_mclk_delay/IDELAYCTRL_RX3]
|
||||
################################################################################################
|
||||
|
||||
set_clock_groups -asynchronous -group [get_clocks {system_top_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]}] -group [get_clocks RXFB_MCLK_IN] -group [get_clocks RX1_MCLK_IN_N] -group [get_clocks RX2_MCLK_IN_P]
|
||||
set_clock_groups -asynchronous -group [get_clocks clk_fpga_0] -group [get_clocks RXFB_MCLK_IN] -group [get_clocks RX1_MCLK_IN_N] -group [get_clocks RX2_MCLK_IN_P]
|
||||
@@ -8,42 +8,42 @@ set_false_path -from [get_clocks RX2_MCLK_IN_P] -to [get_clocks -of_objects [get
|
||||
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks RX2_MCLK_IN_P]
|
||||
################################################################################################
|
||||
#################################### 2 #CX9261A data ila########################################
|
||||
create_debug_core u_ila_0 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
|
||||
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
|
||||
set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
|
||||
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/clk]
|
||||
connect_debug_port u_ila_0/clk [get_nets [list system_top_i/processing_system7_0/inst/FCLK_CLK0]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
||||
set_property port_width 24 [get_debug_ports u_ila_0/probe0]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list {hop_intr/r_hop_cnt[0]} {hop_intr/r_hop_cnt[1]} {hop_intr/r_hop_cnt[2]} {hop_intr/r_hop_cnt[3]} {hop_intr/r_hop_cnt[4]} {hop_intr/r_hop_cnt[5]} {hop_intr/r_hop_cnt[6]} {hop_intr/r_hop_cnt[7]} {hop_intr/r_hop_cnt[8]} {hop_intr/r_hop_cnt[9]} {hop_intr/r_hop_cnt[10]} {hop_intr/r_hop_cnt[11]} {hop_intr/r_hop_cnt[12]} {hop_intr/r_hop_cnt[13]} {hop_intr/r_hop_cnt[14]} {hop_intr/r_hop_cnt[15]} {hop_intr/r_hop_cnt[16]} {hop_intr/r_hop_cnt[17]} {hop_intr/r_hop_cnt[18]} {hop_intr/r_hop_cnt[19]} {hop_intr/r_hop_cnt[20]} {hop_intr/r_hop_cnt[21]} {hop_intr/r_hop_cnt[22]} {hop_intr/r_hop_cnt[23]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe1]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list hop_intr/hop_flag]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list hop_intr/spi_pose_flag]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe3]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list hop_intr/r_hop_cnt_flag]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list hop_intr/hop_neg_flag]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list hop_intr/hop_signal]]
|
||||
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
||||
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
||||
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
||||
connect_debug_port dbg_hub/clk [get_nets MCLK2]
|
||||
# create_debug_core u_ila_0 ila
|
||||
# set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
||||
# set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
|
||||
# set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
|
||||
# set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
|
||||
# set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
|
||||
# set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
||||
# set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
||||
# set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
||||
# set_property port_width 1 [get_debug_ports u_ila_0/clk]
|
||||
# connect_debug_port u_ila_0/clk [get_nets [list system_top_i/processing_system7_0/inst/FCLK_CLK0]]
|
||||
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
||||
# set_property port_width 24 [get_debug_ports u_ila_0/probe0]
|
||||
# connect_debug_port u_ila_0/probe0 [get_nets [list {hop_intr/r_hop_cnt[0]} {hop_intr/r_hop_cnt[1]} {hop_intr/r_hop_cnt[2]} {hop_intr/r_hop_cnt[3]} {hop_intr/r_hop_cnt[4]} {hop_intr/r_hop_cnt[5]} {hop_intr/r_hop_cnt[6]} {hop_intr/r_hop_cnt[7]} {hop_intr/r_hop_cnt[8]} {hop_intr/r_hop_cnt[9]} {hop_intr/r_hop_cnt[10]} {hop_intr/r_hop_cnt[11]} {hop_intr/r_hop_cnt[12]} {hop_intr/r_hop_cnt[13]} {hop_intr/r_hop_cnt[14]} {hop_intr/r_hop_cnt[15]} {hop_intr/r_hop_cnt[16]} {hop_intr/r_hop_cnt[17]} {hop_intr/r_hop_cnt[18]} {hop_intr/r_hop_cnt[19]} {hop_intr/r_hop_cnt[20]} {hop_intr/r_hop_cnt[21]} {hop_intr/r_hop_cnt[22]} {hop_intr/r_hop_cnt[23]}]]
|
||||
# create_debug_port u_ila_0 probe
|
||||
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
||||
# set_property port_width 1 [get_debug_ports u_ila_0/probe1]
|
||||
# connect_debug_port u_ila_0/probe1 [get_nets [list hop_intr/hop_flag]]
|
||||
# create_debug_port u_ila_0 probe
|
||||
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
||||
# set_property port_width 1 [get_debug_ports u_ila_0/probe2]
|
||||
# connect_debug_port u_ila_0/probe2 [get_nets [list hop_intr/spi_pose_flag]]
|
||||
# create_debug_port u_ila_0 probe
|
||||
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
||||
# set_property port_width 1 [get_debug_ports u_ila_0/probe3]
|
||||
# connect_debug_port u_ila_0/probe3 [get_nets [list hop_intr/r_hop_cnt_flag]]
|
||||
# create_debug_port u_ila_0 probe
|
||||
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||
# set_property port_width 1 [get_debug_ports u_ila_0/probe4]
|
||||
# connect_debug_port u_ila_0/probe4 [get_nets [list hop_intr/hop_neg_flag]]
|
||||
# create_debug_port u_ila_0 probe
|
||||
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||
# set_property port_width 1 [get_debug_ports u_ila_0/probe5]
|
||||
# connect_debug_port u_ila_0/probe5 [get_nets [list hop_intr/hop_signal]]
|
||||
# set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
||||
# set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
||||
# set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
||||
# connect_debug_port dbg_hub/clk [get_nets MCLK2]
|
||||
################################################################################################
|
||||
|
||||
+2
-2
@@ -1,8 +1,8 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
|
||||
//Date : Thu Oct 31 11:29:13 2024
|
||||
//Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
|
||||
//Date : Sun Nov 3 17:49:07 2024
|
||||
//Host : gatsby-dev running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa)
|
||||
//Command : generate_target system_top_wrapper.bd
|
||||
//Design : system_top_wrapper
|
||||
|
||||
+60
-133
@@ -1,5 +1,5 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Thu Oct 31 11:29:40 2024" VIVADOVERSION="2024.1">
|
||||
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sun Nov 3 17:49:19 2024" VIVADOVERSION="2024.1.2">
|
||||
|
||||
<SYSTEMINFO ARCH="zynq" BOARD="xilinx.com:zc706:part0:1.4" DEVICE="7z045" NAME="system_top" PACKAGE="ffg900" SPEEDGRADE="-2"/>
|
||||
|
||||
@@ -81,7 +81,7 @@
|
||||
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_RAS_n"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="IO" NAME="DDR_reset_n" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="processing_system7_0_DDR_DRSTB">
|
||||
<PORT DIR="IO" NAME="DDR_reset_n" SIGIS="rst" SIGNAME="processing_system7_0_DDR_DRSTB">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_DRSTB"/>
|
||||
</CONNECTIONS>
|
||||
@@ -473,7 +473,7 @@
|
||||
<CONNECTION INSTANCE="mig_7series_0" PORT="ddr3_ras_n"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="ddr3_sdram_reset_n" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="mig_7series_0_ddr3_reset_n">
|
||||
<PORT DIR="O" NAME="ddr3_sdram_reset_n" SIGIS="rst" SIGNAME="mig_7series_0_ddr3_reset_n">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="mig_7series_0" PORT="ddr3_reset_n"/>
|
||||
</CONNECTIONS>
|
||||
@@ -511,6 +511,7 @@
|
||||
<PORT DIR="I" NAME="miso_i_0" SIGIS="undef" SIGNAME="External_Ports_miso_i_0">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axi4_lite_spi_1" PORT="miso_i"/>
|
||||
<CONNECTION INSTANCE="system_ila_spi" PORT="probe3"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="mosi_o_0" SIGIS="undef" SIGNAME="axi4_lite_spi_1_mosi_o">
|
||||
@@ -542,7 +543,6 @@
|
||||
<PORT DIR="IO" NAME="sdio_0" SIGIS="undef" SIGNAME="External_Ports_sdio_0">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axi4_lite_spi_0" PORT="sdio"/>
|
||||
<CONNECTION INSTANCE="system_ila_0" PORT="probe2"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="ssn_o_0" SIGIS="undef" SIGNAME="axi4_lite_spi_0_ssn_o">
|
||||
@@ -1747,7 +1747,6 @@
|
||||
<PORT DIR="O" NAME="sclk_o" SIGIS="undef" SIGNAME="axi4_lite_spi_0_sclk_o">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="External_Ports" PORT="sclk_o_0"/>
|
||||
<CONNECTION INSTANCE="system_ila_0" PORT="probe1"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="IO" NAME="sdio" SIGIS="undef" SIGNAME="External_Ports_sdio_0">
|
||||
@@ -1758,7 +1757,6 @@
|
||||
<PORT DIR="O" NAME="ssn_o" SIGIS="undef" SIGNAME="axi4_lite_spi_0_ssn_o">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="External_Ports" PORT="ssn_o_0"/>
|
||||
<CONNECTION INSTANCE="system_ila_0" PORT="probe0"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
</PORTS>
|
||||
@@ -1845,6 +1843,7 @@
|
||||
<PORT DIR="O" NAME="mosi_o" SIGIS="undef" SIGNAME="axi4_lite_spi_1_mosi_o">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="External_Ports" PORT="mosi_o_0"/>
|
||||
<CONNECTION INSTANCE="system_ila_spi" PORT="probe0"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT CLKFREQUENCY="1e+08" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
|
||||
@@ -1945,12 +1944,14 @@
|
||||
<PORT DIR="O" NAME="sclk_o" SIGIS="undef" SIGNAME="axi4_lite_spi_1_sclk_o">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="External_Ports" PORT="sclk_o_1"/>
|
||||
<CONNECTION INSTANCE="system_ila_spi" PORT="probe1"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="IO" NAME="sdio" SIGIS="undef"/>
|
||||
<PORT DIR="O" NAME="ssn_o" SIGIS="undef" SIGNAME="axi4_lite_spi_1_ssn_o">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="External_Ports" PORT="ssn_o_1"/>
|
||||
<CONNECTION INSTANCE="system_ila_spi" PORT="probe2"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
</PORTS>
|
||||
@@ -3283,7 +3284,7 @@
|
||||
</BUSINTERFACE>
|
||||
</BUSINTERFACES>
|
||||
</MODULE>
|
||||
<MODULE COREREVISION="32" FULLNAME="/axi_dma_0" HWVERSION="7.1" INSTANCE="axi_dma_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_dma" VLNV="xilinx.com:ip:axi_dma:7.1">
|
||||
<MODULE COREREVISION="33" FULLNAME="/axi_dma_0" HWVERSION="7.1" INSTANCE="axi_dma_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_dma" VLNV="xilinx.com:ip:axi_dma:7.1">
|
||||
<DOCUMENTS>
|
||||
<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_dma;v=v7_1;d=pg021_axi_dma.pdf"/>
|
||||
</DOCUMENTS>
|
||||
@@ -4497,7 +4498,7 @@
|
||||
<PERIPHERAL INSTANCE="mig_7series_0"/>
|
||||
</PERIPHERALS>
|
||||
</MODULE>
|
||||
<MODULE COREREVISION="32" FULLNAME="/axi_dma_1" HWVERSION="7.1" INSTANCE="axi_dma_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_dma" VLNV="xilinx.com:ip:axi_dma:7.1">
|
||||
<MODULE COREREVISION="33" FULLNAME="/axi_dma_1" HWVERSION="7.1" INSTANCE="axi_dma_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_dma" VLNV="xilinx.com:ip:axi_dma:7.1">
|
||||
<DOCUMENTS>
|
||||
<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_dma;v=v7_1;d=pg021_axi_dma.pdf"/>
|
||||
</DOCUMENTS>
|
||||
@@ -5711,7 +5712,7 @@
|
||||
<PERIPHERAL INSTANCE="mig_7series_0"/>
|
||||
</PERIPHERALS>
|
||||
</MODULE>
|
||||
<MODULE COREREVISION="32" FULLNAME="/axi_dma_2" HWVERSION="7.1" INSTANCE="axi_dma_2" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_dma" VLNV="xilinx.com:ip:axi_dma:7.1">
|
||||
<MODULE COREREVISION="33" FULLNAME="/axi_dma_2" HWVERSION="7.1" INSTANCE="axi_dma_2" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_dma" VLNV="xilinx.com:ip:axi_dma:7.1">
|
||||
<DOCUMENTS>
|
||||
<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_dma;v=v7_1;d=pg021_axi_dma.pdf"/>
|
||||
</DOCUMENTS>
|
||||
@@ -6925,7 +6926,7 @@
|
||||
<PERIPHERAL INSTANCE="mig_7series_0"/>
|
||||
</PERIPHERALS>
|
||||
</MODULE>
|
||||
<MODULE COREREVISION="33" FULLNAME="/axi_gpio_0" HWVERSION="2.0" INSTANCE="axi_gpio_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio" VLNV="xilinx.com:ip:axi_gpio:2.0">
|
||||
<MODULE COREREVISION="34" FULLNAME="/axi_gpio_0" HWVERSION="2.0" INSTANCE="axi_gpio_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio" VLNV="xilinx.com:ip:axi_gpio:2.0">
|
||||
<DOCUMENTS>
|
||||
<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_gpio;v=v2_0;d=pg144-axi-gpio.pdf"/>
|
||||
</DOCUMENTS>
|
||||
@@ -7298,7 +7299,7 @@
|
||||
</BUSINTERFACE>
|
||||
</BUSINTERFACES>
|
||||
</MODULE>
|
||||
<MODULE BD="system_top_axi_smc_0" BDTYPE="SBD" COREREVISION="23" DRIVERMODE="CORE" FULLNAME="/axi_smc" HWVERSION="1.0" INSTANCE="axi_smc" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="smartconnect" SIM_BD="system_top_axi_smc_0" VLNV="xilinx.com:ip:smartconnect:1.0">
|
||||
<MODULE BD="system_top_axi_smc_0" BDTYPE="SBD" COREREVISION="24" DRIVERMODE="CORE" FULLNAME="/axi_smc" HWVERSION="1.0" INSTANCE="axi_smc" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="smartconnect" SIM_BD="system_top_axi_smc_0" VLNV="xilinx.com:ip:smartconnect:1.0">
|
||||
<DOCUMENTS>
|
||||
<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=smartconnect;v=v1_0;d=pg247-smartconnect.pdf"/>
|
||||
</DOCUMENTS>
|
||||
@@ -9433,7 +9434,7 @@
|
||||
</BUSINTERFACE>
|
||||
</BUSINTERFACES>
|
||||
</MODULE>
|
||||
<MODULE BD="system_top_axi_smc1_0" BDTYPE="SBD" COREREVISION="23" DRIVERMODE="CORE" FULLNAME="/axi_smc1" HWVERSION="1.0" INSTANCE="axi_smc1" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="smartconnect" SIM_BD="system_top_axi_smc1_0" VLNV="xilinx.com:ip:smartconnect:1.0">
|
||||
<MODULE BD="system_top_axi_smc1_0" BDTYPE="SBD" COREREVISION="24" DRIVERMODE="CORE" FULLNAME="/axi_smc1" HWVERSION="1.0" INSTANCE="axi_smc1" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="smartconnect" SIM_BD="system_top_axi_smc1_0" VLNV="xilinx.com:ip:smartconnect:1.0">
|
||||
<DOCUMENTS>
|
||||
<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=smartconnect;v=v1_0;d=pg247-smartconnect.pdf"/>
|
||||
</DOCUMENTS>
|
||||
@@ -13900,14 +13901,14 @@
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="External_Ports" PORT="ui_clk"/>
|
||||
<CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP1_ACLK"/>
|
||||
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_aclk"/>
|
||||
<CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_s2mm_aclk"/>
|
||||
<CONNECTION INSTANCE="axi_dma_2" PORT="m_axi_s2mm_aclk"/>
|
||||
<CONNECTION INSTANCE="axi_smc1" PORT="aclk"/>
|
||||
<CONNECTION INSTANCE="fifo_generator_0" PORT="m_aclk"/>
|
||||
<CONNECTION INSTANCE="fifo_generator_1" PORT="m_aclk"/>
|
||||
<CONNECTION INSTANCE="fifo_generator_2" PORT="m_aclk"/>
|
||||
<CONNECTION INSTANCE="proc_sys_reset_0" PORT="slowest_sync_clk"/>
|
||||
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_aclk"/>
|
||||
<CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_s2mm_aclk"/>
|
||||
<CONNECTION INSTANCE="axi_dma_2" PORT="m_axi_s2mm_aclk"/>
|
||||
<CONNECTION INSTANCE="axi_smc1" PORT="aclk"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="ui_clk_sync_rst" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
|
||||
@@ -15108,13 +15109,13 @@
|
||||
<CONNECTION INSTANCE="axi4_lite_spi_1" PORT="s_axi_aclk"/>
|
||||
<CONNECTION INSTANCE="axi_bram_ctrl_0" PORT="s_axi_aclk"/>
|
||||
<CONNECTION INSTANCE="axi_bram_ctrl_1" PORT="s_axi_aclk"/>
|
||||
<CONNECTION INSTANCE="rst_ps7_0_200M" PORT="slowest_sync_clk"/>
|
||||
<CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_aclk"/>
|
||||
<CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_aclk"/>
|
||||
<CONNECTION INSTANCE="axi_dma_2" PORT="s_axi_lite_aclk"/>
|
||||
<CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_aclk"/>
|
||||
<CONNECTION INSTANCE="axi_smc" PORT="aclk"/>
|
||||
<CONNECTION INSTANCE="rst_ps7_0_200M" PORT="slowest_sync_clk"/>
|
||||
<CONNECTION INSTANCE="system_ila_0" PORT="clk"/>
|
||||
<CONNECTION INSTANCE="system_ila_spi" PORT="clk"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="FCLK_RESET0_N" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="processing_system7_0_FCLK_RESET0_N">
|
||||
@@ -15929,7 +15930,6 @@
|
||||
<CONNECTION INSTANCE="axi_dma_2" PORT="axi_resetn"/>
|
||||
<CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_aresetn"/>
|
||||
<CONNECTION INSTANCE="axi_smc" PORT="aresetn"/>
|
||||
<CONNECTION INSTANCE="system_ila_0" PORT="resetn"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" LEFT="0" NAME="peripheral_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
|
||||
@@ -15941,7 +15941,7 @@
|
||||
</PORTS>
|
||||
<BUSINTERFACES/>
|
||||
</MODULE>
|
||||
<MODULE BD="system_top_system_ila_0_2" BDTYPE="SBD" COREREVISION="17" DRIVERMODE="MIXED" FULLNAME="/system_ila_0" HWVERSION="1.1" INSTANCE="system_ila_0" IPTYPE="MONITOR" IS_ENABLE="1" MODCLASS="MONITOR" MODTYPE="system_ila" SIM_BD="system_top_system_ila_0_2" VLNV="xilinx.com:ip:system_ila:1.1">
|
||||
<MODULE BD="system_top_system_ila_0_2" BDTYPE="SBD" COREREVISION="18" DRIVERMODE="MIXED" FULLNAME="/system_ila_spi" HWVERSION="1.1" INSTANCE="system_ila_spi" IPTYPE="MONITOR" IS_ENABLE="1" MODCLASS="MONITOR" MODTYPE="system_ila" SIM_BD="system_top_system_ila_0_2" VLNV="xilinx.com:ip:system_ila:1.1">
|
||||
<DOCUMENTS>
|
||||
<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=system_ila;v=v1_1;d=pg261-system-ila.pdf"/>
|
||||
</DOCUMENTS>
|
||||
@@ -15957,8 +15957,8 @@
|
||||
<PARAMETER NAME="C_EN_TIME_TAG" VALUE="0"/>
|
||||
<PARAMETER NAME="C_INPUT_PIPE_STAGES" VALUE="0"/>
|
||||
<PARAMETER NAME="C_MON_TYPE" VALUE="MIX"/>
|
||||
<PARAMETER NAME="C_NUM_MONITOR_SLOTS" VALUE="2"/>
|
||||
<PARAMETER NAME="C_NUM_OF_PROBES" VALUE="3"/>
|
||||
<PARAMETER NAME="C_NUM_MONITOR_SLOTS" VALUE="1"/>
|
||||
<PARAMETER NAME="C_NUM_OF_PROBES" VALUE="4"/>
|
||||
<PARAMETER NAME="C_PROBE0_MU_CNT" VALUE="1"/>
|
||||
<PARAMETER NAME="C_PROBE0_TYPE" VALUE="0"/>
|
||||
<PARAMETER NAME="C_PROBE0_WIDTH" VALUE="1"/>
|
||||
@@ -19074,7 +19074,7 @@
|
||||
<PARAMETER NAME="C_SLOT_0_AXI_W_SEL" VALUE="1"/>
|
||||
<PARAMETER NAME="C_SLOT_0_AXI_W_SEL_DATA" VALUE="1"/>
|
||||
<PARAMETER NAME="C_SLOT_0_AXI_W_SEL_TRIG" VALUE="1"/>
|
||||
<PARAMETER NAME="C_SLOT_0_INTF_TYPE" VALUE="xilinx.com:interface:aximm_rtl:1.0"/>
|
||||
<PARAMETER NAME="C_SLOT_0_INTF_TYPE" VALUE="xilinx.com:interface:spi_rtl:1.0"/>
|
||||
<PARAMETER NAME="C_SLOT_0_MAX_RD_BURSTS" VALUE="2"/>
|
||||
<PARAMETER NAME="C_SLOT_0_MAX_WR_BURSTS" VALUE="2"/>
|
||||
<PARAMETER NAME="C_SLOT_0_TXN_CNTR_EN" VALUE="1"/>
|
||||
@@ -19779,136 +19779,63 @@
|
||||
<PARAMETER NAME="EDK_SPECIAL" VALUE="MONITOR"/>
|
||||
</PARAMETERS>
|
||||
<PORTS>
|
||||
<PORT DIR="I" LEFT="31" NAME="SLOT_0_AXI_araddr" RIGHT="0" SIGIS="undef"/>
|
||||
<PORT DIR="I" LEFT="2" NAME="SLOT_0_AXI_arprot" RIGHT="0" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_AXI_arready" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_AXI_arvalid" SIGIS="undef"/>
|
||||
<PORT DIR="I" LEFT="31" NAME="SLOT_0_AXI_awaddr" RIGHT="0" SIGIS="undef"/>
|
||||
<PORT DIR="I" LEFT="2" NAME="SLOT_0_AXI_awprot" RIGHT="0" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_AXI_awready" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_AXI_awvalid" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_AXI_bready" SIGIS="undef"/>
|
||||
<PORT DIR="I" LEFT="1" NAME="SLOT_0_AXI_bresp" RIGHT="0" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_AXI_bvalid" SIGIS="undef"/>
|
||||
<PORT DIR="I" LEFT="31" NAME="SLOT_0_AXI_rdata" RIGHT="0" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_AXI_rready" SIGIS="undef"/>
|
||||
<PORT DIR="I" LEFT="1" NAME="SLOT_0_AXI_rresp" RIGHT="0" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_AXI_rvalid" SIGIS="undef"/>
|
||||
<PORT DIR="I" LEFT="31" NAME="SLOT_0_AXI_wdata" RIGHT="0" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_AXI_wready" SIGIS="undef"/>
|
||||
<PORT DIR="I" LEFT="3" NAME="SLOT_0_AXI_wstrb" RIGHT="0" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_AXI_wvalid" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_1_SPI_io0_i" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_1_SPI_io0_o" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_1_SPI_io0_t" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_1_SPI_io1_i" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_1_SPI_io1_o" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_1_SPI_io1_t" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_1_SPI_sck_i" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_1_SPI_sck_o" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_1_SPI_sck_t" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_1_SPI_ss1_o" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_1_SPI_ss2_o" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_1_SPI_ss_i" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_1_SPI_ss_o" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_1_SPI_ss_t" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_SPI_io0_i" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_SPI_io0_o" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_SPI_io0_t" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_SPI_io1_i" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_SPI_io1_o" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_SPI_io1_t" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_SPI_sck_i" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_SPI_sck_o" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_SPI_sck_t" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_SPI_ss1_o" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_SPI_ss2_o" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_SPI_ss_i" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_SPI_ss_o" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="SLOT_0_SPI_ss_t" SIGIS="undef"/>
|
||||
<PORT CLKFREQUENCY="1e+08" DIR="I" NAME="clk" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" LEFT="0" NAME="probe0" RIGHT="0" SIGIS="undef" SIGNAME="axi4_lite_spi_0_ssn_o">
|
||||
<PORT DIR="I" LEFT="0" NAME="probe0" RIGHT="0" SIGIS="undef" SIGNAME="axi4_lite_spi_1_mosi_o">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axi4_lite_spi_0" PORT="ssn_o"/>
|
||||
<CONNECTION INSTANCE="axi4_lite_spi_1" PORT="mosi_o"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" LEFT="0" NAME="probe1" RIGHT="0" SIGIS="undef" SIGNAME="axi4_lite_spi_0_sclk_o">
|
||||
<PORT DIR="I" LEFT="0" NAME="probe1" RIGHT="0" SIGIS="undef" SIGNAME="axi4_lite_spi_1_sclk_o">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axi4_lite_spi_0" PORT="sclk_o"/>
|
||||
<CONNECTION INSTANCE="axi4_lite_spi_1" PORT="sclk_o"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" LEFT="0" NAME="probe2" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_sdio_0">
|
||||
<PORT DIR="I" LEFT="0" NAME="probe2" RIGHT="0" SIGIS="undef" SIGNAME="axi4_lite_spi_1_ssn_o">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="External_Ports" PORT="sdio_0"/>
|
||||
<CONNECTION INSTANCE="axi4_lite_spi_1" PORT="ssn_o"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="resetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_ps7_0_200M_peripheral_aresetn">
|
||||
<PORT DIR="I" LEFT="0" NAME="probe3" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_miso_i_0">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="rst_ps7_0_200M" PORT="peripheral_aresetn"/>
|
||||
<CONNECTION INSTANCE="External_Ports" PORT="miso_i_0"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
</PORTS>
|
||||
<BUSINTERFACES>
|
||||
<BUSINTERFACE BUSNAME="axi_smc_M09_AXI" DATAWIDTH="32" NAME="SLOT_0_AXI" TYPE="MONITOR" VLNV="xilinx.com:interface:aximm:1.0">
|
||||
<PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
|
||||
<PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN" VALUE="system_top_processing_system7_0_0_FCLK_CLK0"/>
|
||||
<PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="1e+08"/>
|
||||
<PARAMETER NAME="HAS_BRESP" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_BURST" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_CACHE" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_LOCK" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_PROT" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_QOS" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_REGION" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_RRESP" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
|
||||
<PARAMETER NAME="ID_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
|
||||
<PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="8"/>
|
||||
<PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
|
||||
<PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="8"/>
|
||||
<PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.000"/>
|
||||
<PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
|
||||
<PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
|
||||
<PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
|
||||
<PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
|
||||
<PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
|
||||
<PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
|
||||
<BUSINTERFACE BUSNAME="processing_system7_0_SPI_0" NAME="SLOT_0_SPI" TYPE="MONITOR" VLNV="xilinx.com:interface:spi:1.0">
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="ARADDR" PHYSICAL="SLOT_0_AXI_araddr"/>
|
||||
<PORTMAP LOGICAL="ARPROT" PHYSICAL="SLOT_0_AXI_arprot"/>
|
||||
<PORTMAP LOGICAL="ARREADY" PHYSICAL="SLOT_0_AXI_arready"/>
|
||||
<PORTMAP LOGICAL="ARVALID" PHYSICAL="SLOT_0_AXI_arvalid"/>
|
||||
<PORTMAP LOGICAL="AWADDR" PHYSICAL="SLOT_0_AXI_awaddr"/>
|
||||
<PORTMAP LOGICAL="AWPROT" PHYSICAL="SLOT_0_AXI_awprot"/>
|
||||
<PORTMAP LOGICAL="AWREADY" PHYSICAL="SLOT_0_AXI_awready"/>
|
||||
<PORTMAP LOGICAL="AWVALID" PHYSICAL="SLOT_0_AXI_awvalid"/>
|
||||
<PORTMAP LOGICAL="BREADY" PHYSICAL="SLOT_0_AXI_bready"/>
|
||||
<PORTMAP LOGICAL="BRESP" PHYSICAL="SLOT_0_AXI_bresp"/>
|
||||
<PORTMAP LOGICAL="BVALID" PHYSICAL="SLOT_0_AXI_bvalid"/>
|
||||
<PORTMAP LOGICAL="RDATA" PHYSICAL="SLOT_0_AXI_rdata"/>
|
||||
<PORTMAP LOGICAL="RREADY" PHYSICAL="SLOT_0_AXI_rready"/>
|
||||
<PORTMAP LOGICAL="RRESP" PHYSICAL="SLOT_0_AXI_rresp"/>
|
||||
<PORTMAP LOGICAL="RVALID" PHYSICAL="SLOT_0_AXI_rvalid"/>
|
||||
<PORTMAP LOGICAL="WDATA" PHYSICAL="SLOT_0_AXI_wdata"/>
|
||||
<PORTMAP LOGICAL="WREADY" PHYSICAL="SLOT_0_AXI_wready"/>
|
||||
<PORTMAP LOGICAL="WSTRB" PHYSICAL="SLOT_0_AXI_wstrb"/>
|
||||
<PORTMAP LOGICAL="WVALID" PHYSICAL="SLOT_0_AXI_wvalid"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
<BUSINTERFACE BUSNAME="processing_system7_0_SPI_0" NAME="SLOT_1_SPI" TYPE="MONITOR" VLNV="xilinx.com:interface:spi:1.0">
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="IO0_I" PHYSICAL="SLOT_1_SPI_io0_i"/>
|
||||
<PORTMAP LOGICAL="IO0_O" PHYSICAL="SLOT_1_SPI_io0_o"/>
|
||||
<PORTMAP LOGICAL="IO0_T" PHYSICAL="SLOT_1_SPI_io0_t"/>
|
||||
<PORTMAP LOGICAL="IO1_I" PHYSICAL="SLOT_1_SPI_io1_i"/>
|
||||
<PORTMAP LOGICAL="IO1_O" PHYSICAL="SLOT_1_SPI_io1_o"/>
|
||||
<PORTMAP LOGICAL="IO1_T" PHYSICAL="SLOT_1_SPI_io1_t"/>
|
||||
<PORTMAP LOGICAL="SCK_I" PHYSICAL="SLOT_1_SPI_sck_i"/>
|
||||
<PORTMAP LOGICAL="SCK_O" PHYSICAL="SLOT_1_SPI_sck_o"/>
|
||||
<PORTMAP LOGICAL="SCK_T" PHYSICAL="SLOT_1_SPI_sck_t"/>
|
||||
<PORTMAP LOGICAL="SS1_O" PHYSICAL="SLOT_1_SPI_ss1_o"/>
|
||||
<PORTMAP LOGICAL="SS2_O" PHYSICAL="SLOT_1_SPI_ss2_o"/>
|
||||
<PORTMAP LOGICAL="SS_I" PHYSICAL="SLOT_1_SPI_ss_i"/>
|
||||
<PORTMAP LOGICAL="SS_O" PHYSICAL="SLOT_1_SPI_ss_o"/>
|
||||
<PORTMAP LOGICAL="SS_T" PHYSICAL="SLOT_1_SPI_ss_t"/>
|
||||
<PORTMAP LOGICAL="IO0_I" PHYSICAL="SLOT_0_SPI_io0_i"/>
|
||||
<PORTMAP LOGICAL="IO0_O" PHYSICAL="SLOT_0_SPI_io0_o"/>
|
||||
<PORTMAP LOGICAL="IO0_T" PHYSICAL="SLOT_0_SPI_io0_t"/>
|
||||
<PORTMAP LOGICAL="IO1_I" PHYSICAL="SLOT_0_SPI_io1_i"/>
|
||||
<PORTMAP LOGICAL="IO1_O" PHYSICAL="SLOT_0_SPI_io1_o"/>
|
||||
<PORTMAP LOGICAL="IO1_T" PHYSICAL="SLOT_0_SPI_io1_t"/>
|
||||
<PORTMAP LOGICAL="SCK_I" PHYSICAL="SLOT_0_SPI_sck_i"/>
|
||||
<PORTMAP LOGICAL="SCK_O" PHYSICAL="SLOT_0_SPI_sck_o"/>
|
||||
<PORTMAP LOGICAL="SCK_T" PHYSICAL="SLOT_0_SPI_sck_t"/>
|
||||
<PORTMAP LOGICAL="SS1_O" PHYSICAL="SLOT_0_SPI_ss1_o"/>
|
||||
<PORTMAP LOGICAL="SS2_O" PHYSICAL="SLOT_0_SPI_ss2_o"/>
|
||||
<PORTMAP LOGICAL="SS_I" PHYSICAL="SLOT_0_SPI_ss_i"/>
|
||||
<PORTMAP LOGICAL="SS_O" PHYSICAL="SLOT_0_SPI_ss_o"/>
|
||||
<PORTMAP LOGICAL="SS_T" PHYSICAL="SLOT_0_SPI_ss_t"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
</BUSINTERFACES>
|
||||
|
||||
+26
-14
@@ -5,22 +5,34 @@ COMPILER_FLAGS=
|
||||
EXTRA_COMPILER_FLAGS=
|
||||
LIB=libxil.a
|
||||
|
||||
RELEASEDIR=../../../lib
|
||||
INCLUDEDIR=../../../include
|
||||
INCLUDES=-I./. -I${INCLUDEDIR}
|
||||
CC_FLAGS = $(COMPILER_FLAGS)
|
||||
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
|
||||
|
||||
INCLUDEFILES=*.h
|
||||
LIBSOURCES=*.c
|
||||
OUTS = *.o
|
||||
RELEASEDIR=../../../lib/
|
||||
INCLUDEDIR=../../../include/
|
||||
INCLUDES=-I./. -I$(INCLUDEDIR)
|
||||
|
||||
libs:
|
||||
echo "Compiling Axis_adc_data_packer..."
|
||||
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
|
||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
|
||||
make clean
|
||||
SRCFILES:=$(wildcard *.c)
|
||||
|
||||
include:
|
||||
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
|
||||
OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
|
||||
|
||||
libs: $(OBJECTS)
|
||||
|
||||
DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
|
||||
|
||||
include $(wildcard $(DEPFILES))
|
||||
|
||||
include $(wildcard ../../../../dep.mk)
|
||||
|
||||
$(RELEASEDIR)%.o: %.c
|
||||
${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
|
||||
|
||||
.PHONY: include
|
||||
include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
|
||||
|
||||
$(INCLUDEDIR)%.h: %.h
|
||||
$(CP) $< $@
|
||||
|
||||
clean:
|
||||
rm -rf ${OUTS}
|
||||
rm -rf ${OBJECTS}
|
||||
rm -rf $(DEPFILES)
|
||||
|
||||
+197
@@ -0,0 +1,197 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: labnet.com:user:Axis_adc_data_packer:1.0
|
||||
// IP Revision: 9
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_top_Axis_adc_data_packer_0_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
axis_tvalid,
|
||||
axis_tlast,
|
||||
axis_ready,
|
||||
axis_tdata,
|
||||
m_axis_tvalid,
|
||||
m_axis_tlast,
|
||||
m_axis_ready,
|
||||
m_axis_tdata,
|
||||
s00_axi_awaddr,
|
||||
s00_axi_awprot,
|
||||
s00_axi_awvalid,
|
||||
s00_axi_awready,
|
||||
s00_axi_wdata,
|
||||
s00_axi_wstrb,
|
||||
s00_axi_wvalid,
|
||||
s00_axi_wready,
|
||||
s00_axi_bresp,
|
||||
s00_axi_bvalid,
|
||||
s00_axi_bready,
|
||||
s00_axi_araddr,
|
||||
s00_axi_arprot,
|
||||
s00_axi_arvalid,
|
||||
s00_axi_arready,
|
||||
s00_axi_rdata,
|
||||
s00_axi_rresp,
|
||||
s00_axi_rvalid,
|
||||
s00_axi_rready,
|
||||
s00_axi_aclk,
|
||||
s00_axi_aresetn
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF axis:m_axis, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TVALID" *)
|
||||
input wire axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TLAST" *)
|
||||
input wire axis_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TREADY" *)
|
||||
output wire axis_ready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TDATA" *)
|
||||
input wire [63 : 0] axis_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TVALID" *)
|
||||
output wire m_axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TLAST" *)
|
||||
output wire m_axis_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TREADY" *)
|
||||
input wire m_axis_ready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TDATA" *)
|
||||
output wire [63 : 0] m_axis_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
|
||||
input wire [3 : 0] s00_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
|
||||
input wire [2 : 0] s00_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
|
||||
input wire s00_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
|
||||
output wire s00_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
|
||||
input wire [31 : 0] s00_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
|
||||
input wire [3 : 0] s00_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
|
||||
input wire s00_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
|
||||
output wire s00_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
|
||||
output wire [1 : 0] s00_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
|
||||
output wire s00_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
|
||||
input wire s00_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
|
||||
input wire [3 : 0] s00_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
|
||||
input wire [2 : 0] s00_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
|
||||
input wire s00_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
|
||||
output wire s00_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
|
||||
output wire [31 : 0] s00_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
|
||||
output wire [1 : 0] s00_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
|
||||
output wire s00_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_syste\
|
||||
m7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
|
||||
input wire s00_axi_rready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK" *)
|
||||
input wire s00_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST" *)
|
||||
input wire s00_axi_aresetn;
|
||||
|
||||
Axis_adc_data_packer_v1_0 #(
|
||||
.C_S00_AXI_DATA_WIDTH(32), // Width of S_AXI data bus
|
||||
.C_S00_AXI_ADDR_WIDTH(4) // Width of S_AXI address bus
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.axis_tvalid(axis_tvalid),
|
||||
.axis_tlast(axis_tlast),
|
||||
.axis_ready(axis_ready),
|
||||
.axis_tdata(axis_tdata),
|
||||
.m_axis_tvalid(m_axis_tvalid),
|
||||
.m_axis_tlast(m_axis_tlast),
|
||||
.m_axis_ready(m_axis_ready),
|
||||
.m_axis_tdata(m_axis_tdata),
|
||||
.s00_axi_awaddr(s00_axi_awaddr),
|
||||
.s00_axi_awprot(s00_axi_awprot),
|
||||
.s00_axi_awvalid(s00_axi_awvalid),
|
||||
.s00_axi_awready(s00_axi_awready),
|
||||
.s00_axi_wdata(s00_axi_wdata),
|
||||
.s00_axi_wstrb(s00_axi_wstrb),
|
||||
.s00_axi_wvalid(s00_axi_wvalid),
|
||||
.s00_axi_wready(s00_axi_wready),
|
||||
.s00_axi_bresp(s00_axi_bresp),
|
||||
.s00_axi_bvalid(s00_axi_bvalid),
|
||||
.s00_axi_bready(s00_axi_bready),
|
||||
.s00_axi_araddr(s00_axi_araddr),
|
||||
.s00_axi_arprot(s00_axi_arprot),
|
||||
.s00_axi_arvalid(s00_axi_arvalid),
|
||||
.s00_axi_arready(s00_axi_arready),
|
||||
.s00_axi_rdata(s00_axi_rdata),
|
||||
.s00_axi_rresp(s00_axi_rresp),
|
||||
.s00_axi_rvalid(s00_axi_rvalid),
|
||||
.s00_axi_rready(s00_axi_rready),
|
||||
.s00_axi_aclk(s00_axi_aclk),
|
||||
.s00_axi_aresetn(s00_axi_aresetn)
|
||||
);
|
||||
endmodule
|
||||
+1
-1
@@ -50,7 +50,7 @@
|
||||
// IP VLNV: labnet.com:user:Axis_adc_data_packer:1.0
|
||||
// IP Revision: 9
|
||||
|
||||
(* X_CORE_INFO = "Axis_adc_data_packer_v1_0,Vivado 2024.1" *)
|
||||
(* X_CORE_INFO = "Axis_adc_data_packer_v1_0,Vivado 2024.1.2" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_top_Axis_adc_data_packer_0_0,Axis_adc_data_packer_v1_0,{}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_top_Axis_adc_data_packer_0_0 (
|
||||
|
||||
+1
-1
@@ -39,7 +39,7 @@
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
|
||||
+97
-3
@@ -990,7 +990,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1009,6 +1009,46 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>Axis_adc_data_packer_v1_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:24fe4614</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>system_top_Axis_adc_data_packer_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:24fe4614</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsynthesis</spirit:name>
|
||||
<spirit:displayName>Verilog Synthesis</spirit:displayName>
|
||||
@@ -1021,7 +1061,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1041,7 +1081,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1059,6 +1099,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1071,6 +1112,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1083,6 +1125,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1095,6 +1138,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1110,6 +1154,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1126,6 +1171,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1141,6 +1187,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1153,6 +1200,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1165,6 +1213,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1181,6 +1230,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1197,6 +1247,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1213,6 +1264,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1225,6 +1277,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1237,6 +1290,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1253,6 +1307,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1269,6 +1324,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1281,6 +1337,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1293,6 +1350,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1309,6 +1367,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1321,6 +1380,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1333,6 +1393,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1349,6 +1410,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1365,6 +1427,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1377,6 +1440,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1389,6 +1453,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1405,6 +1470,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1421,6 +1487,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1433,6 +1500,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1445,6 +1513,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1457,6 +1526,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1469,6 +1539,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1533,6 +1604,29 @@
|
||||
<spirit:fileType>cSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9971/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9971/hdl/axis_adc_data_packer.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9971/hdl/Axis_adc_data_packer_v1_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/system_top_Axis_adc_data_packer_0_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
|
||||
+26
-14
@@ -5,22 +5,34 @@ COMPILER_FLAGS=
|
||||
EXTRA_COMPILER_FLAGS=
|
||||
LIB=libxil.a
|
||||
|
||||
RELEASEDIR=../../../lib
|
||||
INCLUDEDIR=../../../include
|
||||
INCLUDES=-I./. -I${INCLUDEDIR}
|
||||
CC_FLAGS = $(COMPILER_FLAGS)
|
||||
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
|
||||
|
||||
INCLUDEFILES=*.h
|
||||
LIBSOURCES=*.c
|
||||
OUTS = *.o
|
||||
RELEASEDIR=../../../lib/
|
||||
INCLUDEDIR=../../../include/
|
||||
INCLUDES=-I./. -I$(INCLUDEDIR)
|
||||
|
||||
libs:
|
||||
echo "Compiling Axis_adc_data_packer..."
|
||||
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
|
||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
|
||||
make clean
|
||||
SRCFILES:=$(wildcard *.c)
|
||||
|
||||
include:
|
||||
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
|
||||
OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
|
||||
|
||||
libs: $(OBJECTS)
|
||||
|
||||
DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
|
||||
|
||||
include $(wildcard $(DEPFILES))
|
||||
|
||||
include $(wildcard ../../../../dep.mk)
|
||||
|
||||
$(RELEASEDIR)%.o: %.c
|
||||
${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
|
||||
|
||||
.PHONY: include
|
||||
include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
|
||||
|
||||
$(INCLUDEDIR)%.h: %.h
|
||||
$(CP) $< $@
|
||||
|
||||
clean:
|
||||
rm -rf ${OUTS}
|
||||
rm -rf ${OBJECTS}
|
||||
rm -rf $(DEPFILES)
|
||||
|
||||
+197
@@ -0,0 +1,197 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: labnet.com:user:Axis_adc_data_packer:1.0
|
||||
// IP Revision: 9
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_top_Axis_adc_data_packer_1_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
axis_tvalid,
|
||||
axis_tlast,
|
||||
axis_ready,
|
||||
axis_tdata,
|
||||
m_axis_tvalid,
|
||||
m_axis_tlast,
|
||||
m_axis_ready,
|
||||
m_axis_tdata,
|
||||
s00_axi_awaddr,
|
||||
s00_axi_awprot,
|
||||
s00_axi_awvalid,
|
||||
s00_axi_awready,
|
||||
s00_axi_wdata,
|
||||
s00_axi_wstrb,
|
||||
s00_axi_wvalid,
|
||||
s00_axi_wready,
|
||||
s00_axi_bresp,
|
||||
s00_axi_bvalid,
|
||||
s00_axi_bready,
|
||||
s00_axi_araddr,
|
||||
s00_axi_arprot,
|
||||
s00_axi_arvalid,
|
||||
s00_axi_arready,
|
||||
s00_axi_rdata,
|
||||
s00_axi_rresp,
|
||||
s00_axi_rvalid,
|
||||
s00_axi_rready,
|
||||
s00_axi_aclk,
|
||||
s00_axi_aresetn
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF axis:m_axis, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_1, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TVALID" *)
|
||||
input wire axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TLAST" *)
|
||||
input wire axis_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TREADY" *)
|
||||
output wire axis_ready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_1, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TDATA" *)
|
||||
input wire [63 : 0] axis_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TVALID" *)
|
||||
output wire m_axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TLAST" *)
|
||||
output wire m_axis_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TREADY" *)
|
||||
input wire m_axis_ready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_1, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TDATA" *)
|
||||
output wire [63 : 0] m_axis_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
|
||||
input wire [3 : 0] s00_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
|
||||
input wire [2 : 0] s00_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
|
||||
input wire s00_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
|
||||
output wire s00_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
|
||||
input wire [31 : 0] s00_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
|
||||
input wire [3 : 0] s00_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
|
||||
input wire s00_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
|
||||
output wire s00_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
|
||||
output wire [1 : 0] s00_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
|
||||
output wire s00_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
|
||||
input wire s00_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
|
||||
input wire [3 : 0] s00_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
|
||||
input wire [2 : 0] s00_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
|
||||
input wire s00_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
|
||||
output wire s00_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
|
||||
output wire [31 : 0] s00_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
|
||||
output wire [1 : 0] s00_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
|
||||
output wire s00_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_syste\
|
||||
m7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
|
||||
input wire s00_axi_rready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK" *)
|
||||
input wire s00_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST" *)
|
||||
input wire s00_axi_aresetn;
|
||||
|
||||
Axis_adc_data_packer_v1_0 #(
|
||||
.C_S00_AXI_DATA_WIDTH(32), // Width of S_AXI data bus
|
||||
.C_S00_AXI_ADDR_WIDTH(4) // Width of S_AXI address bus
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.axis_tvalid(axis_tvalid),
|
||||
.axis_tlast(axis_tlast),
|
||||
.axis_ready(axis_ready),
|
||||
.axis_tdata(axis_tdata),
|
||||
.m_axis_tvalid(m_axis_tvalid),
|
||||
.m_axis_tlast(m_axis_tlast),
|
||||
.m_axis_ready(m_axis_ready),
|
||||
.m_axis_tdata(m_axis_tdata),
|
||||
.s00_axi_awaddr(s00_axi_awaddr),
|
||||
.s00_axi_awprot(s00_axi_awprot),
|
||||
.s00_axi_awvalid(s00_axi_awvalid),
|
||||
.s00_axi_awready(s00_axi_awready),
|
||||
.s00_axi_wdata(s00_axi_wdata),
|
||||
.s00_axi_wstrb(s00_axi_wstrb),
|
||||
.s00_axi_wvalid(s00_axi_wvalid),
|
||||
.s00_axi_wready(s00_axi_wready),
|
||||
.s00_axi_bresp(s00_axi_bresp),
|
||||
.s00_axi_bvalid(s00_axi_bvalid),
|
||||
.s00_axi_bready(s00_axi_bready),
|
||||
.s00_axi_araddr(s00_axi_araddr),
|
||||
.s00_axi_arprot(s00_axi_arprot),
|
||||
.s00_axi_arvalid(s00_axi_arvalid),
|
||||
.s00_axi_arready(s00_axi_arready),
|
||||
.s00_axi_rdata(s00_axi_rdata),
|
||||
.s00_axi_rresp(s00_axi_rresp),
|
||||
.s00_axi_rvalid(s00_axi_rvalid),
|
||||
.s00_axi_rready(s00_axi_rready),
|
||||
.s00_axi_aclk(s00_axi_aclk),
|
||||
.s00_axi_aresetn(s00_axi_aresetn)
|
||||
);
|
||||
endmodule
|
||||
+1
-1
@@ -50,7 +50,7 @@
|
||||
// IP VLNV: labnet.com:user:Axis_adc_data_packer:1.0
|
||||
// IP Revision: 9
|
||||
|
||||
(* X_CORE_INFO = "Axis_adc_data_packer_v1_0,Vivado 2024.1" *)
|
||||
(* X_CORE_INFO = "Axis_adc_data_packer_v1_0,Vivado 2024.1.2" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_top_Axis_adc_data_packer_1_0,Axis_adc_data_packer_v1_0,{}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_top_Axis_adc_data_packer_1_0 (
|
||||
|
||||
+1
-1
@@ -39,7 +39,7 @@
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
|
||||
+97
-3
@@ -990,7 +990,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1009,6 +1009,46 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>Axis_adc_data_packer_v1_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:4b0781e0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>system_top_Axis_adc_data_packer_1_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:4b0781e0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsynthesis</spirit:name>
|
||||
<spirit:displayName>Verilog Synthesis</spirit:displayName>
|
||||
@@ -1021,7 +1061,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1041,7 +1081,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1059,6 +1099,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1071,6 +1112,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1083,6 +1125,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1095,6 +1138,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1110,6 +1154,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1126,6 +1171,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1141,6 +1187,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1153,6 +1200,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1165,6 +1213,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1181,6 +1230,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1197,6 +1247,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1213,6 +1264,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1225,6 +1277,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1237,6 +1290,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1253,6 +1307,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1269,6 +1324,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1281,6 +1337,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1293,6 +1350,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1309,6 +1367,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1321,6 +1380,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1333,6 +1393,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1349,6 +1410,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1365,6 +1427,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1377,6 +1440,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1389,6 +1453,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1405,6 +1470,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1421,6 +1487,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1433,6 +1500,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1445,6 +1513,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1457,6 +1526,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1469,6 +1539,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1533,6 +1604,29 @@
|
||||
<spirit:fileType>cSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9971/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9971/hdl/axis_adc_data_packer.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9971/hdl/Axis_adc_data_packer_v1_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/system_top_Axis_adc_data_packer_1_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
|
||||
+26
-14
@@ -5,22 +5,34 @@ COMPILER_FLAGS=
|
||||
EXTRA_COMPILER_FLAGS=
|
||||
LIB=libxil.a
|
||||
|
||||
RELEASEDIR=../../../lib
|
||||
INCLUDEDIR=../../../include
|
||||
INCLUDES=-I./. -I${INCLUDEDIR}
|
||||
CC_FLAGS = $(COMPILER_FLAGS)
|
||||
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
|
||||
|
||||
INCLUDEFILES=*.h
|
||||
LIBSOURCES=*.c
|
||||
OUTS = *.o
|
||||
RELEASEDIR=../../../lib/
|
||||
INCLUDEDIR=../../../include/
|
||||
INCLUDES=-I./. -I$(INCLUDEDIR)
|
||||
|
||||
libs:
|
||||
echo "Compiling Axis_adc_data_packer..."
|
||||
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
|
||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
|
||||
make clean
|
||||
SRCFILES:=$(wildcard *.c)
|
||||
|
||||
include:
|
||||
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
|
||||
OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
|
||||
|
||||
libs: $(OBJECTS)
|
||||
|
||||
DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
|
||||
|
||||
include $(wildcard $(DEPFILES))
|
||||
|
||||
include $(wildcard ../../../../dep.mk)
|
||||
|
||||
$(RELEASEDIR)%.o: %.c
|
||||
${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
|
||||
|
||||
.PHONY: include
|
||||
include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
|
||||
|
||||
$(INCLUDEDIR)%.h: %.h
|
||||
$(CP) $< $@
|
||||
|
||||
clean:
|
||||
rm -rf ${OUTS}
|
||||
rm -rf ${OBJECTS}
|
||||
rm -rf $(DEPFILES)
|
||||
|
||||
+197
@@ -0,0 +1,197 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: labnet.com:user:Axis_adc_data_packer:1.0
|
||||
// IP Revision: 9
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_top_Axis_adc_data_packer_2_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
axis_tvalid,
|
||||
axis_tlast,
|
||||
axis_ready,
|
||||
axis_tdata,
|
||||
m_axis_tvalid,
|
||||
m_axis_tlast,
|
||||
m_axis_ready,
|
||||
m_axis_tdata,
|
||||
s00_axi_awaddr,
|
||||
s00_axi_awprot,
|
||||
s00_axi_awvalid,
|
||||
s00_axi_awready,
|
||||
s00_axi_wdata,
|
||||
s00_axi_wstrb,
|
||||
s00_axi_wvalid,
|
||||
s00_axi_wready,
|
||||
s00_axi_bresp,
|
||||
s00_axi_bvalid,
|
||||
s00_axi_bready,
|
||||
s00_axi_araddr,
|
||||
s00_axi_arprot,
|
||||
s00_axi_arvalid,
|
||||
s00_axi_arready,
|
||||
s00_axi_rdata,
|
||||
s00_axi_rresp,
|
||||
s00_axi_rvalid,
|
||||
s00_axi_rready,
|
||||
s00_axi_aclk,
|
||||
s00_axi_aresetn
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF axis:m_axis, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_2, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TVALID" *)
|
||||
input wire axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TLAST" *)
|
||||
input wire axis_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TREADY" *)
|
||||
output wire axis_ready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_2, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axis TDATA" *)
|
||||
input wire [63 : 0] axis_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TVALID" *)
|
||||
output wire m_axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TLAST" *)
|
||||
output wire m_axis_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TREADY" *)
|
||||
input wire m_axis_ready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axis, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_top_data_clk_2, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis TDATA" *)
|
||||
output wire [63 : 0] m_axis_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
|
||||
input wire [3 : 0] s00_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
|
||||
input wire [2 : 0] s00_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
|
||||
input wire s00_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
|
||||
output wire s00_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
|
||||
input wire [31 : 0] s00_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
|
||||
input wire [3 : 0] s00_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
|
||||
input wire s00_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
|
||||
output wire s00_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
|
||||
output wire [1 : 0] s00_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
|
||||
output wire s00_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
|
||||
input wire s00_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
|
||||
input wire [3 : 0] s00_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
|
||||
input wire [2 : 0] s00_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
|
||||
input wire s00_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
|
||||
output wire s00_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
|
||||
output wire [31 : 0] s00_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
|
||||
output wire [1 : 0] s00_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
|
||||
output wire s00_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_syste\
|
||||
m7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
|
||||
input wire s00_axi_rready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK" *)
|
||||
input wire s00_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST" *)
|
||||
input wire s00_axi_aresetn;
|
||||
|
||||
Axis_adc_data_packer_v1_0 #(
|
||||
.C_S00_AXI_DATA_WIDTH(32), // Width of S_AXI data bus
|
||||
.C_S00_AXI_ADDR_WIDTH(4) // Width of S_AXI address bus
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.axis_tvalid(axis_tvalid),
|
||||
.axis_tlast(axis_tlast),
|
||||
.axis_ready(axis_ready),
|
||||
.axis_tdata(axis_tdata),
|
||||
.m_axis_tvalid(m_axis_tvalid),
|
||||
.m_axis_tlast(m_axis_tlast),
|
||||
.m_axis_ready(m_axis_ready),
|
||||
.m_axis_tdata(m_axis_tdata),
|
||||
.s00_axi_awaddr(s00_axi_awaddr),
|
||||
.s00_axi_awprot(s00_axi_awprot),
|
||||
.s00_axi_awvalid(s00_axi_awvalid),
|
||||
.s00_axi_awready(s00_axi_awready),
|
||||
.s00_axi_wdata(s00_axi_wdata),
|
||||
.s00_axi_wstrb(s00_axi_wstrb),
|
||||
.s00_axi_wvalid(s00_axi_wvalid),
|
||||
.s00_axi_wready(s00_axi_wready),
|
||||
.s00_axi_bresp(s00_axi_bresp),
|
||||
.s00_axi_bvalid(s00_axi_bvalid),
|
||||
.s00_axi_bready(s00_axi_bready),
|
||||
.s00_axi_araddr(s00_axi_araddr),
|
||||
.s00_axi_arprot(s00_axi_arprot),
|
||||
.s00_axi_arvalid(s00_axi_arvalid),
|
||||
.s00_axi_arready(s00_axi_arready),
|
||||
.s00_axi_rdata(s00_axi_rdata),
|
||||
.s00_axi_rresp(s00_axi_rresp),
|
||||
.s00_axi_rvalid(s00_axi_rvalid),
|
||||
.s00_axi_rready(s00_axi_rready),
|
||||
.s00_axi_aclk(s00_axi_aclk),
|
||||
.s00_axi_aresetn(s00_axi_aresetn)
|
||||
);
|
||||
endmodule
|
||||
+1
-1
@@ -50,7 +50,7 @@
|
||||
// IP VLNV: labnet.com:user:Axis_adc_data_packer:1.0
|
||||
// IP Revision: 9
|
||||
|
||||
(* X_CORE_INFO = "Axis_adc_data_packer_v1_0,Vivado 2024.1" *)
|
||||
(* X_CORE_INFO = "Axis_adc_data_packer_v1_0,Vivado 2024.1.2" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_top_Axis_adc_data_packer_2_0,Axis_adc_data_packer_v1_0,{}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_top_Axis_adc_data_packer_2_0 (
|
||||
|
||||
+1
-1
@@ -39,7 +39,7 @@
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
|
||||
+97
-3
@@ -990,7 +990,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1009,6 +1009,46 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>Axis_adc_data_packer_v1_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:fb0dc9fc</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>system_top_Axis_adc_data_packer_2_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:fb0dc9fc</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsynthesis</spirit:name>
|
||||
<spirit:displayName>Verilog Synthesis</spirit:displayName>
|
||||
@@ -1021,7 +1061,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1041,7 +1081,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:49:49 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1059,6 +1099,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1071,6 +1112,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1083,6 +1125,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1095,6 +1138,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1110,6 +1154,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1126,6 +1171,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1141,6 +1187,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1153,6 +1200,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1165,6 +1213,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1181,6 +1230,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1197,6 +1247,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1213,6 +1264,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1225,6 +1277,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1237,6 +1290,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1253,6 +1307,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1269,6 +1324,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1281,6 +1337,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1293,6 +1350,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1309,6 +1367,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1321,6 +1380,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1333,6 +1393,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1349,6 +1410,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1365,6 +1427,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1377,6 +1440,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1389,6 +1453,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1405,6 +1470,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1421,6 +1487,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1433,6 +1500,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1445,6 +1513,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1457,6 +1526,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1469,6 +1539,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1533,6 +1604,29 @@
|
||||
<spirit:fileType>cSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9971/hdl/Axis_adc_data_packer_v1_0_S00_AXI.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9971/hdl/axis_adc_data_packer.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9971/hdl/Axis_adc_data_packer_v1_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/system_top_Axis_adc_data_packer_2_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
|
||||
+167
@@ -0,0 +1,167 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: cxkj.com:user:axi4_lite_spi:1.0
|
||||
// IP Revision: 2
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* IP_DEFINITION_SOURCE = "package_project" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_top_axi4_lite_spi_0_0 (
|
||||
s_axi_aclk,
|
||||
s_axi_aresetn,
|
||||
s_axi_awaddr,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_araddr,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
sclk_o,
|
||||
ssn_o,
|
||||
miso_i,
|
||||
mosi_o,
|
||||
sdio
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK" *)
|
||||
input wire s_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST" *)
|
||||
input wire s_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS \
|
||||
1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
output wire sclk_o;
|
||||
output wire ssn_o;
|
||||
input wire miso_i;
|
||||
output wire mosi_o;
|
||||
inout wire sdio;
|
||||
|
||||
axi4_lite_spi #(
|
||||
.C_S_AXI_ADDR_WIDTH(32),
|
||||
.C_S_AXI_DATA_WIDTH(32),
|
||||
.REGS_SIZE(24),
|
||||
.SPI_CONFIG(7'B1011101),
|
||||
.BAUD_RATE(16'H0002),
|
||||
.REG_WIDTH(8),
|
||||
.CHIP_ADDR_WIDTH(12),
|
||||
.FOUR_WIRE_SPI("false")
|
||||
) inst (
|
||||
.s_axi_aclk(s_axi_aclk),
|
||||
.s_axi_aresetn(s_axi_aresetn),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.sclk_o(sclk_o),
|
||||
.ssn_o(ssn_o),
|
||||
.miso_i(miso_i),
|
||||
.mosi_o(mosi_o),
|
||||
.sdio(sdio)
|
||||
);
|
||||
endmodule
|
||||
+1
-1
@@ -50,7 +50,7 @@
|
||||
// IP VLNV: cxkj.com:user:axi4_lite_spi:1.0
|
||||
// IP Revision: 2
|
||||
|
||||
(* X_CORE_INFO = "axi4_lite_spi,Vivado 2024.1" *)
|
||||
(* X_CORE_INFO = "axi4_lite_spi,Vivado 2024.1.2" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_top_axi4_lite_spi_0_0,axi4_lite_spi,{}" *)
|
||||
(* IP_DEFINITION_SOURCE = "package_project" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
|
||||
+1
-1
@@ -49,7 +49,7 @@
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
|
||||
+92
-2
@@ -540,6 +540,25 @@
|
||||
</spirit:memoryMaps>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axi4_lite_spi</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:50:02 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:4deb1464</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
@@ -551,7 +570,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:38 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:50:02 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -570,6 +589,26 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>system_top_axi4_lite_spi_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:50:02 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:4deb1464</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Synthesis Wrapper</spirit:displayName>
|
||||
@@ -582,7 +621,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:38 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:50:02 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -600,6 +639,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -612,6 +652,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -628,6 +669,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -643,6 +685,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -658,6 +701,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -674,6 +718,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -693,6 +738,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -708,6 +754,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -723,6 +770,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -739,6 +787,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -751,6 +800,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -763,6 +813,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -782,6 +833,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -797,6 +849,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -812,6 +865,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -828,6 +882,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -844,6 +899,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -856,6 +912,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -868,6 +925,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -883,6 +941,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -895,6 +954,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -907,6 +967,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -919,6 +980,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -931,6 +993,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -987,6 +1050,25 @@
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/cb12/rtl/axi4_lite_wrapper.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/cb12/rtl/spi_master.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/cb12/rtl/sync_one_stage.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/cb12/rtl/axi4_lite_spi.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
@@ -1006,6 +1088,14 @@
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/system_top_axi4_lite_spi_0_0.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
|
||||
+167
@@ -0,0 +1,167 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: cxkj.com:user:axi4_lite_spi:1.0
|
||||
// IP Revision: 2
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* IP_DEFINITION_SOURCE = "package_project" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_top_axi4_lite_spi_0_1 (
|
||||
s_axi_aclk,
|
||||
s_axi_aresetn,
|
||||
s_axi_awaddr,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_araddr,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
sclk_o,
|
||||
ssn_o,
|
||||
miso_i,
|
||||
mosi_o,
|
||||
sdio
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK" *)
|
||||
input wire s_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST" *)
|
||||
input wire s_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS \
|
||||
1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
output wire sclk_o;
|
||||
output wire ssn_o;
|
||||
input wire miso_i;
|
||||
output wire mosi_o;
|
||||
inout wire sdio;
|
||||
|
||||
axi4_lite_spi #(
|
||||
.C_S_AXI_ADDR_WIDTH(32),
|
||||
.C_S_AXI_DATA_WIDTH(32),
|
||||
.REGS_SIZE(24),
|
||||
.SPI_CONFIG(7'B1011101),
|
||||
.BAUD_RATE(16'H0002),
|
||||
.REG_WIDTH(8),
|
||||
.CHIP_ADDR_WIDTH(13),
|
||||
.FOUR_WIRE_SPI("true")
|
||||
) inst (
|
||||
.s_axi_aclk(s_axi_aclk),
|
||||
.s_axi_aresetn(s_axi_aresetn),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.sclk_o(sclk_o),
|
||||
.ssn_o(ssn_o),
|
||||
.miso_i(miso_i),
|
||||
.mosi_o(mosi_o),
|
||||
.sdio(sdio)
|
||||
);
|
||||
endmodule
|
||||
+1
-1
@@ -50,7 +50,7 @@
|
||||
// IP VLNV: cxkj.com:user:axi4_lite_spi:1.0
|
||||
// IP Revision: 2
|
||||
|
||||
(* X_CORE_INFO = "axi4_lite_spi,Vivado 2024.1" *)
|
||||
(* X_CORE_INFO = "axi4_lite_spi,Vivado 2024.1.2" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_top_axi4_lite_spi_0_1,axi4_lite_spi,{}" *)
|
||||
(* IP_DEFINITION_SOURCE = "package_project" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
|
||||
+1
-1
@@ -49,7 +49,7 @@
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
|
||||
+92
-2
@@ -540,6 +540,25 @@
|
||||
</spirit:memoryMaps>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axi4_lite_spi</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:50:02 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:92904f2b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
@@ -551,7 +570,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:38 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:50:02 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -570,6 +589,26 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>system_top_axi4_lite_spi_0_1</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 03 07:50:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:92904f2b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Synthesis Wrapper</spirit:displayName>
|
||||
@@ -582,7 +621,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Oct 31 03:29:40 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 03 07:50:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -600,6 +639,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -612,6 +652,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -628,6 +669,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -643,6 +685,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -658,6 +701,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -674,6 +718,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -693,6 +738,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -708,6 +754,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -723,6 +770,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -739,6 +787,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -751,6 +800,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -763,6 +813,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -782,6 +833,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -797,6 +849,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -812,6 +865,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -828,6 +882,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -844,6 +899,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -856,6 +912,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -868,6 +925,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -883,6 +941,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -895,6 +954,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -907,6 +967,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -919,6 +980,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -931,6 +993,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -987,6 +1050,25 @@
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/cb12/rtl/axi4_lite_wrapper.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/cb12/rtl/spi_master.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/cb12/rtl/sync_one_stage.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/cb12/rtl/axi4_lite_spi.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
@@ -1006,6 +1088,14 @@
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/system_top_axi4_lite_spi_0_1.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
|
||||
+677
@@ -0,0 +1,677 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#include "system_top_axi_bram_ctrl_0_0_sc.h"
|
||||
|
||||
#include "system_top_axi_bram_ctrl_0_0.h"
|
||||
|
||||
#include "axi_bram_ctrl.h"
|
||||
|
||||
#include <map>
|
||||
#include <string>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XILINX_SIMULATOR
|
||||
system_top_axi_bram_ctrl_0_0::system_top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm) : system_top_axi_bram_ctrl_0_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), bram_rst_a("bram_rst_a"), bram_clk_a("bram_clk_a"), bram_en_a("bram_en_a"), bram_we_a("bram_we_a"), bram_addr_a("bram_addr_a"), bram_wrdata_a("bram_wrdata_a"), bram_rddata_a("bram_rddata_a")
|
||||
{
|
||||
|
||||
// initialize pins
|
||||
mp_impl->s_axi_aclk(s_axi_aclk);
|
||||
mp_impl->s_axi_aresetn(s_axi_aresetn);
|
||||
mp_impl->bram_rst_a(bram_rst_a);
|
||||
mp_impl->bram_clk_a(bram_clk_a);
|
||||
mp_impl->bram_en_a(bram_en_a);
|
||||
mp_impl->bram_we_a(bram_we_a);
|
||||
mp_impl->bram_addr_a(bram_addr_a);
|
||||
mp_impl->bram_wrdata_a(bram_wrdata_a);
|
||||
mp_impl->bram_rddata_a(bram_rddata_a);
|
||||
|
||||
// initialize transactors
|
||||
mp_S_AXI_transactor = NULL;
|
||||
|
||||
// initialize socket stubs
|
||||
|
||||
}
|
||||
|
||||
void system_top_axi_bram_ctrl_0_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'S_AXI' transactor
|
||||
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("system_top_axi_bram_ctrl_0_0", "S_AXI_TLM_MODE") != 1)
|
||||
{
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// 'S_AXI' transactor parameters
|
||||
xsc::common_cpp::properties S_AXI_transactor_param_props;
|
||||
S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_transactor_param_props.addLong("FREQ_HZ", "1e+08");
|
||||
S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "15");
|
||||
S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_QOS", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
|
||||
S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
|
||||
S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
|
||||
S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_transactor_param_props.addString("CLK_DOMAIN", "system_top_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
|
||||
|
||||
// S_AXI' transactor ports
|
||||
|
||||
mp_S_AXI_transactor->ARADDR(s_axi_araddr);
|
||||
mp_S_AXI_transactor->ARBURST(s_axi_arburst);
|
||||
mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
|
||||
mp_S_AXI_transactor->ARLEN(s_axi_arlen);
|
||||
mp_S_AXI_transactor->ARLOCK(s_axi_arlock);
|
||||
mp_S_AXI_transactor->ARPROT(s_axi_arprot);
|
||||
mp_S_AXI_transactor->ARREADY(s_axi_arready);
|
||||
mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
|
||||
mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
|
||||
mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
|
||||
mp_S_AXI_transactor->AWBURST(s_axi_awburst);
|
||||
mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
|
||||
mp_S_AXI_transactor->AWLEN(s_axi_awlen);
|
||||
mp_S_AXI_transactor->AWLOCK(s_axi_awlock);
|
||||
mp_S_AXI_transactor->AWPROT(s_axi_awprot);
|
||||
mp_S_AXI_transactor->AWREADY(s_axi_awready);
|
||||
mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
|
||||
mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
|
||||
mp_S_AXI_transactor->BREADY(s_axi_bready);
|
||||
mp_S_AXI_transactor->BRESP(s_axi_bresp);
|
||||
mp_S_AXI_transactor->BVALID(s_axi_bvalid);
|
||||
mp_S_AXI_transactor->RDATA(s_axi_rdata);
|
||||
mp_S_AXI_transactor->RLAST(s_axi_rlast);
|
||||
mp_S_AXI_transactor->RREADY(s_axi_rready);
|
||||
mp_S_AXI_transactor->RRESP(s_axi_rresp);
|
||||
mp_S_AXI_transactor->RVALID(s_axi_rvalid);
|
||||
mp_S_AXI_transactor->WDATA(s_axi_wdata);
|
||||
mp_S_AXI_transactor->WLAST(s_axi_wlast);
|
||||
mp_S_AXI_transactor->WREADY(s_axi_wready);
|
||||
mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
|
||||
mp_S_AXI_transactor->WVALID(s_axi_wvalid);
|
||||
mp_S_AXI_transactor->CLK(s_axi_aclk);
|
||||
mp_S_AXI_transactor->RST(s_axi_aresetn);
|
||||
|
||||
// S_AXI' transactor sockets
|
||||
|
||||
mp_impl->target_0_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_impl->target_0_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // XILINX_SIMULATOR
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
system_top_axi_bram_ctrl_0_0::system_top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm) : system_top_axi_bram_ctrl_0_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), bram_rst_a("bram_rst_a"), bram_clk_a("bram_clk_a"), bram_en_a("bram_en_a"), bram_we_a("bram_we_a"), bram_addr_a("bram_addr_a"), bram_wrdata_a("bram_wrdata_a"), bram_rddata_a("bram_rddata_a")
|
||||
{
|
||||
|
||||
// initialize pins
|
||||
mp_impl->s_axi_aclk(s_axi_aclk);
|
||||
mp_impl->s_axi_aresetn(s_axi_aresetn);
|
||||
mp_impl->bram_rst_a(bram_rst_a);
|
||||
mp_impl->bram_clk_a(bram_clk_a);
|
||||
mp_impl->bram_en_a(bram_en_a);
|
||||
mp_impl->bram_we_a(bram_we_a);
|
||||
mp_impl->bram_addr_a(bram_addr_a);
|
||||
mp_impl->bram_wrdata_a(bram_wrdata_a);
|
||||
mp_impl->bram_rddata_a(bram_rddata_a);
|
||||
|
||||
// initialize transactors
|
||||
mp_S_AXI_transactor = NULL;
|
||||
|
||||
// initialize socket stubs
|
||||
|
||||
}
|
||||
|
||||
void system_top_axi_bram_ctrl_0_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'S_AXI' transactor
|
||||
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("system_top_axi_bram_ctrl_0_0", "S_AXI_TLM_MODE") != 1)
|
||||
{
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// 'S_AXI' transactor parameters
|
||||
xsc::common_cpp::properties S_AXI_transactor_param_props;
|
||||
S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_transactor_param_props.addLong("FREQ_HZ", "1e+08");
|
||||
S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "15");
|
||||
S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_QOS", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
|
||||
S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
|
||||
S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
|
||||
S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_transactor_param_props.addString("CLK_DOMAIN", "system_top_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
|
||||
|
||||
// S_AXI' transactor ports
|
||||
|
||||
mp_S_AXI_transactor->ARADDR(s_axi_araddr);
|
||||
mp_S_AXI_transactor->ARBURST(s_axi_arburst);
|
||||
mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
|
||||
mp_S_AXI_transactor->ARLEN(s_axi_arlen);
|
||||
mp_S_AXI_transactor->ARLOCK(s_axi_arlock);
|
||||
mp_S_AXI_transactor->ARPROT(s_axi_arprot);
|
||||
mp_S_AXI_transactor->ARREADY(s_axi_arready);
|
||||
mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
|
||||
mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
|
||||
mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
|
||||
mp_S_AXI_transactor->AWBURST(s_axi_awburst);
|
||||
mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
|
||||
mp_S_AXI_transactor->AWLEN(s_axi_awlen);
|
||||
mp_S_AXI_transactor->AWLOCK(s_axi_awlock);
|
||||
mp_S_AXI_transactor->AWPROT(s_axi_awprot);
|
||||
mp_S_AXI_transactor->AWREADY(s_axi_awready);
|
||||
mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
|
||||
mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
|
||||
mp_S_AXI_transactor->BREADY(s_axi_bready);
|
||||
mp_S_AXI_transactor->BRESP(s_axi_bresp);
|
||||
mp_S_AXI_transactor->BVALID(s_axi_bvalid);
|
||||
mp_S_AXI_transactor->RDATA(s_axi_rdata);
|
||||
mp_S_AXI_transactor->RLAST(s_axi_rlast);
|
||||
mp_S_AXI_transactor->RREADY(s_axi_rready);
|
||||
mp_S_AXI_transactor->RRESP(s_axi_rresp);
|
||||
mp_S_AXI_transactor->RVALID(s_axi_rvalid);
|
||||
mp_S_AXI_transactor->WDATA(s_axi_wdata);
|
||||
mp_S_AXI_transactor->WLAST(s_axi_wlast);
|
||||
mp_S_AXI_transactor->WREADY(s_axi_wready);
|
||||
mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
|
||||
mp_S_AXI_transactor->WVALID(s_axi_wvalid);
|
||||
mp_S_AXI_transactor->CLK(s_axi_aclk);
|
||||
mp_S_AXI_transactor->RST(s_axi_aresetn);
|
||||
|
||||
// S_AXI' transactor sockets
|
||||
|
||||
mp_impl->target_0_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_impl->target_0_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // XM_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef RIVIERA
|
||||
system_top_axi_bram_ctrl_0_0::system_top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm) : system_top_axi_bram_ctrl_0_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), bram_rst_a("bram_rst_a"), bram_clk_a("bram_clk_a"), bram_en_a("bram_en_a"), bram_we_a("bram_we_a"), bram_addr_a("bram_addr_a"), bram_wrdata_a("bram_wrdata_a"), bram_rddata_a("bram_rddata_a")
|
||||
{
|
||||
|
||||
// initialize pins
|
||||
mp_impl->s_axi_aclk(s_axi_aclk);
|
||||
mp_impl->s_axi_aresetn(s_axi_aresetn);
|
||||
mp_impl->bram_rst_a(bram_rst_a);
|
||||
mp_impl->bram_clk_a(bram_clk_a);
|
||||
mp_impl->bram_en_a(bram_en_a);
|
||||
mp_impl->bram_we_a(bram_we_a);
|
||||
mp_impl->bram_addr_a(bram_addr_a);
|
||||
mp_impl->bram_wrdata_a(bram_wrdata_a);
|
||||
mp_impl->bram_rddata_a(bram_rddata_a);
|
||||
|
||||
// initialize transactors
|
||||
mp_S_AXI_transactor = NULL;
|
||||
|
||||
// initialize socket stubs
|
||||
|
||||
}
|
||||
|
||||
void system_top_axi_bram_ctrl_0_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'S_AXI' transactor
|
||||
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("system_top_axi_bram_ctrl_0_0", "S_AXI_TLM_MODE") != 1)
|
||||
{
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// 'S_AXI' transactor parameters
|
||||
xsc::common_cpp::properties S_AXI_transactor_param_props;
|
||||
S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_transactor_param_props.addLong("FREQ_HZ", "1e+08");
|
||||
S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "15");
|
||||
S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_QOS", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
|
||||
S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
|
||||
S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
|
||||
S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_transactor_param_props.addString("CLK_DOMAIN", "system_top_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
|
||||
|
||||
// S_AXI' transactor ports
|
||||
|
||||
mp_S_AXI_transactor->ARADDR(s_axi_araddr);
|
||||
mp_S_AXI_transactor->ARBURST(s_axi_arburst);
|
||||
mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
|
||||
mp_S_AXI_transactor->ARLEN(s_axi_arlen);
|
||||
mp_S_AXI_transactor->ARLOCK(s_axi_arlock);
|
||||
mp_S_AXI_transactor->ARPROT(s_axi_arprot);
|
||||
mp_S_AXI_transactor->ARREADY(s_axi_arready);
|
||||
mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
|
||||
mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
|
||||
mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
|
||||
mp_S_AXI_transactor->AWBURST(s_axi_awburst);
|
||||
mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
|
||||
mp_S_AXI_transactor->AWLEN(s_axi_awlen);
|
||||
mp_S_AXI_transactor->AWLOCK(s_axi_awlock);
|
||||
mp_S_AXI_transactor->AWPROT(s_axi_awprot);
|
||||
mp_S_AXI_transactor->AWREADY(s_axi_awready);
|
||||
mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
|
||||
mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
|
||||
mp_S_AXI_transactor->BREADY(s_axi_bready);
|
||||
mp_S_AXI_transactor->BRESP(s_axi_bresp);
|
||||
mp_S_AXI_transactor->BVALID(s_axi_bvalid);
|
||||
mp_S_AXI_transactor->RDATA(s_axi_rdata);
|
||||
mp_S_AXI_transactor->RLAST(s_axi_rlast);
|
||||
mp_S_AXI_transactor->RREADY(s_axi_rready);
|
||||
mp_S_AXI_transactor->RRESP(s_axi_rresp);
|
||||
mp_S_AXI_transactor->RVALID(s_axi_rvalid);
|
||||
mp_S_AXI_transactor->WDATA(s_axi_wdata);
|
||||
mp_S_AXI_transactor->WLAST(s_axi_wlast);
|
||||
mp_S_AXI_transactor->WREADY(s_axi_wready);
|
||||
mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
|
||||
mp_S_AXI_transactor->WVALID(s_axi_wvalid);
|
||||
mp_S_AXI_transactor->CLK(s_axi_aclk);
|
||||
mp_S_AXI_transactor->RST(s_axi_aresetn);
|
||||
|
||||
// S_AXI' transactor sockets
|
||||
|
||||
mp_impl->target_0_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_impl->target_0_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // RIVIERA
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef VCSSYSTEMC
|
||||
system_top_axi_bram_ctrl_0_0::system_top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm) : system_top_axi_bram_ctrl_0_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), bram_rst_a("bram_rst_a"), bram_clk_a("bram_clk_a"), bram_en_a("bram_en_a"), bram_we_a("bram_we_a"), bram_addr_a("bram_addr_a"), bram_wrdata_a("bram_wrdata_a"), bram_rddata_a("bram_rddata_a")
|
||||
{
|
||||
// initialize pins
|
||||
mp_impl->s_axi_aclk(s_axi_aclk);
|
||||
mp_impl->s_axi_aresetn(s_axi_aresetn);
|
||||
mp_impl->bram_rst_a(bram_rst_a);
|
||||
mp_impl->bram_clk_a(bram_clk_a);
|
||||
mp_impl->bram_en_a(bram_en_a);
|
||||
mp_impl->bram_we_a(bram_we_a);
|
||||
mp_impl->bram_addr_a(bram_addr_a);
|
||||
mp_impl->bram_wrdata_a(bram_wrdata_a);
|
||||
mp_impl->bram_rddata_a(bram_rddata_a);
|
||||
|
||||
// initialize transactors
|
||||
mp_S_AXI_transactor = NULL;
|
||||
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// configure S_AXI_transactor
|
||||
xsc::common_cpp::properties S_AXI_transactor_param_props;
|
||||
S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_transactor_param_props.addLong("FREQ_HZ", "1e+08");
|
||||
S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "15");
|
||||
S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_QOS", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
|
||||
S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
|
||||
S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
|
||||
S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_transactor_param_props.addString("CLK_DOMAIN", "system_top_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
|
||||
mp_S_AXI_transactor->ARADDR(s_axi_araddr);
|
||||
mp_S_AXI_transactor->ARBURST(s_axi_arburst);
|
||||
mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
|
||||
mp_S_AXI_transactor->ARLEN(s_axi_arlen);
|
||||
mp_S_AXI_transactor->ARLOCK(s_axi_arlock);
|
||||
mp_S_AXI_transactor->ARPROT(s_axi_arprot);
|
||||
mp_S_AXI_transactor->ARREADY(s_axi_arready);
|
||||
mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
|
||||
mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
|
||||
mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
|
||||
mp_S_AXI_transactor->AWBURST(s_axi_awburst);
|
||||
mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
|
||||
mp_S_AXI_transactor->AWLEN(s_axi_awlen);
|
||||
mp_S_AXI_transactor->AWLOCK(s_axi_awlock);
|
||||
mp_S_AXI_transactor->AWPROT(s_axi_awprot);
|
||||
mp_S_AXI_transactor->AWREADY(s_axi_awready);
|
||||
mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
|
||||
mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
|
||||
mp_S_AXI_transactor->BREADY(s_axi_bready);
|
||||
mp_S_AXI_transactor->BRESP(s_axi_bresp);
|
||||
mp_S_AXI_transactor->BVALID(s_axi_bvalid);
|
||||
mp_S_AXI_transactor->RDATA(s_axi_rdata);
|
||||
mp_S_AXI_transactor->RLAST(s_axi_rlast);
|
||||
mp_S_AXI_transactor->RREADY(s_axi_rready);
|
||||
mp_S_AXI_transactor->RRESP(s_axi_rresp);
|
||||
mp_S_AXI_transactor->RVALID(s_axi_rvalid);
|
||||
mp_S_AXI_transactor->WDATA(s_axi_wdata);
|
||||
mp_S_AXI_transactor->WLAST(s_axi_wlast);
|
||||
mp_S_AXI_transactor->WREADY(s_axi_wready);
|
||||
mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
|
||||
mp_S_AXI_transactor->WVALID(s_axi_wvalid);
|
||||
mp_S_AXI_transactor->CLK(s_axi_aclk);
|
||||
mp_S_AXI_transactor->RST(s_axi_aresetn);
|
||||
|
||||
// initialize transactors stubs
|
||||
S_AXI_transactor_target_wr_socket_stub = nullptr;
|
||||
S_AXI_transactor_target_rd_socket_stub = nullptr;
|
||||
|
||||
}
|
||||
|
||||
void system_top_axi_bram_ctrl_0_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'S_AXI' transactor
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("system_top_axi_bram_ctrl_0_0", "S_AXI_TLM_MODE") != 1)
|
||||
{
|
||||
mp_impl->target_0_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_impl->target_0_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
|
||||
S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
|
||||
S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_S_AXI_transactor->disable_transactor();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // VCSSYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
system_top_axi_bram_ctrl_0_0::system_top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm) : system_top_axi_bram_ctrl_0_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), bram_rst_a("bram_rst_a"), bram_clk_a("bram_clk_a"), bram_en_a("bram_en_a"), bram_we_a("bram_we_a"), bram_addr_a("bram_addr_a"), bram_wrdata_a("bram_wrdata_a"), bram_rddata_a("bram_rddata_a")
|
||||
{
|
||||
// initialize pins
|
||||
mp_impl->s_axi_aclk(s_axi_aclk);
|
||||
mp_impl->s_axi_aresetn(s_axi_aresetn);
|
||||
mp_impl->bram_rst_a(bram_rst_a);
|
||||
mp_impl->bram_clk_a(bram_clk_a);
|
||||
mp_impl->bram_en_a(bram_en_a);
|
||||
mp_impl->bram_we_a(bram_we_a);
|
||||
mp_impl->bram_addr_a(bram_addr_a);
|
||||
mp_impl->bram_wrdata_a(bram_wrdata_a);
|
||||
mp_impl->bram_rddata_a(bram_rddata_a);
|
||||
|
||||
// initialize transactors
|
||||
mp_S_AXI_transactor = NULL;
|
||||
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// configure S_AXI_transactor
|
||||
xsc::common_cpp::properties S_AXI_transactor_param_props;
|
||||
S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_transactor_param_props.addLong("FREQ_HZ", "1e+08");
|
||||
S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "15");
|
||||
S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_QOS", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
|
||||
S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
|
||||
S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
|
||||
S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
|
||||
S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_transactor_param_props.addString("CLK_DOMAIN", "system_top_processing_system7_0_0_FCLK_CLK0");
|
||||
|
||||
mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
|
||||
mp_S_AXI_transactor->ARADDR(s_axi_araddr);
|
||||
mp_S_AXI_transactor->ARBURST(s_axi_arburst);
|
||||
mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
|
||||
mp_S_AXI_transactor->ARLEN(s_axi_arlen);
|
||||
mp_S_AXI_transactor->ARLOCK(s_axi_arlock);
|
||||
mp_S_AXI_transactor->ARPROT(s_axi_arprot);
|
||||
mp_S_AXI_transactor->ARREADY(s_axi_arready);
|
||||
mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
|
||||
mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
|
||||
mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
|
||||
mp_S_AXI_transactor->AWBURST(s_axi_awburst);
|
||||
mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
|
||||
mp_S_AXI_transactor->AWLEN(s_axi_awlen);
|
||||
mp_S_AXI_transactor->AWLOCK(s_axi_awlock);
|
||||
mp_S_AXI_transactor->AWPROT(s_axi_awprot);
|
||||
mp_S_AXI_transactor->AWREADY(s_axi_awready);
|
||||
mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
|
||||
mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
|
||||
mp_S_AXI_transactor->BREADY(s_axi_bready);
|
||||
mp_S_AXI_transactor->BRESP(s_axi_bresp);
|
||||
mp_S_AXI_transactor->BVALID(s_axi_bvalid);
|
||||
mp_S_AXI_transactor->RDATA(s_axi_rdata);
|
||||
mp_S_AXI_transactor->RLAST(s_axi_rlast);
|
||||
mp_S_AXI_transactor->RREADY(s_axi_rready);
|
||||
mp_S_AXI_transactor->RRESP(s_axi_rresp);
|
||||
mp_S_AXI_transactor->RVALID(s_axi_rvalid);
|
||||
mp_S_AXI_transactor->WDATA(s_axi_wdata);
|
||||
mp_S_AXI_transactor->WLAST(s_axi_wlast);
|
||||
mp_S_AXI_transactor->WREADY(s_axi_wready);
|
||||
mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
|
||||
mp_S_AXI_transactor->WVALID(s_axi_wvalid);
|
||||
mp_S_AXI_transactor->CLK(s_axi_aclk);
|
||||
mp_S_AXI_transactor->RST(s_axi_aresetn);
|
||||
|
||||
// initialize transactors stubs
|
||||
S_AXI_transactor_target_wr_socket_stub = nullptr;
|
||||
S_AXI_transactor_target_rd_socket_stub = nullptr;
|
||||
|
||||
}
|
||||
|
||||
void system_top_axi_bram_ctrl_0_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'S_AXI' transactor
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("system_top_axi_bram_ctrl_0_0", "S_AXI_TLM_MODE") != 1)
|
||||
{
|
||||
mp_impl->target_0_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_impl->target_0_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
|
||||
S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
|
||||
S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_S_AXI_transactor->disable_transactor();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // MTI_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
system_top_axi_bram_ctrl_0_0::~system_top_axi_bram_ctrl_0_0()
|
||||
{
|
||||
delete mp_S_AXI_transactor;
|
||||
|
||||
}
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
SC_MODULE_EXPORT(system_top_axi_bram_ctrl_0_0);
|
||||
#endif
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
XMSC_MODULE_EXPORT(system_top_axi_bram_ctrl_0_0);
|
||||
#endif
|
||||
|
||||
#ifdef RIVIERA
|
||||
SC_MODULE_EXPORT(system_top_axi_bram_ctrl_0_0);
|
||||
#endif
|
||||
|
||||
+425
@@ -0,0 +1,425 @@
|
||||
#ifndef IP_SYSTEM_TOP_AXI_BRAM_CTRL_0_0_H_
|
||||
#define IP_SYSTEM_TOP_AXI_BRAM_CTRL_0_0_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
#include "system_top_axi_bram_ctrl_0_0_sc.h"
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XILINX_SIMULATOR
|
||||
class DllExport system_top_axi_bram_ctrl_0_0 : public system_top_axi_bram_ctrl_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_top_axi_bram_ctrl_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< bool > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< bool > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< bool > bram_rst_a;
|
||||
sc_core::sc_out< bool > bram_clk_a;
|
||||
sc_core::sc_out< bool > bram_en_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > bram_addr_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_a;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_a;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // XILINX_SIMULATOR
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
class DllExport system_top_axi_bram_ctrl_0_0 : public system_top_axi_bram_ctrl_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_top_axi_bram_ctrl_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< bool > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< bool > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< bool > bram_rst_a;
|
||||
sc_core::sc_out< bool > bram_clk_a;
|
||||
sc_core::sc_out< bool > bram_en_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > bram_addr_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_a;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_a;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // XM_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef RIVIERA
|
||||
class DllExport system_top_axi_bram_ctrl_0_0 : public system_top_axi_bram_ctrl_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_top_axi_bram_ctrl_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< bool > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< bool > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< bool > bram_rst_a;
|
||||
sc_core::sc_out< bool > bram_clk_a;
|
||||
sc_core::sc_out< bool > bram_en_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > bram_addr_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_a;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_a;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // RIVIERA
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef VCSSYSTEMC
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport system_top_axi_bram_ctrl_0_0 : public system_top_axi_bram_ctrl_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_top_axi_bram_ctrl_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< bool > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< bool > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< bool > bram_rst_a;
|
||||
sc_core::sc_out< bool > bram_clk_a;
|
||||
sc_core::sc_out< bool > bram_en_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > bram_addr_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_a;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_a;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // VCSSYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport system_top_axi_bram_ctrl_0_0 : public system_top_axi_bram_ctrl_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
system_top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_top_axi_bram_ctrl_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< bool > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<15> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< bool > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< bool > bram_rst_a;
|
||||
sc_core::sc_out< bool > bram_clk_a;
|
||||
sc_core::sc_out< bool > bram_en_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > bram_addr_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_a;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_a;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,15,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // MTI_SYSTEMC
|
||||
#endif // IP_SYSTEM_TOP_AXI_BRAM_CTRL_0_0_H_
|
||||
+322
@@ -0,0 +1,322 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.1
|
||||
-- IP Revision: 10
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_bram_ctrl_v4_1_10;
|
||||
USE axi_bram_ctrl_v4_1_10.axi_bram_ctrl;
|
||||
|
||||
ENTITY system_top_axi_bram_ctrl_0_0 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_awlock : IN STD_LOGIC;
|
||||
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wlast : IN STD_LOGIC;
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_arlock : IN STD_LOGIC;
|
||||
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rlast : OUT STD_LOGIC;
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
bram_rst_a : OUT STD_LOGIC;
|
||||
bram_clk_a : OUT STD_LOGIC;
|
||||
bram_en_a : OUT STD_LOGIC;
|
||||
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_a : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END system_top_axi_bram_ctrl_0_0;
|
||||
|
||||
ARCHITECTURE system_top_axi_bram_ctrl_0_0_arch OF system_top_axi_bram_ctrl_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_top_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_bram_ctrl IS
|
||||
GENERIC (
|
||||
C_BRAM_INST_MODE : STRING;
|
||||
C_MEMORY_DEPTH : INTEGER;
|
||||
C_BRAM_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_S_AXI_ID_WIDTH : INTEGER;
|
||||
C_S_AXI_PROTOCOL : STRING;
|
||||
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
|
||||
C_SINGLE_PORT_BRAM : INTEGER;
|
||||
C_FAMILY : STRING;
|
||||
C_READ_LATENCY : INTEGER;
|
||||
C_RD_CMD_OPTIMIZATION : INTEGER;
|
||||
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
|
||||
C_ECC : INTEGER;
|
||||
C_ECC_TYPE : INTEGER;
|
||||
C_FAULT_INJECT : INTEGER;
|
||||
C_ECC_ONOFF_RESET_VALUE : INTEGER
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
ecc_interrupt : OUT STD_LOGIC;
|
||||
ecc_ue : OUT STD_LOGIC;
|
||||
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_awlock : IN STD_LOGIC;
|
||||
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wlast : IN STD_LOGIC;
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_arlock : IN STD_LOGIC;
|
||||
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rlast : OUT STD_LOGIC;
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
s_axi_ctrl_awvalid : IN STD_LOGIC;
|
||||
s_axi_ctrl_awready : OUT STD_LOGIC;
|
||||
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_wvalid : IN STD_LOGIC;
|
||||
s_axi_ctrl_wready : OUT STD_LOGIC;
|
||||
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_ctrl_bvalid : OUT STD_LOGIC;
|
||||
s_axi_ctrl_bready : IN STD_LOGIC;
|
||||
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_arvalid : IN STD_LOGIC;
|
||||
s_axi_ctrl_arready : OUT STD_LOGIC;
|
||||
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_ctrl_rvalid : OUT STD_LOGIC;
|
||||
s_axi_ctrl_rready : IN STD_LOGIC;
|
||||
bram_rst_a : OUT STD_LOGIC;
|
||||
bram_clk_a : OUT STD_LOGIC;
|
||||
bram_en_a : OUT STD_LOGIC;
|
||||
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_a : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rst_b : OUT STD_LOGIC;
|
||||
bram_clk_b : OUT STD_LOGIC;
|
||||
bram_en_b : OUT STD_LOGIC;
|
||||
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_b : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_bram_ctrl;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bram_rst_a: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTA, MASTER_TYPE BRAM_CTRL, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXI:S_AXI_CTRL, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 15, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN system_top_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, " &
|
||||
"NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
BEGIN
|
||||
U0 : axi_bram_ctrl
|
||||
GENERIC MAP (
|
||||
C_BRAM_INST_MODE => "EXTERNAL",
|
||||
C_MEMORY_DEPTH => 8192,
|
||||
C_BRAM_ADDR_WIDTH => 13,
|
||||
C_S_AXI_ADDR_WIDTH => 15,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_S_AXI_ID_WIDTH => 1,
|
||||
C_S_AXI_PROTOCOL => "AXI4",
|
||||
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
|
||||
C_SINGLE_PORT_BRAM => 1,
|
||||
C_FAMILY => "zynq",
|
||||
C_READ_LATENCY => 1,
|
||||
C_RD_CMD_OPTIMIZATION => 0,
|
||||
C_S_AXI_CTRL_ADDR_WIDTH => 32,
|
||||
C_S_AXI_CTRL_DATA_WIDTH => 32,
|
||||
C_ECC => 0,
|
||||
C_ECC_TYPE => 0,
|
||||
C_FAULT_INJECT => 0,
|
||||
C_ECC_ONOFF_RESET_VALUE => 0
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awlen => s_axi_awlen,
|
||||
s_axi_awsize => s_axi_awsize,
|
||||
s_axi_awburst => s_axi_awburst,
|
||||
s_axi_awlock => s_axi_awlock,
|
||||
s_axi_awcache => s_axi_awcache,
|
||||
s_axi_awprot => s_axi_awprot,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wlast => s_axi_wlast,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arlen => s_axi_arlen,
|
||||
s_axi_arsize => s_axi_arsize,
|
||||
s_axi_arburst => s_axi_arburst,
|
||||
s_axi_arlock => s_axi_arlock,
|
||||
s_axi_arcache => s_axi_arcache,
|
||||
s_axi_arprot => s_axi_arprot,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rlast => s_axi_rlast,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
s_axi_ctrl_awvalid => '0',
|
||||
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_ctrl_wvalid => '0',
|
||||
s_axi_ctrl_bready => '0',
|
||||
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_ctrl_arvalid => '0',
|
||||
s_axi_ctrl_rready => '0',
|
||||
bram_rst_a => bram_rst_a,
|
||||
bram_clk_a => bram_clk_a,
|
||||
bram_en_a => bram_en_a,
|
||||
bram_we_a => bram_we_a,
|
||||
bram_addr_a => bram_addr_a,
|
||||
bram_wrdata_a => bram_wrdata_a,
|
||||
bram_rddata_a => bram_rddata_a,
|
||||
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
|
||||
);
|
||||
END system_top_axi_bram_ctrl_0_0_arch;
|
||||
+97
@@ -0,0 +1,97 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#include "system_top_axi_bram_ctrl_0_0_sc.h"
|
||||
|
||||
#include "axi_bram_ctrl.h"
|
||||
|
||||
#include <map>
|
||||
#include <string>
|
||||
|
||||
system_top_axi_bram_ctrl_0_0_sc::system_top_axi_bram_ctrl_0_0_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
|
||||
{
|
||||
// configure connectivity manager
|
||||
xsc::utils::xsc_sim_manager::addInstance("system_top_axi_bram_ctrl_0_0", this);
|
||||
|
||||
// initialize module
|
||||
xsc::common_cpp::properties model_param_props;
|
||||
model_param_props.addLong("C_MEMORY_DEPTH", "8192");
|
||||
model_param_props.addLong("C_BRAM_ADDR_WIDTH", "13");
|
||||
model_param_props.addLong("C_S_AXI_ADDR_WIDTH", "15");
|
||||
model_param_props.addLong("C_S_AXI_DATA_WIDTH", "32");
|
||||
model_param_props.addLong("C_S_AXI_ID_WIDTH", "1");
|
||||
model_param_props.addLong("C_S_AXI_SUPPORTS_NARROW_BURST", "0");
|
||||
model_param_props.addLong("C_SINGLE_PORT_BRAM", "1");
|
||||
model_param_props.addLong("C_READ_LATENCY", "1");
|
||||
model_param_props.addLong("C_RD_CMD_OPTIMIZATION", "0");
|
||||
model_param_props.addLong("C_S_AXI_CTRL_ADDR_WIDTH", "32");
|
||||
model_param_props.addLong("C_S_AXI_CTRL_DATA_WIDTH", "32");
|
||||
model_param_props.addLong("C_ECC", "0");
|
||||
model_param_props.addLong("C_ECC_TYPE", "0");
|
||||
model_param_props.addLong("C_FAULT_INJECT", "0");
|
||||
model_param_props.addLong("C_ECC_ONOFF_RESET_VALUE", "0");
|
||||
model_param_props.addString("C_BRAM_INST_MODE", "EXTERNAL");
|
||||
model_param_props.addString("C_S_AXI_PROTOCOL", "AXI4");
|
||||
model_param_props.addString("C_FAMILY", "zynq");
|
||||
model_param_props.addString("COMPONENT_NAME", "system_top_axi_bram_ctrl_0_0");
|
||||
|
||||
mp_impl = new axi_bram_ctrl("inst", model_param_props);
|
||||
|
||||
// initialize AXI sockets
|
||||
target_0_rd_socket = mp_impl->target_0_rd_socket;
|
||||
target_0_wr_socket = mp_impl->target_0_wr_socket;
|
||||
}
|
||||
|
||||
system_top_axi_bram_ctrl_0_0_sc::~system_top_axi_bram_ctrl_0_0_sc()
|
||||
{
|
||||
xsc::utils::xsc_sim_manager::clean();
|
||||
|
||||
delete mp_impl;
|
||||
}
|
||||
|
||||
+96
@@ -0,0 +1,96 @@
|
||||
#ifndef IP_SYSTEM_TOP_AXI_BRAM_CTRL_0_0_SC_H_
|
||||
#define IP_SYSTEM_TOP_AXI_BRAM_CTRL_0_0_SC_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
class axi_bram_ctrl;
|
||||
|
||||
class DllExport system_top_axi_bram_ctrl_0_0_sc : public sc_core::sc_module
|
||||
{
|
||||
public:
|
||||
|
||||
system_top_axi_bram_ctrl_0_0_sc(const sc_core::sc_module_name& nm);
|
||||
virtual ~system_top_axi_bram_ctrl_0_0_sc();
|
||||
|
||||
// module socket-to-socket AXI TLM interfaces
|
||||
|
||||
xtlm::xtlm_aximm_target_socket* target_0_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* target_0_wr_socket;
|
||||
|
||||
// module socket-to-socket TLM interfaces
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
axi_bram_ctrl* mp_impl;
|
||||
|
||||
private:
|
||||
|
||||
system_top_axi_bram_ctrl_0_0_sc(const system_top_axi_bram_ctrl_0_0_sc&);
|
||||
const system_top_axi_bram_ctrl_0_0_sc& operator=(const system_top_axi_bram_ctrl_0_0_sc&);
|
||||
|
||||
};
|
||||
|
||||
#endif // IP_SYSTEM_TOP_AXI_BRAM_CTRL_0_0_SC_H_
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user