900 lines
48 KiB
XML
900 lines
48 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2024.1.2 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
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<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
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<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Workspace/vivado/brd_cx2161a/cx9261a_demo_cmos_20240513/project_fix_dac.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="52f114a9469d466e8cbcc0af3c2d58cd"/>
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<Option Name="Part" Val="xc7z045ffg900-2"/>
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<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
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<Option Name="CompiledLibDirXSim" Val=""/>
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<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
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|
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
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|
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
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|
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
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<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
|
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
|
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
|
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
|
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
|
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
|
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
|
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
|
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
|
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
|
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
|
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
|
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
|
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
|
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
|
|
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
|
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
|
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
|
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
|
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
|
|
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
|
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
|
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
|
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
|
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
|
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
|
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
|
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
|
<Option Name="BoardPart" Val="xilinx.com:zc706:part0:1.4"/>
|
|
<Option Name="ActiveSimSet" Val="sim_1"/>
|
|
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
|
<Option Name="ProjectType" Val="Default"/>
|
|
<Option Name="IPRepoPath" Val="$PPRDIR/ip_repo"/>
|
|
<Option Name="IPRepoPath" Val="$PSRCDIR/sources_1/user_ip"/>
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|
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
|
<Option Name="IPCachePermission" Val="read"/>
|
|
<Option Name="IPCachePermission" Val="write"/>
|
|
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
|
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
|
<Option Name="SimCompileState" Val="TRUE"/>
|
|
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
|
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
|
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
|
<Option Name="EnableBDX" Val="FALSE"/>
|
|
<Option Name="DSABoardId" Val="zc706"/>
|
|
<Option Name="WTXSimLaunchSim" Val="2"/>
|
|
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
|
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
|
<Option Name="WTIesLaunchSim" Val="0"/>
|
|
<Option Name="WTVcsLaunchSim" Val="0"/>
|
|
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
|
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
|
<Option Name="WTXSimExportSim" Val="48"/>
|
|
<Option Name="WTModelSimExportSim" Val="48"/>
|
|
<Option Name="WTQuestaExportSim" Val="48"/>
|
|
<Option Name="WTIesExportSim" Val="39"/>
|
|
<Option Name="WTVcsExportSim" Val="48"/>
|
|
<Option Name="WTRivieraExportSim" Val="48"/>
|
|
<Option Name="WTActivehdlExportSim" Val="48"/>
|
|
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
|
<Option Name="XSimRadix" Val="hex"/>
|
|
<Option Name="XSimTimeUnit" Val="ns"/>
|
|
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
|
<Option Name="XSimTraceLimit" Val="65536"/>
|
|
<Option Name="SimTypes" Val="rtl"/>
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<Option Name="SimTypes" Val="bfm"/>
|
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<Option Name="SimTypes" Val="tlm"/>
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<Option Name="SimTypes" Val="tlm_dpi"/>
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<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
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<Option Name="DcpsUptoDate" Val="TRUE"/>
|
|
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
|
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
|
</Configuration>
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<FileSets Version="1" Minor="32">
|
|
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
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<Filter Type="Srcs"/>
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<File Path="$PSRCDIR/sources_1/ip/vio_hop/vio_hop.xci">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/vio_hop/vio_hop.xci"/>
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<Attr Name="ImportTime" Val="1730303230"/>
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|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/ip/hrc_128_12_03/hrc_128_12_03.xci">
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|
<FileInfo>
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|
<Attr Name="ImportPath" Val="$PPRDIR/../zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/hrc_128_12_03/hrc_128_12_03.xci"/>
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<Attr Name="ImportTime" Val="1730437422"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/ip/hrc_16_12_03/hrc_16_12_03.xci">
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|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/hrc_16_12_03/hrc_16_12_03.xci"/>
|
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<Attr Name="ImportTime" Val="1730437382"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/ip/hrc_4_12_03/hrc_4_12_03.xci">
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|
<FileInfo>
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|
<Attr Name="ImportPath" Val="$PPRDIR/../zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/hrc_4_12_03/hrc_4_12_03.xci"/>
|
|
<Attr Name="ImportTime" Val="1730437339"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/ip/sys_clk_gen/sys_clk_gen.xci">
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<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/sys_clk_gen/sys_clk_gen.xci"/>
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|
<Attr Name="ImportTime" Val="1730446352"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/imports/sources_1/new/cx9261a_if.v">
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<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../IF_SIM/project_1/project_1.srcs/sources_1/new/cx9261a_if.v"/>
|
|
<Attr Name="ImportTime" Val="1653613371"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/imports/sources_1/imports/IF_SIM/cx9261a_if_cmos_port.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/imports/sources_1/imports/IF_SIM/cx9261a_if_cmos_singleport.v">
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|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../IF_SIM/project_1/project_1.srcs/sources_1/imports/IF_SIM/cx9261a_if_cmos_singleport.v"/>
|
|
<Attr Name="ImportTime" Val="1653462507"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/iobuf.v">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../project_1/project_1.srcs/sources_1/new/iobuf.v"/>
|
|
<Attr Name="ImportTime" Val="1652767376"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/mclk_delay.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/imports/new/tx_qpsk_v1.v">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/new/tx_qpsk_v1.v"/>
|
|
<Attr Name="ImportTime" Val="1730438490"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/CX9261A_ZC706.v">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../project_1/project_1.srcs/sources_1/new/CX9261A_ZC706.v"/>
|
|
<Attr Name="ImportTime" Val="1652850441"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/CX9261A_hop_intr.v">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/tx_qpsk.v">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/ip/clk_wiz_0/clk_wiz_0.xci">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/CX9261A_debug.v">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/bd/system_top/hdl/system_top_wrapper.v">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../project_1/project_1.srcs/sources_1/bd/system_top/hdl/system_top_wrapper.v"/>
|
|
<Attr Name="ImportTime" Val="1652852687"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/bd/system_top/ip/system_top_mig_7series_0_0/board.prj">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="ScopedToCell" Val="system_top_mig_7series_0_0"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PPRDIR/rom_data/qec_all_20230823.coe">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PPRDIR/rom_data/RxMultiPointsQEC.coe">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PPRDIR/rom_data/dpd_test1.coe">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/ip/coe/hrc_64_12_025.coe">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/ip/coe/sweep_freq.coe">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/ip/coe/hrc_16_12_03.coe">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/ip/coe/hrc_128_12_03.coe">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/ip/coe/hrc_4_12_03.coe">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="DesignMode" Val="RTL"/>
|
|
<Option Name="TopModule" Val="CX9261A_ZC706"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
|
<Filter Type="Constrs"/>
|
|
<File Path="$PSRCDIR/constrs_1/new/cx9261a_zc706.xdc">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../project_1/project_1.srcs/constrs_1/new/cx9261a_zc706.xdc"/>
|
|
<Attr Name="ImportTime" Val="1652838010"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/constrs_1/new/dbg.xdc">
|
|
<FileInfo>
|
|
<Attr Name="UserDisabled" Val="1"/>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../project_1/project_1.srcs/constrs_1/new/dbg.xdc"/>
|
|
<Attr Name="ImportTime" Val="1652841228"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/constrs_1/new/cx9621a_dbg.xdc">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/constrs_1/new/cx9621a_dbg2.xdc">
|
|
<FileInfo>
|
|
<Attr Name="UserDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/cx9621a_dbg.xdc"/>
|
|
<Option Name="ConstrsType" Val="XDC"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
|
<Filter Type="Srcs"/>
|
|
<File Path="$PSRCDIR/sim_1/new/tb.v">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../project_add_rx_dma/project_add_rx_dma.srcs/sim_1/new/tb.v"/>
|
|
<Attr Name="ImportTime" Val="1652938041"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="DesignMode" Val="RTL"/>
|
|
<Option Name="TopModule" Val="tb"/>
|
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
|
<Option Name="TransportPathDelay" Val="0"/>
|
|
<Option Name="TransportIntDelay" Val="0"/>
|
|
<Option Name="SelectedSimModel" Val="rtl"/>
|
|
<Option Name="PamDesignTestbench" Val=""/>
|
|
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
|
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
|
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
|
<Option Name="SrcSet" Val="sources_1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
|
<Filter Type="Utils"/>
|
|
<Config>
|
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="system_top" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_top">
|
|
<File Path="$PSRCDIR/sources_1/bd/system_top/system_top.bd">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../../../cx9261a_v2/project_eth_single1r1t_3r2t_bd/project_eth_single1r1t.srcs/sources_1/bd/system_top/system_top.bd"/>
|
|
<Attr Name="ImportTime" Val="1655090882"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="system_top"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="vio_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_1">
|
|
<File Path="$PSRCDIR/sources_1/ip/vio_1/vio_1.xci">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="vio_1"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="vio_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_0">
|
|
<File Path="$PSRCDIR/sources_1/ip/vio_0/vio_0.xci">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="vio_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="blk_mem_gen_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/blk_mem_gen_0">
|
|
<File Path="$PSRCDIR/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0.xci">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="blk_mem_gen_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="ila_trx" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_trx">
|
|
<File Path="$PSRCDIR/sources_1/ip/ila_trx/ila_trx.xci">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="ila_trx"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="cmpy_18x8" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cmpy_18x8">
|
|
<File Path="$PSRCDIR/sources_1/ip/cmpy_18x8/cmpy_18x8.xci">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="cmpy_18x8"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="hrc_64_12_025" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hrc_64_12_025">
|
|
<File Path="$PSRCDIR/sources_1/ip/hrc_64_12_025/hrc_64_12_025.xci">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="hrc_64_12_025"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="dds_32b_8b" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dds_32b_8b">
|
|
<File Path="$PSRCDIR/sources_1/ip/dds_32b_8b/dds_32b_8b.xci">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="dds_32b_8b"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="hop_rom" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hop_rom">
|
|
<File Path="$PSRCDIR/sources_1/ip/hop_rom/hop_rom.xci">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="hop_rom"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="vio_manual_ctrl" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_manual_ctrl">
|
|
<File Path="$PSRCDIR/sources_1/ip/vio_manual_ctrl/vio_manual_ctrl.xci">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="vio_manual_ctrl"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="cx9261a_fifo" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cx9261a_fifo">
|
|
<File Path="$PSRCDIR/sources_1/ip/cx9261a_fifo/cx9261a_fifo.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/ip/cx9261a_fifo/cx9261a_fifo.xci"/>
|
|
<Attr Name="ImportTime" Val="1730446661"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="cx9261a_fifo"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
</FileSets>
|
|
<Simulators>
|
|
<Simulator Name="XSim">
|
|
<Option Name="Description" Val="Vivado Simulator"/>
|
|
<Option Name="CompiledLib" Val="0"/>
|
|
</Simulator>
|
|
<Simulator Name="ModelSim">
|
|
<Option Name="Description" Val="ModelSim Simulator"/>
|
|
</Simulator>
|
|
<Simulator Name="Questa">
|
|
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
|
</Simulator>
|
|
<Simulator Name="Xcelium">
|
|
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
|
</Simulator>
|
|
<Simulator Name="VCS">
|
|
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
|
</Simulator>
|
|
<Simulator Name="Riviera">
|
|
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
|
</Simulator>
|
|
</Simulators>
|
|
<Runs Version="1" Minor="22">
|
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z045ffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_top_synth_1" Type="Ft3:Synth" SrcSet="system_top" Part="xc7z045ffg900-2" ConstrsSet="system_top" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_top_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_top_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_top_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="vio_1_synth_1" Type="Ft3:Synth" SrcSet="vio_1" Part="xc7z045ffg900-2" ConstrsSet="vio_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_1_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="vio_0_synth_1" Type="Ft3:Synth" SrcSet="vio_0" Part="xc7z045ffg900-2" ConstrsSet="vio_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_0_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="blk_mem_gen_0_synth_1" Type="Ft3:Synth" SrcSet="blk_mem_gen_0" Part="xc7z045ffg900-2" ConstrsSet="blk_mem_gen_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/blk_mem_gen_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/blk_mem_gen_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/blk_mem_gen_0_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ila_trx_synth_1" Type="Ft3:Synth" SrcSet="ila_trx" Part="xc7z045ffg900-2" ConstrsSet="ila_trx" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_trx_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_trx_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_trx_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="cmpy_18x8_synth_1" Type="Ft3:Synth" SrcSet="cmpy_18x8" Part="xc7z045ffg900-2" ConstrsSet="cmpy_18x8" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/cmpy_18x8_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_18x8_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_18x8_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="hrc_64_12_025_synth_1" Type="Ft3:Synth" SrcSet="hrc_64_12_025" Part="xc7z045ffg900-2" ConstrsSet="hrc_64_12_025" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hrc_64_12_025_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="dds_32b_8b_synth_1" Type="Ft3:Synth" SrcSet="dds_32b_8b" Part="xc7z045ffg900-2" ConstrsSet="dds_32b_8b" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dds_32b_8b_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dds_32b_8b_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dds_32b_8b_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="hop_rom_synth_1" Type="Ft3:Synth" SrcSet="hop_rom" Part="xc7z045ffg900-2" ConstrsSet="hop_rom" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hop_rom_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hop_rom_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hop_rom_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="vio_manual_ctrl_synth_1" Type="Ft3:Synth" SrcSet="vio_manual_ctrl" Part="xc7z045ffg900-2" ConstrsSet="vio_manual_ctrl" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_manual_ctrl_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="cx9261a_fifo_synth_1" Type="Ft3:Synth" SrcSet="cx9261a_fifo" Part="xc7z045ffg900-2" ConstrsSet="cx9261a_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/cx9261a_fifo_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cx9261a_fifo_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cx9261a_fifo_synth_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 16 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream">
|
|
<Option Id="BinFile">1</Option>
|
|
</Step>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="system_top_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="system_top" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_top_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_top_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_top_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="vio_1_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="vio_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_1_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="vio_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="vio_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_0_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="blk_mem_gen_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="blk_mem_gen_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="blk_mem_gen_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/blk_mem_gen_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/blk_mem_gen_0_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="ila_trx_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="ila_trx" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_trx_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_trx_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_trx_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="cmpy_18x8_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="cmpy_18x8" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="cmpy_18x8_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_18x8_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_18x8_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="hrc_64_12_025_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="hrc_64_12_025" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hrc_64_12_025_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="dds_32b_8b_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="dds_32b_8b" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="dds_32b_8b_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dds_32b_8b_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dds_32b_8b_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="hop_rom_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="hop_rom" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hop_rom_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hop_rom_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hop_rom_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="vio_manual_ctrl_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="vio_manual_ctrl" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_manual_ctrl_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
<Run Id="cx9261a_fifo_impl_1" Type="Ft2:EntireDesign" Part="xc7z045ffg900-2" ConstrsSet="cx9261a_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="cx9261a_fifo_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cx9261a_fifo_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cx9261a_fifo_impl_1" ParallelReportGen="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
<RQSFiles/>
|
|
</Run>
|
|
</Runs>
|
|
<Board>
|
|
<Jumpers/>
|
|
</Board>
|
|
<DashboardSummary Version="1" Minor="0">
|
|
<Dashboards>
|
|
<Dashboard Name="default_dashboard">
|
|
<Gadgets>
|
|
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
|
</Gadget>
|
|
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
|
</Gadget>
|
|
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
|
</Gadget>
|
|
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
|
</Gadget>
|
|
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
|
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
|
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
|
</Gadget>
|
|
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
|
</Gadget>
|
|
</Gadgets>
|
|
</Dashboard>
|
|
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
|
</Dashboards>
|
|
</DashboardSummary>
|
|
</Project>
|