78aa37a57878361862c93a8cfba67d461893da1f
upgrade to 2024.1.2; add hop signal to spi ila (#5); change hop control clock; add async clock domain
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3.5 GiB
Languages
VHDL
87.2%
Verilog
4%
SystemVerilog
3.3%
Coq
2.3%
C
1.4%
Other
1.7%