fix: 修改mts sysref生成方式;修改real-time nco驱动时钟;移除xcix文件
1. mts时钟在bd中生成会造成rx信号出现大量毛刺,改为单独模块后rx采样正常; 2. real-time nco由s_axi_aclk也即ps时钟驱动,而非数据接口的时钟,否则会导致时序问题; 3. 原工程部分ip使用core container,现已全部disable
This commit is contained in:
@@ -10,7 +10,8 @@
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{
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"type": "XSDB_V3",
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"name": "dbg_hub",
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"spec": "labtools_xsdbm_v3"
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"spec": "labtools_xsdbm_v3",
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"clk_input_freq_hz": "200000001"
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},
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{
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"type": "ILA_V3",
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@@ -1933,109 +1934,13 @@
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"direction": "OUT",
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"isVector": true,
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"leftIndex": 0,
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"rightIndex": 47,
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"rightIndex": 15,
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"portIndex": 2,
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"nets": [
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{
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"name": "vio_hop_freq",
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"isBus": true,
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"subnets": [
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{
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"name": "vio_hop_freq[47]"
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},
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{
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"name": "vio_hop_freq[46]"
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},
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{
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"name": "vio_hop_freq[45]"
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},
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{
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"name": "vio_hop_freq[44]"
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},
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{
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"name": "vio_hop_freq[43]"
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},
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{
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"name": "vio_hop_freq[42]"
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},
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{
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"name": "vio_hop_freq[41]"
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},
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{
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"name": "vio_hop_freq[40]"
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},
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{
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"name": "vio_hop_freq[39]"
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},
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{
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"name": "vio_hop_freq[38]"
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},
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{
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"name": "vio_hop_freq[37]"
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},
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{
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"name": "vio_hop_freq[36]"
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},
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{
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"name": "vio_hop_freq[35]"
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},
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{
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"name": "vio_hop_freq[34]"
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},
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{
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"name": "vio_hop_freq[33]"
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},
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{
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"name": "vio_hop_freq[32]"
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},
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{
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"name": "vio_hop_freq[31]"
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},
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{
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"name": "vio_hop_freq[30]"
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},
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{
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"name": "vio_hop_freq[29]"
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},
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{
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"name": "vio_hop_freq[28]"
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},
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{
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"name": "vio_hop_freq[27]"
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},
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{
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"name": "vio_hop_freq[26]"
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},
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{
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"name": "vio_hop_freq[25]"
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},
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{
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"name": "vio_hop_freq[24]"
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},
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{
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"name": "vio_hop_freq[23]"
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},
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{
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"name": "vio_hop_freq[22]"
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},
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{
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"name": "vio_hop_freq[21]"
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},
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{
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"name": "vio_hop_freq[20]"
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},
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{
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"name": "vio_hop_freq[19]"
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},
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{
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"name": "vio_hop_freq[18]"
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},
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{
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"name": "vio_hop_freq[17]"
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},
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{
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"name": "vio_hop_freq[16]"
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},
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{
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"name": "vio_hop_freq[15]"
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},
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Binary file not shown.
@@ -10,7 +10,8 @@
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{
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"type": "XSDB_V3",
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"name": "dbg_hub",
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"spec": "labtools_xsdbm_v3"
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"spec": "labtools_xsdbm_v3",
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"clk_input_freq_hz": "200000001"
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},
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{
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"type": "ILA_V3",
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@@ -1933,109 +1934,13 @@
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"direction": "OUT",
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"isVector": true,
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"leftIndex": 0,
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"rightIndex": 47,
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"rightIndex": 15,
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"portIndex": 2,
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"nets": [
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{
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"name": "vio_hop_freq",
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"isBus": true,
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"subnets": [
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{
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"name": "vio_hop_freq[47]"
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},
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{
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"name": "vio_hop_freq[46]"
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},
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{
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"name": "vio_hop_freq[45]"
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},
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{
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"name": "vio_hop_freq[44]"
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},
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{
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"name": "vio_hop_freq[43]"
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},
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{
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"name": "vio_hop_freq[42]"
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},
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{
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"name": "vio_hop_freq[41]"
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},
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{
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"name": "vio_hop_freq[40]"
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},
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{
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"name": "vio_hop_freq[39]"
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},
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{
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"name": "vio_hop_freq[38]"
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},
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{
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"name": "vio_hop_freq[37]"
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},
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{
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"name": "vio_hop_freq[36]"
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},
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{
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"name": "vio_hop_freq[35]"
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},
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{
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"name": "vio_hop_freq[34]"
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},
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{
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"name": "vio_hop_freq[33]"
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},
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{
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"name": "vio_hop_freq[32]"
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},
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{
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"name": "vio_hop_freq[31]"
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},
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{
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"name": "vio_hop_freq[30]"
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},
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{
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"name": "vio_hop_freq[29]"
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},
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{
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"name": "vio_hop_freq[28]"
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},
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{
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"name": "vio_hop_freq[27]"
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},
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{
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"name": "vio_hop_freq[26]"
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},
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{
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"name": "vio_hop_freq[25]"
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},
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{
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"name": "vio_hop_freq[24]"
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},
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{
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"name": "vio_hop_freq[23]"
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},
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{
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"name": "vio_hop_freq[22]"
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},
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{
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"name": "vio_hop_freq[21]"
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},
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{
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"name": "vio_hop_freq[20]"
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},
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{
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"name": "vio_hop_freq[19]"
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},
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{
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"name": "vio_hop_freq[18]"
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},
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{
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"name": "vio_hop_freq[17]"
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},
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{
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"name": "vio_hop_freq[16]"
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},
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{
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"name": "vio_hop_freq[15]"
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},
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@@ -7,5 +7,5 @@ set_property -dict {PACKAGE_PIN AW3 IOSTANDARD LVCMOS18} [get_ports lmk_spi
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set_property -dict {PACKAGE_PIN AW6 IOSTANDARD LVCMOS18} [get_ports lmk_spi_mosi_sdio ] ;# LMK_SPI_SDI_LS
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set_property -dict {PACKAGE_PIN AW4 IOSTANDARD LVCMOS18} [get_ports lmk_spi_miso ] ;# LMK_SPI_SDO_LS
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_system_wrapper/system_ps_i/mts_clk_gen/util_ds_buf_pl_clk/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O]
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set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets u_system_wrapper/system_ps_i/mts_clk_gen/util_bufg_pl_clk/U0/BUFG_O[0]]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_ibufds_pl_refclk_in/O]
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set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets pl_refclk]
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+3
-3
@@ -952,17 +952,17 @@
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"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
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"mode": "slave",
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"parameters": {
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"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"FREQ_HZ": [ { "value": "99999001", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"ADDR_WIDTH": [ { "value": "13", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"ADDR_WIDTH": [ { "value": "13", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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+17
-23
@@ -47,7 +47,7 @@
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"ADC0_Fabric_Freq": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
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"ADC0_OBS_Fabric_Freq": [ { "value": "0.0", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
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"ADC0_Link_Coupling": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"ADC0_Multi_Tile_Sync": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"ADC0_Multi_Tile_Sync": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"ADC0_Band": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
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"ADC0_Refclk_Div": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"ADC0_Clock_Source": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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@@ -137,7 +137,7 @@
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"ADC1_Fabric_Freq": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
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"ADC1_OBS_Fabric_Freq": [ { "value": "0.0", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
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"ADC1_Link_Coupling": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"ADC1_Multi_Tile_Sync": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"ADC1_Multi_Tile_Sync": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"ADC1_Band": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
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"ADC1_Refclk_Div": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"ADC1_Clock_Source": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
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@@ -227,7 +227,7 @@
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"ADC2_Fabric_Freq": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
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"ADC2_OBS_Fabric_Freq": [ { "value": "0.0", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
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"ADC2_Link_Coupling": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"ADC2_Multi_Tile_Sync": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"ADC2_Multi_Tile_Sync": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"ADC2_Band": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
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"ADC2_Refclk_Div": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"ADC2_Clock_Source": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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@@ -317,7 +317,7 @@
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"ADC3_Fabric_Freq": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
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"ADC3_OBS_Fabric_Freq": [ { "value": "0.0", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
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"ADC3_Link_Coupling": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"ADC3_Multi_Tile_Sync": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"ADC3_Multi_Tile_Sync": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"ADC3_Band": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
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"ADC3_Refclk_Div": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"ADC3_Clock_Source": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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@@ -484,7 +484,7 @@
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"DAC0_Outclk_Freq": [ { "value": "37.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
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"DAC0_Fabric_Freq": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
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"DAC0_Link_Coupling": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"DAC0_Multi_Tile_Sync": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"DAC0_Multi_Tile_Sync": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"DAC0_Band": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
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"DAC0_VOP": [ { "value": "20.0", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
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"DAC0_Refclk_Div": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
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@@ -562,7 +562,7 @@
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"DAC1_Outclk_Freq": [ { "value": "37.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
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"DAC1_Fabric_Freq": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
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"DAC1_Link_Coupling": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"DAC1_Multi_Tile_Sync": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"DAC1_Multi_Tile_Sync": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"DAC1_Band": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
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"DAC1_VOP": [ { "value": "20.0", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
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"DAC1_Refclk_Div": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
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@@ -640,7 +640,7 @@
|
||||
"DAC2_Outclk_Freq": [ { "value": "37.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"DAC2_Fabric_Freq": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"DAC2_Link_Coupling": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DAC2_Multi_Tile_Sync": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"DAC2_Multi_Tile_Sync": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"DAC2_Band": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"DAC2_VOP": [ { "value": "20.0", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"DAC2_Refclk_Div": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -718,7 +718,7 @@
|
||||
"DAC3_Outclk_Freq": [ { "value": "37.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"DAC3_Fabric_Freq": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"DAC3_Link_Coupling": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DAC3_Multi_Tile_Sync": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"DAC3_Multi_Tile_Sync": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"DAC3_Band": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"DAC3_VOP": [ { "value": "20.0", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"DAC3_Refclk_Div": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -913,7 +913,7 @@
|
||||
"C_ADC0_Vco": [ { "value": "9600.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_ADC0_Fabric_Freq": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_ADC0_OBS_Fabric_Freq": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_ADC0_Multi_Tile_Sync": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_ADC0_Multi_Tile_Sync": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_ADC0_Link_Coupling": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADC0_Band": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADC0_Refclk_Div": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@@ -1013,7 +1013,7 @@
|
||||
"C_ADC1_Vco": [ { "value": "9600.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_ADC1_Fabric_Freq": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_ADC1_OBS_Fabric_Freq": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_ADC1_Multi_Tile_Sync": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_ADC1_Multi_Tile_Sync": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_ADC1_Link_Coupling": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADC1_Band": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADC1_Refclk_Div": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@@ -1113,7 +1113,7 @@
|
||||
"C_ADC2_Vco": [ { "value": "9600.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_ADC2_Fabric_Freq": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_ADC2_OBS_Fabric_Freq": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_ADC2_Multi_Tile_Sync": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_ADC2_Multi_Tile_Sync": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_ADC2_Link_Coupling": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADC2_Band": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADC2_Refclk_Div": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@@ -1213,7 +1213,7 @@
|
||||
"C_ADC3_Vco": [ { "value": "9600.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_ADC3_Fabric_Freq": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_ADC3_OBS_Fabric_Freq": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_ADC3_Multi_Tile_Sync": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_ADC3_Multi_Tile_Sync": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_ADC3_Link_Coupling": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADC3_Band": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADC3_Refclk_Div": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@@ -1312,7 +1312,7 @@
|
||||
"C_DAC0_OutDiv": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DAC0_Vco": [ { "value": "9600.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_DAC0_Fabric_Freq": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_DAC0_Multi_Tile_Sync": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_DAC0_Multi_Tile_Sync": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_DAC0_Link_Coupling": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DAC0_Band": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DAC0_VOP": [ { "value": "20.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
@@ -1396,7 +1396,7 @@
|
||||
"C_DAC1_OutDiv": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DAC1_Vco": [ { "value": "9600.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_DAC1_Fabric_Freq": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_DAC1_Multi_Tile_Sync": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_DAC1_Multi_Tile_Sync": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_DAC1_Link_Coupling": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DAC1_Band": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DAC1_VOP": [ { "value": "20.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
@@ -1480,7 +1480,7 @@
|
||||
"C_DAC2_OutDiv": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DAC2_Vco": [ { "value": "9600.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_DAC2_Fabric_Freq": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_DAC2_Multi_Tile_Sync": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_DAC2_Multi_Tile_Sync": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_DAC2_Link_Coupling": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DAC2_Band": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DAC2_VOP": [ { "value": "20.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
@@ -1564,7 +1564,7 @@
|
||||
"C_DAC3_OutDiv": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DAC3_Vco": [ { "value": "9600.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_DAC3_Fabric_Freq": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_DAC3_Multi_Tile_Sync": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_DAC3_Multi_Tile_Sync": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_DAC3_Link_Coupling": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DAC3_Band": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DAC3_VOP": [ { "value": "20.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
@@ -1713,8 +1713,6 @@
|
||||
"irq": [ { "direction": "out" } ],
|
||||
"sysref_in_p": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"sysref_in_n": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"user_sysref_adc": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"user_sysref_dac": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"vin0_01_p": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"vin0_01_n": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"vin0_23_p": [ { "direction": "in", "driver_value": "0" } ],
|
||||
@@ -1844,8 +1842,6 @@
|
||||
"dac00_nco_update_en": [ { "direction": "in", "size_left": "5", "size_right": "0", "driver_value": "0" } ],
|
||||
"dac02_nco_update_en": [ { "direction": "in", "size_left": "5", "size_right": "0", "driver_value": "0" } ],
|
||||
"dac0_nco_update_req": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"dac0_sysref_int_gating": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"dac0_sysref_int_reenable": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"dac0_nco_update_busy": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"dac10_nco_freq": [ { "direction": "in", "size_left": "47", "size_right": "0", "driver_value": "0" } ],
|
||||
"dac12_nco_freq": [ { "direction": "in", "size_left": "47", "size_right": "0", "driver_value": "0" } ],
|
||||
@@ -3196,9 +3192,7 @@
|
||||
"CONVERTER2_PHASE_RESET": [ { "physical_name": "dac02_nco_phase_rst" } ],
|
||||
"CONVERTER2_UPDATE_EN": [ { "physical_name": "dac02_nco_update_en" } ],
|
||||
"NCO_UPDATE_BUSY": [ { "physical_name": "dac0_nco_update_busy" } ],
|
||||
"NCO_UPDATE_REQUEST": [ { "physical_name": "dac0_nco_update_req" } ],
|
||||
"SYSREF_INT_GATING": [ { "physical_name": "dac0_sysref_int_gating" } ],
|
||||
"SYSREF_INT_REENABLE": [ { "physical_name": "dac0_sysref_int_reenable" } ]
|
||||
"NCO_UPDATE_REQUEST": [ { "physical_name": "dac0_nco_update_req" } ]
|
||||
}
|
||||
},
|
||||
"dac1_nco": {
|
||||
|
||||
-99
@@ -1,99 +0,0 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_ps_util_ds_buf_0_0",
|
||||
"cell_name": "mts_clk_gen/util_ds_buf_pl_clk",
|
||||
"component_reference": "xilinx.com:ip:util_ds_buf:2.2",
|
||||
"ip_revision": "32",
|
||||
"gen_directory": "../../../../../../rfsoc_eval_nco.gen/sources_1/bd/system_ps/ip/system_ps_util_ds_buf_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_SIZE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_BUF_TYPE": [ { "value": "IBUFDS", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_ps_util_ds_buf_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BOARD_PARAMETER": [ { "value": " ", "resolve_type": "user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "156250000", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"DIFF_CLK_IN_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_BUFG_GT_SYNC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_BUF_TYPE": [ { "value": "IBUFDS", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SIZE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BUFG_GT_SYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SIM_DEVICE": [ { "value": "VERSAL_AI_CORE_ES1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu48dr" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "fsvg1517" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "32" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../rfsoc_eval_nco.gen/sources_1/bd/system_ps/ip/system_ps_util_ds_buf_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"IBUF_DS_P": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"IBUF_DS_N": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"IBUF_OUT": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"CLK_IN_D": {
|
||||
"vlnv": "xilinx.com:interface:diff_clock:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:diff_clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "DIFF_CLK_IN_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"CAN_DEBUG": [ { "value": "false", "value_permission": "bd", "resolve_type": "generated", "format": "bool", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "245760000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_P": [ { "physical_name": "IBUF_DS_P" } ],
|
||||
"CLK_N": [ { "physical_name": "IBUF_DS_N" } ]
|
||||
}
|
||||
},
|
||||
"IBUF_OUT": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "245760000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_ps_util_ds_buf_0_0_IBUF_OUT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "IBUF_OUT" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
-102
@@ -1,102 +0,0 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_ps_util_ds_buf_pl_clk_0",
|
||||
"cell_name": "mts_clk_gen/util_bufg_pl_clk",
|
||||
"component_reference": "xilinx.com:ip:util_ds_buf:2.2",
|
||||
"ip_revision": "32",
|
||||
"gen_directory": "../../../../../../rfsoc_eval_nco.gen/sources_1/bd/system_ps/ip/system_ps_util_ds_buf_pl_clk_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_SIZE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_BUF_TYPE": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_ps_util_ds_buf_pl_clk_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BOARD_PARAMETER": [ { "value": " ", "resolve_type": "user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "156250000", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"DIFF_CLK_IN_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_BUFG_GT_SYNC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_BUF_TYPE": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SIZE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BUFG_GT_SYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SIM_DEVICE": [ { "value": "VERSAL_AI_CORE_ES1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu48dr" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "fsvg1517" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "32" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../rfsoc_eval_nco.gen/sources_1/bd/system_ps/ip/system_ps_util_ds_buf_pl_clk_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"BUFG_I": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"BUFG_O": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"BUFG_I": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "245760000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_ps_util_ds_buf_0_0_IBUF_OUT", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "BUFG_I" } ]
|
||||
}
|
||||
},
|
||||
"BUFG_O": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "245760000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_ps_util_ds_buf_0_0_IBUF_OUT", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "BUFG_O" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
-99
@@ -1,99 +0,0 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_ps_util_ds_buf_pl_clk_1",
|
||||
"cell_name": "mts_clk_gen/util_ds_buf_pl_sysref",
|
||||
"component_reference": "xilinx.com:ip:util_ds_buf:2.2",
|
||||
"ip_revision": "32",
|
||||
"gen_directory": "../../../../../../rfsoc_eval_nco.gen/sources_1/bd/system_ps/ip/system_ps_util_ds_buf_pl_clk_1",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_SIZE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_BUF_TYPE": [ { "value": "IBUFDS", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_ps_util_ds_buf_pl_clk_1", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BOARD_PARAMETER": [ { "value": " ", "resolve_type": "user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "156250000", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"DIFF_CLK_IN_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_BUFG_GT_SYNC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_BUF_TYPE": [ { "value": "IBUFDS", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SIZE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BUFG_GT_SYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SIM_DEVICE": [ { "value": "VERSAL_AI_CORE_ES1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu48dr" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "fsvg1517" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "32" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../rfsoc_eval_nco.gen/sources_1/bd/system_ps/ip/system_ps_util_ds_buf_pl_clk_1" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"IBUF_DS_P": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"IBUF_DS_N": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"IBUF_OUT": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"CLK_IN_D": {
|
||||
"vlnv": "xilinx.com:interface:diff_clock:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:diff_clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "DIFF_CLK_IN_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"CAN_DEBUG": [ { "value": "false", "value_permission": "bd", "resolve_type": "generated", "format": "bool", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_P": [ { "physical_name": "IBUF_DS_P" } ],
|
||||
"CLK_N": [ { "physical_name": "IBUF_DS_N" } ]
|
||||
}
|
||||
},
|
||||
"IBUF_OUT": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_ps_util_ds_buf_pl_clk_1_IBUF_OUT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "IBUF_OUT" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
-50
@@ -1,50 +0,0 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_ps_xlconstant_0_0",
|
||||
"cell_name": "mts_clk_gen/xlconstant_0",
|
||||
"component_reference": "xilinx.com:ip:xlconstant:1.1",
|
||||
"ip_revision": "9",
|
||||
"gen_directory": "../../../../../../rfsoc_eval_nco.gen/sources_1/bd/system_ps/ip/system_ps_xlconstant_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "system_ps_xlconstant_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"CONST_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CONST_VAL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"CONST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CONST_VAL": [ { "value": "0x0", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu48dr" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "fsvg1517" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "9" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../rfsoc_eval_nco.gen/sources_1/bd/system_ps/ip/system_ps_xlconstant_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"dout": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
-126
@@ -1,126 +0,0 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_ps_xpm_cdc_gen_0_0",
|
||||
"cell_name": "mts_clk_gen/xpm_cdc_gen_pl_sysref",
|
||||
"component_reference": "xilinx.com:ip:xpm_cdc_gen:1.0",
|
||||
"ip_revision": "4",
|
||||
"gen_directory": "../../../../../../rfsoc_eval_nco.gen/sources_1/bd/system_ps/ip/system_ps_xpm_cdc_gen_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"CDC_TYPE": [ { "value": "xpm_cdc_single", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"SRC_CLK_PERIOD": [ { "value": "5000", "resolve_type": "user", "usage": "all" } ],
|
||||
"DEST_CLK_PERIOD": [ { "value": "2500", "resolve_type": "user", "usage": "all" } ],
|
||||
"SIM_ASSERT_CHK": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"DEST_SYNC_FF": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"INIT_SYNC_FF": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SRC_INPUT_REG": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SIM_LOSSLESS_GRAY_CHK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"DEST_EXT_HSK": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"REG_OUTPUT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"RST_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"INIT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SRC_SYNC_FF": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RST_ACTIVE_HIGH": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_ps_xpm_cdc_gen_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_CDC_TYPE": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SRC_CLK_PERIOD": [ { "value": "5000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DEST_CLK_PERIOD": [ { "value": "2500", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SIM_ASSERT_CHK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DEST_SYNC_FF": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"INIT_SYNC_FF": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SRC_INPUT_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"REG_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"SIM_LOSSLESS_GRAY_CHK": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"SRC_SYNC_FF": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"DEST_EXT_HSK": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"RST_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"INIT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"RST_ACTIVE_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu48dr" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "fsvg1517" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "4" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../rfsoc_eval_nco.gen/sources_1/bd/system_ps/ip/system_ps_xpm_cdc_gen_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"src_clk": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"dest_clk": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"src_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
|
||||
"dest_out": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"dest_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "245760000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_ps_util_ds_buf_0_0_IBUF_OUT", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "dest_clk" } ]
|
||||
}
|
||||
},
|
||||
"src_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "src_clk" } ]
|
||||
}
|
||||
},
|
||||
"RST": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
-126
@@ -1,126 +0,0 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_ps_xpm_cdc_gen_pl_sysref_0",
|
||||
"cell_name": "mts_clk_gen/xpm_cdc_gen_mts_sysref",
|
||||
"component_reference": "xilinx.com:ip:xpm_cdc_gen:1.0",
|
||||
"ip_revision": "4",
|
||||
"gen_directory": "../../../../../../rfsoc_eval_nco.gen/sources_1/bd/system_ps/ip/system_ps_xpm_cdc_gen_pl_sysref_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"CDC_TYPE": [ { "value": "xpm_cdc_single", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"SRC_CLK_PERIOD": [ { "value": "5000", "resolve_type": "user", "usage": "all" } ],
|
||||
"DEST_CLK_PERIOD": [ { "value": "2500", "resolve_type": "user", "usage": "all" } ],
|
||||
"SIM_ASSERT_CHK": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"DEST_SYNC_FF": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"INIT_SYNC_FF": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SRC_INPUT_REG": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SIM_LOSSLESS_GRAY_CHK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"DEST_EXT_HSK": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"REG_OUTPUT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"RST_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"INIT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SRC_SYNC_FF": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RST_ACTIVE_HIGH": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_ps_xpm_cdc_gen_pl_sysref_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_CDC_TYPE": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SRC_CLK_PERIOD": [ { "value": "5000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DEST_CLK_PERIOD": [ { "value": "2500", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SIM_ASSERT_CHK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DEST_SYNC_FF": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"INIT_SYNC_FF": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SRC_INPUT_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"REG_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"SIM_LOSSLESS_GRAY_CHK": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"SRC_SYNC_FF": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"DEST_EXT_HSK": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"RST_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"INIT": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"RST_ACTIVE_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu48dr" } ],
|
||||
"NEXTGEN_VERSAL": [ { "value": "0" } ],
|
||||
"PACKAGE": [ { "value": "fsvg1517" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "4" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../rfsoc_eval_nco.gen/sources_1/bd/system_ps/ip/system_ps_xpm_cdc_gen_pl_sysref_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"src_clk": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"dest_clk": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"src_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
|
||||
"dest_out": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"dest_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "245760000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_ps_clk_wiz_0_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "dest_clk" } ]
|
||||
}
|
||||
},
|
||||
"src_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "src_clk" } ]
|
||||
}
|
||||
},
|
||||
"RST": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,7 +1,7 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0xBC34A81DA0FF0228",
|
||||
"boundary_crc": "0x3D81255E924307E2",
|
||||
"device": "xczu48dr-fsvg1517-2-i",
|
||||
"gen_directory": "../../../../rfsoc_eval_nco.gen/sources_1/bd/system_ps",
|
||||
"name": "system_ps",
|
||||
@@ -42,15 +42,6 @@
|
||||
},
|
||||
"usp_rf_data_converter": "",
|
||||
"zynq_ultra_ps_e": "",
|
||||
"mts_clk_gen": {
|
||||
"util_ds_buf_pl_clk": "",
|
||||
"util_bufg_pl_clk": "",
|
||||
"util_ds_buf_pl_sysref": "",
|
||||
"xpm_cdc_gen_pl_sysref": "",
|
||||
"xlconstant_0": "",
|
||||
"xpm_cdc_gen_mts_sysref": "",
|
||||
"clk_wiz_pl_clk": ""
|
||||
},
|
||||
"axi_bram_ctrl_hop": "",
|
||||
"hop_ram": "",
|
||||
"system_management": "",
|
||||
@@ -2123,63 +2114,6 @@
|
||||
}
|
||||
}
|
||||
},
|
||||
"pl_clk": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0",
|
||||
"vlnv": "xilinx.com:interface:diff_clock_rtl:1.0",
|
||||
"parameters": {
|
||||
"CAN_DEBUG": {
|
||||
"value": "false",
|
||||
"value_src": "default"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "245760000"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_P": {
|
||||
"physical_name": "pl_clk_clk_p",
|
||||
"direction": "I",
|
||||
"left": "0",
|
||||
"right": "0"
|
||||
},
|
||||
"CLK_N": {
|
||||
"physical_name": "pl_clk_clk_n",
|
||||
"direction": "I",
|
||||
"left": "0",
|
||||
"right": "0"
|
||||
}
|
||||
}
|
||||
},
|
||||
"pl_sysref": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0",
|
||||
"vlnv": "xilinx.com:interface:diff_clock_rtl:1.0",
|
||||
"parameters": {
|
||||
"CAN_DEBUG": {
|
||||
"value": "false",
|
||||
"value_src": "default"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000",
|
||||
"value_src": "default"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_P": {
|
||||
"physical_name": "pl_sysref_clk_p",
|
||||
"direction": "I",
|
||||
"left": "0",
|
||||
"right": "0"
|
||||
},
|
||||
"CLK_N": {
|
||||
"physical_name": "pl_sysref_clk_n",
|
||||
"direction": "I",
|
||||
"left": "0",
|
||||
"right": "0"
|
||||
}
|
||||
}
|
||||
},
|
||||
"dac0_nco": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:rfdc_nco_pins:1.0",
|
||||
@@ -2238,14 +2172,6 @@
|
||||
"NCO_UPDATE_REQUEST": {
|
||||
"physical_name": "dac0_nco_nco_update_request",
|
||||
"direction": "I"
|
||||
},
|
||||
"SYSREF_INT_GATING": {
|
||||
"physical_name": "dac0_nco_sysref_int_gating",
|
||||
"direction": "I"
|
||||
},
|
||||
"SYSREF_INT_REENABLE": {
|
||||
"physical_name": "dac0_nco_sysref_int_reenable",
|
||||
"direction": "I"
|
||||
}
|
||||
}
|
||||
},
|
||||
@@ -3157,35 +3083,6 @@
|
||||
}
|
||||
}
|
||||
},
|
||||
"sys_rstn": {
|
||||
"direction": "O"
|
||||
},
|
||||
"sys_clk": {
|
||||
"type": "clk",
|
||||
"direction": "O",
|
||||
"parameters": {
|
||||
"CLK_DOMAIN": {
|
||||
"value": "system_ps_clk_wiz_0_0_clk_out1",
|
||||
"value_src": "default_prop"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "245760000",
|
||||
"value_src": "ip_prop"
|
||||
},
|
||||
"FREQ_TOLERANCE_HZ": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "0.0",
|
||||
"value_src": "ip_prop"
|
||||
}
|
||||
}
|
||||
},
|
||||
"ps_rstn": {
|
||||
"type": "rst",
|
||||
"direction": "O",
|
||||
@@ -3201,6 +3098,12 @@
|
||||
"value_src": "const_prop"
|
||||
}
|
||||
}
|
||||
},
|
||||
"user_sysref_adc": {
|
||||
"direction": "I"
|
||||
},
|
||||
"user_sysref_dac": {
|
||||
"direction": "I"
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
@@ -4339,7 +4242,7 @@
|
||||
"value": "0"
|
||||
},
|
||||
"ADC0_Multi_Tile_Sync": {
|
||||
"value": "true"
|
||||
"value": "false"
|
||||
},
|
||||
"ADC0_Outclk_Freq": {
|
||||
"value": "37.500"
|
||||
@@ -4359,9 +4262,6 @@
|
||||
"ADC1_Clock_Dist": {
|
||||
"value": "1"
|
||||
},
|
||||
"ADC1_Multi_Tile_Sync": {
|
||||
"value": "true"
|
||||
},
|
||||
"ADC1_Outclk_Freq": {
|
||||
"value": "37.500"
|
||||
},
|
||||
@@ -4380,9 +4280,6 @@
|
||||
"ADC2_Clock_Source": {
|
||||
"value": "1"
|
||||
},
|
||||
"ADC2_Multi_Tile_Sync": {
|
||||
"value": "true"
|
||||
},
|
||||
"ADC2_Outclk_Freq": {
|
||||
"value": "37.500"
|
||||
},
|
||||
@@ -4398,9 +4295,6 @@
|
||||
"ADC3_Clock_Source": {
|
||||
"value": "1"
|
||||
},
|
||||
"ADC3_Multi_Tile_Sync": {
|
||||
"value": "true"
|
||||
},
|
||||
"ADC3_Outclk_Freq": {
|
||||
"value": "37.500"
|
||||
},
|
||||
@@ -4618,7 +4512,7 @@
|
||||
"value": "1"
|
||||
},
|
||||
"DAC0_Multi_Tile_Sync": {
|
||||
"value": "true"
|
||||
"value": "false"
|
||||
},
|
||||
"DAC0_Outclk_Freq": {
|
||||
"value": "37.500"
|
||||
@@ -4635,9 +4529,6 @@
|
||||
"DAC1_Clock_Source": {
|
||||
"value": "4"
|
||||
},
|
||||
"DAC1_Multi_Tile_Sync": {
|
||||
"value": "true"
|
||||
},
|
||||
"DAC1_Outclk_Freq": {
|
||||
"value": "37.500"
|
||||
},
|
||||
@@ -4653,9 +4544,6 @@
|
||||
"DAC2_Clock_Source": {
|
||||
"value": "4"
|
||||
},
|
||||
"DAC2_Multi_Tile_Sync": {
|
||||
"value": "true"
|
||||
},
|
||||
"DAC2_Outclk_Freq": {
|
||||
"value": "37.500"
|
||||
},
|
||||
@@ -4671,9 +4559,6 @@
|
||||
"DAC3_Clock_Source": {
|
||||
"value": "4"
|
||||
},
|
||||
"DAC3_Multi_Tile_Sync": {
|
||||
"value": "true"
|
||||
},
|
||||
"DAC3_Outclk_Freq": {
|
||||
"value": "37.500"
|
||||
},
|
||||
@@ -7942,234 +7827,6 @@
|
||||
}
|
||||
}
|
||||
},
|
||||
"mts_clk_gen": {
|
||||
"interface_ports": {
|
||||
"pl_clk": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0",
|
||||
"vlnv": "xilinx.com:interface:diff_clock_rtl:1.0"
|
||||
},
|
||||
"pl_sysref": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0",
|
||||
"vlnv": "xilinx.com:interface:diff_clock_rtl:1.0"
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"sys_rstn": {
|
||||
"direction": "O"
|
||||
},
|
||||
"mts_sysref": {
|
||||
"direction": "O",
|
||||
"left": "0",
|
||||
"right": "0"
|
||||
},
|
||||
"sys_clk": {
|
||||
"type": "clk",
|
||||
"direction": "O"
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
"util_ds_buf_pl_clk": {
|
||||
"vlnv": "xilinx.com:ip:util_ds_buf:2.2",
|
||||
"ip_revision": "32",
|
||||
"xci_name": "system_ps_util_ds_buf_0_0",
|
||||
"xci_path": "ip/system_ps_util_ds_buf_0_0/system_ps_util_ds_buf_0_0.xci",
|
||||
"inst_hier_path": "mts_clk_gen/util_ds_buf_pl_clk"
|
||||
},
|
||||
"util_bufg_pl_clk": {
|
||||
"vlnv": "xilinx.com:ip:util_ds_buf:2.2",
|
||||
"ip_revision": "32",
|
||||
"xci_name": "system_ps_util_ds_buf_pl_clk_0",
|
||||
"xci_path": "ip/system_ps_util_ds_buf_pl_clk_0/system_ps_util_ds_buf_pl_clk_0.xci",
|
||||
"inst_hier_path": "mts_clk_gen/util_bufg_pl_clk",
|
||||
"parameters": {
|
||||
"C_BUF_TYPE": {
|
||||
"value": "BUFG"
|
||||
}
|
||||
}
|
||||
},
|
||||
"util_ds_buf_pl_sysref": {
|
||||
"vlnv": "xilinx.com:ip:util_ds_buf:2.2",
|
||||
"ip_revision": "32",
|
||||
"xci_name": "system_ps_util_ds_buf_pl_clk_1",
|
||||
"xci_path": "ip/system_ps_util_ds_buf_pl_clk_1/system_ps_util_ds_buf_pl_clk_1.xci",
|
||||
"inst_hier_path": "mts_clk_gen/util_ds_buf_pl_sysref"
|
||||
},
|
||||
"xpm_cdc_gen_pl_sysref": {
|
||||
"vlnv": "xilinx.com:ip:xpm_cdc_gen:1.0",
|
||||
"ip_revision": "4",
|
||||
"xci_name": "system_ps_xpm_cdc_gen_0_0",
|
||||
"xci_path": "ip/system_ps_xpm_cdc_gen_0_0/system_ps_xpm_cdc_gen_0_0.xci",
|
||||
"inst_hier_path": "mts_clk_gen/xpm_cdc_gen_pl_sysref",
|
||||
"parameters": {
|
||||
"CDC_TYPE": {
|
||||
"value": "xpm_cdc_single"
|
||||
},
|
||||
"DEST_SYNC_FF": {
|
||||
"value": "2"
|
||||
},
|
||||
"SIM_ASSERT_CHK": {
|
||||
"value": "false"
|
||||
},
|
||||
"SRC_INPUT_REG": {
|
||||
"value": "false"
|
||||
},
|
||||
"WIDTH": {
|
||||
"value": "1"
|
||||
}
|
||||
}
|
||||
},
|
||||
"xlconstant_0": {
|
||||
"vlnv": "xilinx.com:ip:xlconstant:1.1",
|
||||
"ip_revision": "9",
|
||||
"xci_name": "system_ps_xlconstant_0_0",
|
||||
"xci_path": "ip/system_ps_xlconstant_0_0/system_ps_xlconstant_0_0.xci",
|
||||
"inst_hier_path": "mts_clk_gen/xlconstant_0",
|
||||
"parameters": {
|
||||
"CONST_VAL": {
|
||||
"value": "0"
|
||||
}
|
||||
}
|
||||
},
|
||||
"xpm_cdc_gen_mts_sysref": {
|
||||
"vlnv": "xilinx.com:ip:xpm_cdc_gen:1.0",
|
||||
"ip_revision": "4",
|
||||
"xci_name": "system_ps_xpm_cdc_gen_pl_sysref_0",
|
||||
"xci_path": "ip/system_ps_xpm_cdc_gen_pl_sysref_0/system_ps_xpm_cdc_gen_pl_sysref_0.xci",
|
||||
"inst_hier_path": "mts_clk_gen/xpm_cdc_gen_mts_sysref",
|
||||
"parameters": {
|
||||
"CDC_TYPE": {
|
||||
"value": "xpm_cdc_single"
|
||||
},
|
||||
"DEST_SYNC_FF": {
|
||||
"value": "2"
|
||||
},
|
||||
"SIM_ASSERT_CHK": {
|
||||
"value": "false"
|
||||
},
|
||||
"SRC_INPUT_REG": {
|
||||
"value": "false"
|
||||
},
|
||||
"WIDTH": {
|
||||
"value": "1"
|
||||
}
|
||||
}
|
||||
},
|
||||
"clk_wiz_pl_clk": {
|
||||
"vlnv": "xilinx.com:ip:clk_wiz:6.0",
|
||||
"ip_revision": "14",
|
||||
"xci_name": "system_ps_clk_wiz_0_0",
|
||||
"xci_path": "ip/system_ps_clk_wiz_0_0/system_ps_clk_wiz_0_0.xci",
|
||||
"inst_hier_path": "mts_clk_gen/clk_wiz_pl_clk",
|
||||
"parameters": {
|
||||
"CLKIN1_JITTER_PS": {
|
||||
"value": "40.69"
|
||||
},
|
||||
"CLKOUT1_JITTER": {
|
||||
"value": "85.228"
|
||||
},
|
||||
"CLKOUT1_PHASE_ERROR": {
|
||||
"value": "77.902"
|
||||
},
|
||||
"CLKOUT1_REQUESTED_OUT_FREQ": {
|
||||
"value": "245.76"
|
||||
},
|
||||
"MMCM_CLKFBOUT_MULT_F": {
|
||||
"value": "4.875"
|
||||
},
|
||||
"MMCM_CLKIN1_PERIOD": {
|
||||
"value": "4.069"
|
||||
},
|
||||
"MMCM_CLKIN2_PERIOD": {
|
||||
"value": "10.0"
|
||||
},
|
||||
"MMCM_CLKOUT0_DIVIDE_F": {
|
||||
"value": "4.875"
|
||||
},
|
||||
"MMCM_DIVCLK_DIVIDE": {
|
||||
"value": "1"
|
||||
},
|
||||
"PRIM_IN_FREQ": {
|
||||
"value": "245.76"
|
||||
},
|
||||
"PRIM_SOURCE": {
|
||||
"value": "Global_buffer"
|
||||
},
|
||||
"USE_RESET": {
|
||||
"value": "false"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"Conn1": {
|
||||
"interface_ports": [
|
||||
"util_ds_buf_pl_clk/CLK_IN_D",
|
||||
"pl_clk"
|
||||
]
|
||||
},
|
||||
"Conn2": {
|
||||
"interface_ports": [
|
||||
"util_ds_buf_pl_sysref/CLK_IN_D",
|
||||
"pl_sysref"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"clk_wiz_pl_clk_clk_out1": {
|
||||
"ports": [
|
||||
"clk_wiz_pl_clk/clk_out1",
|
||||
"sys_clk",
|
||||
"xpm_cdc_gen_mts_sysref/dest_clk"
|
||||
]
|
||||
},
|
||||
"clk_wiz_pl_clk_locked": {
|
||||
"ports": [
|
||||
"clk_wiz_pl_clk/locked",
|
||||
"sys_rstn"
|
||||
]
|
||||
},
|
||||
"util_bufg_pl_clk_BUFG_O": {
|
||||
"ports": [
|
||||
"util_bufg_pl_clk/BUFG_O",
|
||||
"xpm_cdc_gen_pl_sysref/dest_clk",
|
||||
"clk_wiz_pl_clk/clk_in1"
|
||||
]
|
||||
},
|
||||
"util_ds_buf_pl_clk_IBUF_OUT": {
|
||||
"ports": [
|
||||
"util_ds_buf_pl_clk/IBUF_OUT",
|
||||
"util_bufg_pl_clk/BUFG_I"
|
||||
]
|
||||
},
|
||||
"util_ds_buf_pl_sysref_IBUF_OUT": {
|
||||
"ports": [
|
||||
"util_ds_buf_pl_sysref/IBUF_OUT",
|
||||
"xpm_cdc_gen_pl_sysref/src_in"
|
||||
]
|
||||
},
|
||||
"xlconstant_0_dout": {
|
||||
"ports": [
|
||||
"xlconstant_0/dout",
|
||||
"xpm_cdc_gen_pl_sysref/src_clk",
|
||||
"xpm_cdc_gen_mts_sysref/src_clk"
|
||||
]
|
||||
},
|
||||
"xpm_cdc_gen_mts_sysref_dest_out": {
|
||||
"ports": [
|
||||
"xpm_cdc_gen_mts_sysref/dest_out",
|
||||
"mts_sysref"
|
||||
]
|
||||
},
|
||||
"xpm_cdc_gen_pl_sysref_dest_out": {
|
||||
"ports": [
|
||||
"xpm_cdc_gen_pl_sysref/dest_out",
|
||||
"xpm_cdc_gen_mts_sysref/src_in"
|
||||
]
|
||||
}
|
||||
}
|
||||
},
|
||||
"axi_bram_ctrl_hop": {
|
||||
"vlnv": "xilinx.com:ip:axi_bram_ctrl:4.1",
|
||||
"ip_revision": "10",
|
||||
@@ -8254,18 +7911,6 @@
|
||||
"hop_ram/BRAM_PORTB"
|
||||
]
|
||||
},
|
||||
"CLK_IN_D_0_1": {
|
||||
"interface_ports": [
|
||||
"pl_clk",
|
||||
"mts_clk_gen/pl_clk"
|
||||
]
|
||||
},
|
||||
"CLK_IN_D_1_1": {
|
||||
"interface_ports": [
|
||||
"pl_sysref",
|
||||
"mts_clk_gen/pl_sysref"
|
||||
]
|
||||
},
|
||||
"Vp_Vn_0_1": {
|
||||
"interface_ports": [
|
||||
"vp_vn",
|
||||
@@ -8694,25 +8339,6 @@
|
||||
"usp_rf_data_converter/m3_axis_aresetn"
|
||||
]
|
||||
},
|
||||
"mts_clk_gen_clk_out1_0": {
|
||||
"ports": [
|
||||
"mts_clk_gen/sys_clk",
|
||||
"sys_clk"
|
||||
]
|
||||
},
|
||||
"mts_clk_gen_locked_0": {
|
||||
"ports": [
|
||||
"mts_clk_gen/sys_rstn",
|
||||
"sys_rstn"
|
||||
]
|
||||
},
|
||||
"mts_clk_gen_mts_sysref": {
|
||||
"ports": [
|
||||
"mts_clk_gen/mts_sysref",
|
||||
"usp_rf_data_converter/user_sysref_adc",
|
||||
"usp_rf_data_converter/user_sysref_dac"
|
||||
]
|
||||
},
|
||||
"rst_ps8_96M_peripheral_aresetn1": {
|
||||
"ports": [
|
||||
"rst_ps8_96M/peripheral_aresetn",
|
||||
|
||||
@@ -1,28 +1,34 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.0",
|
||||
"Default View_TopLeft":"-257,-308",
|
||||
"Default View_TopLeft":"-257,-340",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
|
||||
# -string -flagsOSRD
|
||||
preplace port pl_clk -pg 1 -lvl 0 -x 0 -y 60 -defaultsOSRD
|
||||
preplace port pl_sysref -pg 1 -lvl 0 -x 0 -y 170 -defaultsOSRD
|
||||
preplace port port-id_sys_rstn -pg 1 -lvl 5 -x 1270 -y 210 -defaultsOSRD
|
||||
preplace port port-id_sys_clk -pg 1 -lvl 5 -x 1270 -y 50 -defaultsOSRD
|
||||
preplace portBus mts_sysref -pg 1 -lvl 5 -x 1270 -y 130 -defaultsOSRD
|
||||
preplace inst util_ds_buf_pl_clk -pg 1 -lvl 1 -x 350 -y 60 -defaultsOSRD
|
||||
preplace inst util_bufg_pl_clk -pg 1 -lvl 2 -x 610 -y 60 -defaultsOSRD -resize 220 88
|
||||
preplace inst util_ds_buf_pl_sysref -pg 1 -lvl 1 -x 350 -y 170 -defaultsOSRD -resize 220 88
|
||||
preplace inst xpm_cdc_gen_pl_sysref -pg 1 -lvl 3 -x 880 -y 30 -defaultsOSRD
|
||||
preplace inst xlconstant_0 -pg 1 -lvl 2 -x 610 -y -70 -defaultsOSRD
|
||||
preplace inst xpm_cdc_gen_mts_sysref -pg 1 -lvl 4 -x 1120 -y 130 -defaultsOSRD -resize 200 116
|
||||
preplace inst clk_wiz_0 -pg 1 -lvl 3 -x 880 -y 240 -defaultsOSRD
|
||||
preplace inst xpm_cdc_gen_mts_sysref -pg 1 -lvl 4 -x 1130 -y 130 -defaultsOSRD -resize 200 116
|
||||
preplace inst clk_wiz_pl_clk -pg 1 -lvl 3 -x 880 -y 200 -defaultsOSRD
|
||||
preplace netloc clk_wiz_pl_clk_clk_out1 1 3 2 1010 50 NJ
|
||||
preplace netloc clk_wiz_pl_clk_locked 1 3 2 NJ 210 NJ
|
||||
preplace netloc util_bufg_pl_clk_BUFG_O 1 2 1 760 30n
|
||||
preplace netloc util_ds_buf_pl_clk_IBUF_OUT 1 1 1 N 60
|
||||
preplace netloc util_ds_buf_pl_sysref_IBUF_OUT 1 1 2 480J -10 740
|
||||
preplace netloc xlconstant_0_dout 1 2 2 750 110 N
|
||||
preplace netloc util_bufg_pl_clk_BUFG_O 1 2 1 760 30n
|
||||
preplace netloc xpm_cdc_gen_mts_sysref_dest_out 1 4 1 NJ 130
|
||||
preplace netloc xpm_cdc_gen_pl_sysref_dest_out 1 3 1 1000 30n
|
||||
preplace netloc Conn1 1 0 1 N 60
|
||||
preplace netloc Conn2 1 0 1 N 170
|
||||
levelinfo -pg 1 0 350 610 880 1120 1240
|
||||
pagesize -pg 1 -db -bbox -sgen -120 -360 1240 310
|
||||
levelinfo -pg 1 0 350 610 880 1130 1270
|
||||
pagesize -pg 1 -db -bbox -sgen -120 -360 1430 310
|
||||
"
|
||||
}
|
||||
|
||||
0
|
||||
|
||||
@@ -1,191 +1,183 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"0.696459",
|
||||
"Default View_TopLeft":"-171,3",
|
||||
"Default View_ScaleFactor":"0.472382",
|
||||
"Default View_TopLeft":"-1213,2",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
|
||||
# -string -flagsOSRD
|
||||
preplace port sysref_in -pg 1 -lvl 0 -x 0 -y 1170 -defaultsOSRD
|
||||
preplace port vin0_01 -pg 1 -lvl 0 -x 0 -y 1010 -defaultsOSRD
|
||||
preplace port vin0_23 -pg 1 -lvl 0 -x 0 -y 1030 -defaultsOSRD
|
||||
preplace port vin1_01 -pg 1 -lvl 0 -x 0 -y 1050 -defaultsOSRD
|
||||
preplace port vin1_23 -pg 1 -lvl 0 -x 0 -y 1070 -defaultsOSRD
|
||||
preplace port vout00 -pg 1 -lvl 4 -x 1540 -y 1260 -defaultsOSRD
|
||||
preplace port vout02 -pg 1 -lvl 4 -x 1540 -y 1280 -defaultsOSRD
|
||||
preplace port vout10 -pg 1 -lvl 4 -x 1540 -y 1300 -defaultsOSRD
|
||||
preplace port vout12 -pg 1 -lvl 4 -x 1540 -y 1320 -defaultsOSRD
|
||||
preplace port s00_axis -pg 1 -lvl 0 -x 0 -y 810 -defaultsOSRD
|
||||
preplace port s10_axis -pg 1 -lvl 0 -x 0 -y 850 -defaultsOSRD
|
||||
preplace port s02_axis -pg 1 -lvl 0 -x 0 -y 830 -defaultsOSRD
|
||||
preplace port s12_axis -pg 1 -lvl 0 -x 0 -y 870 -defaultsOSRD
|
||||
preplace port m02_axis -pg 1 -lvl 4 -x 1540 -y 980 -defaultsOSRD
|
||||
preplace port m10_axis -pg 1 -lvl 4 -x 1540 -y 1020 -defaultsOSRD
|
||||
preplace port m12_axis -pg 1 -lvl 4 -x 1540 -y 1060 -defaultsOSRD
|
||||
preplace port m11_axis -pg 1 -lvl 4 -x 1540 -y 1040 -defaultsOSRD
|
||||
preplace port m00_axis -pg 1 -lvl 4 -x 1540 -y 940 -defaultsOSRD
|
||||
preplace port m13_axis -pg 1 -lvl 4 -x 1540 -y 1080 -defaultsOSRD
|
||||
preplace port adc1_clk -pg 1 -lvl 0 -x 0 -y 970 -defaultsOSRD
|
||||
preplace port dac0_clk -pg 1 -lvl 0 -x 0 -y 990 -defaultsOSRD
|
||||
preplace port m20_axis -pg 1 -lvl 4 -x 1540 -y 1100 -defaultsOSRD
|
||||
preplace port m21_axis -pg 1 -lvl 4 -x 1540 -y 1120 -defaultsOSRD
|
||||
preplace port m32_axis -pg 1 -lvl 4 -x 1540 -y 1220 -defaultsOSRD
|
||||
preplace port m31_axis -pg 1 -lvl 4 -x 1540 -y 1200 -defaultsOSRD
|
||||
preplace port m22_axis -pg 1 -lvl 4 -x 1540 -y 1140 -defaultsOSRD
|
||||
preplace port m23_axis -pg 1 -lvl 4 -x 1540 -y 1160 -defaultsOSRD
|
||||
preplace port m30_axis -pg 1 -lvl 4 -x 1540 -y 1180 -defaultsOSRD
|
||||
preplace port m33_axis -pg 1 -lvl 4 -x 1540 -y 1240 -defaultsOSRD
|
||||
preplace port vin2_01 -pg 1 -lvl 0 -x 0 -y 1090 -defaultsOSRD
|
||||
preplace port vin2_23 -pg 1 -lvl 0 -x 0 -y 1110 -defaultsOSRD
|
||||
preplace port vin3_01 -pg 1 -lvl 0 -x 0 -y 1130 -defaultsOSRD
|
||||
preplace port vin3_23 -pg 1 -lvl 0 -x 0 -y 1150 -defaultsOSRD
|
||||
preplace port m03_axis -pg 1 -lvl 4 -x 1540 -y 1000 -defaultsOSRD
|
||||
preplace port m01_axis -pg 1 -lvl 4 -x 1540 -y 960 -defaultsOSRD
|
||||
preplace port s20_axis -pg 1 -lvl 0 -x 0 -y 890 -defaultsOSRD
|
||||
preplace port s22_axis -pg 1 -lvl 0 -x 0 -y 910 -defaultsOSRD
|
||||
preplace port s30_axis -pg 1 -lvl 0 -x 0 -y 930 -defaultsOSRD
|
||||
preplace port s32_axis -pg 1 -lvl 0 -x 0 -y 950 -defaultsOSRD
|
||||
preplace port vout20 -pg 1 -lvl 4 -x 1540 -y 1340 -defaultsOSRD
|
||||
preplace port vout22 -pg 1 -lvl 4 -x 1540 -y 1360 -defaultsOSRD
|
||||
preplace port vout30 -pg 1 -lvl 4 -x 1540 -y 1380 -defaultsOSRD
|
||||
preplace port vout32 -pg 1 -lvl 4 -x 1540 -y 1400 -defaultsOSRD
|
||||
preplace port spi -pg 1 -lvl 4 -x 1540 -y 520 -defaultsOSRD
|
||||
preplace port pl_clk -pg 1 -lvl 0 -x 0 -y 1840 -defaultsOSRD
|
||||
preplace port pl_sysref -pg 1 -lvl 0 -x 0 -y 1860 -defaultsOSRD
|
||||
preplace port dac0_nco -pg 1 -lvl 0 -x 0 -y 1190 -defaultsOSRD
|
||||
preplace port dac1_nco -pg 1 -lvl 0 -x 0 -y 1210 -defaultsOSRD
|
||||
preplace port dac2_nco -pg 1 -lvl 0 -x 0 -y 1230 -defaultsOSRD
|
||||
preplace port dac3_nco -pg 1 -lvl 0 -x 0 -y 1250 -defaultsOSRD
|
||||
preplace port adc0_nco -pg 1 -lvl 0 -x 0 -y 1270 -defaultsOSRD
|
||||
preplace port adc1_nco -pg 1 -lvl 0 -x 0 -y 1290 -defaultsOSRD
|
||||
preplace port adc2_nco -pg 1 -lvl 0 -x 0 -y 1310 -defaultsOSRD
|
||||
preplace port adc3_nco -pg 1 -lvl 0 -x 0 -y 1330 -defaultsOSRD
|
||||
preplace port hop_ram -pg 1 -lvl 0 -x 0 -y 350 -defaultsOSRD
|
||||
preplace port sysref_in -pg 1 -lvl 0 -x 0 -y 1150 -defaultsOSRD
|
||||
preplace port vin0_01 -pg 1 -lvl 0 -x 0 -y 990 -defaultsOSRD
|
||||
preplace port vin0_23 -pg 1 -lvl 0 -x 0 -y 1010 -defaultsOSRD
|
||||
preplace port vin1_01 -pg 1 -lvl 0 -x 0 -y 1030 -defaultsOSRD
|
||||
preplace port vin1_23 -pg 1 -lvl 0 -x 0 -y 1050 -defaultsOSRD
|
||||
preplace port vout00 -pg 1 -lvl 4 -x 1490 -y 1220 -defaultsOSRD
|
||||
preplace port vout02 -pg 1 -lvl 4 -x 1490 -y 1240 -defaultsOSRD
|
||||
preplace port vout10 -pg 1 -lvl 4 -x 1490 -y 1260 -defaultsOSRD
|
||||
preplace port vout12 -pg 1 -lvl 4 -x 1490 -y 1280 -defaultsOSRD
|
||||
preplace port s00_axis -pg 1 -lvl 0 -x 0 -y 790 -defaultsOSRD
|
||||
preplace port s10_axis -pg 1 -lvl 0 -x 0 -y 830 -defaultsOSRD
|
||||
preplace port s02_axis -pg 1 -lvl 0 -x 0 -y 810 -defaultsOSRD
|
||||
preplace port s12_axis -pg 1 -lvl 0 -x 0 -y 850 -defaultsOSRD
|
||||
preplace port m02_axis -pg 1 -lvl 4 -x 1490 -y 940 -defaultsOSRD
|
||||
preplace port m10_axis -pg 1 -lvl 4 -x 1490 -y 980 -defaultsOSRD
|
||||
preplace port m12_axis -pg 1 -lvl 4 -x 1490 -y 1020 -defaultsOSRD
|
||||
preplace port m11_axis -pg 1 -lvl 4 -x 1490 -y 1000 -defaultsOSRD
|
||||
preplace port m00_axis -pg 1 -lvl 4 -x 1490 -y 900 -defaultsOSRD
|
||||
preplace port m13_axis -pg 1 -lvl 4 -x 1490 -y 1040 -defaultsOSRD
|
||||
preplace port adc1_clk -pg 1 -lvl 0 -x 0 -y 950 -defaultsOSRD
|
||||
preplace port dac0_clk -pg 1 -lvl 0 -x 0 -y 970 -defaultsOSRD
|
||||
preplace port m20_axis -pg 1 -lvl 4 -x 1490 -y 1060 -defaultsOSRD
|
||||
preplace port m21_axis -pg 1 -lvl 4 -x 1490 -y 1080 -defaultsOSRD
|
||||
preplace port m32_axis -pg 1 -lvl 4 -x 1490 -y 1180 -defaultsOSRD
|
||||
preplace port m31_axis -pg 1 -lvl 4 -x 1490 -y 1160 -defaultsOSRD
|
||||
preplace port m22_axis -pg 1 -lvl 4 -x 1490 -y 1100 -defaultsOSRD
|
||||
preplace port m23_axis -pg 1 -lvl 4 -x 1490 -y 1120 -defaultsOSRD
|
||||
preplace port m30_axis -pg 1 -lvl 4 -x 1490 -y 1140 -defaultsOSRD
|
||||
preplace port m33_axis -pg 1 -lvl 4 -x 1490 -y 1200 -defaultsOSRD
|
||||
preplace port vin2_01 -pg 1 -lvl 0 -x 0 -y 1070 -defaultsOSRD
|
||||
preplace port vin2_23 -pg 1 -lvl 0 -x 0 -y 1090 -defaultsOSRD
|
||||
preplace port vin3_01 -pg 1 -lvl 0 -x 0 -y 1110 -defaultsOSRD
|
||||
preplace port vin3_23 -pg 1 -lvl 0 -x 0 -y 1130 -defaultsOSRD
|
||||
preplace port m03_axis -pg 1 -lvl 4 -x 1490 -y 960 -defaultsOSRD
|
||||
preplace port m01_axis -pg 1 -lvl 4 -x 1490 -y 920 -defaultsOSRD
|
||||
preplace port s20_axis -pg 1 -lvl 0 -x 0 -y 870 -defaultsOSRD
|
||||
preplace port s22_axis -pg 1 -lvl 0 -x 0 -y 890 -defaultsOSRD
|
||||
preplace port s30_axis -pg 1 -lvl 0 -x 0 -y 910 -defaultsOSRD
|
||||
preplace port s32_axis -pg 1 -lvl 0 -x 0 -y 930 -defaultsOSRD
|
||||
preplace port vout20 -pg 1 -lvl 4 -x 1490 -y 1300 -defaultsOSRD
|
||||
preplace port vout22 -pg 1 -lvl 4 -x 1490 -y 1320 -defaultsOSRD
|
||||
preplace port vout30 -pg 1 -lvl 4 -x 1490 -y 1340 -defaultsOSRD
|
||||
preplace port vout32 -pg 1 -lvl 4 -x 1490 -y 1360 -defaultsOSRD
|
||||
preplace port spi -pg 1 -lvl 4 -x 1490 -y 480 -defaultsOSRD
|
||||
preplace port dac0_nco -pg 1 -lvl 0 -x 0 -y 1170 -defaultsOSRD
|
||||
preplace port dac1_nco -pg 1 -lvl 0 -x 0 -y 1190 -defaultsOSRD
|
||||
preplace port dac2_nco -pg 1 -lvl 0 -x 0 -y 1210 -defaultsOSRD
|
||||
preplace port dac3_nco -pg 1 -lvl 0 -x 0 -y 1230 -defaultsOSRD
|
||||
preplace port adc0_nco -pg 1 -lvl 0 -x 0 -y 1250 -defaultsOSRD
|
||||
preplace port adc1_nco -pg 1 -lvl 0 -x 0 -y 1270 -defaultsOSRD
|
||||
preplace port adc2_nco -pg 1 -lvl 0 -x 0 -y 1290 -defaultsOSRD
|
||||
preplace port adc3_nco -pg 1 -lvl 0 -x 0 -y 1310 -defaultsOSRD
|
||||
preplace port hop_ram -pg 1 -lvl 0 -x 0 -y 340 -defaultsOSRD
|
||||
preplace port vp_vn -pg 1 -lvl 0 -x 0 -y 100 -defaultsOSRD
|
||||
preplace port port-id_spi_active -pg 1 -lvl 4 -x 1540 -y 540 -defaultsOSRD
|
||||
preplace port port-id_m0_axis_aclk -pg 1 -lvl 0 -x 0 -y 1450 -defaultsOSRD
|
||||
preplace port port-id_s1_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1630 -defaultsOSRD
|
||||
preplace port port-id_s0_axis_aclk -pg 1 -lvl 0 -x 0 -y 1610 -defaultsOSRD
|
||||
preplace port port-id_m0_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1430 -defaultsOSRD
|
||||
preplace port port-id_s0_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1590 -defaultsOSRD
|
||||
preplace port port-id_m1_axis_aclk -pg 1 -lvl 0 -x 0 -y 1490 -defaultsOSRD
|
||||
preplace port port-id_m1_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1470 -defaultsOSRD
|
||||
preplace port port-id_s1_axis_aclk -pg 1 -lvl 0 -x 0 -y 1650 -defaultsOSRD
|
||||
preplace port port-id_ps_clk0 -pg 1 -lvl 4 -x 1540 -y 220 -defaultsOSRD
|
||||
preplace port port-id_m2_axis_aclk -pg 1 -lvl 0 -x 0 -y 1530 -defaultsOSRD
|
||||
preplace port port-id_m2_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1510 -defaultsOSRD
|
||||
preplace port port-id_m3_axis_aclk -pg 1 -lvl 0 -x 0 -y 1570 -defaultsOSRD
|
||||
preplace port port-id_m3_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1550 -defaultsOSRD
|
||||
preplace port port-id_s2_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1670 -defaultsOSRD
|
||||
preplace port port-id_s2_axis_aclk -pg 1 -lvl 0 -x 0 -y 1690 -defaultsOSRD
|
||||
preplace port port-id_s3_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1710 -defaultsOSRD
|
||||
preplace port port-id_s3_axis_aclk -pg 1 -lvl 0 -x 0 -y 1730 -defaultsOSRD
|
||||
preplace port port-id_sys_rstn -pg 1 -lvl 4 -x 1540 -y 1830 -defaultsOSRD
|
||||
preplace port port-id_sys_clk -pg 1 -lvl 4 -x 1540 -y 1870 -defaultsOSRD
|
||||
preplace portBus ps_rstn -pg 1 -lvl 4 -x 1540 -y 740 -defaultsOSRD
|
||||
preplace inst axi_spi_engine -pg 1 -lvl 3 -x 1310 -y 540 -defaultsOSRD
|
||||
preplace inst rst_ps8_96M -pg 1 -lvl 3 -x 1310 -y 700 -defaultsOSRD
|
||||
preplace inst xlconcat_irq -pg 1 -lvl 3 -x 1310 -y 1490 -defaultsOSRD -orient R180
|
||||
preplace inst ps8_axi_periph -pg 1 -lvl 2 -x 720 -y 550 -defaultsOSRD
|
||||
preplace inst usp_rf_data_converter -pg 1 -lvl 2 -x 720 -y 1260 -defaultsOSRD
|
||||
preplace inst zynq_ultra_ps_e -pg 1 -lvl 2 -x 720 -y 270 -defaultsOSRD
|
||||
preplace inst mts_clk_gen -pg 1 -lvl 2 -x 720 -y 1850 -defaultsOSRD
|
||||
preplace inst axi_bram_ctrl_hop -pg 1 -lvl 1 -x 200 -y 210 -defaultsOSRD
|
||||
preplace inst hop_ram -pg 1 -lvl 1 -x 200 -y 340 -defaultsOSRD
|
||||
preplace inst system_management -pg 1 -lvl 3 -x 1310 -y 110 -defaultsOSRD
|
||||
preplace inst axi_timer -pg 1 -lvl 1 -x 200 -y 500 -defaultsOSRD
|
||||
preplace netloc axi_spi_engine_active_0 1 3 1 N 540
|
||||
preplace netloc axi_spi_engine_irq 1 3 1 1500 560n
|
||||
preplace netloc m0_axis_aclk_0_1 1 0 2 NJ 1450 N
|
||||
preplace netloc m0_axis_aresetn_0_1 1 0 2 NJ 1430 N
|
||||
preplace netloc m1_axis_aclk_0_1 1 0 2 NJ 1490 N
|
||||
preplace netloc m1_axis_aresetn_0_1 1 0 2 NJ 1470 N
|
||||
preplace netloc m2_axis_aclk_0_1 1 0 2 NJ 1530 N
|
||||
preplace netloc m2_axis_aresetn_0_1 1 0 2 NJ 1510 N
|
||||
preplace netloc m3_axis_aclk_0_1 1 0 2 NJ 1570 N
|
||||
preplace netloc m3_axis_aresetn_0_1 1 0 2 NJ 1550 N
|
||||
preplace netloc mts_clk_gen_clk_out1_0 1 2 2 NJ 1870 NJ
|
||||
preplace netloc mts_clk_gen_locked_0 1 2 2 NJ 1830 NJ
|
||||
preplace netloc mts_clk_gen_mts_sysref 1 1 2 380 140 1070
|
||||
preplace netloc rst_ps8_96M_peripheral_aresetn1 1 0 4 50 120 360 130 1100 800 1520
|
||||
preplace netloc s0_axis_aclk_0_1 1 0 2 NJ 1610 N
|
||||
preplace netloc s0_axis_aresetn_0_1 1 0 2 NJ 1590 N
|
||||
preplace netloc s1_axis_aclk_0_1 1 0 2 NJ 1650 N
|
||||
preplace netloc s1_axis_aresetn_0_1 1 0 2 NJ 1630 N
|
||||
preplace netloc s2_axis_aclk_0_1 1 0 2 N 1690 N
|
||||
preplace netloc s2_axis_aresetn_0_1 1 0 2 N 1670 N
|
||||
preplace netloc s3_axis_aclk_0_1 1 0 2 N 1730 N
|
||||
preplace netloc s3_axis_aresetn_0_1 1 0 2 N 1710 N
|
||||
preplace netloc usp_rf_data_converter_irq 1 2 2 N 1580 1490
|
||||
preplace netloc xlconcat_irq_dout 1 1 2 390 160 1080
|
||||
preplace netloc zynq_ultra_ps_e_pl_clk0 1 0 4 40 610 370 120 1130J 220 NJ
|
||||
preplace netloc zynq_ultra_ps_e_pl_resetn0 1 2 1 1090 270n
|
||||
preplace netloc system_management_ip2intc_irpt 1 3 1 1510 60n
|
||||
preplace netloc axi_timer_interrupt 1 1 3 350J 150 1120J 230 1490
|
||||
preplace netloc BRAM_PORTB_0_1 1 0 1 N 350
|
||||
preplace netloc CLK_IN_D_0_1 1 0 2 N 1840 N
|
||||
preplace netloc CLK_IN_D_1_1 1 0 2 N 1860 N
|
||||
preplace netloc adc0_nco_0_1 1 0 2 N 1270 N
|
||||
preplace netloc adc1_clk_1 1 0 2 N 970 N
|
||||
preplace netloc adc1_nco_0_1 1 0 2 N 1290 N
|
||||
preplace netloc adc2_nco_0_1 1 0 2 N 1310 N
|
||||
preplace netloc adc3_nco_0_1 1 0 2 N 1330 N
|
||||
preplace netloc axi_bram_ctrl_hop_BRAM_PORTA 1 0 2 60 130 340
|
||||
preplace netloc axi_spi_engine_spi_1 1 3 1 N 520
|
||||
preplace netloc dac0_clk_1 1 0 2 N 990 N
|
||||
preplace netloc dac0_nco_0_1 1 0 2 N 1190 N
|
||||
preplace netloc dac1_nco_0_1 1 0 2 N 1210 N
|
||||
preplace netloc dac2_nco_0_1 1 0 2 N 1230 N
|
||||
preplace netloc dac3_nco_0_1 1 0 2 N 1250 N
|
||||
preplace netloc ps8_axi_periph_M00_AXI 1 2 1 N 510
|
||||
preplace netloc ps8_axi_periph_M01_AXI 1 1 2 400 170 1060
|
||||
preplace netloc ps8_axi_periph_M02_AXI 1 0 3 40 90 NJ 90 1050
|
||||
preplace netloc s00_axis_0_1 1 0 2 NJ 810 N
|
||||
preplace netloc s02_axis_0_1 1 0 2 NJ 830 N
|
||||
preplace netloc s10_axis_0_1 1 0 2 NJ 850 N
|
||||
preplace netloc s12_axis_0_1 1 0 2 NJ 870 N
|
||||
preplace netloc s20_axis_0_1 1 0 2 N 890 N
|
||||
preplace netloc s22_axis_0_1 1 0 2 N 910 N
|
||||
preplace netloc s30_axis_0_1 1 0 2 N 930 N
|
||||
preplace netloc s32_axis_0_1 1 0 2 N 950 N
|
||||
preplace netloc sysref_in_1 1 0 2 NJ 1170 N
|
||||
preplace netloc usp_rf_data_converter_m00_axis 1 2 2 NJ 940 NJ
|
||||
preplace netloc usp_rf_data_converter_m01_axis 1 2 2 NJ 960 NJ
|
||||
preplace netloc usp_rf_data_converter_m02_axis 1 2 2 NJ 980 NJ
|
||||
preplace netloc usp_rf_data_converter_m03_axis 1 2 2 NJ 1000 NJ
|
||||
preplace netloc usp_rf_data_converter_m10_axis 1 2 2 NJ 1020 NJ
|
||||
preplace netloc usp_rf_data_converter_m11_axis 1 2 2 NJ 1040 NJ
|
||||
preplace netloc usp_rf_data_converter_m12_axis 1 2 2 NJ 1060 NJ
|
||||
preplace netloc usp_rf_data_converter_m13_axis 1 2 2 NJ 1080 NJ
|
||||
preplace netloc usp_rf_data_converter_m20_axis 1 2 2 NJ 1100 NJ
|
||||
preplace netloc usp_rf_data_converter_m21_axis 1 2 2 NJ 1120 NJ
|
||||
preplace netloc usp_rf_data_converter_m22_axis 1 2 2 NJ 1140 NJ
|
||||
preplace netloc usp_rf_data_converter_m23_axis 1 2 2 NJ 1160 NJ
|
||||
preplace netloc usp_rf_data_converter_m30_axis 1 2 2 NJ 1180 NJ
|
||||
preplace netloc usp_rf_data_converter_m31_axis 1 2 2 NJ 1200 NJ
|
||||
preplace netloc usp_rf_data_converter_m32_axis 1 2 2 NJ 1220 NJ
|
||||
preplace netloc usp_rf_data_converter_m33_axis 1 2 2 NJ 1240 NJ
|
||||
preplace netloc usp_rf_data_converter_vout00 1 2 2 NJ 1260 NJ
|
||||
preplace netloc usp_rf_data_converter_vout02 1 2 2 NJ 1280 NJ
|
||||
preplace netloc usp_rf_data_converter_vout10 1 2 2 NJ 1300 NJ
|
||||
preplace netloc usp_rf_data_converter_vout12 1 2 2 NJ 1320 NJ
|
||||
preplace netloc usp_rf_data_converter_vout20 1 2 2 NJ 1340 NJ
|
||||
preplace netloc usp_rf_data_converter_vout22 1 2 2 NJ 1360 NJ
|
||||
preplace netloc usp_rf_data_converter_vout30 1 2 2 NJ 1380 NJ
|
||||
preplace netloc usp_rf_data_converter_vout32 1 2 2 NJ 1400 NJ
|
||||
preplace netloc vin0_01_1 1 0 2 NJ 1010 N
|
||||
preplace netloc vin0_23_1 1 0 2 NJ 1030 N
|
||||
preplace netloc vin1_01_1 1 0 2 NJ 1050 N
|
||||
preplace netloc vin1_23_1 1 0 2 NJ 1070 N
|
||||
preplace netloc vin2_01_0_1 1 0 2 N 1090 N
|
||||
preplace netloc vin2_23_0_1 1 0 2 N 1110 N
|
||||
preplace netloc vin3_01_0_1 1 0 2 N 1130 N
|
||||
preplace netloc vin3_23_0_1 1 0 2 N 1150 N
|
||||
preplace netloc zynq_ultra_ps_e_M_AXI_HPM0_FPD 1 1 2 410 180 1030
|
||||
preplace port port-id_spi_active -pg 1 -lvl 4 -x 1490 -y 500 -defaultsOSRD
|
||||
preplace port port-id_m0_axis_aclk -pg 1 -lvl 0 -x 0 -y 1390 -defaultsOSRD
|
||||
preplace port port-id_s1_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1570 -defaultsOSRD
|
||||
preplace port port-id_s0_axis_aclk -pg 1 -lvl 0 -x 0 -y 1550 -defaultsOSRD
|
||||
preplace port port-id_m0_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1370 -defaultsOSRD
|
||||
preplace port port-id_s0_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1530 -defaultsOSRD
|
||||
preplace port port-id_m1_axis_aclk -pg 1 -lvl 0 -x 0 -y 1430 -defaultsOSRD
|
||||
preplace port port-id_m1_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1410 -defaultsOSRD
|
||||
preplace port port-id_s1_axis_aclk -pg 1 -lvl 0 -x 0 -y 1590 -defaultsOSRD
|
||||
preplace port port-id_ps_clk0 -pg 1 -lvl 4 -x 1490 -y 220 -defaultsOSRD
|
||||
preplace port port-id_m2_axis_aclk -pg 1 -lvl 0 -x 0 -y 1470 -defaultsOSRD
|
||||
preplace port port-id_m2_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1450 -defaultsOSRD
|
||||
preplace port port-id_m3_axis_aclk -pg 1 -lvl 0 -x 0 -y 1510 -defaultsOSRD
|
||||
preplace port port-id_m3_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1490 -defaultsOSRD
|
||||
preplace port port-id_s2_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1610 -defaultsOSRD
|
||||
preplace port port-id_s2_axis_aclk -pg 1 -lvl 0 -x 0 -y 1630 -defaultsOSRD
|
||||
preplace port port-id_s3_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1650 -defaultsOSRD
|
||||
preplace port port-id_s3_axis_aclk -pg 1 -lvl 0 -x 0 -y 1670 -defaultsOSRD
|
||||
preplace port port-id_user_sysref_adc -pg 1 -lvl 0 -x 0 -y 20 -defaultsOSRD
|
||||
preplace port port-id_user_sysref_dac -pg 1 -lvl 0 -x 0 -y 40 -defaultsOSRD
|
||||
preplace portBus ps_rstn -pg 1 -lvl 4 -x 1490 -y 700 -defaultsOSRD
|
||||
preplace inst axi_spi_engine -pg 1 -lvl 3 -x 1260 -y 500 -defaultsOSRD
|
||||
preplace inst rst_ps8_96M -pg 1 -lvl 3 -x 1260 -y 660 -defaultsOSRD
|
||||
preplace inst xlconcat_irq -pg 1 -lvl 3 -x 1260 -y 1450 -defaultsOSRD -orient R180
|
||||
preplace inst ps8_axi_periph -pg 1 -lvl 2 -x 700 -y 510 -defaultsOSRD
|
||||
preplace inst usp_rf_data_converter -pg 1 -lvl 2 -x 700 -y 1220 -defaultsOSRD
|
||||
preplace inst zynq_ultra_ps_e -pg 1 -lvl 2 -x 700 -y 230 -defaultsOSRD
|
||||
preplace inst axi_bram_ctrl_hop -pg 1 -lvl 1 -x 200 -y 200 -defaultsOSRD
|
||||
preplace inst hop_ram -pg 1 -lvl 1 -x 200 -y 330 -defaultsOSRD
|
||||
preplace inst system_management -pg 1 -lvl 3 -x 1260 -y 110 -defaultsOSRD
|
||||
preplace inst axi_timer -pg 1 -lvl 1 -x 200 -y 490 -defaultsOSRD
|
||||
preplace netloc axi_spi_engine_active_0 1 3 1 N 500
|
||||
preplace netloc axi_spi_engine_irq 1 3 1 1450 520n
|
||||
preplace netloc axi_timer_interrupt 1 1 3 360J 130 1070J 230 1440
|
||||
preplace netloc m0_axis_aclk_0_1 1 0 2 NJ 1390 N
|
||||
preplace netloc m0_axis_aresetn_0_1 1 0 2 NJ 1370 N
|
||||
preplace netloc m1_axis_aclk_0_1 1 0 2 NJ 1430 N
|
||||
preplace netloc m1_axis_aresetn_0_1 1 0 2 NJ 1410 N
|
||||
preplace netloc m2_axis_aclk_0_1 1 0 2 NJ 1470 N
|
||||
preplace netloc m2_axis_aresetn_0_1 1 0 2 NJ 1450 N
|
||||
preplace netloc m3_axis_aclk_0_1 1 0 2 NJ 1510 N
|
||||
preplace netloc m3_axis_aresetn_0_1 1 0 2 NJ 1490 N
|
||||
preplace netloc rst_ps8_96M_peripheral_aresetn1 1 0 4 20 110 350 110 1050 760 1470
|
||||
preplace netloc s0_axis_aclk_0_1 1 0 2 NJ 1550 N
|
||||
preplace netloc s0_axis_aresetn_0_1 1 0 2 NJ 1530 N
|
||||
preplace netloc s1_axis_aclk_0_1 1 0 2 NJ 1590 N
|
||||
preplace netloc s1_axis_aresetn_0_1 1 0 2 NJ 1570 N
|
||||
preplace netloc s2_axis_aclk_0_1 1 0 2 N 1630 N
|
||||
preplace netloc s2_axis_aresetn_0_1 1 0 2 N 1610 N
|
||||
preplace netloc s3_axis_aclk_0_1 1 0 2 N 1670 N
|
||||
preplace netloc s3_axis_aresetn_0_1 1 0 2 N 1650 N
|
||||
preplace netloc system_management_ip2intc_irpt 1 3 1 1460 60n
|
||||
preplace netloc usp_rf_data_converter_irq 1 2 2 N 1540 1440
|
||||
preplace netloc xlconcat_irq_dout 1 1 2 380 1730 1020
|
||||
preplace netloc zynq_ultra_ps_e_pl_clk0 1 0 4 40 600 370 120 1080J 220 NJ
|
||||
preplace netloc zynq_ultra_ps_e_pl_resetn0 1 2 1 1040 230n
|
||||
preplace netloc BRAM_PORTB_0_1 1 0 1 N 340
|
||||
preplace netloc Vp_Vn_0_1 1 0 3 NJ 100 NJ 100 NJ
|
||||
preplace netloc ps8_axi_periph_M03_AXI 1 2 1 1110 80n
|
||||
preplace netloc ps8_axi_periph_M04_AXI 1 0 3 30 110 NJ 110 1040
|
||||
levelinfo -pg 1 0 200 720 1310 1540
|
||||
pagesize -pg 1 -db -bbox -sgen -170 0 1680 1920
|
||||
preplace netloc adc0_nco_0_1 1 0 2 N 1250 N
|
||||
preplace netloc adc1_clk_1 1 0 2 N 950 N
|
||||
preplace netloc adc1_nco_0_1 1 0 2 N 1270 N
|
||||
preplace netloc adc2_nco_0_1 1 0 2 N 1290 N
|
||||
preplace netloc adc3_nco_0_1 1 0 2 N 1310 N
|
||||
preplace netloc axi_bram_ctrl_hop_BRAM_PORTA 1 0 2 60 120 340
|
||||
preplace netloc axi_spi_engine_spi_1 1 3 1 N 480
|
||||
preplace netloc dac0_clk_1 1 0 2 N 970 N
|
||||
preplace netloc dac0_nco_0_1 1 0 2 N 1170 N
|
||||
preplace netloc dac1_nco_0_1 1 0 2 N 1190 N
|
||||
preplace netloc dac2_nco_0_1 1 0 2 N 1210 N
|
||||
preplace netloc dac3_nco_0_1 1 0 2 N 1230 N
|
||||
preplace netloc ps8_axi_periph_M00_AXI 1 2 1 N 470
|
||||
preplace netloc ps8_axi_periph_M01_AXI 1 1 2 390 710 1010
|
||||
preplace netloc ps8_axi_periph_M02_AXI 1 0 3 30 80 NJ 80 1020
|
||||
preplace netloc ps8_axi_periph_M03_AXI 1 2 1 1060 80n
|
||||
preplace netloc ps8_axi_periph_M04_AXI 1 0 3 50 90 NJ 90 1030
|
||||
preplace netloc s00_axis_0_1 1 0 2 NJ 790 N
|
||||
preplace netloc s02_axis_0_1 1 0 2 NJ 810 N
|
||||
preplace netloc s10_axis_0_1 1 0 2 NJ 830 N
|
||||
preplace netloc s12_axis_0_1 1 0 2 NJ 850 N
|
||||
preplace netloc s20_axis_0_1 1 0 2 N 870 N
|
||||
preplace netloc s22_axis_0_1 1 0 2 N 890 N
|
||||
preplace netloc s30_axis_0_1 1 0 2 N 910 N
|
||||
preplace netloc s32_axis_0_1 1 0 2 N 930 N
|
||||
preplace netloc sysref_in_1 1 0 2 NJ 1150 N
|
||||
preplace netloc usp_rf_data_converter_m00_axis 1 2 2 NJ 900 NJ
|
||||
preplace netloc usp_rf_data_converter_m01_axis 1 2 2 NJ 920 NJ
|
||||
preplace netloc usp_rf_data_converter_m02_axis 1 2 2 NJ 940 NJ
|
||||
preplace netloc usp_rf_data_converter_m03_axis 1 2 2 NJ 960 NJ
|
||||
preplace netloc usp_rf_data_converter_m10_axis 1 2 2 NJ 980 NJ
|
||||
preplace netloc usp_rf_data_converter_m11_axis 1 2 2 NJ 1000 NJ
|
||||
preplace netloc usp_rf_data_converter_m12_axis 1 2 2 NJ 1020 NJ
|
||||
preplace netloc usp_rf_data_converter_m13_axis 1 2 2 NJ 1040 NJ
|
||||
preplace netloc usp_rf_data_converter_m20_axis 1 2 2 NJ 1060 NJ
|
||||
preplace netloc usp_rf_data_converter_m21_axis 1 2 2 NJ 1080 NJ
|
||||
preplace netloc usp_rf_data_converter_m22_axis 1 2 2 NJ 1100 NJ
|
||||
preplace netloc usp_rf_data_converter_m23_axis 1 2 2 NJ 1120 NJ
|
||||
preplace netloc usp_rf_data_converter_m30_axis 1 2 2 NJ 1140 NJ
|
||||
preplace netloc usp_rf_data_converter_m31_axis 1 2 2 NJ 1160 NJ
|
||||
preplace netloc usp_rf_data_converter_m32_axis 1 2 2 NJ 1180 NJ
|
||||
preplace netloc usp_rf_data_converter_m33_axis 1 2 2 NJ 1200 NJ
|
||||
preplace netloc usp_rf_data_converter_vout00 1 2 2 NJ 1220 NJ
|
||||
preplace netloc usp_rf_data_converter_vout02 1 2 2 NJ 1240 NJ
|
||||
preplace netloc usp_rf_data_converter_vout10 1 2 2 NJ 1260 NJ
|
||||
preplace netloc usp_rf_data_converter_vout12 1 2 2 NJ 1280 NJ
|
||||
preplace netloc usp_rf_data_converter_vout20 1 2 2 NJ 1300 NJ
|
||||
preplace netloc usp_rf_data_converter_vout22 1 2 2 NJ 1320 NJ
|
||||
preplace netloc usp_rf_data_converter_vout30 1 2 2 NJ 1340 NJ
|
||||
preplace netloc usp_rf_data_converter_vout32 1 2 2 NJ 1360 NJ
|
||||
preplace netloc vin0_01_1 1 0 2 NJ 990 N
|
||||
preplace netloc vin0_23_1 1 0 2 NJ 1010 N
|
||||
preplace netloc vin1_01_1 1 0 2 NJ 1030 N
|
||||
preplace netloc vin1_23_1 1 0 2 NJ 1050 N
|
||||
preplace netloc vin2_01_0_1 1 0 2 N 1070 N
|
||||
preplace netloc vin2_23_0_1 1 0 2 N 1090 N
|
||||
preplace netloc vin3_01_0_1 1 0 2 N 1110 N
|
||||
preplace netloc vin3_23_0_1 1 0 2 N 1130 N
|
||||
preplace netloc zynq_ultra_ps_e_M_AXI_HPM0_FPD 1 1 2 390 140 1010
|
||||
levelinfo -pg 1 0 200 700 1260 1490
|
||||
pagesize -pg 1 -db -bbox -sgen -170 0 1630 1740
|
||||
"
|
||||
}
|
||||
{
|
||||
|
||||
Binary file not shown.
@@ -0,0 +1,213 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "cmpy_18x8",
|
||||
"component_reference": "xilinx.com:ip:cmpy:6.0",
|
||||
"ip_revision": "24",
|
||||
"gen_directory": "../../../../rfsoc_eval_nco.gen/sources_1/ip/cmpy_18x8",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "cmpy_18x8", "resolve_type": "user", "usage": "all" } ],
|
||||
"APortWidth": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HasATLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HasATUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ATUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"BPortWidth": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HasBTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HasBTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"BTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MultType": [ { "value": "Use_LUTs", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"OptimizeGoal": [ { "value": "Resources", "resolve_type": "user", "usage": "all" } ],
|
||||
"FlowControl": [ { "value": "NonBlocking", "resolve_type": "user", "usage": "all" } ],
|
||||
"RoundMode": [ { "value": "Truncate", "resolve_type": "user", "usage": "all" } ],
|
||||
"OutputWidth": [ { "value": "27", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HasCTRLTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HasCTRLTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CTRLTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"OutTLASTBehv": [ { "value": "Null", "resolve_type": "user", "usage": "all" } ],
|
||||
"LatencyConfig": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
|
||||
"MinimumLatency": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ARESETN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_XDEVICE": [ { "value": "xczu48dr", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_A_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUT_WIDTH": [ { "value": "27", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LATENCY": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MULT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OPTIMIZE_GOAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"HAS_NEGATE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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Binary file not shown.
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Binary file not shown.
@@ -0,0 +1,350 @@
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|
||||
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|
||||
}
|
||||
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|
||||
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|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
},
|
||||
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|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
},
|
||||
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|
||||
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|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
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|
||||
"aresetn_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
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|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"aclken_intf": {
|
||||
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|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
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|
||||
}
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"mode": "master",
|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
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|
||||
}
|
||||
Binary file not shown.
@@ -0,0 +1,350 @@
|
||||
{
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_data_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_data_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_data_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS_DATA": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "3", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
+50
-51
@@ -1,14 +1,13 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_ps_clk_wiz_0_0",
|
||||
"cell_name": "mts_clk_gen/clk_wiz_pl_clk",
|
||||
"xci_name": "sys_clk_gen",
|
||||
"component_reference": "xilinx.com:ip:clk_wiz:6.0",
|
||||
"ip_revision": "14",
|
||||
"gen_directory": "../../../../../../rfsoc_eval_nco.gen/sources_1/bd/system_ps/ip/system_ps_clk_wiz_0_0",
|
||||
"gen_directory": "../../../../rfsoc_eval_nco.gen/sources_1/ip/sys_clk_gen",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "system_ps_clk_wiz_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "sys_clk_gen", "resolve_type": "user", "usage": "all" } ],
|
||||
"USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
@@ -33,14 +32,14 @@
|
||||
"USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
|
||||
"PRIM_IN_FREQ": [ { "value": "245.76", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIM_IN_FREQ": [ { "value": "200", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
|
||||
"PHASESHIFT_MODE": [ { "value": "LATENCY", "resolve_type": "user", "usage": "all" } ],
|
||||
"IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
|
||||
"RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SECONDARY_IN_FREQ": [ { "value": "100.000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
|
||||
"SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
||||
@@ -49,7 +48,7 @@
|
||||
"CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN1_JITTER_PS": [ { "value": "40.69", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN1_JITTER_PS": [ { "value": "50.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT2_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
@@ -85,7 +84,7 @@
|
||||
"PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "245.76", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "200", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
@@ -115,7 +114,7 @@
|
||||
"CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PRIM_SOURCE": [ { "value": "Global_buffer", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT1_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT2_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT3_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
|
||||
@@ -155,12 +154,12 @@
|
||||
"SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_MULT_F": [ { "value": "4.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_MULT_F": [ { "value": "6.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKIN1_PERIOD": [ { "value": "4.069", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
@@ -168,7 +167,7 @@
|
||||
"MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "4.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "6.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
@@ -246,8 +245,8 @@
|
||||
"CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
|
||||
"ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_JITTER": [ { "value": "85.228", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_PHASE_ERROR": [ { "value": "77.902", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_JITTER": [ { "value": "92.799", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_PHASE_ERROR": [ { "value": "82.655", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
@@ -290,7 +289,7 @@
|
||||
"C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"c_component_name": [ { "value": "system_ps_clk_wiz_0_0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"c_component_name": [ { "value": "sys_clk_gen", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_PHASE_ALIGNMENT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@@ -308,13 +307,13 @@
|
||||
"C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_IN_FREQ": [ { "value": "245.76", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRIM_IN_FREQ": [ { "value": "200", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PRIM_SOURCE": [ { "value": "Global_buffer", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PHASESHIFT_MODE": [ { "value": "LATENCY", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
|
||||
@@ -335,18 +334,18 @@
|
||||
"C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW1": [ { "value": "__primary__________245.76____________0.010", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW1": [ { "value": "__primary_____________200____________0.010", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__245.76000______0.000______50.0_______85.228_____77.902", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__200.00000______0.000______50.0_______92.799_____82.655", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW2": [ { "value": "no_CLK_OUT2_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "245.76", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "200", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
@@ -367,7 +366,7 @@
|
||||
"C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_OUT_FREQ": [ { "value": "245.76000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_OUT_FREQ": [ { "value": "200.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
@@ -399,8 +398,8 @@
|
||||
"C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_MULT_F": [ { "value": "4.875", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKIN1_PERIOD": [ { "value": "4.069", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_MULT_F": [ { "value": "6.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
@@ -409,7 +408,7 @@
|
||||
"C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "4.875", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "6.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@@ -503,7 +502,7 @@
|
||||
"C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKIN1_JITTER_PS": [ { "value": "40.69", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKIN1_JITTER_PS": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
|
||||
@@ -541,12 +540,12 @@
|
||||
"C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE2_AUTO": [ { "value": "0.20512820512820512", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE3_AUTO": [ { "value": "0.20512820512820512", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE4_AUTO": [ { "value": "0.20512820512820512", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE5_AUTO": [ { "value": "0.20512820512820512", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE6_AUTO": [ { "value": "0.20512820512820512", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE7_AUTO": [ { "value": "0.20512820512820512", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE2_AUTO": [ { "value": "0.16666666666666666", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE3_AUTO": [ { "value": "0.16666666666666666", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE4_AUTO": [ { "value": "0.16666666666666666", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE5_AUTO": [ { "value": "0.16666666666666666", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE6_AUTO": [ { "value": "0.16666666666666666", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE7_AUTO": [ { "value": "0.16666666666666666", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
@@ -567,7 +566,7 @@
|
||||
"C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_ACTUAL_FREQ": [ { "value": "245.76000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_ACTUAL_FREQ": [ { "value": "200.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
@@ -598,12 +597,12 @@
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "14" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../rfsoc_eval_nco.gen/sources_1/bd/system_ps/ip/system_ps_clk_wiz_0_0" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../rfsoc_eval_nco.gen/sources_1/ip/sys_clk_gen" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2024.1.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
@@ -620,15 +619,15 @@
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "245760000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_ps_util_ds_buf_0_0_IBUF_OUT", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "value_permission": "bd", "usage": "all", "is_static_object": false } ]
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_IN1": [ { "physical_name": "clk_in1" } ]
|
||||
@@ -639,13 +638,13 @@
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "245760000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_ps_clk_wiz_0_0_clk_out1", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,130 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2022/05/09 20:05:45
|
||||
// Design Name:
|
||||
// Module Name: mts_clk_gen
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
// This module is designed to generate synchronous PL Sysref to PL clock, so
|
||||
// that PL sysref can be reliably captured by the RFDC device.
|
||||
// Reference: Xilinx rdf0476-zcu111-rf-dc-eval-tool-2019-1 MTSDesign_8x8 Project
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module mts_clk_gen
|
||||
(
|
||||
input pl_clk ,
|
||||
input pl_sysref ,
|
||||
output sys_clk ,
|
||||
output sys_rstn ,
|
||||
output mts_sysref
|
||||
);
|
||||
|
||||
sys_clk_gen u_sys_clk_gen
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1 (sys_clk ), // output clk_out1
|
||||
// Status and control signals
|
||||
.locked (sys_rstn ), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1 (pl_clk ) // input clk_in1
|
||||
);
|
||||
|
||||
// Parameter usage table, organized as follows:
|
||||
// +---------------------------------------------------------------------------------------------------------------------+
|
||||
// | Parameter name | Data type | Restrictions, if applicable |
|
||||
// |---------------------------------------------------------------------------------------------------------------------|
|
||||
// | Description |
|
||||
// +---------------------------------------------------------------------------------------------------------------------+
|
||||
// +---------------------------------------------------------------------------------------------------------------------+
|
||||
// | DEST_SYNC_FF | Integer | Range: 2 - 10. Default value = 4. |
|
||||
// |---------------------------------------------------------------------------------------------------------------------|
|
||||
// | Number of register stages used to synchronize signal in the destination clock domain. |
|
||||
// +---------------------------------------------------------------------------------------------------------------------+
|
||||
// | INIT_SYNC_FF | Integer | Allowed values: 0, 1. Default value = 0. |
|
||||
// |---------------------------------------------------------------------------------------------------------------------|
|
||||
// | 0- Disable behavioral simulation initialization value(s) on synchronization registers. |
|
||||
// | 1- Enable behavioral simulation initialization value(s) on synchronization registers. |
|
||||
// +---------------------------------------------------------------------------------------------------------------------+
|
||||
// | SIM_ASSERT_CHK | Integer | Allowed values: 0, 1. Default value = 0. |
|
||||
// |---------------------------------------------------------------------------------------------------------------------|
|
||||
// | 0- Disable simulation message reporting. Messages related to potential misuse will not be reported. |
|
||||
// | 1- Enable simulation message reporting. Messages related to potential misuse will be reported. |
|
||||
// +---------------------------------------------------------------------------------------------------------------------+
|
||||
// | SRC_INPUT_REG | Integer | Allowed values: 1, 0. Default value = 1. |
|
||||
// |---------------------------------------------------------------------------------------------------------------------|
|
||||
// | 0- Do not register input (src_in) |
|
||||
// | 1- Register input (src_in) once using src_clk |
|
||||
// +---------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
// Port usage table, organized as follows:
|
||||
// +---------------------------------------------------------------------------------------------------------------------+
|
||||
// | Port name | Direction | Size, in bits | Domain | Sense | Handling if unused |
|
||||
// |---------------------------------------------------------------------------------------------------------------------|
|
||||
// | Description |
|
||||
// +---------------------------------------------------------------------------------------------------------------------+
|
||||
// +---------------------------------------------------------------------------------------------------------------------+
|
||||
// | dest_clk | Input | 1 | NA | Rising edge | Required |
|
||||
// |---------------------------------------------------------------------------------------------------------------------|
|
||||
// | Clock signal for the destination clock domain. |
|
||||
// +---------------------------------------------------------------------------------------------------------------------+
|
||||
// | dest_out | Output | 1 | dest_clk| NA | Required |
|
||||
// |---------------------------------------------------------------------------------------------------------------------|
|
||||
// | src_in synchronized to the destination clock domain. This output is registered. |
|
||||
// +---------------------------------------------------------------------------------------------------------------------+
|
||||
// | src_clk | Input | 1 | NA | Rising edge | Tie to 1'b0 |
|
||||
// |---------------------------------------------------------------------------------------------------------------------|
|
||||
// | Input clock signal for src_in if SRC_INPUT_REG = 1. |
|
||||
// | Unused when SRC_INPUT_REG = 0. |
|
||||
// +---------------------------------------------------------------------------------------------------------------------+
|
||||
// | src_in | Input | 1 | src_clk | NA | Required |
|
||||
// |---------------------------------------------------------------------------------------------------------------------|
|
||||
// | Input signal to be synchronized to dest_clk domain. |
|
||||
// +---------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
wire pl_sysref_sync;
|
||||
|
||||
// [pl_sysref] sync to [pl_clk]
|
||||
xpm_cdc_single #(
|
||||
.DEST_SYNC_FF (2), // DECIMAL; range: 2-10
|
||||
.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
.SIM_ASSERT_CHK (0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
.SRC_INPUT_REG (0) // DECIMAL; 0=do not register input, 1=register input
|
||||
)
|
||||
u_xpm_cdc_single_pl_sysref_sync
|
||||
(
|
||||
.dest_out (pl_sysref_sync ), // 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
|
||||
.dest_clk (pl_clk ), // 1-bit input: Clock signal for the destination clock domain.
|
||||
.src_clk (1'b0 ), // 1-bit input: optional; required when SRC_INPUT_REG = 1
|
||||
.src_in (pl_sysref ) // 1-bit input: Input signal to be synchronized to dest_clk domain.
|
||||
);
|
||||
|
||||
// [pl_sysref_sync] sync to [mts_sysref]
|
||||
xpm_cdc_single #(
|
||||
.DEST_SYNC_FF (2), // DECIMAL; range: 2-10
|
||||
.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
.SIM_ASSERT_CHK (0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
.SRC_INPUT_REG (0) // DECIMAL; 0=do not register input, 1=register input
|
||||
)
|
||||
u_xpm_cdc_single_mts_sysref_adc
|
||||
(
|
||||
.dest_out (mts_sysref ), // 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
|
||||
.dest_clk (sys_clk ), // 1-bit input: Clock signal for the destination clock domain.
|
||||
.src_clk (1'b0 ), // 1-bit input: optional; required when SRC_INPUT_REG = 1
|
||||
.src_in (pl_sysref_sync ) // 1-bit input: Input signal to be synchronized to dest_clk domain.
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -99,14 +99,52 @@ module system_top
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/////////////// Input/Output Buffer and System Clock Generation ////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
wire pl_sysref;
|
||||
wire pl_refclk_in;
|
||||
wire pl_refclk;
|
||||
wire sys_clk;
|
||||
wire sys_rstn;
|
||||
|
||||
IBUFDS u_ibufds_pl_sysref
|
||||
(
|
||||
.I (pl_sysref_p),
|
||||
.IB (pl_sysref_n),
|
||||
.O (pl_sysref )
|
||||
);
|
||||
|
||||
IBUFDS u_ibufds_pl_refclk_in
|
||||
(
|
||||
.I (pl_refclk_p ),
|
||||
.IB (pl_refclk_n ),
|
||||
.O (pl_refclk_in )
|
||||
);
|
||||
|
||||
BUFGCE i_bufg_pl_refclk
|
||||
(
|
||||
.I (pl_refclk_in ),
|
||||
.CE (1'b1 ),
|
||||
.O (pl_refclk )
|
||||
);
|
||||
|
||||
mts_clk_gen u_mts_clk_gen
|
||||
(
|
||||
.pl_clk (pl_refclk ), // input pl_clk
|
||||
.pl_sysref (pl_sysref ), // input pl_sysref
|
||||
.sys_clk (sys_clk ), // output sys_clk
|
||||
.sys_rstn (sys_rstn ), // output sys_rstn
|
||||
.mts_sysref (mts_sysref ) // output mts_sysref
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////// Block Design Interface ////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// clocks and resets
|
||||
wire ps_clk0;
|
||||
wire ps_clk_100m;
|
||||
wire ps_rstn;
|
||||
wire sys_clk;
|
||||
wire sys_rstn;
|
||||
|
||||
// spi interface
|
||||
wire spi_sclk ;
|
||||
@@ -131,10 +169,10 @@ wire hop_ram_en;
|
||||
wire hop_ram_rst;
|
||||
wire [7:0] hop_ram_we;
|
||||
|
||||
assign hop_ram_clk = sys_clk;
|
||||
assign hop_ram_clk = ps_clk_100m;
|
||||
assign hop_ram_din = 'b0;
|
||||
assign hop_ram_en = sys_rstn;
|
||||
assign hop_ram_rst = ~sys_rstn;
|
||||
assign hop_ram_en = ps_rstn;
|
||||
assign hop_ram_rst = ~ps_rstn;
|
||||
assign hop_ram_we = 'b0;
|
||||
|
||||
// -----------------------------------------------------------------------------
|
||||
@@ -331,21 +369,17 @@ system_ps_wrapper u_system_wrapper
|
||||
// **************************** Clock and Reset ****************************
|
||||
// *************************************************************************
|
||||
// output ps clock
|
||||
.ps_clk0 (ps_clk0 ), // output ps_clk0
|
||||
.ps_clk0 (ps_clk_100m ), // output ps_clk0
|
||||
.ps_rstn (ps_rstn ), // output ps_rstn
|
||||
// output pl clock
|
||||
.sys_clk (sys_clk ), // output sys_clk
|
||||
.sys_rstn (sys_rstn ), // output sys_rstn
|
||||
// input pl clock
|
||||
.pl_clk_clk_p (pl_refclk_p ), // input [0:0]pl_clk_clk_p
|
||||
.pl_clk_clk_n (pl_refclk_n ), // input [0:0]pl_clk_clk_n
|
||||
// input pl sysref
|
||||
.pl_sysref_clk_p (pl_sysref_p ), // input [0:0]pl_sysref_clk_p
|
||||
.pl_sysref_clk_n (pl_sysref_n ), // input [0:0]pl_sysref_clk_n
|
||||
// input rf sysref
|
||||
// rf sysref
|
||||
.sysref_in_diff_p (rf_sysref_p ), // input sysref_in_diff_p
|
||||
.sysref_in_diff_n (rf_sysref_n ), // input sysref_in_diff_n
|
||||
|
||||
// pl sysref
|
||||
.user_sysref_adc (mts_sysref ), // input user_sysref_adc
|
||||
.user_sysref_dac (mts_sysref ), // input user_sysref_dac
|
||||
|
||||
|
||||
// *************************************************************************
|
||||
// ***************************** SPI Interface *****************************
|
||||
// *************************************************************************
|
||||
@@ -795,7 +829,7 @@ system_ps_wrapper u_system_wrapper
|
||||
wire vio_hop_en; // 1: hop enable; 0: hop disable
|
||||
wire vio_hop_trig; // vio control, switching hop_trig causes hop_flag to flip
|
||||
reg vio_hop_trig_d = 'b0;
|
||||
wire [47:0] vio_hop_freq;
|
||||
wire [15:0] vio_hop_freq; // only control highest 16 bit, due to tight timing
|
||||
wire [31:0] vio_hop_inter;
|
||||
|
||||
reg [31:0] hop_cnt = 'b0;
|
||||
@@ -808,8 +842,8 @@ wire vio_nco_phase_reset;
|
||||
wire [5:0] vio_nco_update_en;
|
||||
reg nco_update_req = 'b0;
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (!sys_rstn) begin
|
||||
always @(posedge ps_clk_100m) begin
|
||||
if (!ps_rstn) begin
|
||||
vio_hop_trig_d <= 'b0;
|
||||
hop_cnt <= 'b0;
|
||||
hop_ram_addr <= 'b0;
|
||||
@@ -848,9 +882,8 @@ always @(posedge sys_clk) begin
|
||||
nco_freq <= (hop_cnt == 1'b1) ? hop_ram_dout[0 +: 48] : nco_freq;
|
||||
end
|
||||
else begin
|
||||
nco_freq <= vio_hop_freq;
|
||||
nco_freq <= {vio_hop_freq,32'b0};
|
||||
end
|
||||
|
||||
if (vio_hop_en) begin
|
||||
nco_update_req <= (hop_cnt == 2'd2) ? 1'b1 : 1'b0;
|
||||
end
|
||||
@@ -1081,7 +1114,7 @@ vio_manual_ctrl u_vio_manual_ctrl
|
||||
|
||||
vio_hop_ctrl u_vio_hop_ctrl
|
||||
(
|
||||
.clk (sys_clk ), // input wire clk
|
||||
.clk (ps_clk_100m ), // input wire clk
|
||||
.probe_out0 (vio_hop_en ), // output wire [0 : 0] probe_out0
|
||||
.probe_out1 (vio_hop_trig ), // output wire [0 : 0] probe_out1
|
||||
.probe_out2 (vio_hop_freq ), // output wire [47 : 0] probe_out2
|
||||
@@ -1093,7 +1126,7 @@ vio_hop_ctrl u_vio_hop_ctrl
|
||||
|
||||
ila_hop u_ila_hop
|
||||
(
|
||||
.clk (sys_clk ), // input wire clk
|
||||
.clk (ps_clk_100m ), // input wire clk
|
||||
.probe0 (vio_hop_en ), // input wire [0:0] probe0
|
||||
.probe1 (hop_cnt ), // input wire [31:0] probe1
|
||||
.probe2 (hop_ram_addr ), // input wire [31:0] probe2
|
||||
|
||||
Binary file not shown.
@@ -66,13 +66,13 @@
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="115"/>
|
||||
<Option Name="WTModelSimExportSim" Val="115"/>
|
||||
<Option Name="WTQuestaExportSim" Val="115"/>
|
||||
<Option Name="WTXSimExportSim" Val="125"/>
|
||||
<Option Name="WTModelSimExportSim" Val="125"/>
|
||||
<Option Name="WTQuestaExportSim" Val="125"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="115"/>
|
||||
<Option Name="WTRivieraExportSim" Val="115"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="115"/>
|
||||
<Option Name="WTVcsExportSim" Val="125"/>
|
||||
<Option Name="WTRivieraExportSim" Val="125"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="125"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
@@ -96,18 +96,6 @@
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_ps.bd" FileRelPathName="ip/system_ps_auto_ds_3/system_ps_auto_ds_3.xci">
|
||||
<Proxy FileSetName="system_ps_auto_ds_3"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_ps.bd" FileRelPathName="ip/system_ps_auto_ds_4/system_ps_auto_ds_4.xci">
|
||||
<Proxy FileSetName="system_ps_auto_ds_4"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_ps.bd" FileRelPathName="ip/system_ps_auto_pc_2/system_ps_auto_pc_2.xci">
|
||||
<Proxy FileSetName="system_ps_auto_pc_2"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_ps.bd" FileRelPathName="ip/system_ps_auto_pc_3/system_ps_auto_pc_3.xci">
|
||||
<Proxy FileSetName="system_ps_auto_pc_3"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_ps.bd" FileRelPathName="ip/system_ps_axi_bram_ctrl_0_0/system_ps_axi_bram_ctrl_0_0.xci">
|
||||
<Proxy FileSetName="system_ps_axi_bram_ctrl_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
@@ -120,9 +108,6 @@
|
||||
<CompFileExtendedInfo CompFileName="system_ps.bd" FileRelPathName="ip/system_ps_blk_mem_gen_0_0/system_ps_blk_mem_gen_0_0.xci">
|
||||
<Proxy FileSetName="system_ps_blk_mem_gen_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_ps.bd" FileRelPathName="ip/system_ps_clk_wiz_0_0/system_ps_clk_wiz_0_0.xci">
|
||||
<Proxy FileSetName="system_ps_clk_wiz_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_ps.bd" FileRelPathName="ip/system_ps_rst_ps8_96M_0/system_ps_rst_ps8_96M_0.xci">
|
||||
<Proxy FileSetName="system_ps_rst_ps8_96M_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
@@ -135,24 +120,9 @@
|
||||
<CompFileExtendedInfo CompFileName="system_ps.bd" FileRelPathName="ip/system_ps_usp_rf_data_converter_0_0/system_ps_usp_rf_data_converter_0_0.xci">
|
||||
<Proxy FileSetName="system_ps_usp_rf_data_converter_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_ps.bd" FileRelPathName="ip/system_ps_util_ds_buf_0_0/system_ps_util_ds_buf_0_0.xci">
|
||||
<Proxy FileSetName="system_ps_util_ds_buf_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_ps.bd" FileRelPathName="ip/system_ps_util_ds_buf_pl_clk_0/system_ps_util_ds_buf_pl_clk_0.xci">
|
||||
<Proxy FileSetName="system_ps_util_ds_buf_pl_clk_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_ps.bd" FileRelPathName="ip/system_ps_util_ds_buf_pl_clk_1/system_ps_util_ds_buf_pl_clk_1.xci">
|
||||
<Proxy FileSetName="system_ps_util_ds_buf_pl_clk_1"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_ps.bd" FileRelPathName="ip/system_ps_xbar_0/system_ps_xbar_0.xci">
|
||||
<Proxy FileSetName="system_ps_xbar_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_ps.bd" FileRelPathName="ip/system_ps_xpm_cdc_gen_0_0/system_ps_xpm_cdc_gen_0_0.xci">
|
||||
<Proxy FileSetName="system_ps_xpm_cdc_gen_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_ps.bd" FileRelPathName="ip/system_ps_xpm_cdc_gen_pl_sysref_0/system_ps_xpm_cdc_gen_pl_sysref_0.xci">
|
||||
<Proxy FileSetName="system_ps_xpm_cdc_gen_pl_sysref_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_ps.bd" FileRelPathName="ip/system_ps_zynq_ultra_ps_e_0_0/system_ps_zynq_ultra_ps_e_0_0.xci">
|
||||
<Proxy FileSetName="system_ps_zynq_ultra_ps_e_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
@@ -164,6 +134,13 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/mts_clk_gen.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/system_ps/hdl/system_ps_wrapper.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
@@ -375,15 +352,10 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="hrc_25_12_03" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hrc_25_12_03" RelGenDir="$PGENDIR/hrc_25_12_03">
|
||||
<File Path="$PSRCDIR/sources_1/ip/hrc_25_12_03.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/ip/hrc_25_12_03/hrc_25_12_03.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PSRCDIR/sources_1/ip/hrc_25_12_03/hrc_25_12_03.xci"/>
|
||||
<Attr Name="ImportTime" Val="1730778808"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
@@ -395,15 +367,10 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="hrc_50_12_03" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hrc_50_12_03" RelGenDir="$PGENDIR/hrc_50_12_03">
|
||||
<File Path="$PSRCDIR/sources_1/ip/hrc_50_12_03.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/ip/hrc_50_12_03/hrc_50_12_03.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PSRCDIR/sources_1/ip/hrc_50_12_03/hrc_50_12_03.xci"/>
|
||||
<Attr Name="ImportTime" Val="1730778858"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
@@ -415,15 +382,10 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="hrc_400_12_03" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hrc_400_12_03" RelGenDir="$PGENDIR/hrc_400_12_03">
|
||||
<File Path="$PSRCDIR/sources_1/ip/hrc_400_12_03.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/ip/hrc_400_12_03/hrc_400_12_03.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PSRCDIR/sources_1/ip/hrc_400_12_03/hrc_400_12_03.xci"/>
|
||||
<Attr Name="ImportTime" Val="1730778900"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
@@ -435,15 +397,10 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="dds_32b_8b" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dds_32b_8b" RelGenDir="$PGENDIR/dds_32b_8b">
|
||||
<File Path="$PSRCDIR/sources_1/ip/dds_32b_8b.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/ip/dds_32b_8b/dds_32b_8b.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PSRCDIR/sources_1/ip/dds_32b_8b/dds_32b_8b.xci"/>
|
||||
<Attr Name="ImportTime" Val="1730790663"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
@@ -455,15 +412,10 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="cmpy_18x8" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cmpy_18x8" RelGenDir="$PGENDIR/cmpy_18x8">
|
||||
<File Path="$PSRCDIR/sources_1/ip/cmpy_18x8.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/ip/cmpy_18x8/cmpy_18x8.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PSRCDIR/sources_1/ip/cmpy_18x8/cmpy_18x8.xci"/>
|
||||
<Attr Name="ImportTime" Val="1730790701"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
@@ -475,15 +427,10 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="vio_hop_ctrl" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_hop_ctrl" RelGenDir="$PGENDIR/vio_hop_ctrl">
|
||||
<File Path="$PSRCDIR/sources_1/ip/vio_hop_ctrl.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/ip/vio_hop_ctrl/vio_hop_ctrl.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PSRCDIR/sources_1/ip/vio_hop_ctrl/vio_hop_ctrl.xci"/>
|
||||
<Attr Name="ImportTime" Val="1730991426"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
@@ -495,15 +442,10 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="ila_hop" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_hop" RelGenDir="$PGENDIR/ila_hop">
|
||||
<File Path="$PSRCDIR/sources_1/ip/ila_hop.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/ip/ila_hop/ila_hop.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PSRCDIR/sources_1/ip/ila_hop/ila_hop.xci"/>
|
||||
<Attr Name="ImportTime" Val="1730803803"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
@@ -514,42 +456,6 @@
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_ps_util_ds_buf_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_ps_util_ds_buf_0_0" RelGenDir="$PGENDIR/system_ps_util_ds_buf_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_ps_util_ds_buf_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_ps_util_ds_buf_pl_clk_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_ps_util_ds_buf_pl_clk_0" RelGenDir="$PGENDIR/system_ps_util_ds_buf_pl_clk_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_ps_util_ds_buf_pl_clk_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_ps_util_ds_buf_pl_clk_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_ps_util_ds_buf_pl_clk_1" RelGenDir="$PGENDIR/system_ps_util_ds_buf_pl_clk_1">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_ps_util_ds_buf_pl_clk_1"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_ps_xpm_cdc_gen_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_ps_xpm_cdc_gen_0_0" RelGenDir="$PGENDIR/system_ps_xpm_cdc_gen_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_ps_xpm_cdc_gen_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_ps_xpm_cdc_gen_pl_sysref_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_ps_xpm_cdc_gen_pl_sysref_0" RelGenDir="$PGENDIR/system_ps_xpm_cdc_gen_pl_sysref_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_ps_xpm_cdc_gen_pl_sysref_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_ps_clk_wiz_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_ps_clk_wiz_0_0" RelGenDir="$PGENDIR/system_ps_clk_wiz_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_ps_clk_wiz_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_ps_axi_bram_ctrl_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_ps_axi_bram_ctrl_0_0" RelGenDir="$PGENDIR/system_ps_axi_bram_ctrl_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_ps_axi_bram_ctrl_0_0"/>
|
||||
@@ -562,42 +468,33 @@
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_ps_auto_pc_2" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_ps_auto_pc_2" RelGenDir="$PGENDIR/system_ps_auto_pc_2">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_ps_auto_pc_2"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_ps_system_management_wiz_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_ps_system_management_wiz_0_0" RelGenDir="$PGENDIR/system_ps_system_management_wiz_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_ps_system_management_wiz_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_ps_auto_ds_3" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_ps_auto_ds_3" RelGenDir="$PGENDIR/system_ps_auto_ds_3">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_ps_auto_ds_3"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_ps_auto_ds_4" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_ps_auto_ds_4" RelGenDir="$PGENDIR/system_ps_auto_ds_4">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_ps_auto_ds_4"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_ps_auto_pc_3" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_ps_auto_pc_3" RelGenDir="$PGENDIR/system_ps_auto_pc_3">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_ps_auto_pc_3"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_ps_axi_timer_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_ps_axi_timer_0_0" RelGenDir="$PGENDIR/system_ps_axi_timer_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_ps_axi_timer_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sys_clk_gen" Type="BlockSrcs" RelSrcDir="$PSRCDIR/sys_clk_gen" RelGenDir="$PGENDIR/sys_clk_gen">
|
||||
<File Path="$PSRCDIR/sources_1/ip/sys_clk_gen/sys_clk_gen.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PSRCDIR/sources_1/ip/sys_clk_gen/sys_clk_gen.xci"/>
|
||||
<Attr Name="ImportTime" Val="1730977142"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="sys_clk_gen"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
@@ -801,66 +698,6 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_util_ds_buf_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_ps_util_ds_buf_0_0" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_util_ds_buf_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_ps_util_ds_buf_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_util_ds_buf_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_util_ds_buf_0_0_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_util_ds_buf_pl_clk_0_synth_1" Type="Ft3:Synth" SrcSet="system_ps_util_ds_buf_pl_clk_0" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_util_ds_buf_pl_clk_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_ps_util_ds_buf_pl_clk_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_util_ds_buf_pl_clk_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_util_ds_buf_pl_clk_0_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_util_ds_buf_pl_clk_1_synth_1" Type="Ft3:Synth" SrcSet="system_ps_util_ds_buf_pl_clk_1" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_util_ds_buf_pl_clk_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_ps_util_ds_buf_pl_clk_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_util_ds_buf_pl_clk_1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_util_ds_buf_pl_clk_1_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_xpm_cdc_gen_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_ps_xpm_cdc_gen_0_0" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_xpm_cdc_gen_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_ps_xpm_cdc_gen_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_xpm_cdc_gen_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_xpm_cdc_gen_0_0_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_xpm_cdc_gen_pl_sysref_0_synth_1" Type="Ft3:Synth" SrcSet="system_ps_xpm_cdc_gen_pl_sysref_0" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_xpm_cdc_gen_pl_sysref_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_ps_xpm_cdc_gen_pl_sysref_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_xpm_cdc_gen_pl_sysref_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_xpm_cdc_gen_pl_sysref_0_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_clk_wiz_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_ps_clk_wiz_0_0" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_clk_wiz_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_ps_clk_wiz_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_clk_wiz_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_clk_wiz_0_0_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_axi_bram_ctrl_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_ps_axi_bram_ctrl_0_0" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_axi_bram_ctrl_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_ps_axi_bram_ctrl_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_axi_bram_ctrl_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_axi_bram_ctrl_0_0_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
||||
@@ -881,59 +718,9 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_auto_pc_2_synth_1" Type="Ft3:Synth" SrcSet="system_ps_auto_pc_2" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_auto_pc_2" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_ps_auto_pc_2_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_auto_pc_2_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_auto_pc_2_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_system_management_wiz_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_ps_system_management_wiz_0_0" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_system_management_wiz_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_ps_system_management_wiz_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_system_management_wiz_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_system_management_wiz_0_0_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_auto_ds_3_synth_1" Type="Ft3:Synth" SrcSet="system_ps_auto_ds_3" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_auto_ds_3" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_ps_auto_ds_3_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_auto_ds_3_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_auto_ds_3_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_auto_ds_4_synth_1" Type="Ft3:Synth" SrcSet="system_ps_auto_ds_4" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_auto_ds_4" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_ps_auto_ds_4_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_auto_ds_4_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_auto_ds_4_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_auto_pc_3_synth_1" Type="Ft3:Synth" SrcSet="system_ps_auto_pc_3" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_auto_pc_3" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_ps_auto_pc_3_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_auto_pc_3_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_auto_pc_3_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -942,6 +729,16 @@
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_axi_timer_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_ps_axi_timer_0_0" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_axi_timer_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_ps_axi_timer_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_axi_timer_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_axi_timer_0_0_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="sys_clk_gen_synth_1" Type="Ft3:Synth" SrcSet="sys_clk_gen" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="sys_clk_gen" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/sys_clk_gen_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/sys_clk_gen_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/sys_clk_gen_synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
@@ -1260,108 +1057,6 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_util_ds_buf_0_0_impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_util_ds_buf_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_ps_util_ds_buf_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_util_ds_buf_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_util_ds_buf_0_0_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_util_ds_buf_pl_clk_0_impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_util_ds_buf_pl_clk_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_ps_util_ds_buf_pl_clk_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_util_ds_buf_pl_clk_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_util_ds_buf_pl_clk_0_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_util_ds_buf_pl_clk_1_impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_util_ds_buf_pl_clk_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_ps_util_ds_buf_pl_clk_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_util_ds_buf_pl_clk_1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_util_ds_buf_pl_clk_1_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_xpm_cdc_gen_0_0_impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_xpm_cdc_gen_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_ps_xpm_cdc_gen_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_xpm_cdc_gen_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_xpm_cdc_gen_0_0_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_xpm_cdc_gen_pl_sysref_0_impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_xpm_cdc_gen_pl_sysref_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_ps_xpm_cdc_gen_pl_sysref_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_xpm_cdc_gen_pl_sysref_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_xpm_cdc_gen_pl_sysref_0_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_clk_wiz_0_0_impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_clk_wiz_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_ps_clk_wiz_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_clk_wiz_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_clk_wiz_0_0_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_axi_bram_ctrl_0_0_impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_axi_bram_ctrl_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_ps_axi_bram_ctrl_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_axi_bram_ctrl_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_axi_bram_ctrl_0_0_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
||||
@@ -1396,87 +1091,9 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_auto_pc_2_impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_auto_pc_2" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_ps_auto_pc_2_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_auto_pc_2_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_auto_pc_2_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_system_management_wiz_0_0_impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_system_management_wiz_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_ps_system_management_wiz_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_system_management_wiz_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_system_management_wiz_0_0_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_auto_ds_3_impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_auto_ds_3" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_ps_auto_ds_3_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_auto_ds_3_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_auto_ds_3_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_auto_ds_4_impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_auto_ds_4" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_ps_auto_ds_4_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_auto_ds_4_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_auto_ds_4_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_auto_pc_3_impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_auto_pc_3" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_ps_auto_pc_3_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_auto_pc_3_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_auto_pc_3_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -1492,6 +1109,23 @@
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_ps_axi_timer_0_0_impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="system_ps_axi_timer_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_ps_axi_timer_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ps_axi_timer_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_ps_axi_timer_0_0_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="sys_clk_gen_impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="sys_clk_gen" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="sys_clk_gen_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/sys_clk_gen_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/sys_clk_gen_impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
|
||||
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