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fix: 修改RF-DAC输出电流;修改LMK04828 PL SYSREF输出

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1. RF-DAC无法发出信号,经查原理图启用了3.0V端接电压,可能与20mA输出无法匹配;
2. PL SYSREF在原有LMK04828配置中被关闭,现开启(虽然此版本RFDC未启用MTS).
This commit is contained in:
josh
2024-11-08 18:19:13 +08:00
parent 814724c417
commit d555d25452
8 changed files with 66 additions and 70 deletions
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rfsoc_eval_nco/rfsoc_eval_nco.xpr
+2 -6
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@@ -740,9 +740,7 @@
</Run>
<Run Id="sys_clk_gen_synth_1" Type="Ft3:Synth" SrcSet="sys_clk_gen" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="sys_clk_gen" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/sys_clk_gen_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/sys_clk_gen_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/sys_clk_gen_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1127,9 +1125,7 @@
</Run>
<Run Id="sys_clk_gen_impl_1" Type="Ft2:EntireDesign" Part="xczu48dr-fsvg1517-2-i" ConstrsSet="sys_clk_gen" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="sys_clk_gen_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/sys_clk_gen_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/sys_clk_gen_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>