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fix: 修改RF-DAC输出电流;修改LMK04828 PL SYSREF输出

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1. RF-DAC无法发出信号,经查原理图启用了3.0V端接电压,可能与20mA输出无法匹配;
2. PL SYSREF在原有LMK04828配置中被关闭,现开启(虽然此版本RFDC未启用MTS).
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josh
2024-11-08 18:19:13 +08:00
parent 814724c417
commit d555d25452
8 changed files with 66 additions and 70 deletions
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rfsoc_eval_nco/vitis_classic_autobuild/source/dev_profile/lmk04828_profile.c
+1 -1
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@@ -87,7 +87,7 @@ const struct lmk04828_config lmk04828_default_config[] = {
{0x0123, 0x00}, // DCLK: [7-3] analog delay (ADLY) value, 25 ps per lsb; [2] ADLY input mux; [1-0] DCLK input mux
{0x0124, 0x22}, // [6] DCLK half step value; [5] SDCLK output MUX; [4-1] SDCLK DDLY; [0] SYSREF half step value
{0x0125, 0x00}, // SYSREF: [4] ADLY enable; [3:0] ADLY value, 600 ps + 150 ps per lsb
{0x0126, 0xF1}, // [7] DCLK DDLY enable; [6] DCLK glitchless half step enable; [5] DCLK glitchless ADLY enable; [4] DCLK ADLY enable; [3]: clock group enable; [2-1] SYSREF disable mode; [0]: SYSREF disable
{0x0126, 0xF0}, // [7] DCLK DDLY enable; [6] DCLK glitchless half step enable; [5] DCLK glitchless ADLY enable; [4] DCLK ADLY enable; [3]: clock group enable; [2-1] SYSREF disable mode; [0]: SYSREF disable
{0x0127, 0x55}, // [7] SDCLK output polarity; [6-4] SDCLK output format; [3] DCLK output polarity; [2:0] DCLK output format
// device clock 10
{0x0128, 0x00}, // [6] output drive level (ODL); [5] input drive level (IDL); [4-0] device clock (DCLK) output divider