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fix: 修改时隙表编号,配置时隙表时同时修改初始建网时隙表;修改自检回令

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This commit is contained in:
josh
2025-08-21 16:30:50 +08:00
parent 7d3624e946
commit 9e4fb6ffb5
8 changed files with 68 additions and 43 deletions
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doc/comtool-plugin-hsjl.py
+18 -18
View File
@@ -78,19 +78,19 @@ class Plugin(Plugin_Base):
)
},
{
"caption": "装订 - 【主 - 0x01】128 kbps，时隙表 0",
"caption": "装订 - 【主 - 0x01】128 kbps，时隙表 1",
"icon": "fa5.play-circle",
"data": "5A 54 E3 EE AA 01 22 00 00 9E 06 5A FE"
"data": "5A 54 E3 EE AA 01 22 01 00 9F 06 5A FE"
},
{
"caption": "装订 - 【主 - 0x01】512 kbps，时隙表 1",
"caption": "装订 - 【主 - 0x01】512 kbps，时隙表 2",
"icon": "fa5.play-circle",
"data": "5A 54 E3 EE AA 01 33 01 00 B0 06 5A FE"
"data": "5A 54 E3 EE AA 01 33 02 00 B1 06 5A FE"
},
{
"caption": "装订 - 【主 - 0x01】2 Mbps，时隙表 2",
"caption": "装订 - 【主 - 0x01】2 Mbps，时隙表 3",
"icon": "fa5.play-circle",
"data": "5A 54 E3 EE AA 01 44 02 00 C2 06 5A FE"
"data": "5A 54 E3 EE AA 01 44 03 00 C3 06 5A FE"
},
{
"caption": "装订 - 【主 - 0x01】静默",
@@ -98,19 +98,19 @@ class Plugin(Plugin_Base):
"data": "5A 54 E3 EE 55 01 22 00 00 49 06 5A FE"
},
{
"caption": "装订 - 【从 - 0x02】128 kbps，时隙表 0",
"caption": "装订 - 【从 - 0x02】128 kbps，时隙表 1",
"icon": "fa5.play-circle",
"data": "5A 54 E3 EE AA 02 22 00 00 9F 06 5A FE"
"data": "5A 54 E3 EE AA 02 22 01 00 A0 06 5A FE"
},
{
"caption": "装订 - 【从 - 0x02】512 kbps，时隙表 1",
"caption": "装订 - 【从 - 0x02】512 kbps，时隙表 2",
"icon": "fa5.play-circle",
"data": "5A 54 E3 EE AA 02 33 01 00 B1 06 5A FE"
"data": "5A 54 E3 EE AA 02 33 02 00 B2 06 5A FE"
},
{
"caption": "装订 - 【从 - 0x02】2M bps，时隙表 2",
"caption": "装订 - 【从 - 0x02】2M bps，时隙表 3",
"icon": "fa5.play-circle",
"data": "5A 54 E3 EE AA 02 44 02 00 C3 06 5A FE"
"data": "5A 54 E3 EE AA 02 44 03 00 C4 06 5A FE"
},
{
"caption": "装订 - 【从 - 0x02】静默",
@@ -118,19 +118,19 @@ class Plugin(Plugin_Base):
"data": "5A 54 E3 EE 55 02 22 00 00 4A 06 5A FE"
},
{
"caption": "装订 - 【从 - 0x03】128 kbps，时隙表 0",
"caption": "装订 - 【从 - 0x03】128 kbps，时隙表 1",
"icon": "fa5.play-circle",
"data": "5A 54 E3 EE AA 03 22 00 00 A0 06 5A FE"
"data": "5A 54 E3 EE AA 03 22 01 00 A1 06 5A FE"
},
{
"caption": "装订 - 【从 - 0x03】512 kbps，时隙表 1",
"caption": "装订 - 【从 - 0x03】512 kbps，时隙表 2",
"icon": "fa5.play-circle",
"data": "5A 54 E3 EE AA 03 33 01 00 B2 06 5A FE"
"data": "5A 54 E3 EE AA 03 33 02 00 B3 06 5A FE"
},
{
"caption": "装订 - 【从 - 0x03】2 Mbps，时隙表 2",
"caption": "装订 - 【从 - 0x03】2 Mbps，时隙表 3",
"icon": "fa5.play-circle",
"data": "5A 54 E3 EE AA 03 44 02 00 C4 06 5A FE"
"data": "5A 54 E3 EE AA 03 44 03 00 C5 06 5A FE"
},
{
"caption": "装订 - 【从 - 0x03】静默",
src/main.c
+14 -9
View File
@@ -80,7 +80,7 @@ struct callback_desc apptimer_callback_desc = {
// .headId = L2_HEAD_ID,
// .netScale = L2_NET_SCALE,
// .initTable = initRoutTable,
// .normalTable = normalRoutTable0,
// .normalTable = normalRoutTable1,
// .serviceRate = L2_SVC_512K,
// .phyInstPtr = NULL, // physical layer reference
// .tmcInstPtr = NULL
@@ -93,7 +93,7 @@ L2_CONFIG linkConfig = {
.headId = L2_HEAD_ID,
.netScale = L2_NET_SCALE,
.initTable = initRoutTable,
.normalTable = normalRoutTable0,
.normalTable = normalRoutTable1,
.serviceRate = L2_SVC_512K,
.phyInstPtr = NULL, // physical layer reference
.tmcInstPtr = NULL
@@ -202,6 +202,7 @@ int32_t SetupInterruptSystem(struct irq_ctrl_desc *descPtr)
XScuGic_CPUWriteReg((XScuGic *)(xil_dev->instance), XSCUGIC_EOI_OFFSET, intrState);
/* Initialize physical layer interrupt. */
// Set interrupt trigger level
Status = irq_trigger_level_set(descPtr, PHY_INTR_ID, IRQ_EDGE_RISING);
if (Status != SUCCESS)
{
@@ -224,6 +225,7 @@ int32_t SetupInterruptSystem(struct irq_ctrl_desc *descPtr)
}
/* Initialize linklayer layer interrupt. */
// Set interrupt trigger level
Status = irq_trigger_level_set(descPtr, PERIODIC_5MS_INTR_ID, IRQ_EDGE_RISING);
if (Status != SUCCESS)
{
@@ -246,17 +248,18 @@ int32_t SetupInterruptSystem(struct irq_ctrl_desc *descPtr)
}
/* Initialize system bus interrupt. */
// Set interrupt trigger level
Status = irq_trigger_level_set(descPtr, SYSBUS_TX_INTR_ID, IRQ_EDGE_RISING);
if (Status != SUCCESS)
{
DBG_ERROR("PHY_INTR trigger level set FAILED, ErrorCode: %" PRId32 ".\n", Status);
DBG_ERROR("SYSBUS_TX_INTR trigger level set FAILED, ErrorCode: %" PRId32 ".\n", Status);
return Status;
}
// Set interrupt priority
Status = irq_set_priority(descPtr, SYSBUS_TX_INTR_ID, 0x10);
if (Status != SUCCESS)
{
DBG_ERROR("PHY_INTR priority level set FAILED, ErrorCode: %" PRId32 ".\n", Status);
DBG_ERROR("SYSBUS_TX_INTR priority level set FAILED, ErrorCode: %" PRId32 ".\n", Status);
return Status;
}
@@ -264,20 +267,22 @@ int32_t SetupInterruptSystem(struct irq_ctrl_desc *descPtr)
Status = irq_register_callback(descPtr, SYSBUS_TX_INTR_ID, &sysbus_tx_callback_desc);
if (Status != SUCCESS)
{
DBG_ERROR("PHY_INTR register callback FAILED, ErrorCode: %" PRId32 ".\n", Status);
DBG_ERROR("SYSBUS_TX_INTR register callback FAILED, ErrorCode: %" PRId32 ".\n", Status);
return Status;
}
// Set interrupt trigger level
Status = irq_trigger_level_set(descPtr, SYSBUS_RX_INTR_ID, IRQ_EDGE_RISING);
if (Status != SUCCESS)
{
DBG_ERROR("PHY_INTR trigger level set FAILED, ErrorCode: %" PRId32 ".\n", Status);
DBG_ERROR("SYSBUS_RX_INTR trigger level set FAILED, ErrorCode: %" PRId32 ".\n", Status);
return Status;
}
// Set interrupt priority
Status = irq_set_priority(descPtr, SYSBUS_RX_INTR_ID, 0x18);
if (Status != SUCCESS)
{
DBG_ERROR("PHY_INTR priority level set FAILED, ErrorCode: %" PRId32 ".\n", Status);
DBG_ERROR("SYSBUS_RX_INTR priority level set FAILED, ErrorCode: %" PRId32 ".\n", Status);
return Status;
}
@@ -285,7 +290,7 @@ int32_t SetupInterruptSystem(struct irq_ctrl_desc *descPtr)
Status = irq_register_callback(descPtr, SYSBUS_RX_INTR_ID, &sysbus_rx_callback_desc);
if (Status != SUCCESS)
{
DBG_ERROR("PHY_INTR register callback FAILED, ErrorCode: %" PRId32 ".\n", Status);
DBG_ERROR("SYSBUS_RX_INTR register callback FAILED, ErrorCode: %" PRId32 ".\n", Status);
return Status;
}
@@ -294,7 +299,7 @@ int32_t SetupInterruptSystem(struct irq_ctrl_desc *descPtr)
Status = irq_register_callback(descPtr, APPTIMER_INTR_ID, &apptimer_callback_desc);
if (Status != SUCCESS)
{
DBG_ERROR("PHY_INTR register callback FAILED, ErrorCode: %" PRId32 ".\n", Status);
DBG_ERROR("APPTIMER_INTR register callback FAILED, ErrorCode: %" PRId32 ".\n", Status);
return Status;
}
src/networking/link_layer/link_layer.c
+1 -1
View File
@@ -890,7 +890,7 @@ int32_t Linklayer_EventHandler(L2_INST *instPtr, const L2_EVENT *l2Event)
{
UpdateMainSate(instPtr, L2_NORMAL_STATE);
instPtr->rtneConfig.rtneTable = instPtr->config.normalTable;
instPtr->rtneConfig.rtnePrd = ARRAY_SIZE(normalRoutTable0);
instPtr->rtneConfig.rtnePrd = ARRAY_SIZE(normalRoutTable1);
}
else
{
src/networking/link_layer/link_layer.h
+1 -1
View File
@@ -132,9 +132,9 @@ typedef struct
/************************** Variable Definitions *****************************/
extern L2_RTNE_TABLE_ENTRY *initRoutTable[L2_INIT_RTNE_PERIOD];
extern L2_RTNE_TABLE_ENTRY *normalRoutTable0[L2_INIT_RTNE_PERIOD];
extern L2_RTNE_TABLE_ENTRY *normalRoutTable1[L2_INIT_RTNE_PERIOD];
extern L2_RTNE_TABLE_ENTRY *normalRoutTable2[L2_INIT_RTNE_PERIOD];
extern L2_RTNE_TABLE_ENTRY *normalRoutTable3[L2_INIT_RTNE_PERIOD];
/************************** Function Prototypes ******************************/
/**
* @defgroup LinkLayer_Main
src/networking/link_layer/routine_table.c
+3 -3
View File
@@ -858,17 +858,17 @@ L2_RTNE_TABLE_ENTRY *initRoutTable[L2_INIT_RTNE_PERIOD] =
tab10Mng10Svc
};
L2_RTNE_TABLE_ENTRY *normalRoutTable0[L2_INIT_RTNE_PERIOD] =
L2_RTNE_TABLE_ENTRY *normalRoutTable1[L2_INIT_RTNE_PERIOD] =
{
tab10Mng10Svc
};
L2_RTNE_TABLE_ENTRY *normalRoutTable1[L2_INIT_RTNE_PERIOD] =
L2_RTNE_TABLE_ENTRY *normalRoutTable2[L2_INIT_RTNE_PERIOD] =
{
tab10Mng3Svc
};
L2_RTNE_TABLE_ENTRY *normalRoutTable2[L2_INIT_RTNE_PERIOD] =
L2_RTNE_TABLE_ENTRY *normalRoutTable3[L2_INIT_RTNE_PERIOD] =
{
tab3Mng3Svc
};
src/networking/phy_layer/phy_layer.c
+9 -5
View File
@@ -1026,9 +1026,10 @@ void Phy_RefreshHwSate(PHY_INST *instPtr)
instPtr->hwSate.spFpgaTemp = (evalData > TEMPERATURE_MAX)
? INT8_MAX
: ((evalData < TEMPERATURE_MIN) ? INT8_MIN : (int8_t)round(evalData / TEMPERATURE_LSB));
instPtr->hwSate.isSpOk = (instPtr->hwSate.spFpgaVolt == (VOLT_PS_OK | VOLT_PSAUX_OK | VOLT_DDR_OK | VOLT_PL_OK | VOLT_PLAUX_OK | VOLT_BRAM_OK))
&& (instPtr->hwSate.spClkState == (CLK_SP_PLL1_LOCK | CLK_SP_PLL2_LOCK))
&& (instPtr->hwSate.spAdLockState == (CLK_AD0_BBPLL_LOCK | CLK_AD0_RFPLL_LOCK | CLK_AD1_BBPLL_LOCK | CLK_AD1_RFPLL_LOCK));
// FIXME: XADC range needs further refine
// instPtr->hwSate.isSpOk = (instPtr->hwSate.spFpgaVolt == (VOLT_PS_OK | VOLT_PSAUX_OK | VOLT_DDR_OK | VOLT_PL_OK | VOLT_PLAUX_OK | VOLT_BRAM_OK))
// && (instPtr->hwSate.spClkState == (CLK_SP_PLL1_LOCK | CLK_SP_PLL2_LOCK));
instPtr->hwSate.isSpOk = (instPtr->hwSate.spClkState == (CLK_SP_PLL1_LOCK | CLK_SP_PLL2_LOCK));
#else
double evalData;
instPtr->hwSate.isSpOk = true;
@@ -1109,8 +1110,11 @@ void Phy_RefreshHwSate(PHY_INST *instPtr)
instPtr->hwSate.spFpgaTemp = (evalData > TEMPERATURE_MAX)
? INT8_MAX
: ((evalData < TEMPERATURE_MIN) ? INT8_MIN : (int8_t)round(evalData / TEMPERATURE_LSB));
instPtr->hwSate.isSpOk = (instPtr->hwSate.spFpgaVolt == (VOLT_PS_OK | VOLT_PSAUX_OK | VOLT_DDR_OK | VOLT_PL_OK | VOLT_PLAUX_OK | VOLT_BRAM_OK))
&& (instPtr->hwSate.spClkState == (CLK_SP_PLL1_LOCK | CLK_SP_PLL2_LOCK))
// FIXME: XADC readback is required
// instPtr->hwSate.isSpOk = (instPtr->hwSate.spFpgaVolt == (VOLT_PS_OK | VOLT_PSAUX_OK | VOLT_DDR_OK | VOLT_PL_OK | VOLT_PLAUX_OK | VOLT_BRAM_OK))
// && (instPtr->hwSate.spClkState == (CLK_SP_PLL1_LOCK | CLK_SP_PLL2_LOCK))
// && (instPtr->hwSate.spAdLockState == (CLK_AD0_BBPLL_LOCK | CLK_AD0_RFPLL_LOCK | CLK_AD1_BBPLL_LOCK | CLK_AD1_RFPLL_LOCK));
instPtr->hwSate.isSpOk = (instPtr->hwSate.spClkState == (CLK_SP_PLL1_LOCK | CLK_SP_PLL2_LOCK))
&& (instPtr->hwSate.spAdLockState == (CLK_AD0_BBPLL_LOCK | CLK_AD0_RFPLL_LOCK | CLK_AD1_BBPLL_LOCK | CLK_AD1_RFPLL_LOCK));
#endif
#else
src/systembus/systembus.c
+12 -6
View File
@@ -345,24 +345,30 @@ static int32_t SystemBus_SystemConfig(SYSBUS *instPtr, uint8_t *msg)
{
switch (msg[WD_RTNE_CMD])
{
case 0:
{
reconfig |= (linkConfig.normalTable != normalRoutTable0);
linkConfig.normalTable = normalRoutTable0;
break;
}
case 1:
{
reconfig |= (linkConfig.initTable != normalRoutTable1);
reconfig |= (linkConfig.normalTable != normalRoutTable1);
linkConfig.initTable = normalRoutTable1;
linkConfig.normalTable = normalRoutTable1;
break;
}
case 2:
{
reconfig |= (linkConfig.initTable != normalRoutTable2);
reconfig |= (linkConfig.normalTable != normalRoutTable2);
linkConfig.initTable = normalRoutTable2;
linkConfig.normalTable = normalRoutTable2;
break;
}
case 3:
{
reconfig |= (linkConfig.initTable != normalRoutTable3);
reconfig |= (linkConfig.normalTable != normalRoutTable3);
linkConfig.initTable = normalRoutTable3;
linkConfig.normalTable = normalRoutTable3;
break;
}
default:
{
// Ignore current command
src/systembus/systembus.h
+10
View File
@@ -61,6 +61,15 @@
#define VOLT_ANT_NIL_OK BIT(4)
#define ANT_STATE_OK BIT(6)
#ifdef HSJL_GE
// Xilinx Recommended
#define IS_PS_VALID(x) (x <= 0.892 && x >= 0.808)
#define IS_PSAUX_VALID(x) (x <= 1.89 && x >= 1.71)
#define IS_DDR_VALID(x) (x <= 1.89 && x >= 1.14)
#define IS_PL_VALID(x) (x <= 0.892 && x >= 0.808)
#define IS_PLAUX_VALID(x) (x <= 1.89 && x >= 1.71)
#define IS_BRAM_VALID(x) (x <= 0.892 && x >= 0.808)
#else
// Xilinx Recommended
// #define IS_PS_VALID(x) (x <= 1.05 && x >= 0.95)
// #define IS_PSAUX_VALID(x) (x <= 1.89 && x >= 1.71)
@@ -74,6 +83,7 @@
#define IS_PL_VALID(x) (x <= 1.1 && (x) >= 0.9)
#define IS_PLAUX_VALID(x) ((x) <= 2.0 && (x) >= 1.6)
#define IS_BRAM_VALID(x) ((x) <= 1.1 && (x) >= 0.9)
#endif
#define CLK_SP_PLL1_LOCK BIT(0)
#define CLK_SP_PLL2_LOCK BIT(2)