add post josh-verilog-7

2023-04-16 14:39:19 +08:00
parent 0de9bc010f
commit 2ae9ba3003
3 changed files with 1332 additions and 2 deletions
@@ -1,6 +1,6 @@
 ---
 title: Josh 的学习笔记之 Verilog（Part 6——如何写好状态机）
-mathjax: true
+mathjax: false
 comments: true
 copyright: true
 toc: