update some post name

2023-04-18 23:54:26 +08:00
parent cc3a554bd5
commit ed034469eb
18 changed files with 24 additions and 24 deletions
@@ -1,5 +1,5 @@
 ---
-title: Josh 的学习笔记之 Verilog（Part 4 —— RTL 概念与常用 RTL 建模）
+title: "Josh's Notes: Verilog（Part 4 — RTL 概念与常用 RTL 建模）"
 mathjax: true
 comments: true
 copyright: true