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feat: add debug ios

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josh
2024-11-04 13:20:45 +08:00
parent 217de5babb
commit 9b451dbd05
6 changed files with 33 additions and 21 deletions
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sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.runs/impl_1/system_top.bit
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sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/constrs_1/imports/new/dj_47dr.xdc
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@@ -16,12 +16,23 @@ set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS33} [get_ports lmx_dac
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_mosi ] ;# LMX_RF_DAC_SDI set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_mosi ] ;# LMX_RF_DAC_SDI
set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_miso ] ;# LMX_RF_DAC_SDO set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_miso ] ;# LMX_RF_DAC_SDO
#RS485 # RS485
set_property -dict {PACKAGE_PIN J12 IOSTANDARD LVCMOS33} [get_ports RS_485_RxD ] ;# 47DR_RS422_RO_1 set_property -dict {PACKAGE_PIN J12 IOSTANDARD LVCMOS33} [get_ports RS_485_RxD ] ;# 47DR_RS422_RO_1
set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS33} [get_ports RS_485_RE_n ] ;# 47DR_RS422_RE_B_1 set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS33} [get_ports RS_485_RE_n ] ;# 47DR_RS422_RE_B_1
set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS33} [get_ports RS_485_TxD ] ;# 47DR_RS422_DI_1 set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS33} [get_ports RS_485_TxD ] ;# 47DR_RS422_DI_1
set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS33} [get_ports RS_485_DE ] ;# 47DR_RS422_DE set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS33} [get_ports RS_485_DE ] ;# 47DR_RS422_DE
# DEBUG IO
set_property -dict {PACKAGE_PIN E9 IOSTANDARD LVCMOS33} [get_ports debug_io_1 ] ;# 47DR_LVCMOS_1
set_property -dict {PACKAGE_PIN E10 IOSTANDARD LVCMOS33} [get_ports debug_io_2 ] ;# 47DR_LVCMOS_2
set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS33} [get_ports debug_io_3 ] ;# 47DR_LVCMOS_3
set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS33} [get_ports debug_io_4 ] ;# 47DR_LVCMOS_4
set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS33} [get_ports debug_io_5 ] ;# 47DR_LVCMOS_5
set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports debug_io_6 ] ;# 47DR_LVCMOS_6
set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS33} [get_ports debug_io_7 ] ;# 47DR_LVCMOS_7
set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS33} [get_ports debug_io_8 ] ;# 47DR_LVCMOS_8
set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS33} [get_ports debug_io_9 ] ;# 47DR_LVCMOS_9
# Route HDGC clock through BUFG to adjacent CMT # Route HDGC clock through BUFG to adjacent CMT
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_system_bd_wrapper/system_bd_i/mts_clk_gen/util_ds_buf_pl_clk/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O] #set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_system_bd_wrapper/system_bd_i/mts_clk_gen/util_ds_buf_pl_clk/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_system_bd_wrapper/system_bd_wrapper_i/mts_clk_gen/util_ds_buf_pl_clk/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O] set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_system_bd_wrapper/system_bd_wrapper_i/mts_clk_gen/util_ds_buf_pl_clk/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O]
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/sources_1/imports/new/system_top.v
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@@ -110,10 +110,19 @@ module system_top
input RS_485_RxD , input RS_485_RxD ,
output RS_485_RE_n , output RS_485_RE_n ,
output RS_485_TxD , output RS_485_TxD ,
output RS_485_DE output RS_485_DE ,
// ************************************************************************* // *************************************************************************
// ******************************* DEBUG IO ******************************** // ******************************* DEBUG IO ********************************
// ************************************************************************* // *************************************************************************
output debug_io_1 ,
output debug_io_2 ,
output debug_io_3 ,
output debug_io_4 ,
output debug_io_5 ,
output debug_io_6 ,
output debug_io_7 ,
output debug_io_8 ,
output debug_io_9
); );
sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.srcs/utils_1/imports/synth_1/system_top.dcp
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sjl_dj_rfsoc_df/sjl_dj_rfsoc_df.xpr
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@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2024.1 (64-bit) --> <!-- Product Version: Vivado v2024.1.2 (64-bit) -->
<!-- --> <!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. --> <!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
@@ -4414,9 +4414,7 @@
</Run> </Run>
<Run Id="system_bd_wrapper_auto_pc_4_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_auto_pc_4" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_auto_pc_4" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_auto_pc_4_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_4_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_4_synth_1" ParallelReportGen="true"> <Run Id="system_bd_wrapper_auto_pc_4_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_auto_pc_4" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_auto_pc_4" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_auto_pc_4_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_4_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_4_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/> <Step Id="synth_design"/>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -4426,9 +4424,7 @@
</Run> </Run>
<Run Id="system_bd_wrapper_auto_pc_3_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_auto_pc_3" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_auto_pc_3" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_auto_pc_3_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_3_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_3_synth_1" ParallelReportGen="true"> <Run Id="system_bd_wrapper_auto_pc_3_synth_1" Type="Ft3:Synth" SrcSet="system_bd_wrapper_auto_pc_3" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_auto_pc_3" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_wrapper_auto_pc_3_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_3_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_3_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/> <Step Id="synth_design"/>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -6105,9 +6101,7 @@
</Run> </Run>
<Run Id="system_bd_wrapper_auto_pc_4_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_auto_pc_4" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_wrapper_auto_pc_4_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_4_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_4_impl_1" ParallelReportGen="true"> <Run Id="system_bd_wrapper_auto_pc_4_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_auto_pc_4" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_wrapper_auto_pc_4_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_4_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_4_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/> <Step Id="init_design"/>
<Step Id="opt_design"/> <Step Id="opt_design"/>
<Step Id="power_opt_design"/> <Step Id="power_opt_design"/>
@@ -6124,9 +6118,7 @@
</Run> </Run>
<Run Id="system_bd_wrapper_auto_pc_3_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_auto_pc_3" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_wrapper_auto_pc_3_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_3_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_3_impl_1" ParallelReportGen="true"> <Run Id="system_bd_wrapper_auto_pc_3_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_wrapper_auto_pc_3" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_wrapper_auto_pc_3_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_3_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_wrapper_auto_pc_3_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/> <Step Id="init_design"/>
<Step Id="opt_design"/> <Step Id="opt_design"/>
<Step Id="power_opt_design"/> <Step Id="power_opt_design"/>
sjl_dj_rfsoc_df/system_top.xsa
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