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archive dl814_dj_48m, add dl814_k7_cal_coarse

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josh
2023-03-21 20:20:28 +08:00
parent fa4d745322
commit 0832a08d3d
3264 changed files with 9610614 additions and 13 deletions
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projects/datalink_814/dl814_dj_48m/ip/vio_manual_ctrl.xcix
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projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.runs/impl_1/debug_nets.ltx
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projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/SDK.log
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19:50:44 INFO : Registering command handlers for SDK TCF services
19:50:45 INFO : Launching XSCT server: xsct.bat -interactive D:\vivado-git\projects\datalink_814\dl814_dj_48m\project\dl814_dj_48m\dl814_dj_48m.sdk\temp_xsdb_launch_script.tcl
19:50:47 INFO : XSCT server has started successfully.
19:50:47 INFO : Successfully done setting XSCT server connection channel
19:50:47 INFO : Successfully done setting SDK workspace
19:50:47 INFO : Processing command line option -hwspec D:/vivado-git/projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/system_top.hdf.
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/.cproject
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projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/.project
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<name>dl814_dj</name>
<comment>Created by SDK v2019.1. dl814_dj_bsp - ps7_cortexa9_0</comment>
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projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/README.txt
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Empty application. Add your own sources.
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/Xilinx.spec
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*startfile:
crti%O%s crtbegin%O%s
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/common.c
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/**
* \file common.c
* \brief Contains Mykonos API common wrapper functions for user hardware platform drivers
*/
/**
* \page Disclaimer Legal Disclaimer
* Copyright 2015-2017 Analog Devices Inc.
* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
*
*/
#include <stdio.h>
#include <time.h>
#include <errno.h>
#include <stdint.h>
#include <stdlib.h>
#include "common.h"
#include "platform_drivers.h"
#include "parameters.h"
ADI_LOGLEVEL CMB_LOGLEVEL = ADIHAL_LOG_NONE;
static uint32_t _desired_time_to_elapse_us = 0;
struct spi_desc *spi_ad_desc;
struct gpio_desc *gpio_ad9371_resetb;
struct gpio_desc *gpio_ad9528_resetb;
struct gpio_desc *gpio_ad9528_sysref_req;
commonErr_t CMB_initPlatform(void)
{
struct spi_init_param spi_param;
int32_t status = COMMONERR_OK;
status |= gpio_get(&gpio_ad9371_resetb, AD9371_RESET_B);
status |= gpio_get(&gpio_ad9528_resetb, AD9528_RESET_B);
status |= gpio_get(&gpio_ad9528_sysref_req, AD9528_SYSREF_REQ);
spi_param.id = 0;
spi_param.mode = SPI_MODE_0;
spi_param.chip_select = AD9371_CS;
spi_param.max_speed_hz = 25000000u;
status |= spi_init(&spi_ad_desc, &spi_param);
if (status != SUCCESS) {
return COMMONERR_FAILED;
}
return COMMONERR_OK;
}
commonErr_t CMB_closeHardware(void)
{
return(COMMONERR_OK);
}
commonErr_t CMB_setGPIO(uint32_t GPIO)
{
return(COMMONERR_OK);
}
commonErr_t CMB_hardReset(uint8_t spiChipSelectIndex)
{
struct gpio_desc *reset_gpio;
switch (spiChipSelectIndex) {
case AD9371_CS:
reset_gpio = gpio_ad9371_resetb;
break;
case AD9528_CS:
reset_gpio = gpio_ad9528_resetb;
break;
default:
return(COMMONERR_FAILED);
}
gpio_direction_output(reset_gpio, 1);
CMB_wait_ms(1);
gpio_direction_output(reset_gpio, 0);
CMB_wait_ms(1);
gpio_direction_output(reset_gpio, 1);
CMB_wait_ms(1);
return(COMMONERR_OK);
}
commonErr_t CMB_setSPIOptions(spiSettings_t *spiSettings)
{
return(COMMONERR_OK);
}
commonErr_t CMB_setSPIChannel(uint16_t chipSelectIndex )
{
return(COMMONERR_OK);
}
commonErr_t CMB_SPIWriteByte(spiSettings_t *spiSettings, uint16_t addr,
uint8_t data)
{
uint8_t buf[3];
spi_ad_desc->chip_select = spiSettings->chipSelectIndex - 1;
buf[0] = (uint8_t) ((addr >> 8) & 0x7f);
buf[1] = (uint8_t) (addr & 0xff);
buf[2] = (uint8_t) data;
spi_write_and_read(spi_ad_desc, buf, 3);
return(COMMONERR_OK);
}
commonErr_t CMB_SPIWriteBytes(spiSettings_t *spiSettings, uint16_t *addr,
uint8_t *data, uint32_t count)
{
uint32_t index;
for (index = 0; index < count; index++)
if (CMB_SPIWriteByte(spiSettings, *(addr + index),
*(data + index)) != COMMONERR_OK)
return(COMMONERR_FAILED);
return(COMMONERR_OK);
}
commonErr_t CMB_SPIReadByte(spiSettings_t *spiSettings, uint16_t addr,
uint8_t *readdata)
{
uint8_t buf[3];
spi_ad_desc->chip_select = spiSettings->chipSelectIndex - 1;
buf[0] = (uint8_t) ((addr >> 8) | 0x80);
buf[1] = (uint8_t) (addr & 0xff);
buf[2] = (uint8_t) 0x00;
spi_write_and_read(spi_ad_desc, buf, 3);
*readdata = buf[2];
return(COMMONERR_OK);
}
commonErr_t CMB_SPIWriteField(spiSettings_t *spiSettings, uint16_t addr,
uint8_t field_val, uint8_t mask, uint8_t start_bit)
{
uint8_t data;
if (CMB_SPIReadByte(spiSettings, addr, &data) != COMMONERR_OK)
return(COMMONERR_FAILED);
data = (data & ~mask) | ((field_val << start_bit) & mask);
if (CMB_SPIWriteByte(spiSettings, addr, data) != COMMONERR_OK)
return(COMMONERR_FAILED);
return(COMMONERR_OK);
}
/* read a field in a single register space (not multibyte fields) */
commonErr_t CMB_SPIReadField(spiSettings_t *spiSettings, uint16_t addr,
uint8_t *field_val, uint8_t mask, uint8_t start_bit)
{
uint8_t data;
if (CMB_SPIReadByte(spiSettings, addr, &data) != COMMONERR_OK)
return(COMMONERR_FAILED);
data = (data & mask) >> start_bit;
*field_val = data;
return(COMMONERR_OK);
}
commonErr_t CMB_writeToLog(ADI_LOGLEVEL level, uint8_t deviceIndex,
uint32_t errorCode, const char *comment)
{
if((CMB_LOGLEVEL & ADIHAL_LOG_ERROR) && (level == ADIHAL_LOG_ERROR)) {
printf("ERROR: %d: %s", (int)errorCode, comment);
} else if((CMB_LOGLEVEL & ADIHAL_LOG_WARNING)
&& (level == ADIHAL_LOG_WARNING)) {
printf("WARNING: %d: %s",(int)errorCode, comment);
} else if((CMB_LOGLEVEL & ADIHAL_LOG_MESSAGE)
&& (level == ADIHAL_LOG_MESSAGE)) {
printf("MESSAGE: %d: %s",(int)errorCode, comment);
} else if(CMB_LOGLEVEL == ADIHAL_LOG_NONE ) {
//printf("MESSAGE: %d: %s",(int)errorCode, comment);
} else {
printf("Undefined Log Level: 0x%X", level);
}
return(COMMONERR_OK);
}
/* if filename null, a default path will be used in logging.c */
commonErr_t CMB_openLog(const char *filename)
{
return(COMMONERR_OK);
}
commonErr_t CMB_closeLog(void)
{
return(COMMONERR_OK);
}
commonErr_t CMB_flushLog(void)
{
return(COMMONERR_OK);
}
commonErr_t CMB_wait_ms(uint32_t time_ms)
{
mdelay(time_ms);
return(COMMONERR_OK);
}
commonErr_t CMB_wait_us(uint32_t time_us)
{
udelay(time_us);
return(COMMONERR_OK);
}
commonErr_t CMB_setTimeout_ms(uint32_t timeOut_ms)
{
#ifdef _XPARAMETERS_PS_H_
_desired_time_to_elapse_us = timeOut_ms * 1000;
#else
_desired_time_to_elapse_us = timeOut_ms * 50; // FIXME
#endif
return(COMMONERR_OK);
}
commonErr_t CMB_setTimeout_us(uint32_t timeOut_us)
{
_desired_time_to_elapse_us = timeOut_us;
return(COMMONERR_OK);
}
commonErr_t CMB_hasTimeoutExpired()
{
udelay(1);
_desired_time_to_elapse_us--;
if (_desired_time_to_elapse_us > 0)
return(COMMONERR_OK);
return(COMMONERR_FAILED);
}
commonErr_t CMB_regRead(uint32_t offset, uint32_t *data)
{
return(COMMONERR_OK);
}
commonErr_t CMB_regWrite(uint32_t offset, uint32_t data)
{
return(COMMONERR_OK);
}
commonErr_t CMB_memRead(uint32_t offset, uint32_t *data, uint32_t len)
{
return(COMMONERR_OK);
}
commonErr_t CMB_memWrite(uint32_t offset, uint32_t *data, uint32_t len)
{
return(COMMONERR_OK);
}
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/common.h
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/**
* \file common.h
* \brief Contains type definitions and prototype declarations for common.c
*/
/**
* \page Disclaimer Legal Disclaimer
* Copyright 2015-2017 Analog Devices Inc.
* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
*
*/
#ifndef _COMMON_H_
#define _COMMON_H_
#ifdef __cplusplus
extern "C" {
#endif
/* build project settings include the path to the desired platform folder for correct includes */
#include "stdint.h"
#define THROW_ERROR()
#define SPIARRAYSIZE 1024
/* assuming 3 byte SPI message - integer math enforces floor() */
#define SPIARRAYTRIPSIZE ((SPIARRAYSIZE / 3) * 3)
/*========================================
* Enums and structures
*=======================================*/
/* proposed to increase number of error return values to make unique for each return */
typedef enum
{
ADIERR_OK=0,
ADIERR_INV_PARM,
ADIERR_FAILED
} ADI_ERR;
/*!< \brief COMMON layer error reporting enumerated types */
typedef enum
{
COMMONERR_OK=0,
COMMONERR_FAILED
} commonErr_t;
/* bit 0 is MESSAGE, bit 1 is WARNING, bit 2 is ERROR */
typedef enum
{
ADIHAL_LOG_NONE = 0x0,
ADIHAL_LOG_MESSAGE = 0x1,
ADIHAL_LOG_WARNING = 0x2,
ADIHAL_LOG_ERROR = 0x4,
ADIHAL_LOG_SPI = 0x8,
ADIHAL_LOG_AXI_REG = 0x10,
ADIHAL_LOG_AXI_MEM = 0x20,
ADIHAL_LOG_ALL = 0x3F
} ADI_LOGLEVEL;
/**
* \brief Data structure to hold SPI settings for all system device types
*/
typedef struct
{
uint8_t chipSelectIndex; ///< valid 1~8
uint8_t writeBitPolarity; ///< the level of the write bit of a SPI write instruction word, value is inverted for SPI read operation
uint8_t longInstructionWord; ///< 1 = 16bit instruction word, 0 = 8bit instruction word
uint8_t MSBFirst; ///< 1 = MSBFirst, 0 = LSBFirst
uint8_t CPHA; ///< clock phase, sets which clock edge the data updates (valid 0 or 1)
uint8_t CPOL; ///< clock polarity 0 = clock starts low, 1 = clock starts high
uint8_t enSpiStreaming; ///< Not implemented. SW feature to improve SPI throughput.
uint8_t autoIncAddrUp; ///< Not implemented. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr = addr-1
uint8_t fourWireMode; ///< 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode.
uint32_t spiClkFreq_Hz; ///< SPI Clk frequency in Hz (default 25000000), platform will use next lowest frequency that it's baud rate generator can create */
} spiSettings_t;
/* global variable so application layer can set the log level */
extern ADI_LOGLEVEL CMB_LOGLEVEL;
extern struct spi_desc *spi_ad_desc;
extern struct gpio_desc *gpio_ad9371_resetb;
extern struct gpio_desc *gpio_ad9528_resetb;
extern struct gpio_desc *gpio_ad9528_sysref_req;
/* initialize hardware platform */
commonErr_t CMB_initPlatform(void);
/* close hardware pointers */
commonErr_t CMB_closeHardware(void);
/* GPIO function */
commonErr_t CMB_setGPIO(uint32_t GPIO);
/* hardware reset function */
commonErr_t CMB_hardReset(uint8_t spiChipSelectIndex);
/* SPI read/write functions */
commonErr_t CMB_setSPIOptions(spiSettings_t *spiSettings); /* allows the platform HAL to work with devices with various SPI settings */
commonErr_t CMB_setSPIChannel(uint16_t chipSelectIndex ); /* value of 0 deasserts all chip selects */
commonErr_t CMB_SPIWriteByte(spiSettings_t *spiSettings, uint16_t addr, uint8_t data); /* single SPI byte write function */
commonErr_t CMB_SPIWriteBytes(spiSettings_t *spiSettings, uint16_t *addr, uint8_t *data, uint32_t count);
commonErr_t CMB_SPIReadByte (spiSettings_t *spiSettings, uint16_t addr, uint8_t *readdata); /* single SPI byte read function */
commonErr_t CMB_SPIWriteField(spiSettings_t *spiSettings, uint16_t addr, uint8_t field_val, uint8_t mask, uint8_t start_bit); /* write a field in a single register */
commonErr_t CMB_SPIReadField (spiSettings_t *spiSettings, uint16_t addr, uint8_t *field_val, uint8_t mask, uint8_t start_bit); /* read a field in a single register */
/* platform timer functions */
commonErr_t CMB_wait_ms(uint32_t time_ms);
commonErr_t CMB_wait_us(uint32_t time_us);
commonErr_t CMB_setTimeout_ms(uint32_t timeOut_ms);
commonErr_t CMB_setTimeout_us(uint32_t timeOut_us);
commonErr_t CMB_hasTimeoutExpired();
/* platform logging functions */
commonErr_t CMB_openLog(const char *filename);
commonErr_t CMB_closeLog(void);
commonErr_t CMB_writeToLog(ADI_LOGLEVEL level, uint8_t deviceIndex, uint32_t errorCode, const char *comment);
commonErr_t CMB_flushLog(void);
/* platform FPGA AXI register read/write functions */
commonErr_t CMB_regRead(uint32_t offset, uint32_t *data);
commonErr_t CMB_regWrite(uint32_t offset, uint32_t data);
/* platform DDR3 memory read/write functions */
commonErr_t CMB_memRead(uint32_t offset, uint32_t *data, uint32_t len);
commonErr_t CMB_memWrite(uint32_t offset, uint32_t *data, uint32_t len);
#ifdef __cplusplus
}
#endif
#endif
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/headless.c
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/*
* headless.h
*
* Created on: 2021Äê6ÔÂ8ÈÕ
* Author: Josh
*/
#ifndef SRC_HEADLESS_H_
#define SRC_HEADLESS_H_
/***************************** Include Files ********************************/
#include <stdlib.h>
#include <stdio.h>
#include "xil_cache.h"
#include "xscugic.h"
//#include "xgpio.h"
#include "common.h"
#include "./mykonos/ad9528.h"
#include "./mykonos/mykonos.h"
#include "./mykonos/Mykonos_M3.h"
#include "./mykonos/mykonos_gpio.h"
#include "myk_ad9528init.h"
#include "myk_init.h"
#include "parameters.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/*
*
* This function setups ad9528 and ad9371 via spi.
*
* @param None.
*
* @return
* - ADIERR_FAILED if successful,
* - ADIERR_OK if not succesful
*
* @note None.
*
******************************************************************************/
int HARDWARE_initialize();
int HARDWARE_ad9371Config(void);
/*****************************************************************************/
/*
*
* Setup up Axi Gpio, through which ad9371 can be reconfigured. Axi Gpio
* instance and interrupt system initialization are included.
*
* @param None.
*
* @return
* - ADIERR_FAILED if successful,
* - ADIERR_OK if not succesful
*
* @note None.
*
******************************************************************************/
int HW_ad9371DynamicCfgInit(void);
/*****************************************************************************/
/*
*
* Setup up interrupt system, initialize exception handlers.
*
* @param DeviceId is the unique identifier for a device.
* @param GicPtr is a pointer to the XScuGic instance.
*
* @return
* - XST_SUCCESS if successful,
* - XST_FAILURE if not succesful
*
* @note None.
*
******************************************************************************/
int HW_setupIntrSystem(u16 DeviceId, XScuGic * GicPtr);
/*****************************************************************************/
/*
*
* Make the connection between the Int_Id of the interrupt source and the
* associated handler. Set the interrupt priority and trigger type for the
* specified IRQ source..
*
* @param GicPtr is a pointer to the XScuGic instance.
* @param Int_Id contains the ID of the interrupt source and should be
* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
* @param Handler to the handler for that interrupt.
* @param CallBackRef is the callback reference, usually the instance
* pointer of the connecting driver.
* @param Priority is the new priority for the IRQ source. 0 is highest
* priority, 0xF8(248) is lowest. There are 32 priority levels
* supported with a step of 8. Hence the supported priorities are
* 0, 8, 16, 32, 40 ..., 248.
* @param Trigger is the new trigger type for the IRQ source.
* Each bit pair describes the configuration for an INT_ID.
* SFI Read Only b10 always
* PPI Read Only depending on how the PPIs are configured.
* b01 Active HIGH level sensitive
* b11 Rising edge sensitive
* SPI LSB is read only.
* b01 Active HIGH level sensitive
* b11 Rising edge sensitive/
*
* @return
* - XST_SUCCESS if successful,
* - XST_FAILURE if not succesful
*
* @note None.
*
******************************************************************************/
int HW_connectIntr(XScuGic *GicPtr,u32 IntrId,Xil_InterruptHandler Handler,
void *CallBackRef, u8 Priority, u8 Trigger);
/*****************************************************************************/
/*
*
* Initialize Analog Device related configuration profile. This is a HARDWARE-
* ASSOTIATED function, which may differ between different board.
*
* @param None.
*
* @return
* - ADIERR_OK if configuration profile exists,
* - ADIERR_FAILED if onfiguration profile does not exist
*
* @note None.
*
******************************************************************************/
int HW_adiCfgProfileInit(void);
/******************************************************************************/
/**
*
* This function conducts AD9528 device configuration initializing procedure.
*
* @param clockAD9528_device is a pointer to the data structure holding
* AD9528 settings, which contains basic AD9528 settings such as
* spi and gpio.
*
* @return
* - ADIERR_OK if successful.
* - ADIERR_FAILED if not successful.
*
* @note None.
*
*******************************************************************************/
int HW_9528Config(ad9528Device_t *clockAD9528_device);
/******************************************************************************/
/**
*
* This function read AD9528 reg508 status, to check whether ad9528 is locked or
* not.
*
* @param clockAD9528_device is a pointer to the data structure holding
* AD9528 settings, which contains basic AD9528 settings.
*
* @return
* - ADIERR_OK if successful.
* - ADIERR_FAILED if not successful.
*
* @note None.
*
*******************************************************************************/
int HW_9528GetLockStatus(ad9528Device_t *device, uint8_t *reg508);
/******************************************************************************/
/**
*
* Conduct AD9371 device configuration initializing procedure.
*
* @param clockAD9528_device is a pointer to the data structure holding
* AD9528 settings, which contains basic AD9528 settings.
* @param mykDevice is ADI hardware layer settings pointer specific to
* a Mykonos instance which contains basic settings such as spi,
* gpio, tx/rx and jesd configurations.
*
* @return
* - ADIERR_OK if successful.
* - ADIERR_FAILED if not successful.
*
* @note None.
*
*******************************************************************************/
int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice);
/******************************************************************************/
/**
*
* Read AD9371's RX framer, ORX framer and TX deframer status, to check jesd204b
* sync status.
*
* @param mykDevice is ADI hardware layer settings pointer specific to
* a Mykonos instance which contains basic settings such as spi,
* gpio, tx/rx and jesd configurations.
* @param framerStatus is the RX framer status byte read
* framerStatus | Description
* -------------|-----------------------------------------------------------------------------
* [7] | SYSREF phase error ? a new SYSREF had different timing than the first that set the LMFC timing.
* [6] | Framer lane FIFO read/write pointer delta has changed. Can help debug issues with deterministic latency.
* [5] | Framer has received the SYSREF and has retimed its LMFC
* [4:2] | Framer ILAS state: 0=CGS, 1= 1st Multframe, 2= 2nd Multiframe, 3= 3rd Multiframe, 4= 4th multiframe, 5= Last multiframe, 6=invalid, 7= ILAS complete
* [1:0] | Framer Tx state: 0=CGS, 1= ILAS, 2 = ADC Data
* @param obsFramerStatus is the ORX framer status byte read
* obsFramerStatus | Description
* ----------------|-----------------------------------------------------------------------------
* [7] | SYSREF phase error ? a new SYSREF had different timing than the first that set the LMFC timing.
* [6] | Framer lane FIFO read/write pointer delta has changed. Can help debug issues with deterministic latency.
* [5] | Framer has received the SYSREF and has retimed its LMFC
* [4:2] | Framer ILAS state: 0=CGS, 1= 1st Multframe, 2= 2nd Multiframe, 3= 3rd Multiframe, 4= 4th multiframe, 5= Last multiframe, 6=invalid, 7= ILAS complete
* [1:0] | Framer Tx state: 0=CGS, 1= ILAS, 2 = ADC Data
* @param deframerStatus is the TX deframer status byte read
* deframerStatus | Bit Name | Description
* ----------------|--------------------------|---------------------------------------------
* [7] | Unused | Unused
* [6] | Deframer IRQ | This bit indicates that the IRQ interrupt was asserted.
* [5] | Deframer SYSREF Received | When this bit is set, it indicates that the SYSREF pulse was received by the deframer IP
* [4] | Deframer Receiver Error | This bit is set when PRBS has received an error.
* [3] | Valid Checksum | This bit is set when the received ILAS checksum is valid.
* [2] | EOF Event | This bit captures the internal status of the framer End of Frame event. Value =1 if framing error during ILAS
* [1] | EOMF Event | This bit captures the internal status of the framer End of Multi-Frame event. Value =1 if framing error during ILAS
* [0] | FS Lost | This bit captures the internal status of the framer Frame Symbol event. Value =1 if framing error during ILAS or user data (invalid replacement characters)
*
* @return
* - ADIERR_OK if successful.
* - ADIERR_FAILED if not successful.
*
* @note None.
*
*******************************************************************************/
int HW_9371CheckJesdStatus(mykonosDevice_t *mykDevice, uint8_t *framerStatus,
uint8_t *obsFramerStatus, uint8_t *deframerStatus);
/******************************************************************************/
/**
*
* This function conducts AD9371/9375 samll RF PLL frequcny change procedure. The
* procedure is performed as follows:
* 1. Move the device into the radio off state.
* 2. Program the new local oscillator (LO) frequency.
* 3. Reset the external channel.(ignored)
* 4. Move the device back into the radio on state.
* 5. Reenable tracking calibrations.(ignored)
*
* @param mykDevice is ADI hardware layer settings pointer specific to
* a Mykonos instance which contains basic settings such as spi,
* gpio, tx/rx and jesd configurations.
* @param freq_Hz is the target frequancy in Hz.
*
* @return None.
*
* @note The procedure is used when a radio frequency (RF) phased-lock loop
* (PLL) change is required with the following conditions:
* - A desire to change the Rx, Tx, and ORx frequencies.
* - The frequency step change is less than 100 MHz.
* - The frequency step does not cross the divide by 2 boundaries outlined
* in AD9371/9375-UG-992-Rev.B-Table 96.
*
*******************************************************************************/
int HW_9371SmallFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz);
/******************************************************************************/
/**
*
* This function conducts AD9371/9375 large RF PLL frequcny change procedure. The
* procedure is performed as follows:
* 1. Move the device into the radio off state.
* 2. Program the new local oscillator (LO) frequency.
* 3. Rerun the initialization calibrations.
* 4. Move the device back into the radio on state.
* 5. Reenable tracking calibrations.(ignored)
*
* @param mykDevice is ADI hardware layer settings pointer specific to
* a Mykonos instance which contains basic settings such as spi,
* gpio, tx/rx and jesd configurations.
* @param freq_Hz is the target frequancy in Hz.
*
* @return None.
*
* @note The procedure is used when a radio frequency (RF) phased-lock loop
* (PLL) change is required with the following conditions:
* - A desire to change the Rx, Tx, and ORx frequencies.
* - The frequency step change is more than 100 MHz.
* - The frequency step does cross the divide by 2 boundaries outlined
* in AD9371/9375-UG-992-Rev.B-Table 96.
*
*******************************************************************************/
int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz);
/******************************************************************************/
/**
*
* Handles AD9371 TX & RX frequency change axi gpio interruput.
*
* @param CallBackRef is the callback reference, usually the instance
* pointer of the connecting driver.
*
* @return None.
*
* @note None.
*
*******************************************************************************/
void FreqIntrHandler(void *CallbackRef);
/******************************************************************************/
/**
*
* Handles AD9371 Rx gain index change axi gpio interruput.
*
* @param CallBackRef is the callback reference, usually the instance
* pointer of the connecting driver.
*
* @return None.
*
* @note None.
*
*******************************************************************************/
void GainIntrHandler(void *CallbackRef);
/******************************************************************************/
/**
*
* Handles AD9371 Tx attenuation change axi gpio interruput.
*
* @param CallBackRef is the callback reference, usually the instance
* pointer of the connecting driver.
*
* @return None.
*
* @note None.
*
*******************************************************************************/
void AttnIntrHandler(void *CallbackRef);
#endif /* SRC_HEADLESS_H_ */
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/myk_ad9528init.c
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///*
// * myk_clock_init.c
// *
// */
//
///**
//* \page Disclaimer Legal Disclaimer
//* Copyright 2015-2017 Analog Devices Inc.
//* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
//*
//*/
//
//#ifndef MYK_CLOCK_INIT_C_
//#define MYK_CLOCK_INIT_C_
//#include <stdint.h>
//#include <stdlib.h>
//#include <stddef.h>
//#include "common.h"
//
//#include "ad9528.h"
//#include "t_ad9528.h"
//#include "myk_ad9528init.h"
//#include "parameters.h"
//
//static ad9528pll1Settings_t clockPll1Settings =
//{
// .refA_Frequency_Hz = 30720000,
// .refA_Divider = 1,
// .refA_bufferCtrl = DISABLED,
// .refB_Frequency_Hz = 0,
// .refB_Divider = 1,
// .refB_bufferCtrl = DISABLED,
// .vcxo_Frequency_Hz = 122880000,
// .vcxoBufferCtrl = NEG_SINGLE_ENDED,
// .nDivider = 4,
// .bypassPll1 = 0
//};
//
//static ad9528pll2Settings_t clockPll2Settings =
//{
// .rfDivider = 4,
// .n2Divider = 10,
// .totalNdiv = 30
//};
//
//static ad9528outputSettings_t clockOutputSettings =
//{
// .outPowerDown = 53237, // 0xCFF5
// .outSource = {
// CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV, SYSREF,
// CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV,
// CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV,
// SYSREF, CHANNEL_DIV},
// .outBufferCtrl = {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
// .outAnalogDelay = {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
// .outDigitalDelay = {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
// .outChannelDiv = {10,10,10,10,10,10,10,10,10,10,10,10,10,10},
// .outFrequency_Hz = {122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000}
//};
//
//static ad9528sysrefSettings_t clockSysrefSettings =
//{
// .sysrefRequestMethod = PIN,
// .sysrefSource = INTERNAL,
// .sysrefPinEdgeMode = LEVEL_ACTIVE_HIGH,
// .sysrefPinBufferMode = DISABLED,
// .sysrefPatternMode = NSHOT,
// .sysrefNshotMode = ONE_PULSE,
// .sysrefDivide = 512
//};
//
//static spiSettings_t clockSpiSettings =
//{
// .chipSelectIndex = AD9528_CS, //chip select Index
// .writeBitPolarity = 0, //Write bit polarity
// .longInstructionWord = 1, //16bit instruction word
// .MSBFirst = 1, //MSB first
// .CPHA = 0, //Clock phase
// .CPOL = 0, //Clock polarity
// .enSpiStreaming = 0, //uint8_t enSpiStreaming;
// .autoIncAddrUp = 1, //uint8_t autoIncAddrUp;
// .fourWireMode = 1 //uint8_t fourWireMode;
//};
//
//ad9528Device_t clockAD9528_ =
//{
// &clockSpiSettings,
// &clockPll1Settings,
// &clockPll2Settings,
// &clockOutputSettings,
// &clockSysrefSettings
//};
//
//ad9528Device_t *ad9528Init = &clockAD9528_;
//
//#endif /* MYK_CLOCK_INIT_C_ */
/* AD9528 data structure initialization file */
#include <stdint.h>
#include <stdlib.h>
#include <stddef.h>
#include "common.h"
#include "./mykonos/ad9528.h"
#include "./mykonos/t_ad9528.h"
#include "myk_ad9528init.h"
#include "parameters.h"
static ad9528pll1Settings_t clockPll1Settings = {
.refA_Frequency_Hz = 122880000,
.refA_Divider = 1,
.refA_bufferCtrl = SINGLE_ENDED,
.refB_Frequency_Hz = 0,
.refB_Divider = 1,
.refB_bufferCtrl = DISABLED,
.vcxo_Frequency_Hz = 122880000,
.vcxoBufferCtrl = DIFFERENTIAL,
.nDivider = 1,
.bypassPll1 = 0
};
static ad9528pll2Settings_t clockPll2Settings = {
.rfDivider = 3,
.n2Divider = 10,
.totalNdiv = 30
};
/*******************************************************************
* Output Distribution Settings
* 9369CE02A uses the following clock outputs
* OUT 1: FPGA_REF_CLK
* OUT 2: FPGA_AUX_CLK
* OUT 3: FPGA_SYSREF
* OUT 12: SYSREF_IN
* OUT 13: DEV_CLK_IN
*******************************************************************
*/
static ad9528outputSettings_t clockOutputSettings = {
.outPowerDown = 0x0,
.outSource = {
SYSREF, SYSREF, CHANNEL_DIV, SYSREF,
CHANNEL_DIV, CHANNEL_DIV, SYSREF, SYSREF,
CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV,
SYSREF , CHANNEL_DIV
},
.outBufferCtrl = {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
.outAnalogDelay = {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
.outDigitalDelay = {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
.outChannelDiv = {10,10,10,10,10,10,10,10,10,10,10,10,10,10},
.outFrequency_Hz = {
122880000, 122880000, 122880000, 122880000,
122880000, 122880000, 122880000, 122880000,
122880000, 122880000, 122880000, 122880000,
122880000, 122880000
}
};
static ad9528sysrefSettings_t clockSysrefSettings = {
.sysrefRequestMethod = SPI,
.sysrefSource = INTERNAL,
.sysrefPinEdgeMode = LEVEL_ACTIVE_HIGH,
.sysrefPinBufferMode = DISABLED,
.sysrefPatternMode = CONTINUOUS,
.sysrefNshotMode = FOUR_PULSES,
.sysrefDivide = 512
};
static spiSettings_t clockSpiSettings = {
.chipSelectIndex = 2, //chip select Index
.writeBitPolarity = 0, //Write bit polarity
.longInstructionWord = 1, //16bit instruction word
.MSBFirst = 1, //MSB first
.CPHA = 0, //Clock phase
.CPOL = 0, //Clock polarity
.enSpiStreaming = 0, //uint8_t enSpiStreaming;
.autoIncAddrUp = 1, //uint8_t autoIncAddrUp;
.fourWireMode = 1 //uint8_t fourWireMode;
};
ad9528Device_t clockAD9528_ = {
&clockSpiSettings,
&clockPll1Settings,
&clockPll2Settings,
&clockOutputSettings,
&clockSysrefSettings
};
ad9528Device_t *ad9528Init = &clockAD9528_;
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/myk_ad9528init.h
+20
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/*
* myk_clock_init.h
*
*/
/**
* \page Disclaimer Legal Disclaimer
* Copyright 2015-2017 Analog Devices Inc.
* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
*
*/
#ifndef MYK_CLOCK_INIT_H_
#define MYK_CLOCK_INIT_H_
#include "./mykonos/ad9528.h"
extern ad9528Device_t *ad9528Init;
#endif /* MYK_CLOCK_INIT_H_ */
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/myk_init.c
+558
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/**
* \file myk_init.c
*
* \brief Contains init setting structure declarations for the _instance API
*
* The top level structure mykonosDevice_t mykDevice uses keyword
* extern to allow the application layer main() to have visibility
* to these settings.
*
* All data structures required for operation have been initialized with values which reflect
* these settings:
*
* Device Clock = $122.88$ Mhz
* Rx enabled channels = $2$
* Tx enabled channels = $2$
*
* Mykonos Framer:
* Lane Rate = $4915.2$ Mbs
* L = $2$
* K = $32$
* M = $4$
* F = $4$
*
* Mykonos Deframer:
* Lane Rate = $4915.2$ Mbs
* L = $2$
* K = $32$
* M = $4$
* F = $4$
*
* Mykonos Observation framer:
* Lane Rate = $4915.2$ Mbs
* L = $2$
* K = $32$
* M = $4$
* F = $4$
*
* Using these profiles:
* $Rx 100Mhz, IQrate 122.88Mhz, Dec5$
* $Tx 100/100Mhz, IQrate 122.88Mhz, Dec5$
* $ORX 100Mhz, IQrate 122.88Mhz, Dec5$
* $SRx 20Mhz, IQrate 30.72Mhz, Dec5$
*
*/
/**
* \page Disclaimer Legal Disclaimer
* Copyright 2015-2017 Analog Devices Inc.
* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
*
*/
#include <stddef.h>
#include "./mykonos/t_mykonos.h"
#include "myk_init.h"
#include "parameters.h"
#include "./mykonos/mykonos_gpio.h"
static int16_t txFirCoefs[] = {-94,-26,282,177,-438,-368,756,732,-1170,-1337,1758,2479,-2648,-5088,4064,16760,16759,4110,-4881,-2247,2888,1917,-1440,-1296,745,828,-358,-474,164,298,-16,-94};
static mykonosFir_t txFir =
{
6, /* Filter gain in dB*/
32, /* Number of coefficients in the FIR filter*/
&txFirCoefs[0] /* A pointer to an array of filter coefficients*/
};
static int16_t rxFirCoefs[] = {-20,6,66,22,-128,-54,240,126,-402,-248,634,444,-956,-756,1400,1244,-2028,-2050,2978,3538,-4646,-7046,9536,30880,30880,9536,-7046,-4646,3538,2978,-2050,-2028,1244,1400,-756,-956,444,634,-248,-402,126,240,-54,-128,22,66,6,-20};
static mykonosFir_t rxFir =
{
-6, /* Filter gain in dB*/
48, /* Number of coefficients in the FIR filter*/
&rxFirCoefs[0] /* A pointer to an array of filter coefficients*/
};
static int16_t obsrxFirCoefs[] = {-14,-19,44,41,-89,-95,175,178,-303,-317,499,527,-779,-843,1184,1317,-1781,-2059,2760,3350,-4962,-7433,9822,32154,32154,9822,-7433,-4962,3350,2760,-2059,-1781,1317,1184,-843,-779,527,499,-317,-303,178,175,-95,-89,41,44,-19,-14};
static mykonosFir_t obsrxFir =
{
-6, /* Filter gain in dB*/
48, /* Number of coefficients in the FIR filter*/
&obsrxFirCoefs[0]/* A pointer to an array of filter coefficients*/
};
static int16_t snifferFirCoefs[] = {-1,-5,-14,-23,-16,24,92,137,80,-120,-378,-471,-174,507,1174,1183,98,-1771,-3216,-2641,942,7027,13533,17738,17738,13533,7027,942,-2641,-3216,-1771,98,1183,1174,507,-174,-471,-378,-120,80,137,92,24,-16,-23,-14,-5,-1};
static mykonosFir_t snifferRxFir=
{
-6, /* Filter gain in dB*/
48, /* Number of coefficients in the FIR filter*/
&snifferFirCoefs[0]/* A pointer to an array of filter coefficients*/
};
static mykonosJesd204bFramerConfig_t rxFramer =
{
0, /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15)*/
0, /* JESD204B Configuration Device ID - link identification number. (Valid 0..255)*/
0, /* JESD204B Configuration starting Lane ID. If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31)*/
4, /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain*/
32, /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes)*/
0, /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled.*/
1, /* 0=use internal SYSREF, 1= use external SYSREF*/
0x03, /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled*/
0xE4, /* serializerLaneCrossbar*/
22, /* serializerAmplitude - default 22 (valid (0-31)*/
4, /* preEmphasis - < default 4 (valid 0 - 7)*/
0, /* invertLanePolarity - default 0 ([0] will invert lane [0], bit1 will invert lane1)*/
0, /* lmfcOffset - LMFC_Offset offset value for deterministic latency setting*/
0, /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, 0 = not set*/
0, /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/
0, /* Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 = use OBSRX_SYNCB for this framer*/
0, /* Flag for determining if CMOS mode for RX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/
0, /* Selects framer bit repeat or oversampling mode for lane rate matching. Where, 0 = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same lane rate between ObsRx framer and Rx framer and oversamples the ADC samples)*/
0 /* Flag for determining if API will calculate the appropriate settings for framer lane outputs to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in serializerLaneCrossbar will be used*/
};
static mykonosJesd204bFramerConfig_t obsRxFramer =
{
0, /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15)*/
0, /* JESD204B Configuration Device ID - link identification number. (Valid 0..255)*/
0, /* JESD204B Configuration starting Lane ID. If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31)*/
2, /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain*/
32, /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes)*/
0, /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled.*/
1, /* 0=use internal SYSREF, 1= use external SYSREF*/
0x04, /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled*/
0xE4, /* Lane crossbar to map framer lane outputs to physical lanes*/
22, /* serializerAmplitude - default 22 (valid (0-31)*/
4, /* preEmphasis - < default 4 (valid 0 - 7)*/
0, /* invertLanePolarity - default 0 ([0] will invert lane [0], bit1 will invert lane1)*/
0, /* lmfcOffset - LMFC_Offset offset value for deterministic latency setting*/
0, /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, 0 = not set*/
0, /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/
1, /* Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 = use OBSRX_SYNCB for this framer*/
0, /* Flag for determining if CMOS mode for RX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/
0, /* Selects framer bit repeat or oversampling mode for lane rate matching. Where, 0 = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same lane rate between ObsRx framer and Rx framer and oversamples the ADC samples)*/
0 /* Flag for determining if API will calculate the appropriate settings for framer lane outputs to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in serializerLaneCrossbar will be used*/
};
static mykonosJesd204bDeframerConfig_t deframer =
{
0, /* bankId extension to Device ID (Valid 0..15)*/
0, /* deviceId link identification number. (Valid 0..255)*/
0, /* lane0Id Lane0 ID. (Valid 0..31)*/
4, /* M number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
32, /* K #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes)*/
0, /* scramble scrambling off if scramble= 0.*/
1, /* External SYSREF select. 0 = use internal SYSREF, 1 = external SYSREF*/
0x03, /* Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */
0xE4, /* Lane crossbar to map physical lanes to deframer lane inputs [1:0] = Deframer Input 0 Lane section, [3:2] = Deframer Input 1 lane select, etc */
1, /* Equalizer setting. Applied to all deserializer lanes. Range is 0..4*/
0, /* PN inversion per each lane. bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc).*/
0, /* LMFC_Offset offset value to adjust deterministic latency. Range is 0..31*/
0, /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, '0' = not set*/
0, /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/
0, /* Flag for determining if CMOS mode for TX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/
0 /* Flag for determining if API will calculate the appropriate settings for deframer lane in to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in deserializerLaneCrossbar will be used*/
};
static mykonosRxGainControl_t rxGainControl =
{
MGC, /* Current Rx gain control mode setting*/
255, /* Rx1 Gain Index, can be used in different ways for manual and AGC gain control*/
255, /* Rx2 Gain Index, can be used in different ways for manual and AGC gain control*/
255, /* Max gain index for the currently loaded Rx1 Gain table*/
195, /* Min gain index for the currently loaded Rx1 Gain table*/
255, /* Max gain index for the currently loaded Rx2 Gain table*/
195, /* Min gain index for the currently loaded Rx2 Gain table*/
0, /* Stores Rx1 RSSI value read back from the Mykonos*/
0 /* Stores Rx2 RSSI value read back from the Mykonos*/
};
static mykonosORxGainControl_t orxGainControl =
{
MGC, /* Current ORx gain control mode setting*/
255, /* ORx1 Gain Index, can be used in different ways for manual and AGC gain control*/
255, /* ORx2 Gain Index, can be used in different ways for manual and AGC gain control*/
255, /* Max gain index for the currently loaded ORx Gain table*/
237 /* Min gain index for the currently loaded ORx Gain table*/
};
static mykonosSnifferGainControl_t snifferGainControl =
{
MGC, /* Current Sniffer gain control mode setting*/
255, /* Current Sniffer gain index. Can be used differently for MANUAL Gain control/AGC*/
255, /* Max gain index for the currently loaded Sniffer Gain table*/
203 /* Min gain index for the currently loaded Sniffer Gain table*/
};
static mykonosPeakDetAgcCfg_t rxPeakAgc =
{
0x0C, /* apdHighThresh: */
0x08, /* apdLowThresh */
0xB5, /* hb2HighThresh */
0x80, /* hb2LowThresh */
0x40, /* hb2VeryLowThresh */
0x06, /* apdHighThreshExceededCnt */
0x04, /* apdLowThreshExceededCnt */
0x06, /* hb2HighThreshExceededCnt */
0x04, /* hb2LowThreshExceededCnt */
0x04, /* hb2VeryLowThreshExceededCnt */
0x4, /* apdHighGainStepAttack */
0x2, /* apdLowGainStepRecovery */
0x4, /* hb2HighGainStepAttack */
0x2, /* hb2LowGainStepRecovery */
0x4, /* hb2VeryLowGainStepRecovery */
0x1, /* apdFastAttack */
0x1, /* hb2FastAttack */
0x1, /* hb2OverloadDetectEnable */
0x1, /* hb2OverloadDurationCnt */
0x1 /* hb2OverloadThreshCnt */
};
static mykonosPowerMeasAgcCfg_t rxPwrAgc =
{
0x01, /* pmdUpperHighThresh */
0x03, /* pmdUpperLowThresh */
0x0C, /* pmdLowerHighThresh */
0x00, /* pmdLowerLowThresh */
0x4, /* pmdUpperHighGainStepAttack */
0x2, /* pmdUpperLowGainStepAttack */
0x2, /* pmdLowerHighGainStepRecovery */
0x4, /* pmdLowerLowGainStepRecovery */
0x08, /* pmdMeasDuration */
0x02 /* pmdMeasConfig */
};
static mykonosAgcCfg_t rxAgcConfig =
{
255, /* agcRx1MaxGainIndex */
195, /* agcRx1MinGainIndex */
255, /* agcRx2MaxGainIndex */
195, /* agcRx2MinGainIndex: */
255, /* agcObsRxMaxGainIndex */
203, /* agcObsRxMinGainIndex */
1, /* agcObsRxSelect */
1, /* agcPeakThresholdMode */
1, /* agcLowThsPreventGainIncrease */
30720, /* agcGainUpdateCounter */
3, /* agcSlowLoopSettlingDelay */
2, /* agcPeakWaitTime */
1, /* agcResetOnRxEnable */
0, /* agcEnableSyncPulseForGainCounter */
&rxPeakAgc,
&rxPwrAgc
};
static mykonosPeakDetAgcCfg_t obsRxPeakAgc =
{
0x1F, /* apdHighThresh: */
0x16, /* apdLowThresh */
0xB5, /* hb2HighThresh */
0x80, /* hb2LowThresh */
0x40, /* hb2VeryLowThresh */
0x06, /* apdHighThreshExceededCnt */
0x04, /* apdLowThreshExceededCnt */
0x06, /* hb2HighThreshExceededCnt */
0x04, /* hb2LowThreshExceededCnt */
0x04, /* hb2VeryLowThreshExceededCnt */
0x4, /* apdHighGainStepAttack */
0x2, /* apdLowGainStepRecovery */
0x4, /* hb2HighGainStepAttack */
0x2, /* hb2LowGainStepRecovery */
0x4, /* hb2VeryLowGainStepRecovery */
0x1, /* apdFastAttack */
0x1, /* hb2FastAttack */
0x1, /* hb2OverloadDetectEnable */
0x1, /* hb2OverloadDurationCnt */
0x1 /* hb2OverloadThreshCnt */
};
static mykonosPowerMeasAgcCfg_t obsRxPwrAgc =
{
0x01, /* pmdUpperHighThresh */
0x03, /* pmdUpperLowThresh */
0x0C, /* pmdLowerHighThresh */
0x00, /* pmdLowerLowThresh */
0x4, /* pmdUpperHighGainStepAttack */
0x2, /* pmdUpperLowGainStepAttack */
0x2, /* pmdLowerHighGainStepRecovery */
0x4, /* pmdLowerLowGainStepRecovery */
0x08, /* pmdMeasDuration */
0x02 /* pmdMeasConfig */
};
static mykonosAgcCfg_t obsRxAgcConfig =
{
255, /* agcRx1MaxGainIndex */
195, /* agcRx1MinGainIndex */
255, /* agcRx2MaxGainIndex */
195, /* agcRx2MinGainIndex: */
255, /* agcObsRxMaxGainIndex */
203, /* agcObsRxMinGainIndex */
1, /* agcObsRxSelect */
1, /* agcPeakThresholdMode */
1, /* agcLowThsPreventGainIncrease */
30720, /* agcGainUpdateCounter */
3, /* agcSlowLoopSettlingDelay */
2, /* agcPeakWaitTime */
1, /* agcResetOnRxEnable */
0, /* agcEnableSyncPulseForGainCounter */
&obsRxPeakAgc,
&obsRxPwrAgc
};
static mykonosRxProfile_t rxProfile =
{/* Rx 100MHz, IQrate 122.88MSPS, Dec5 */
1, /* The divider used to generate the ADC clock*/
&rxFir, /* Pointer to Rx FIR filter structure*/
2, /* Rx FIR decimation (1,2,4)*/
5, /* Decimation of Dec5 or Dec4 filter (5,4)*/
1, /* If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter (1=Enabled, 0=Disabled)*/
1, /* RX Half band 1 decimation (1 or 2)*/
122880, /* Rx IQ data rate in kHz*/
100000000, /* The Rx RF passband bandwidth for the profile*/
100000, /* Rx BBF 3dB corner in kHz*/
NULL /* pointer to custom ADC profile*/
};
static mykonosRxProfile_t orxProfile =
{/* ORX 100MHz, IQrate 122.88MSPS, Dec5 */
1, /* The divider used to generate the ADC clock*/
&obsrxFir, /* Pointer to Rx FIR filter structure or NULL*/
2, /* Rx FIR decimation (1,2,4)*/
5, /* Decimation of Dec5 or Dec4 filter (5,4)*/
0, /* If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter (1=Enabled, 0=Disabled)*/
1, /* RX Half band 1 decimation (1 or 2)*/
122880, /* Rx IQ data rate in kHz*/
100000000, /* The Rx RF passband bandwidth for the profile*/
100000, /* Rx BBF 3dB corner in kHz*/
NULL /* pointer to custom ADC profile*/
};
static mykonosRxProfile_t snifferProfile =
{ /* SRx 20MHz, IQrate 30.72MSPS, Dec5 */
1, /* The divider used to generate the ADC clock*/
&snifferRxFir, /* Pointer to Rx FIR filter structure or NULL*/
4, /* Rx FIR decimation (1,2,4)*/
5, /* Decimation of Dec5 or Dec4 filter (5,4)*/
0, /* If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter (1=Enabled, 0=Disabled)*/
2, /* RX Half band 1 decimation (1 or 2)*/
30720, /* Rx IQ data rate in kHz*/
10000000, /* The Rx RF passband bandwidth for the profile*/
100000, /* Rx BBF 3dB corner in kHz*/
NULL /* pointer to custom ADC profile*/
};
static mykonosTxProfile_t txProfile =
{ /* Tx 20/100MHz, IQrate 122.88MSPS, Dec5 */
DACDIV_2p5, /* The divider used to generate the DAC clock*/
&txFir, /* Pointer to Tx FIR filter structure*/
2, /* The Tx digital FIR filter interpolation (1,2,4)*/
2, /* Tx Halfband1 filter interpolation (1,2)*/
1, /* Tx Halfband2 filter interpolation (1,2)*/
1, /* TxInputHbInterpolation (1,2)*/
122880, /* Tx IQ data rate in kHz*/
100000000, /* Primary Signal BW*/
100000000, /* The Tx RF passband bandwidth for the profile*/
710539, /* The DAC filter 3dB corner in kHz*/
50000, /* Tx BBF 3dB corner in kHz*/
0 /* Enable DPD, only valid for AD9373*/
};
static mykonosDigClocks_t mykonosClocks =
{
122880, /* CLKPLL and device reference clock frequency in kHz*/
9830400, /* CLKPLL VCO frequency in kHz*/
VCODIV_2, /* CLKPLL VCO divider*/
4 /* CLKPLL high speed clock divider*/
};
static mykonosRxSettings_t rxSettings =
{
&rxProfile, /* Rx datapath profile, 3dB corner frequencies, and digital filter enables*/
&rxFramer, /* Rx JESD204b framer configuration structure*/
&rxGainControl, /* Rx Gain control settings structure*/
&rxAgcConfig, /* Rx AGC control settings structure*/
RX1_RX2, /* The desired Rx Channels to enable during initialization*/
0, /* Internal LO = 0, external LO*2 = 1*/
2550000000U, /* Rx PLL LO Frequency (internal or external LO)*/
0 /* Flag to choose if complex baseband or real IF data are selected for Rx and ObsRx paths. Where, if > 0 = real IF data, '0' = zero IF (IQ) data*/
};
static mykonosDpdConfig_t dpdConfig =
{
5, /* 1/2^(damping + 8) fraction of power `forgotten' per sample (default: `1/8192' = 5, valid 0 to 15), 0 = infinite damping*/
1, /* number of weights to use for int8_cpx weights weights member of this structure (default = 1)*/
2, /* DPD model version: one of four different generalized polynomial models: 0 = same as R0 silicon, 1-3 are new and the best one depends on the PA (default: 2)*/
1, /* 1 = Update saved model whenever peak Tx digital RMS is within 1dB of historical peak Tx RMS*/
20, /* Determines how much weight the loaded prior model has on DPD modeling (Valid 0 - 32, default 20)*/
0, /* Default off = 0, 1=enables automatic outlier removal during DPD modeling */
512, /* Number of samples to capture (default: 512, valid 64-32768)*/
4096, /* threshold for sample in AM-AM plot outside of 1:1 line to be thrown out. (default: 50% = 8192/2, valid 8192 to 1)*/
0, /* 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64)*/
255, /* Default 255 (-30dBFs=(20Log10(value/8192)), (valid range 1 to 8191)*/
{{64,0},{0,0},{0,0}}/* DPD model error weighting (real/imag valid from -128 to 127)*/
};
static mykonosClgcConfig_t clgcConfig =
{
-2000, /* (value = 100 * dB (valid range -32768 to 32767) - total gain and attenuation from Mykonos Tx1 output to ORx1 input in (dB * 100)*/
-2000, /* (value = 100 * dB (valid range -32768 to 32767) - total gain and attenuation from Mykonos Tx2 output to ORx2 input in (dB * 100)*/
0, /* (valid range 0 - 40dB), no default, depends on PA, Protects PA by making sure Tx1Atten is not reduced below the limit*/
0, /* (valid range 0 - 40dB), no default, depends on PA, Protects PA by making sure Tx2Atten is not reduced below the limit*/
75, /* valid range 1-100, default 75*/
75, /* valid range 1-100, default 45*/
0, /* 0= allow CLGC to run, but Tx1Atten will not be updated. User can still read back power measurements. 1=CLGC runs, and Tx1Atten automatically updated*/
0, /* 0= allow CLGC to run, but Tx2Atten will not be updated. User can still read back power measurements. 1=CLGC runs, and Tx2Atten automatically updated*/
0, /* 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64)*/
255, /* Default 255 (-30dBFs=(20Log10(value/8192)), (valid range 1 to 8191)*/
600, /* Threshold for Tx1 in order to stop tracking, value = 100 * dB, default 6db then value = 600*/
600, /* Threshold for Tx2 in order to stop tracking, value = 100 * dB, default 6db then value = 600*/
0, /* Threshold feature enable for Tx1, 0 = disable, 1 = enable, default = 0*/
0 /* Threshold feature enable for Tx1, 0 = disable, 1 = enable, default = 0*/
};
static mykonosVswrConfig_t vswrConfig =
{
0, /* 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64)*/
255, /* Default 255 (-30dBFs=(20Log10(value/8192)), (valid range 1 to 8191)*/
0, /* 3p3V GPIO pin to use to control VSWR switch for Tx1 (valid 0-11) (output from Mykonos)*/
1, /* 3p3V GPIO pin to use to control VSWR switch for Tx2 (valid 0-11) (output from Mykonos)*/
0, /* 3p3v GPIO pin polarity for forward path of Tx1, opposite used for reflection path (1 = high level, 0 = low level)*/
0, /* 3p3v GPIO pin polarity for forward path of Tx2, opposite used for reflection path (1 = high level, 0 = low level)*/
50, /* Delay for Tx1 after flipping the VSWR switch until measurement is made. In us resolution*/
50 /* Delay for Tx2 after flipping the VSWR switch until measurement is made. In us resolution*/
};
static mykonosTxSettings_t txSettings =
{
&txProfile, /* Tx datapath profile, 3dB corner frequencies, and digital filter enables*/
&deframer, /* Mykonos JESD204b deframer config for the Tx data path*/
TX1_TX2, /* The desired Tx channels to enable during initialization*/
0, /* Internal LO=0, external LO*2 if =1*/
2500000000U, /* Tx PLL LO frequency (internal or external LO)*/
TXATTEN_0P05_DB,/* Initial and current Tx1 Attenuation*/
10000, /* Initial and current Tx1 Attenuation mdB*/
10000, /* Initial and current Tx2 Attenuation mdB*/
NULL, /* DPD,CLGC,VSWR settings. Only valid for AD9373 device, set pointer to NULL otherwise*/
NULL, /* CLGC Config Structure. Only valid for AD9373 device, set pointer to NULL otherwise*/
NULL /* VSWR Config Structure. Only valid for AD9373 device, set pointer to NULL otherwise*/
};
static mykonosObsRxSettings_t obsRxSettings =
{
&orxProfile, /* ORx datapath profile, 3dB corner frequencies, and digital filter enables*/
&orxGainControl,/* ObsRx gain control settings structure*/
&obsRxAgcConfig,/* ORx AGC control settings structure*/
&snifferProfile,/* Sniffer datapath profile, 3dB corner frequencies, and digital filter enables*/
&snifferGainControl,/* SnRx gain control settings structure*/
&obsRxFramer, /* ObsRx JESD204b framer configuration structure */
(MYK_ORX1_ORX2 | MYK_SNRXA_B_C),/* obsRxChannel */
OBSLO_TX_PLL, /* (obsRxLoSource) The Obs Rx mixer can use the Tx Synth(TX_PLL) or Sniffer Synth (SNIFFER_PLL) */
2600000000U, /* SnRx PLL LO frequency in Hz */
0, /* Flag to choose if complex baseband or real IF data are selected for Rx and ObsRx paths. Where if > 0 = real IF data, '0' = complex data*/
NULL, /* Custom Loopback ADC profile to set the bandwidth of the ADC response */
OBS_RXOFF /* Default ObsRx channel to enter when radioOn called */
};
static mykonosArmGpioConfig_t armGpio =
{
1, // useRx2EnablePin; /*!< 0= RX1_ENABLE controls RX1 and RX2, 1 = separate RX1_ENABLE/RX2_ENABLE pins */
1, // useTx2EnablePin; /*!< 0= TX1_ENABLE controls TX1 and TX2, 1 = separate TX1_ENABLE/TX2_ENABLE pins */
0, // txRxPinMode; /*!< 0= ARM command mode, 1 = Pin mode to power up Tx/Rx chains */
0, // orxPinMode; /*!< 0= ARM command mode, 1 = Pin mode to power up ObsRx receiver*/
/*Mykonos ARM input GPIO pins -- Only valid if orxPinMode = 1 */
0, // orxTriggerPin; /*!< Select desired GPIO pin (valid 4-15) */
0, // orxMode2Pin; /*!< Select desired GPIO pin (valid 0-18) */
0, // orxMode1Pin; /*!< Select desired GPIO pin (valid 0-18) */
0, // orxMode0Pin; /*!< Select desired GPIO pin (valid 0-18) */
/* Mykonos ARM output GPIO pins -- always available, even when pin mode not enabled*/
0, // rx1EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
0, // rx2EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
0, // tx1EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
0, // tx2EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
0, // orx1EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
0, // orx2EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
0, // srxEnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
0 // txObsSelect; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
/* When 2Tx are used with only 1 ORx input, this GPIO tells the BBIC which Tx channel is */
/* active for calibrations, so BBIC can route correct RF Tx path into the single ORx input*/
};
static mykonosGpio3v3_t gpio3v3 =
{
0, /*!< Oe per pin, 1=output, 0 = input */
GPIO3V3_BITBANG_MODE, /*!< Mode for GPIO3V3[3:0] */
GPIO3V3_BITBANG_MODE, /*!< Mode for GPIO3V3[7:4] */
GPIO3V3_BITBANG_MODE, /*!< Mode for GPIO3V3[11:8] */
};
static mykonosGpioLowVoltage_t gpio =
{
0,/* Oe per pin, 1=output, 0 = input */
GPIO_MONITOR_MODE,/* Mode for GPIO[3:0] */
GPIO_MONITOR_MODE,/* Mode for GPIO[7:4] */
GPIO_MONITOR_MODE,/* Mode for GPIO[11:8] */
GPIO_MONITOR_MODE,/* Mode for GPIO[15:12] */
GPIO_MONITOR_MODE,/* Mode for GPIO[18:16] */
};
static mykonosAuxIo_t mykonosAuxIo =
{
0, //auxDacEnableMask uint16_t
{0,0,0,0,0,0,0,0,0,0}, //AuxDacValue uint16[10]
{0,0,0,0,0,0,0,0,0,0}, //AuxDacSlope uint8[10]
{0,0,0,0,0,0,0,0,0,0}, //AuxDacVref uint8[10]
&gpio3v3, //pointer to gpio3v3 struct
&gpio, //pointer to gpio1v8 struct
&armGpio
};
static spiSettings_t mykSpiSettings =
{
1, /* chip select index - valid 1~8 */
0, /* the level of the write bit of a SPI write instruction word, value is inverted for SPI read operation */
1, /* 1 = 16-bit instruction word, 0 = 8-bit instruction word */
1, /* 1 = MSBFirst, 0 = LSBFirst */
0, /* clock phase, sets which clock edge the data updates (valid 0 or 1) */
0, /* clock polarity 0 = clock starts low, 1 = clock starts high */
0, /* Not implemented in ADIs platform layer. SW feature to improve SPI throughput */
1, /* Not implemented in ADIs platform layer. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr=addr-1 */
1 /* 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode */
};
static mykonosTempSensorConfig_t tempSensor =
{
7, /* 3-bit value that controls the AuxADC decimation factor when used for temp sensor calculations; AuxADC_decimation = 256 * 2^tempDecimation*/
67, /* 8-bit offset that gets added to temp sensor code internally*/
1, /* this bit overrides the factory-calibrated fuse offset and uses the value stored in the offset member*/
15, /* 4-bit code with a resolution of 1°C/LSB, each time a temperature measurement is performed, the device compares the current temperature against the previous value.*/
};
static mykonosTempSensorStatus_t tempStatus =
{
0, /* 16-bit signed temperature value (in deg C) that is read back*/
0, /* If the absolute value of the difference is greater than the value in temperature configuration tempWindow, the windowExceeded flag is set.*/
0, /* when windowExceeded member gets set, this bit is set to 1 if current value is greater than previous value, else reset*/
0, /* when the reading is complete and a valid temperature value stored in tempCode.*/
};
mykonosDevice_t mykDevice =
{
&mykSpiSettings, /* SPI settings data structure pointer */
&rxSettings, /* Rx settings data structure pointer */
&txSettings, /* Tx settings data structure pointer */
&obsRxSettings, /* ObsRx settings data structure pointer */
&mykonosAuxIo, /* Auxiliary IO settings data structure pointer */
&mykonosClocks, /* Holds settings for CLKPLL and reference clock */
0 /* Mykonos initialize function uses this as an output to remember which profile data structure pointers are valid */
};
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/myk_init.h
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/**
* \file myk_init.h
*
* \brief Contains structure definitions for myk_init.c
*
* The top level structure mykonosDevice_t mykDevice uses keyword
* extern to allow the application layer main() to have visibility
* to these settings.
*/
/**
* \page Disclaimer Legal Disclaimer
* Copyright 2015-2017 Analog Devices Inc.
* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
*
*/
#ifndef MYK_INIT_H_
#define MYK_INIT_H_
extern mykonosDevice_t mykDevice;
#endif
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/mykonos/Mykonos_M3.c
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projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/mykonos/Mykonos_M3.h
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/**
SOFTWARE LICENSE AGREEMENT
20180301-AD937X-CTSLA
**/
// Version 5.2.2
#ifndef SRC_MYKONOS_BIN_H_
#define SRC_MYKONOS_BIN_H_
unsigned char firmware_Mykonos_M3_bin[];
unsigned int firmware_Mykonos_M3_bin_len;
#endif
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/mykonos/ad9528.c
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/**
* \file ad9528.c
* \brief Contains source code for configuring and initializing AD9528 clock device
*/
/**
* \page Disclaimer Legal Disclaimer
* Copyright 2015-2017 Analog Devices Inc.
* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
*
*/
#include "ad9528.h"
/**
* \brief Performs a hard reset on the AD9528 DUT
*
* <B>Dependencies</B>
* - device->spiSettings->chipSelectIndex
*
* \param device is structure pointer to the AD9528 data structure containing settings
* \return Returns enum ADI_ERR, ADIERR_OK=pass, !ADIERR_OK=fail
*/
ADI_ERR AD9528_resetDevice(ad9528Device_t *device)
{
/* toggle RESETB on device with matching spi chip select index */
CMB_hardReset(device->spiSettings->chipSelectIndex);
return ADIERR_OK;
}
/**
* \brief Sets the AD9528 device SPI settings (3wire/4wire, MSBFirst, etc).
*
* This function will use the settings in the device->spiSettings structure
* to set SPI stream mode, address auto increment direction, MSBFirst/LSBfirst,
* and 3wire/4wire mode. The AD9528 device always uses SPI MODE 0 (CPHA=0, CPOL=0).
* This function will update your device->spiSettings to set CHPA=0 and CPOL=0 and
* longInstructionWord =1 to use a 16bit instruction word.
*
* <B>Dependencies</B>
* - writes device->spiSettings->CPHA = 0
* - writes device->spiSettings->CPOL = 0
* - writes device->spiSettings->longInstructionWord = 1
*
* - device->spiSettings->MSBFirst
* - device->spiSettings->enSpiStreaming
* - device->spiSettings->autoIncAddrUp
* - device->spiSettings->fourWireMode
*
* \param device is structure pointer to the AD9528 data structure containing settings
*
* \return Returns enum ADI_ERR, ADIERR_OK=pass, !ADIERR_OK=fail
*/
ADI_ERR AD9528_setSpiSettings(ad9528Device_t *device)
{
//device->spiSettings->enSpiStreaming
uint8_t spiReg = 0;
device->spiSettings->CPHA = 0;
device->spiSettings->CPOL = 0;
device->spiSettings->longInstructionWord = 1;
if (device->spiSettings->MSBFirst == 0)
{
spiReg |= 0x42; /* SPI bit is 1=LSB first */
}
if (device->spiSettings->autoIncAddrUp > 0)
{
spiReg |= 0x24;
}
if (device->spiSettings->fourWireMode > 0)
{
spiReg |= 0x18;
}
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_ADI_SPI_CONFIG_A, spiReg);
if (device->spiSettings->enSpiStreaming > 0)
{
/* Allow SPI streaming mode: SPI message ends when chip select deasserts */
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_ADI_SPI_CONFIG_B, 0x00);
}
else
{
/* Force single instruction mode */
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_ADI_SPI_CONFIG_B, 0x80);
}
return ADIERR_OK;
}
/**
* \brief Helper function for ADI transceiver eval boards to init the AD9528 data structure
*
* This function inits the AD9528 device data structure with defaults that
* are known to work with the ADI AD9369 and AD9371 evaluation boards. NOTE: This function will
* modify the contents of the AD9528 device data structure.
*
* <B>Dependencies</B>
* - spi->chipSelectIndex
* - spi
*
* \param device Pointer to the AD9528 device data structure to initialize
* \param vcxoFrequency_Hz The VCXO frequency that is connected to the AD9528
* \param refAFrequency_Hz The reference clock frequency being input into the AD9528 REFCLK A input
* \param outputDeviceClock_Hz Desired output clock frequency to the FPGA and transceiver device
*
* \return Returns enum ADI_ERR, 0=pass, >0 = fail
*/
ADI_ERR AD9528_initDeviceDataStruct(ad9528Device_t *device, uint32_t vcxoFrequency_Hz, uint32_t refAFrequency_Hz, uint32_t outputDeviceClock_Hz)
{
// uint16_t chDiv;
// uint8_t i = 0;
//
// uint32_t pll1PfdFreq_Hz = 0;
// uint8_t pll1Ndiv = 0;
// uint8_t validPll1DivSetting = 0;
// uint8_t refAdiv = 1;
//
//
// uint8_t pll2RfDiv = 3; /* Valid values 3,4,5 */
// uint16_t pll2Ndiv = 1; /* Valid values 1-256 */
// uint32_t pll2InputFreq_Hz = 0;
// uint64_t pll2VcoFreq_Hz = 0;
// uint16_t pll2NdivStart = 0;
// uint8_t validPll2DivSetting = 0;
// uint64_t chDivU64 = 0;
//
// static const uint64_t PLL2_MIN_VCO_FREQ_HZ = 3450000000ULL;
// static const uint64_t PLL2_MAX_VCO_FREQ_HZ = 4025000000ULL;
// /*******************************************************************
// * PLL1 Settings
// *******************************************************************
// */
//
// /* find valid PLL1 Ndiv and REFA div */
// for (pll1Ndiv = 1; pll1Ndiv < 20; pll1Ndiv++)
// {
// pll1PfdFreq_Hz = vcxoFrequency_Hz / pll1Ndiv;
//
// if ((pll1PfdFreq_Hz <= 110000000) && (pll1PfdFreq_Hz >= 1000000) &&
// (pll1PfdFreq_Hz <= refAFrequency_Hz) &&
// (refAFrequency_Hz % pll1PfdFreq_Hz == 0)
// )
// {
// validPll1DivSetting = 1;
// refAdiv = refAFrequency_Hz / pll1PfdFreq_Hz ;
// break;
// }
// }
//
// if (validPll1DivSetting == 0)
// {
// return ADIERR_INV_PARM;
// }
//
// device->pll1Settings->nDivider = pll1Ndiv; //This init function always runs PLL1 at 30.72MHz Pfd rate
// device->pll1Settings->refA_bufferCtrl = DIFFERENTIAL; //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL
// device->pll1Settings->refA_Divider = refAdiv;
// device->pll1Settings->refA_Frequency_Hz = refAFrequency_Hz;
// device->pll1Settings->refB_bufferCtrl = DISABLED; //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL
// device->pll1Settings->refB_Divider = 1;
// device->pll1Settings->refB_Frequency_Hz = 0;
// device->pll1Settings->vcxoBufferCtrl = NEG_SINGLE_ENDED; //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL
// device->pll1Settings->vcxo_Frequency_Hz = vcxoFrequency_Hz;
//
// /*******************************************************************
// * PLL2 Settings
// *******************************************************************
// */
//
// /*******************************************************************
// * Output Distribution Settings
// * 9369CE02A uses the following clock outputs
// * OUT 1: FPGA REFCLK
// * OUT 3: FPGA SYSREF
// * OUT 12: DUT SYSREF
// * OUT 13: DUT REFCLK
// *******************************************************************
// */
//
// /* PLL 2 input clock can be several different things. Currently hard coded by this init funciton to use
// * PLL 1 output (VCXO Frequency) with no scaling
// */
// pll2InputFreq_Hz = device->pll1Settings->vcxo_Frequency_Hz;
// validPll2DivSetting = 0;
//
// /* Sweep PLL2 Divider settings to find something that has a valid integer divide (3,4,5)*/
// for (pll2RfDiv = 3; pll2RfDiv <= 5; pll2RfDiv++)
// {
//
// pll2NdivStart = (PLL2_MIN_VCO_FREQ_HZ / pll2RfDiv / pll2InputFreq_Hz);
// /* find valid PLL2 Ndiv (1-256) */
// for (pll2Ndiv = pll2NdivStart; pll2Ndiv <= 256; pll2Ndiv++)
// {
// pll2VcoFreq_Hz = (pll2InputFreq_Hz * pll2RfDiv * pll2Ndiv);
//
// if (pll2VcoFreq_Hz < PLL2_MIN_VCO_FREQ_HZ)
// {
// /* Continue to next PLL2 N div */
// continue;
// }
// else if (pll2VcoFreq_Hz > PLL2_MAX_VCO_FREQ_HZ)
// {
// /* Break to next PLL2 RF div */
// break;
// }
//
// if (((pll2VcoFreq_Hz / pll2RfDiv) % outputDeviceClock_Hz) == 0)
// {
//
// device->pll2Settings->rfDivider = pll2RfDiv;
// device->pll2Settings->n2Divider = pll2Ndiv;
// device->pll2Settings->totalNdiv = pll2RfDiv * pll2Ndiv;
// chDivU64 = ((pll2VcoFreq_Hz / pll2RfDiv) / outputDeviceClock_Hz);
//
// if ((chDivU64 < 1) || (chDivU64 > 256))
// {
// return ADIERR_INV_PARM;
// }
// else
// {
// chDiv = (uint16_t)(chDivU64);
// }
//
// validPll2DivSetting = 1;
// break;
// }
// }
//
// if (validPll2DivSetting == 1)
// {
// break;
// }
// }
//
// if (validPll2DivSetting == 0)
// {
// return ADIERR_INV_PARM;
// }
//
// device->outputSettings->outPowerDown = (uint16_t)(~0x300A); //enable outputs 13,12,3 and 1
//
// for (i=0; i<14; i++){
// device->outputSettings->outSource[i] = CHANNEL_DIV; //CHANNEL_DIV , PLL1_OUTPUT, SYSREF, INV_PLL1_OUTPUT
// device->outputSettings->outBufferCtrl[i] = LVDS; //LVDS, LVDS_BOOST, HSTL
// device->outputSettings->outChannelDiv[i] = chDiv;
// device->outputSettings->outFrequency_Hz[i] = outputDeviceClock_Hz;
// device->outputSettings->outAnalogDelay[i] = 0;
// device->outputSettings->outDigitalDelay[i] = 0;
// }
//
//
// device->outputSettings->outSource[3] = SYSREF;
// device->outputSettings->outSource[12] = SYSREF;
//
//
// device->sysrefSettings->sysrefDivide = 512; //SYSREF frequency = VCXO / 2 / sysrefDivde
// device->sysrefSettings->sysrefNshotMode = ONE_PULSE; //ONE_PULSE=0, TWO_PULSES=2, FOUR_PULSES=3, SIX_PULSES=4, EIGHT_PULSES=5
// device->sysrefSettings->sysrefPatternMode = NSHOT; //NSHOT=0, CONTINUOUS=1, PRBS=2, STOP=3
// device->sysrefSettings->sysrefPinBufferMode = DISABLED; //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL
// device->sysrefSettings->sysrefPinEdgeMode = LEVEL_ACTIVE_HIGH; //LEVEL_ACTIVE_HIGH=0, LEVEL_ACTIVE_LOW=1, RISING_EDGE=2, FALLING_EDGE=3
// device->sysrefSettings->sysrefRequestMethod = SPI; //SPI=0,PIN=1
// device->sysrefSettings->sysrefSource = INTERNAL; //EXTERNAL=0, EXT_RESAMPLED=1, INTERNAL=2
return ADIERR_OK;
}
/**
* \brief Debug function to print out summary of AD9528 setup
*
* \param device AD9528 Device data structure describing setup of device.
*
* \return Returns enum ADI_ERR, 0=pass, >0 = fail
***********************************************************************************/
ADI_ERR AD9528_reportClockRates(ad9528Device_t *device)
{
return ADIERR_OK;
} //debug function to help verify data structure is setup correctly.
/**
* \brief Initializes the AD9528 by writing all SPI registers
*
* Initializes the AD9528 for use with the AD9369 transceiver. Designed to work with
* a reference clock of 122.88MHz. Reference clock is expected to be 30.72MHz.
* The output clocks from the AD9528 can run at 122.88M, 153.6M, 184.32M, 245.76M, or 307.2M.
* Typical setup: REFA frequency = 30.72, VCXO = 122.88MHz
* SYNC(SYSREF) pulses output at rate of 120kHz
*
* <B>Dependencies</B>
* - All parameters in device structure
*
* \param device is structure pointer to AD9528 clock device structure
*
* \return Returns enum ADI_ERR, 0=pass, >0 = fail
*/
ADI_ERR AD9528_initialize(ad9528Device_t *device) { //writes all registers to desired values, leaves clock outputs off, SYSREF output disabled.
uint8_t pll2_Adiv=0;
uint8_t pll2_Bdiv=0;
uint8_t reg108=0;
uint8_t reg109=0;
uint8_t i = 0;
uint8_t j = 0;
uint8_t reg508;
ADI_ERR retval = ADIERR_OK;
CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, ADIERR_OK, "\n// AD9528_initialize\n");
//CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_ADI_SPI_CONFIG_A, 0x18); //[4] and [3] =1 enable 4 wire SPI
//CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_ADI_SPI_CONFIG_B, 0x00);
retval = AD9528_setSpiSettings(device);
if (retval != ADIERR_OK)
{
return retval;
}
/**********************************************************************
* Configure PLL1
**********************************************************************
*/
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_REF_A_DIVIDER_LSB,
device->pll1Settings->refA_Divider & 0xFF); //REF A div[7:0]
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_REF_A_DIVIDER_MSB,
(device->pll1Settings->refA_Divider >> 8) & 0x03); //REF A div[9:8]
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_REF_B_DIVIDER_LSB,
device->pll1Settings->refB_Divider & 0xFF); //REF B div[7:0]
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_REF_B_DIVIDER_MSB,
(device->pll1Settings->refB_Divider >> 8) & 0x03); //REF B div[9:8]
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL1_N_DIV_LSB,
device->pll1Settings->nDivider & 0xFF); //PLL1 N div[7:0]
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL1_N_DIV_MSB,
(device->pll1Settings->nDivider >> 8) & 0x03); //PLL1 N div[9:8]
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL1_CHARGEPUMP,
0x0A); //PLL1 Charge Pump control 1
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL1_CP_CTRL2,
0x03); //PLL1 Charge Pump control 2
switch (device->pll1Settings->refA_bufferCtrl){
case DISABLED:
reg108 &= ~0x28;
reg109 &= ~0x01;
break; //clear all REFA enable bits
case SINGLE_ENDED:
reg108 |= 0x08;
reg109 &= ~0x01;
break; //Set REFA receiver enable, clear REFA SE negative input enable
case NEG_SINGLE_ENDED:
reg108 |= 0x08;
reg108 &= ~0x10;
reg109 |= 0x01;
break; //Disable REFA diff receiver, enable REFA receiver and use negative REFA input
case DIFFERENTIAL:
reg108 |= 0x28;
reg109 &= ~0x01;
break;
default:
reg108 |= 0x08;
reg109 &= ~0x01;
break; //default to single ended case
}
switch (device->pll1Settings->refB_bufferCtrl){
case DISABLED:
reg108 &= ~0x50;
reg109 &= ~0x02;
break; //clear all REFB enable bits
case SINGLE_ENDED:
reg108 |= 0x10;
reg109 &= ~0x02;
break; //Set REFB receiver enable, clear REFB SE negative input enable
case NEG_SINGLE_ENDED:
reg108 |= 0x10;
reg108 &= ~0x40;
reg109 |= 0x02;
break; //Disable REFB diff receiver, enable REFB receiver and use negative REFB input
case DIFFERENTIAL:
reg108 |= 0x50;
reg109 &= ~0x02;
break;
default:
reg108 |= 0x10;
reg109 &= ~0x02;
break; //default to single ended case
}
switch (device->pll1Settings->vcxoBufferCtrl){
case DISABLED:
reg108 &= ~0x03;
reg108 |= 0x04;
break; //power down VCXO input
case SINGLE_ENDED:
reg108 &= ~0x07;
break; //Clear VCXO receiver power down, defaults to Single ended mode
case NEG_SINGLE_ENDED:
reg108 &= ~0x07;
reg108 |= 0x02;
break; //Clear VCXO power down, enable Negative single ended mode[1]
case DIFFERENTIAL:
reg108 &= ~0x07;
reg108 |= 0x01;
break; //Clear VCXO power down, enable differential input buffer[0]
default:
reg108 &= ~0x07;
break; //default to positive single ended case
}
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_INPUT_RECEIVERS1,
reg108); //Input receiver settings (single ended or differential clock inputs)
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_INPUT_RECEIVERS2,
reg109); //Input receiver settings
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_INPUT_RECEIVERS3,
0x0A); //Reference selection mode
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL1_FASTLOCK,
0x00); //Disable Fast lock
/**********************************************************************
* Configure PLL2
**********************************************************************
*/
pll2_Bdiv = device->pll2Settings->totalNdiv / 4;
pll2_Adiv = device->pll2Settings->totalNdiv % 4;
if (pll2_Adiv > 3) { //A div valid range (0 to 3)
CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, ADIERR_INV_PARM, "\n// AD9528 PLL2 A Divider out of range (0 to 3)\n");
return ADIERR_INV_PARM;
}
if (pll2_Bdiv < 3 || pll2_Bdiv > 63) {
CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, ADIERR_INV_PARM, "\n// AD9528 PLL2 B Divider out of range (3 to 63)\n");
return ADIERR_INV_PARM;
}
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_CHARGEPUMP,
0xE6); //PLL2 Charge Pump[7:0]
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_N_DIV,
((pll2_Adiv & 0x3) << 6) | (pll2_Bdiv & 0x3F)); //PLL2 A and B divider
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_CTRL, 0x03); //PLL2 control
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_VCO_CTRL, 0x01); //Manual VCO CAL
if (device->pll2Settings->rfDivider < 3 || device->pll2Settings->rfDivider > 5) {
CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, ADIERR_INV_PARM, "\n// AD9528 PLL2 RF Divider out of range (3,4, or 5)\n");
return ADIERR_INV_PARM;
}
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_VCO_DIV,
device->pll2Settings->rfDivider); //VCO divider
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_LF_CTRL1,
0x3A); //PLL2 Loop filter [7:0]
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_LF_CTRL2,
0x00); //PLL2 Loop filter [8]
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_RDIV,
0x00); //R divider
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_REPLICA_CHDIV,
(device->pll2Settings->totalNdiv / device->pll2Settings->rfDivider)
-1 ); //Replica channel divider: Ndivider = rfDivider * R divider
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_REPLICA_DIV_PHASE,
0x00); //Replica Channel Divider phase
/**********************************************************************
* Configure Output Distribution
**********************************************************************
*/
for (i=0; i<14; i=i+1){
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_OUT0_CTRL1 + j,
((device->outputSettings->outSource[i] & 0x7) << 5) |
(device->outputSettings->outAnalogDelay[i] & 0x1F));
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_OUT0_CTRL2 + j,
((device->outputSettings->outBufferCtrl[i] & 0x3) << 6) |
(device->outputSettings->outDigitalDelay[i] & 0x3F));
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_OUT0_CHDIV + j,
device->outputSettings->outChannelDiv[i]-1);
j = j+3;
}
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_OUTPUT_SYNC, 0x00); //Sync outputs
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_MASK_SYNC1, 0x00); //Mask SYNC[7:0]
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_MASK_SYNC2, 0x00); //Mask SYNC[13:8]
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_EN_OUTPUT_PATH_SEL1,
0x00); //Bypass SYSREF resample [6:0], bit0:Enable VCXO to feed output distrubution
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_EN_OUTPUT_PATH_SEL2,
0x00); //Bypass SYSREF resample [13:7]
/**********************************************************************
* Configure SYSREF operation
**********************************************************************
*/
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSERF_DIV_LSB,
device->sysrefSettings->sysrefDivide & 0xFF); //SYSREF divider [7:0]
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSERF_DIV_MSB,
(device->sysrefSettings->sysrefDivide >> 8) & 0xFF); //SYSREF divider [7:0]
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL3,
((device->sysrefSettings->sysrefRequestMethod & 0x1) << 7) |
((device->sysrefSettings->sysrefPinEdgeMode & 0x3) << 5) );
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL4,
((device->sysrefSettings->sysrefSource & 0x03) << 6) |
((device->sysrefSettings->sysrefPatternMode & 0x3) << 4 ) |
((device->sysrefSettings->sysrefNshotMode & 0x7) << 1) );
if(device->sysrefSettings->sysrefPinBufferMode == DISABLED)
{
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL5,
0x04); //power down input buffer for external SYSREF
}
else if(device->sysrefSettings->sysrefPinBufferMode == SINGLE_ENDED)
{
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL5,
0x00); //enable positive singled ended input
}
else if(device->sysrefSettings->sysrefPinBufferMode == NEG_SINGLE_ENDED)
{
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL5,
0x02); //enable negative singled ended input
}
else if(device->sysrefSettings->sysrefPinBufferMode == DIFFERENTIAL)
{
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL5,
0x01); //enable differential input buffer
}
else
{
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL5,
0x04); //power down input buffer for external SYSREF
}
/**********************************************************************
* Power down control
**********************************************************************
*/
if (device->pll1Settings->bypassPll1 > 0)
{
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_POWERDOWN_CTRL,
0x14);// power up PLL2 and output distribution, power down PLL1
}
else
{
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_POWERDOWN_CTRL,
0x10);// power up PLL1, PLL2 and output distribution
}
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_POWERDOWN1,
device->outputSettings->outPowerDown & 0xFF); //power down out[7:0]
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_POWERDOWN2,
((device->outputSettings->outPowerDown >> 8) & 0x3F)); //power down out[13:8]
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_LDO_ENABLES1,
0xFF); //LDO enable per output channel [7:0]
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_LDO_ENABLES2,
0xFF); //LDO enable per output channel [15:8]
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_STATUS0_CTRL,
0x07); //STATUS 0 outputs REFA present
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_STATUS1_CTRL,
0x01); //STATUS 1 outputs PLL1 and PLL2 locked
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_STATUS_OE,
0x0C);// Make Status0 and Status1 outputs after reset.
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_IO_UPDATE,
0x01); //IO update to make all these settings valid in the 9528
CMB_setTimeout_ms(1000);
do{
CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_STATUS_READBACK0, &reg508);
if(CMB_hasTimeoutExpired() > 0)
{
return ADIERR_FAILED;
}
}while((reg508 & 0xA2) != 0xA2);
return ADIERR_OK;
}
/// Send a SPI message to request a SYSREF pulse or continuous SYSREF from the AD9528.
/*******************************************************************************//**
* Requests a SYSREF from the AD9528. It will use whatever settings for SYSREF
* that are current configured in the AD9528. This could be a single pulse,
* multiple pulses, or continuous pulses.
* <B>Dependencies</B>
* - device->spiSettings
* - device->sysrefSettings->sysrefPatternMode
*
* \param device is structure pointer to AD9528 clock device structure
* \param enableSYSREF If NSHOT SYSREF mode, this parameter is ignored. If PRBS/CONTINUOUS SYSREF mode, 1= enable SYSREF, 0= disable SYSREF.
*
* \return Returns enum ADI_ERR, 0=pass, >0 = fail
***********************************************************************************/
ADI_ERR AD9528_requestSysref(ad9528Device_t *device, uint8_t enableSYSREF){
uint8_t _enableSYSREF=0;
if (device->sysrefSettings->sysrefPatternMode == NSHOT || enableSYSREF > 0)
{
_enableSYSREF = 1;
}
else
{
_enableSYSREF = 0;
}
CMB_SPIWriteField(device->spiSettings, AD9528_ADDR_SYSREF_CTRL4, _enableSYSREF, 0x01, 0x00); //Set SPI SYSREF request bit
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_IO_UPDATE, 0x01); //IO update to make all these settings valid in the 9528
return ADIERR_OK;
}
/// Allow changing the 9528 SYSREF frequency and pattern mode(CONTINUOUS, PRBS vs NSHOT mode)
/*******************************************************************************//**
* NOTE: this function will update the device structure with the parameter values passed
* into this function. The device->sysrefSettings->sysrefPatternMode, device->sysrefSettings->sysrefNshotMode,
* and device->sysrefSettings->sysrefDivide values will be updated in the device structure.
*
* <B>Dependencies</B>
* - device->spiSettings
*
* \param device is structure pointer to AD9528 clock device structure
* \param divideFromPll1Out Sets the SYSREF pulse frequency. SYSREF frequency = PLL1_VCXO frequency/divideFromPll1Out
* \param sysrefPatternMode Valid settings: NSHOT, CONTINUOUS, PRBS, STOP
* \param nShotPulses Valid settings: ONE_PULSE=0, TWO_PULSES=2, FOUR_PULSES=3, SIX_PULSES=4, EIGHT_PULSES=5
*
* \return Returns enum ADI_ERR, 0=pass, >0 = fail
***********************************************************************************/
ADI_ERR AD9528_setupSYSREF(ad9528Device_t *device, uint16_t divideFromPll1Out, sysrefPatternMode_t sysrefPatternMode, sysrefNshotMode_t nShotPulses)
{
uint8_t reg403=0;
device->sysrefSettings->sysrefPatternMode = sysrefPatternMode;
device->sysrefSettings->sysrefNshotMode = nShotPulses;
device->sysrefSettings->sysrefDivide = divideFromPll1Out >> 1; //SYSREF frequency is (PLL1)VCXO frequency / 2 / device->sysrefSettings->sysrefDivide
CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL4, &reg403);
reg403 = reg403 & ~0x01; //clear bit 0 to stop a continuous sysref if it is on.
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL4, reg403);
reg403 = reg403 & ~0x3E; //clear bits for pattern mode and Nshot mode bitfields
reg403 = reg403 | ((sysrefPatternMode & 0x3) << 4) | ((nShotPulses & 0x7) << 1);
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL4, reg403); //update internal sysref pattern mode and Nshot mode (number of pulses)
//SYSREF request bit x403[0] is left 0. The next call to AD9528_requestSysref will start the SYSREF
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_IO_UPDATE, 0x01); //IO update to make all these settings valid in the 9528
return ADIERR_OK;
}
/// Update the AD9528 clock outputs that are enabled.
/*******************************************************************************//**
* NOTE: this function will update the device structure with the parameter values passed
* into this function. The device->sysrefSettings->sysrefPatternMode, device->sysrefSettings->sysrefNshotMode,
* and device->sysrefSettings->sysrefDivide values will be updated in the device structure.
*
* <B>Dependencies</B>
* - device->spiSettings
*
* \param device is structure pointer to AD9528 clock device structure
* \param clkEnable Sets which clock outputs are enabled. Bit per clock output. bit0 = out0, etc.
*
* \return Returns enum ADI_ERR, 0=pass, >0 = fail
***********************************************************************************/
ADI_ERR AD9528_enableClockOutputs(ad9528Device_t *device, uint16_t clkEnable)
{ //clkEnable: bit per clock output
device->outputSettings->outPowerDown = ~clkEnable;
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_POWERDOWN1, device->outputSettings->outPowerDown & 0xFF); //power down out[7:0]
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_POWERDOWN2, ((device->outputSettings->outPowerDown >> 8) & 0x3F)); //power down out[13:8]
CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_IO_UPDATE, 0x01); //IO update to make all these settings valid in the 9528
return ADIERR_OK;
}
/// Waits for PLL1 and PLL2 to lock and the REFA and VCXO clocks to be present
/*******************************************************************************//**
* Waits until Reference A clock and VCXO clock input to be detected (present),
* and PLL1 and PLL2 to lock. Will timeout after 1 second and return ADIERR_FAILED.
* If clock are detected and PLLs locked, returns ADIERR_OK.
*
* <B>Dependencies</B>
* - device->spiSettings
*
* \param device is structure pointer to AD9528 clock device structure
*
* \return Returns enum ADI_ERR, 0=pass, >0 = fail
***********************************************************************************/
ADI_ERR AD9528_waitForPllLock(ad9528Device_t *device)
{
uint8_t reg508;
CMB_setTimeout_ms(1000);
do{
CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_STATUS_READBACK0, &reg508);
if(CMB_hasTimeoutExpired() > 0)
{
return ADIERR_FAILED;
}
}while((reg508 & 0x27) != 0x27);
return ADIERR_OK;
}
/// Reads the Lock Status of the PLLs and present detect of the reference clocks
/*******************************************************************************//**
* NOTE: This is a non blocking function that reads a register to see if PLL1
* and PLL2 are locked and Reference clock A and the VCXO input clock are
* detected (present). If the *status parameter is not NULL, the status will
* be returned. If *status is NULL, the error return value will denote if
* the PllStatus is locked or not with ADIERR_OK or ADIERR_FAILED.
*
* <B>Dependencies</B>
* - device->spiSettings
*
* \param device is structure pointer to AD9528 clock device structure
*
* \return Returns enum ADI_ERR, 0=pass, >0 = fail
***********************************************************************************/
ADI_ERR AD9528_readPllStatus(ad9528Device_t *device, uint8_t *status)
{
uint8_t reg508;
//bit5 is VCXO clock detected
//bit2 is REFCLK A detected
//bit1 is PLL2 lock detect
//bit0 is PLL1 lock detect
/* read twice to refresh status bits */
CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_STATUS_READBACK0, &reg508);
CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_STATUS_READBACK0, &reg508);
/* if status is a valid pointer, return the PLL status */
if (status > 0)
{
*status = reg508;
}
/* PLLs 1 and 2 are locked and VCXO and REFA detected if reg508 has bits 5,2,1 and 0 set */
if((reg508 & 0x27) == 0x27)
return ADIERR_OK;
else
return ADIERR_FAILED;
}
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/mykonos/ad9528.h
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/**
* \file ad9528.h
* \brief Contains function declarations and ad9528Device_t structure typedef for ad9528.c
*/
/**
* \page Disclaimer Legal Disclaimer
* Copyright 2015-2017 Analog Devices Inc.
* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
*
*/
#ifndef _AD9528_LIB_H_
#define _AD9528_LIB_H_
#include <stdint.h>
#include "../common.h"
#include "t_ad9528.h"
#ifdef __cplusplus
extern "C" {
#endif
#define CLEMENTE_TDD_AD9528_CLKOUT_INDEX 13
//Helper function to setup the 9528 device data structure specifically for the ADI transceiver evaluation cards
ADI_ERR AD9528_initDeviceDataStruct(ad9528Device_t *device, uint32_t vcxoFrequency_Hz, uint32_t refAFrequency_Hz, uint32_t outputDeviceClock_Hz);
ADI_ERR AD9528_reportClockRates(ad9528Device_t *device); //debug function to help verify data structure is setup correctly.
//AD9528 API functions
ADI_ERR AD9528_resetDevice(ad9528Device_t *device);
ADI_ERR AD9528_setSpiSettings(ad9528Device_t *device);
ADI_ERR AD9528_initialize(ad9528Device_t *device); //writes all registers to desired values, leaves clock outputs off.
ADI_ERR AD9528_waitForPllLock(ad9528Device_t *device);
ADI_ERR AD9528_readPllStatus(ad9528Device_t *device, uint8_t *status);
ADI_ERR AD9528_enableClockOutputs(ad9528Device_t *device, uint16_t clkEnable); //clkEnable: bit per clock output
ADI_ERR AD9528_setupSYSREF(ad9528Device_t *device, uint16_t divideFromPll1Out, sysrefPatternMode_t sysrefPatternMode, sysrefNshotMode_t nShotPulses);
ADI_ERR AD9528_requestSysref(ad9528Device_t *device, uint8_t enableSYSREF);
#ifdef __cplusplus
}
#endif
#endif
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/mykonos/mykonos.c
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projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/mykonos/mykonos.h
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/*!
* \file mykonos.h
* \brief Contains macro definitions and function prototypes for mykonos.c
*
* Mykonos API version: 1.5.2.3566
*/
/**
* \page Disclaimer Legal Disclaimer
* Copyright 2015-2017 Analog Devices Inc.
* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
*
*/
#ifndef _MYKONOS_LIB_H_
#define _MYKONOS_LIB_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "t_mykonos.h"
#include "mykonos_version.h"
#define TX_PROFILE_VALID 0x01
#define RX_PROFILE_VALID 0x02
#define ORX_PROFILE_VALID 0x04
#define SNIFF_PROFILE_VALID 0x08
/*
****************************************************************************
* General Initialization functions
****************************************************************************
*/
mykonosErr_t MYKONOS_resetDevice(mykonosDevice_t *device);
mykonosErr_t MYKONOS_getDeviceRev(mykonosDevice_t *device, uint8_t *revision);
mykonosErr_t MYKONOS_getProductId(mykonosDevice_t *device, uint8_t *productId);
mykonosErr_t MYKONOS_setSpiSettings(mykonosDevice_t *device);
mykonosErr_t MYKONOS_verifyDeviceDataStructure(mykonosDevice_t *device);
mykonosErr_t MYKONOS_verifyProfiles(mykonosDevice_t *device);
mykonosErr_t MYKONOS_initialize(mykonosDevice_t *device);
mykonosErr_t MYKONOS_waitForEvent(mykonosDevice_t *device, waitEvent_t waitEvent, uint32_t timeout_us);
mykonosErr_t MYKONOS_readEventStatus(mykonosDevice_t *device, waitEvent_t waitEvent, uint8_t *eventDone);
mykonosErr_t MYKONOS_getApiVersion (mykonosDevice_t *device, uint32_t *siVer, uint32_t *majorVer, uint32_t *minorVer, uint32_t *buildVer);
/*
*****************************************************************************
* PLL / Synthesizer functions
*****************************************************************************
*/
mykonosErr_t MYKONOS_initDigitalClocks(mykonosDevice_t *device);
mykonosErr_t MYKONOS_setRfPllFrequency(mykonosDevice_t *device, mykonosRfPllName_t pllName, uint64_t rfPllLoFrequency_Hz);
mykonosErr_t MYKONOS_getRfPllFrequency(mykonosDevice_t *device, mykonosRfPllName_t pllName, uint64_t *rfPllLoFrequency_Hz);
mykonosErr_t MYKONOS_checkPllsLockStatus(mykonosDevice_t *device, uint8_t *pllLockStatus);
mykonosErr_t MYKONOS_setRfPllLoopFilter(mykonosDevice_t *device, mykonosRfPllName_t pllName, uint16_t loopBandwidth_kHz, uint8_t stability);
mykonosErr_t MYKONOS_getRfPllLoopFilter(mykonosDevice_t *device, mykonosRfPllName_t pllName, uint16_t *loopBandwidth_kHz, uint8_t *stability);
/*
*****************************************************************************
* ARM Processor Control Functions
*****************************************************************************
*/
mykonosErr_t MYKONOS_initArm(mykonosDevice_t *device);
mykonosErr_t MYKONOS_loadArmFromBinary(mykonosDevice_t *device, uint8_t *binary, uint32_t count);
mykonosErr_t MYKONOS_loadArmConcurrent(mykonosDevice_t *device, uint8_t *binary, uint32_t count);
mykonosErr_t MYKONOS_verifyArmChecksum(mykonosDevice_t *device);
mykonosErr_t MYKONOS_checkArmState(mykonosDevice_t *device, mykonosArmState_t armStateCheck);
mykonosErr_t MYKONOS_getArmVersion(mykonosDevice_t *device, uint8_t *majorVer, uint8_t *minorVer, uint8_t *rcVer, mykonosBuild_t *buildType);
mykonosErr_t MYKONOS_configDpd(mykonosDevice_t *device);
mykonosErr_t MYKONOS_getDpdConfig(mykonosDevice_t *device);
mykonosErr_t MYKONOS_getDpdStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosDpdStatus_t *dpdStatus);
mykonosErr_t MYKONOS_restoreDpdModel(mykonosDevice_t *device, mykonosTxChannels_t txChannel, uint8_t *modelDataBuffer, uint32_t modelNumberBytes);
mykonosErr_t MYKONOS_saveDpdModel(mykonosDevice_t *device, mykonosTxChannels_t txChannel, uint8_t *modelDataBuffer, uint32_t modelNumberBytes);
mykonosErr_t MYKONOS_setDpdActState(mykonosDevice_t *device, mykonosTxChannels_t txChannel, uint8_t actState);
mykonosErr_t MYKONOS_resetDpd(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosDpdResetMode_t reset);
mykonosErr_t MYKONOS_setDpdBypassConfig(mykonosDevice_t *device, mykonosDpdBypassConfig_t *actConfig);
mykonosErr_t MYKONOS_getDpdBypassConfig(mykonosDevice_t *device, mykonosDpdBypassConfig_t *actConfig);
mykonosErr_t MYKONOS_setDpdActuatorCheck(mykonosDevice_t *device, mykonosDpdActuatorCheck_t *actCheck);
mykonosErr_t MYKONOS_getDpdActuatorCheck(mykonosDevice_t *device, mykonosDpdActuatorCheck_t *actCheck);
mykonosErr_t MYKONOS_setClgcAttenTuningConfig(mykonosDevice_t *device, mykonosClgcAttenTuningConfig_t *attRangeCfg);
mykonosErr_t MYKONOS_getClgcAttenTuningConfig(mykonosDevice_t *device, mykonosClgcAttenTuningConfig_t *attRangeCfg);
mykonosErr_t MYKONOS_configClgc(mykonosDevice_t *device);
mykonosErr_t MYKONOS_getClgcConfig(mykonosDevice_t *device);
mykonosErr_t MYKONOS_getClgcStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosClgcStatus_t *clgcStatus);
mykonosErr_t MYKONOS_setClgcGain(mykonosDevice_t *device, mykonosTxChannels_t txChannel, int16_t gain);
mykonosErr_t MYKONOS_configVswr(mykonosDevice_t *device);
mykonosErr_t MYKONOS_getVswrConfig(mykonosDevice_t *device);
mykonosErr_t MYKONOS_getVswrStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosVswrStatus_t *vswrStatus);
mykonosErr_t MYKONOS_runInitCals(mykonosDevice_t *device, uint32_t calMask);
mykonosErr_t MYKONOS_waitInitCals(mykonosDevice_t *device, uint32_t timeoutMs, uint8_t *errorFlag, uint8_t *errorCode);
mykonosErr_t MYKONOS_abortInitCals(mykonosDevice_t *device, uint32_t *calsCompleted);
mykonosErr_t MYKONOS_getInitCalStatus(mykonosDevice_t *device, mykonosInitCalStatus_t *initCalStatus);
mykonosErr_t MYKONOS_resetExtTxLolChannel(mykonosDevice_t *device, mykonosTxChannels_t channelSel);
mykonosErr_t MYKONOS_radioOn(mykonosDevice_t *device);
mykonosErr_t MYKONOS_radioOff(mykonosDevice_t *device);
mykonosErr_t MYKONOS_getRadioState(mykonosDevice_t *device, uint32_t *radioStatus);
mykonosErr_t MYKONOS_enableTrackingCals(mykonosDevice_t *device, uint32_t enableMask);
mykonosErr_t MYKONOS_rescheduleTrackingCal(mykonosDevice_t *device, mykonosTrackingCalibrations_t trackingCal);
mykonosErr_t MYKONOS_setAllTrackCalState(mykonosDevice_t *device, uint32_t trackingCalMask);
mykonosErr_t MYKONOS_getAllTrackCalState(mykonosDevice_t *device, uint32_t *trackCals);
mykonosErr_t MYKONOS_setTrackingCalState(mykonosDevice_t *device, mykonosTrackingCalibrations_t trackingCal, uint8_t trackCalState);
mykonosErr_t MYKONOS_getTrackingCalState(mykonosDevice_t *device, mykonosTrackingCalibrations_t trackingCal, uint8_t *trackCalState);
mykonosErr_t MYKONOS_getEnabledTrackingCals(mykonosDevice_t *device, uint32_t *enableMask);
mykonosErr_t MYKONOS_getPendingTrackingCals(mykonosDevice_t *device, uint32_t *pendingCalMask);
mykonosErr_t MYKONOS_getTxLolStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosTxLolStatus_t *txLolStatus);
mykonosErr_t MYKONOS_getTxQecStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosTxQecStatus_t *txQecStatus);
mykonosErr_t MYKONOS_getRxQecStatus(mykonosDevice_t *device, mykonosRxChannels_t rxChannel, mykonosRxQecStatus_t *rxQecStatus);
mykonosErr_t MYKONOS_getOrxQecStatus(mykonosDevice_t *device, mykonosObsRxChannels_t orxChannel, mykonosOrxQecStatus_t *orxQecStatus);
mykonosErr_t MYKONOS_setSnifferChannel(mykonosDevice_t *device, mykonosSnifferChannel_t snifferChannel);
mykonosErr_t MYKONOS_setRadioControlPinMode(mykonosDevice_t *device);
mykonosErr_t MYKONOS_setPathDelay(mykonosDevice_t *device, mykonosPathdelay_t *pathDelay);
mykonosErr_t MYKONOS_getPathDelay(mykonosDevice_t *device, mykonosPathDelaySel_t select, mykonosPathdelay_t *pathDelay);
mykonosErr_t MYKONOS_getDpdErrorCounters(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosDpdErrorCounters_t *dpdErrCnt);
/* Low level ARM functions */
mykonosErr_t MYKONOS_readArmMem(mykonosDevice_t *device, uint32_t address, uint8_t *returnData, uint32_t bytesToRead, uint8_t autoIncrement);
mykonosErr_t MYKONOS_writeArmMem(mykonosDevice_t *device, uint32_t address, uint8_t *data, uint32_t byteCount);
mykonosErr_t MYKONOS_writeArmConfig(mykonosDevice_t *device, uint8_t objectId, uint16_t offset, uint8_t *data, uint8_t byteCount);
mykonosErr_t MYKONOS_readArmConfig(mykonosDevice_t *device, uint8_t objectId, uint16_t offset, uint8_t *data, uint8_t byteCount);
mykonosErr_t MYKONOS_sendArmCommand(mykonosDevice_t *device, uint8_t opCode, uint8_t *extendedData, uint8_t extendedDataNumBytes);
mykonosErr_t MYKONOS_readArmCmdStatus(mykonosDevice_t *device, uint16_t *errorWord, uint16_t *statusWord);
mykonosErr_t MYKONOS_readArmCmdStatusByte(mykonosDevice_t *device, uint8_t opCode, uint8_t *cmdStatByte);
mykonosErr_t MYKONOS_waitArmCmdStatus(mykonosDevice_t *device, uint8_t opCode, uint32_t timeoutMs, uint8_t *cmdStatByte);
mykonosErr_t MYKONOS_writeArmProfile(mykonosDevice_t *device);
mykonosErr_t MYKONOS_loadAdcProfiles(mykonosDevice_t *device);
/*
*****************************************************************************
* JESD204B Datapath Functions
*****************************************************************************
*/
/* Functions to setup the JESD204B IP */
mykonosErr_t MYKONOS_resetDeframer(mykonosDevice_t *device);
mykonosErr_t MYKONOS_setupSerializers(mykonosDevice_t *device);
mykonosErr_t MYKONOS_setupDeserializers(mykonosDevice_t *device);
mykonosErr_t MYKONOS_setupJesd204bFramer(mykonosDevice_t *device);
mykonosErr_t MYKONOS_setupJesd204bObsRxFramer(mykonosDevice_t *device);
mykonosErr_t MYKONOS_setupJesd204bDeframer(mykonosDevice_t *device);
mykonosErr_t MYKONOS_enableRxFramerLink(mykonosDevice_t *device, uint8_t enable);
mykonosErr_t MYKONOS_enableObsRxFramerLink(mykonosDevice_t *device, uint8_t enable);
/* Functions to initialize the JESD204B link */
mykonosErr_t MYKONOS_enableMultichipSync(mykonosDevice_t *device, uint8_t enableMcs, uint8_t *mcsStatus);
mykonosErr_t MYKONOS_enableSysrefToRxFramer(mykonosDevice_t *device, uint8_t enable);
mykonosErr_t MYKONOS_enableSysrefToObsRxFramer(mykonosDevice_t *device, uint8_t enable);
mykonosErr_t MYKONOS_enableSysrefToDeframer(mykonosDevice_t *device, uint8_t enable);
/* Functions to help debug the JESD204B link */
mykonosErr_t MYKONOS_readRxFramerStatus(mykonosDevice_t *device, uint8_t *framerStatus);
mykonosErr_t MYKONOS_readOrxFramerStatus(mykonosDevice_t *device, uint8_t *obsFramerStatus);
mykonosErr_t MYKONOS_readDeframerStatus(mykonosDevice_t *device, uint8_t *deframerStatus);
mykonosErr_t MYKONOS_getDeframerFifoDepth(mykonosDevice_t *device, uint8_t *fifoDepth, uint8_t *readEnLmfcCount);
/* PRBS debug functions */
mykonosErr_t MYKONOS_enableRxFramerPrbs(mykonosDevice_t *device, mykonosPrbsOrder_t polyOrder, uint8_t enable);
mykonosErr_t MYKONOS_enableObsRxFramerPrbs(mykonosDevice_t *device, mykonosPrbsOrder_t polyOrder, uint8_t enable);
mykonosErr_t MYKONOS_rxInjectPrbsError(mykonosDevice_t *device);
mykonosErr_t MYKONOS_obsRxInjectPrbsError(mykonosDevice_t *device);
mykonosErr_t MYKONOS_enableDeframerPrbsChecker(mykonosDevice_t *device, uint8_t lanes, mykonosPrbsOrder_t polyOrder, uint8_t enable);
mykonosErr_t MYKONOS_clearDeframerPrbsCounters(mykonosDevice_t *device);
mykonosErr_t MYKONOS_readDeframerPrbsCounters(mykonosDevice_t *device, uint8_t counterSelect, uint32_t *prbsErrorCount);
/* Miscellaneous debug functions */
mykonosErr_t MYKONOS_jesd204bIlasCheck(mykonosDevice_t *device, uint16_t *mismatch);
mykonosErr_t MYKONOS_setRxFramerDataSource(mykonosDevice_t *device, uint8_t dataSource);
mykonosErr_t MYKONOS_setObsRxFramerDataSource(mykonosDevice_t *device, uint8_t dataSource);
/*
*****************************************************************************
* Shared Data path functions
*****************************************************************************
*/
mykonosErr_t MYKONOS_programFir(mykonosDevice_t *device, mykonosfirName_t filterToProgram, mykonosFir_t *firFilter);
mykonosErr_t MYKONOS_readFir(mykonosDevice_t *device, mykonosfirName_t filterToRead, mykonosFir_t *firFilter);
/*
*****************************************************************************
* Rx Data path functions
*****************************************************************************
*/
mykonosErr_t MYKONOS_programRxGainTable(mykonosDevice_t *device, uint8_t *gainTablePtr, uint8_t numGainIndexesInTable, mykonosGainTable_t rxChannel);
mykonosErr_t MYKONOS_setRx1ManualGain(mykonosDevice_t *device, uint8_t gainIndex);
mykonosErr_t MYKONOS_setRx2ManualGain(mykonosDevice_t *device, uint8_t gainIndex);
mykonosErr_t MYKONOS_getRx1Gain(mykonosDevice_t *device, uint8_t *rx1GainIndex);
mykonosErr_t MYKONOS_getRx2Gain(mykonosDevice_t *device, uint8_t *rx2GainIndex);
mykonosErr_t MYKONOS_setupRxAgc(mykonosDevice_t *device);
mykonosErr_t MYKONOS_resetRxAgc(mykonosDevice_t *device);
mykonosErr_t MYKONOS_setRxAgcMinMaxGainIndex(mykonosDevice_t *device, mykonosRxChannels_t rxChannelSelect, uint8_t maxGainIndex, uint8_t minGainIndex);
mykonosErr_t MYKONOS_setObsRxAgcMinMaxGainIndex(mykonosDevice_t *device, mykonosObsRxChannels_t obsRxChannelSelect, uint8_t maxGainIndex, uint8_t minGainIndex);
mykonosErr_t MYKONOS_setRx1TempGainComp(mykonosDevice_t *device, int16_t rx1TempCompGain_mdB);
mykonosErr_t MYKONOS_getRx1TempGainComp(mykonosDevice_t *device, int16_t *rx1TempCompGain_mdB);
mykonosErr_t MYKONOS_setRx2TempGainComp(mykonosDevice_t *device, int16_t rx2TempCompGain_mdB);
mykonosErr_t MYKONOS_getRx2TempGainComp(mykonosDevice_t *device, int16_t *rx2TempCompGain_mdB);
mykonosErr_t MYKONOS_setObsRxTempGainComp(mykonosDevice_t *device, int16_t obsRxTempCompGain_mdB);
mykonosErr_t MYKONOS_getObsRxTempGainComp(mykonosDevice_t *device, int16_t *obsRxTempCompGain_mdB);
mykonosErr_t MYKONOS_enableRxGainCtrSyncPulse(mykonosDevice_t *device, uint8_t enable);
mykonosErr_t MYKONOS_setRxGainControlMode(mykonosDevice_t *device, mykonosGainMode_t mode);
mykonosErr_t MYKONOS_getRx1DecPower(mykonosDevice_t *device, uint16_t *rx1DecPower_mdBFS);
mykonosErr_t MYKONOS_getRx2DecPower(mykonosDevice_t *device, uint16_t *rx2DecPower_mdBFS);
/*
*****************************************************************************
* Observation Rx Data path functions
*****************************************************************************
*/
mykonosErr_t MYKONOS_setDefaultObsRxPath(mykonosDevice_t *device, mykonosObsRxChannels_t defaultObsRxCh);
mykonosErr_t MYKONOS_setObsRxPathSource(mykonosDevice_t *device, mykonosObsRxChannels_t obsRxCh);
mykonosErr_t MYKONOS_getObsRxPathSource(mykonosDevice_t *device, mykonosObsRxChannels_t *obsRxCh);
mykonosErr_t MYKONOS_setObsRxManualGain(mykonosDevice_t *device, mykonosObsRxChannels_t obsRxCh, uint8_t gainIndex);
mykonosErr_t MYKONOS_getObsRxGain(mykonosDevice_t *device, uint8_t *gainIndex);
mykonosErr_t MYKONOS_setupObsRxAgc(mykonosDevice_t *device);
mykonosErr_t MYKONOS_enableObsRxGainCtrSyncPulse(mykonosDevice_t *device, uint8_t enable);
mykonosErr_t MYKONOS_setObsRxGainControlMode(mykonosDevice_t *device, mykonosGainMode_t mode);
mykonosErr_t MYKONOS_getObsRxDecPower(mykonosDevice_t *device, uint16_t *obsRxDecPower_mdBFS);
/*
*****************************************************************************
* Tx Data path functions
*****************************************************************************
*/
mykonosErr_t MYKONOS_setTx1Attenuation(mykonosDevice_t *device, uint16_t tx1Attenuation_mdB);
mykonosErr_t MYKONOS_setTx2Attenuation(mykonosDevice_t *device, uint16_t tx2Attenuation_mdB);
mykonosErr_t MYKONOS_getTx1Attenuation(mykonosDevice_t *device, uint16_t *tx1Attenuation_mdB);
mykonosErr_t MYKONOS_getTx2Attenuation(mykonosDevice_t *device, uint16_t *tx2Attenuation_mdB);
mykonosErr_t MYKONOS_getTxFilterOverRangeStatus(mykonosDevice_t *device, uint8_t *txFilterStatus);
mykonosErr_t MYKONOS_enableTxNco(mykonosDevice_t *device, uint8_t enable, int32_t tx1ToneFreq_kHz, int32_t tx2ToneFreq_kHz);
/*
*****************************************************************************
* PA Protection Functions
*****************************************************************************
*/
mykonosErr_t MYKONOS_setupPaProtection(mykonosDevice_t *device, uint16_t powerThreshold, uint8_t attenStepSize, uint8_t avgDuration, uint8_t stickyFlagEnable, uint8_t txAttenControlEnable);
mykonosErr_t MYKONOS_enablePaProtection(mykonosDevice_t *device, uint8_t enable);
mykonosErr_t MYKONOS_getDacPower(mykonosDevice_t *device, mykonosTxChannels_t channel, uint16_t *channelPower);
mykonosErr_t MYKONOS_getPaProtectErrorFlagStatus(mykonosDevice_t *device, uint8_t *errorFlagStatus);
mykonosErr_t MYKONOS_clearPaErrorFlag(mykonosDevice_t *device);
/*
*****************************************************************************
* Low level functions and helper functions. BBP should not need to call
*****************************************************************************
*/
const char* getMykonosErrorMessage(mykonosErr_t errorCode);
mykonosErr_t MYKONOS_initSubRegisterTables(mykonosDevice_t *device);
mykonosErr_t MYKONOS_setTxPfirSyncClk(mykonosDevice_t *device); /* Helper function */
mykonosErr_t MYKONOS_setRxPfirSyncClk(mykonosDevice_t *device); /* Helper function */
/*
*****************************************************************************
* Functions to configure DC offsets
*****************************************************************************
*/
mykonosErr_t MYKONOS_setRfDcOffsetCnt(mykonosDevice_t *device, mykonosDcOffsetChannels_t channel, uint16_t measureCount);
mykonosErr_t MYKONOS_getRfDcOffsetCnt(mykonosDevice_t *device, mykonosDcOffsetChannels_t channel, uint16_t *measureCount);
mykonosErr_t MYKONOS_setDigDcOffsetMShift(mykonosDevice_t *device, mykonosDcOffsetChannels_t channel, uint8_t mShift);
mykonosErr_t MYKONOS_getDigDcOffsetMShift(mykonosDevice_t *device, mykonosDcOffsetChannels_t channel, uint8_t *mShift);
mykonosErr_t MYKONOS_setDigDcOffsetEn(mykonosDevice_t *device, uint8_t enableMask);
mykonosErr_t MYKONOS_getDigDcOffsetEn(mykonosDevice_t *device, uint8_t *enableMask);
#ifdef __cplusplus
}
#endif
#endif
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/mykonos/mykonosMmap.c
+136
View File
@@ -0,0 +1,136 @@
/**
* \file mykonosMmap.c
* \brief Contains the Mykonos memory mapping
*
* Mykonos API version: 1.5.2.3566
*/
/**
* \page Disclaimer Legal Disclaimer
* Copyright 2015-2017 Analog Devices Inc.
* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
*
*/
#include <stdint.h>
uint8_t mykonosMmap [] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x13,0x03,0x03,0x13,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
0x00,0xE4,0xE4,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA5,0xA5,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x01,0x00,0xE4,0xE4,0x00,0x00,0x00,0x1F,0x00,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x9F,0xE0,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0xF5,0x8F,0x0F,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/*!< Mykonos memory map */
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/mykonos/mykonos_gpio.c
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projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/mykonos/mykonos_gpio.h
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/*!
* \file mykonos_gpio.h
* \brief Contains macro definitions and function prototypes for mykonos_gpio.c
*
* Mykonos API version: 1.5.2.3566
*/
/**
* \page Disclaimer Legal Disclaimer
* Copyright 2015-2017 Analog Devices Inc.
* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
*
*/
#ifndef MYKONOSGPIO_H_
#define MYKONOSGPIO_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "t_mykonos.h"
#include "t_mykonos_gpio.h"
/*
*****************************************************************************
* GPIO functions
*****************************************************************************
*/
/* GPIO CMOS and SPI setting Functions */
mykonosGpioErr_t MYKONOS_setGpioDrv(mykonosDevice_t *device, uint32_t gpioDrv);
mykonosGpioErr_t MYKONOS_getGpioDrv(mykonosDevice_t *device, uint32_t *gpioDrv);
mykonosGpioErr_t MYKONOS_setGpioSlewRate(mykonosDevice_t *device, mykonosGpioSelect_t gpioSelect, mykonosGpioSlewRate_t slewRate);
mykonosGpioErr_t MYKONOS_getGpioSlewRate(mykonosDevice_t *device, mykonosGpioSelect_t gpioSelect, mykonosGpioSlewRate_t *slewRate);
mykonosGpioErr_t MYKONOS_setCmosDrv(mykonosDevice_t *device, mykonosCmosPadDrvStr_t spiDrv);
mykonosGpioErr_t MYKONOS_getCmosDrv(mykonosDevice_t *device, mykonosCmosPadDrvStr_t *spiDrv);
/* Monitor output Functions */
mykonosGpioErr_t MYKONOS_setGpioMonitorOut(mykonosDevice_t *device, uint8_t monitorIndex, uint8_t monitorMask);
mykonosGpioErr_t MYKONOS_getGpioMonitorOut(mykonosDevice_t *device, uint8_t *monitorIndex, uint8_t *monitorMask);
/* RX GPIO Functions */
mykonosGpioErr_t MYKONOS_setRx1GainCtrlPin(mykonosDevice_t *device, uint8_t incStep, uint8_t decStep, mykonosGpioSelect_t rx1GainIncPin, mykonosGpioSelect_t rx1GainDecPin, uint8_t enable);
mykonosGpioErr_t MYKONOS_setRx2GainCtrlPin(mykonosDevice_t *device, uint8_t incStep, uint8_t decStep, mykonosGpioSelect_t rx2GainIncPin, mykonosGpioSelect_t rx2GainDecPin, uint8_t enable);
mykonosGpioErr_t MYKONOS_getRx1GainCtrlPin(mykonosDevice_t *device, uint8_t *incStep, uint8_t *decStep, mykonosGpioSelect_t *rx1GainIncPin, mykonosGpioSelect_t *rx1GainDecPin, uint8_t *enable);
mykonosGpioErr_t MYKONOS_getRx2GainCtrlPin(mykonosDevice_t *device, uint8_t *incStep, uint8_t *decStep, mykonosGpioSelect_t *rx2GainIncPin, mykonosGpioSelect_t *rx2GainDecPin, uint8_t *enable);
mykonosGpioErr_t MYKONOS_setRxHybridGainChangePin(mykonosDevice_t *device, mykonosGpioSelect_t rx1GainChangePin, mykonosGpioSelect_t rx2GainChangePin);
mykonosGpioErr_t MYKONOS_getRxHybridGainChangePin(mykonosDevice_t *device, mykonosGpioSelect_t *rx1GainChangePin, mykonosGpioSelect_t *rx2GainChangePin);
mykonosGpioErr_t MYKONOS_setObsRxHybridGainChangePin(mykonosDevice_t *device, mykonosGpioSelect_t obsRxGainChangePin);
mykonosGpioErr_t MYKONOS_getObsRxHybridGainChangePin(mykonosDevice_t *device, mykonosGpioSelect_t *obsRxGainChangePin);
mykonosGpioErr_t MYKONOS_setRxAgcEnSyncPin(mykonosDevice_t *device, mykonosGpioSelect_t rx1AgcSyncPin, mykonosGpioSelect_t rx2AgcSyncPin);
mykonosGpioErr_t MYKONOS_getRxAgcEnSyncPin(mykonosDevice_t *device, mykonosGpioSelect_t *rx1AgcSyncPin, mykonosGpioSelect_t *rx2AgcSyncPin);
mykonosGpioErr_t MYKONOS_setObsRxAgcEnSyncPin(mykonosDevice_t *device, mykonosGpioSelect_t obsRxAgcSyncPin);
mykonosGpioErr_t MYKONOS_getObsRxAgcEnSyncPin(mykonosDevice_t *device, mykonosGpioSelect_t *obsRxAgcSyncPin);
/* TX GPIO Functions */
mykonosGpioErr_t MYKONOS_setTx1AttenCtrlPin(mykonosDevice_t *device, uint8_t stepSize, mykonosGpioSelect_t tx1AttenIncPin, mykonosGpioSelect_t tx1AttenDecPin, uint8_t enable, uint8_t useTx1ForTx2);
mykonosGpioErr_t MYKONOS_setTx2AttenCtrlPin(mykonosDevice_t *device, uint8_t stepSize, mykonosGpioSelect_t tx2AttenIncPin, mykonosGpioSelect_t tx2AttenDecPin, uint8_t enable);
mykonosGpioErr_t MYKONOS_getTx1AttenCtrlPin(mykonosDevice_t *device, uint8_t *stepSize, mykonosGpioSelect_t *tx1AttenIncPin, mykonosGpioSelect_t *tx1AttenDecPin, uint8_t *enable, uint8_t *useTx1ForTx2);
mykonosGpioErr_t MYKONOS_getTx2AttenCtrlPin(mykonosDevice_t *device, uint8_t *stepSize, mykonosGpioSelect_t *tx2AttenIncPin, mykonosGpioSelect_t *tx2AttenDecPin, uint8_t *enable, uint8_t *useTx1ForTx2);
mykonosGpioErr_t MYKONOS_spi2GpioSetup(mykonosDevice_t *device, uint8_t enable, uint8_t updateTxAttenPinSelect);
/* GPIO memory source Functions */
mykonosGpioErr_t MYKONOS_setGpioPinLevel(mykonosDevice_t *device, uint32_t gpioPinLevel);
mykonosGpioErr_t MYKONOS_getGpioPinLevel(mykonosDevice_t *device, uint32_t *gpioPinLevel);
mykonosGpioErr_t MYKONOS_getGpioSetLevel(mykonosDevice_t *device, uint32_t *gpioPinSetLevel);
/* Gain Compensation Functions */
mykonosGpioErr_t MYKONOS_setRxGainCompensation (mykonosDevice_t *device, mykonosGainComp_t *gainComp, uint8_t enable);
mykonosGpioErr_t MYKONOS_getRxGainCompensation (mykonosDevice_t *device, mykonosGainComp_t *gainComp, uint8_t *enabled);
mykonosGpioErr_t MYKONOS_setObsRxGainCompensation (mykonosDevice_t *device, mykonosObsRxGainComp_t *gainComp, uint8_t enable);
mykonosGpioErr_t MYKONOS_getObsRxGainCompensation (mykonosDevice_t *device, mykonosObsRxGainComp_t *gainComp, uint8_t *enabled);
/* SLICER Functions */
mykonosGpioErr_t MYKONOS_setRxSlicerCtrl(mykonosDevice_t *device, uint8_t slicerStep, mykonosRxSlicer_t rx1Pins, mykonosRxSlicer_t rx2Pins, uint8_t enable);
mykonosGpioErr_t MYKONOS_getRxSlicerCtrl(mykonosDevice_t *device, uint8_t *slicerStep, mykonosRxSlicer_t *rx1Pins, mykonosRxSlicer_t *rx2Pins, uint8_t *enable);
mykonosGpioErr_t MYKONOS_setObsRxSlicerCtrl(mykonosDevice_t *device, uint8_t slicerStep, mykonosObsRxSlicer_t obsRxPins, uint8_t enable);
mykonosGpioErr_t MYKONOS_getObsRxSlicerCtrl(mykonosDevice_t *device, uint8_t *slicerStep, mykonosObsRxSlicer_t *obsRxPins, uint8_t *enable);
/* Floating Point Formatter Functions */
mykonosGpioErr_t MYKONOS_setFloatPointFrmt (mykonosDevice_t *device, mykonosFloatPntFrmt_t *floatFrmt);
mykonosGpioErr_t MYKONOS_getFloatPointFrmt (mykonosDevice_t *device, mykonosFloatPntFrmt_t *floatFrmt);
mykonosGpioErr_t MYKONOS_setRxEnFloatPntFrmt (mykonosDevice_t *device, uint8_t rx1Att, uint8_t rx2Att, uint8_t enable);
mykonosGpioErr_t MYKONOS_getRxEnFloatPntFrmt (mykonosDevice_t *device, uint8_t *rx1Att, uint8_t *rx2Att, uint8_t *enable);
mykonosGpioErr_t MYKONOS_setOrxEnFloatPntFrmt (mykonosDevice_t *device, uint8_t orxAtt, uint8_t enable);
mykonosGpioErr_t MYKONOS_getOrxEnFloatPntFrmt (mykonosDevice_t *device, uint8_t *orxAtt, uint8_t *enable);
/*
*****************************************************************************
* General Purpose Interrupt functions
*****************************************************************************
*/
mykonosGpioErr_t MYKONOS_configGpInterrupt(mykonosDevice_t *device, uint16_t gpMask);
mykonosGpioErr_t MYKONOS_readGpInterruptStatus(mykonosDevice_t *device, uint16_t *status);
/*
*****************************************************************************
* ARM GPIO usage functions
*****************************************************************************
*/
mykonosGpioErr_t MYKONOS_setArmGpioPins(mykonosDevice_t *device);
/*
*****************************************************************************
* AuxADC/AuxDAC functions
*****************************************************************************
*/
mykonosGpioErr_t MYKONOS_setupAuxAdcs(mykonosDevice_t *device, uint8_t adcDecimation, uint8_t enable);
mykonosGpioErr_t MYKONOS_setAuxAdcChannel(mykonosDevice_t *device, mykonosAuxAdcChannels_t auxAdcChannel);
mykonosGpioErr_t MYKONOS_readAuxAdc(mykonosDevice_t *device, uint16_t *adcCode);
mykonosGpioErr_t MYKONOS_setupAuxDacs(mykonosDevice_t *device);
mykonosGpioErr_t MYKONOS_writeAuxDac(mykonosDevice_t *device, uint8_t auxDacIndex, uint16_t auxDacCode);
/*
*****************************************************************************
* GPIO3v3 functions
*****************************************************************************
*/
mykonosGpioErr_t MYKONOS_setupGpio3v3(mykonosDevice_t *device);
mykonosGpioErr_t MYKONOS_setGpio3v3PinLevel(mykonosDevice_t *device, uint16_t gpio3v3PinLevel);
mykonosGpioErr_t MYKONOS_getGpio3v3SetLevel(mykonosDevice_t *device, uint16_t *gpio3v3SetLevel);
mykonosGpioErr_t MYKONOS_getGpio3v3PinLevel(mykonosDevice_t *device, uint16_t *gpio3v3PinLevel);
mykonosGpioErr_t MYKONOS_setGpio3v3Oe(mykonosDevice_t *device, uint16_t gpio3v3OutEn);
mykonosGpioErr_t MYKONOS_getGpio3v3Oe(mykonosDevice_t *device, uint16_t *gpio3v3OutEn);
mykonosGpioErr_t MYKONOS_setGpio3v3SourceCtrl(mykonosDevice_t *device, uint16_t gpio3v3SrcCtrl);
mykonosGpioErr_t MYKONOS_getGpio3v3SourceCtrl(mykonosDevice_t *device, uint16_t *gpio3v3SrcCtrl);
/*
*****************************************************************************
* GPIO helper functions
*****************************************************************************
*/
mykonosGpioErr_t MYKONOS_setupGpio(mykonosDevice_t *device);
mykonosGpioErr_t MYKONOS_setGpioOe(mykonosDevice_t *device, uint32_t gpioOutEn, uint32_t gpioUsedMask);
mykonosGpioErr_t MYKONOS_getGpioOe(mykonosDevice_t *device, uint32_t *gpioOutEn);
mykonosGpioErr_t MYKONOS_setGpioSourceCtrl(mykonosDevice_t *device, uint32_t gpioSrcCtrl);
mykonosGpioErr_t MYKONOS_getGpioSourceCtrl(mykonosDevice_t *device, uint32_t *gpioSrcCtrl);
/*
*****************************************************************************
* Temperature Sensor functions
*****************************************************************************
*/
mykonosGpioErr_t MYKONOS_setupTempSensor(mykonosDevice_t *device, mykonosTempSensorConfig_t *tempSensor);
mykonosGpioErr_t MYKONOS_getTempSensorConfig(mykonosDevice_t *device, mykonosTempSensorConfig_t *tempSensor);
mykonosGpioErr_t MYKONOS_startTempMeasurement(mykonosDevice_t *device);
mykonosGpioErr_t MYKONOS_readTempSensor(mykonosDevice_t *device, mykonosTempSensorStatus_t *tempStatus);
const char* getGpioMykonosErrorMessage(mykonosGpioErr_t errorCode);
#ifdef __cplusplus
}
#endif
#endif /* MYKONOSGPIO_H_ */
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/mykonos/mykonos_macros.h
+707
View File
@@ -0,0 +1,707 @@
/**
* \file mykonos_macros.h
* \brief Contains address and miscellaneous macro definitions for Mykonos API
*
* Mykonos API version: 1.5.2.3566
*/
/**
* \page Disclaimer Legal Disclaimer
* Copyright 2015-2017 Analog Devices Inc.
* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
*
*/
#ifndef CLEMENTE_TDD_MACROS_H
#define CLEMENTE_TDD_MACROS_H
#ifdef __cplusplus
extern "C" {
#endif
#define MYKONOS_ADDR_CONFIGURATION_CONTROL_0 0x000
#define MYKONOS_ADDR_SPI_CONFIGURATION_CONTROL_1 0x001
#define MYKONOS_ADDR_PRODUCT_ID 0x004
#define MYKONOS_GPIO_DRV_CTL_0 0x020
#define MYKONOS_GPIO_DRV_CTL_1 0x021
#define MYKONOS_GPIO_SLEW_CTL_0 0x022
#define MYKONOS_GPIO_SLEW_CTL_1 0x023
#define MYKONOS_GPIO_SLEW_CTL_2 0x024
#define MYKONOS_GPIO_SLEW_CTL_3 0x025
#define MYKONOS_ADDR_DIGITAL_IO_CONTROL 0x028
#define MYKONOS_ADDR_SYSREF_PAD_CONFIG 0x040
#define MYKONOS_ADDR_TX1_SYNC_PAD_CONFIG 0x041
#define MYKONOS_ADDR_TX2_SYNC_PAD_CONFIG 0x042
#define MYKONOS_ADDR_RX1_SYNC_CONFIG 0x043
#define MYKONOS_ADDR_RX2_SYNC_CONFIG 0x044
/* Mykonos Framer Registers */
#define MYKONOS_ADDR_FRAMER_RESET 0x059
#define MYKONOS_ADDR_FRAMER_CLK_EN 0x05A
#define MYKONOS_ADDR_FRAMER_ADDR 0x05B
#define MYKONOS_ADDR_FRAMER_DATA 0x05C
#define MYKONOS_ADDR_FRAMER_WRITE_EN 0x05D
#define MYKONOS_ADDR_FRAMER_SYSREF_FIFO_EN 0x05E
#define MYKONOS_ADDR_FRAMER_CONFIG_F 0x05F
#define MYKONOS_ADDR_FRAMER_LANE_CTL 0x060
#define MYKONOS_ADDR_FRAMER_ADC_XBAR_SEL 0x061
#define MYKONOS_ADDR_FRAMER_LANE_XBAR_SEL 0x062
#define MYKONOS_ADDR_FRAMER_CONFIG_LOOPBACK_XBAR_REV 0x063
#define MYKONOS_ADDR_FRAMER_SYNCN_FILT 0x064
#define MYKONOS_ADDR_FRAMER_LMFC_F_OFFSET 0x065
#define MYKONOS_ADDR_FRAMER_LMFC_K_OFFSET 0x066
#define MYKONOS_ADDR_FRAMER_TEST_CNTR_CTL 0x067
#define MYKONOS_ADDR_FRAMER_STATUS_STRB 0x068
#define MYKONOS_ADDR_FRAMER_STATUS 0x069
#define MYKONOS_ADDR_FRAMER_SYSREF_TO_LMFC_CNTR_STAT 0x06A
#define MYKONOS_ADDR_FRAMER_SYSREF_TO_LMFC_ERR_MARGIN 0x06B
#define MYKONOS_ADDR_FRAMER_LANE_FIFO_STRB 0x06C
#define MYKONOS_ADDR_FRAMER_LANE0_FIFO_RDWR_ADDR 0x06D
#define MYKONOS_ADDR_FRAMER_LANE1_FIFO_RDWR_ADDR 0x06E
#define MYKONOS_ADDR_FRAMER_LANE2_FIFO_RDWR_ADDR 0x06F
#define MYKONOS_ADDR_FRAMER_LANE3_FIFO_RDWR_ADDR 0x070
#define MYKONOS_ADDR_FRAMER_PRBS10_CTL 0x071
#define MYKONOS_ADDR_FRAMER_PRBS20_CTL 0x072
#define MYKONOS_ADDR_FRAMER_PATTERN_GEN_EN 0x073
#define MYKONOS_ADDR_FRAMER_PATTERN_GEN_7_TO_0 0x074
#define MYKONOS_ADDR_FRAMER_PATTERN_GEN_15_TO_8 0x075
#define MYKONOS_ADDR_FRAMER_PATTERN_GEN_19_TO_16 0x076
#define MYKONOS_ADDR_FRAMER_CONFIG_JTX_GEN 0x077
#define MYKONOS_ADDR_FRAMER_LANE_DATA_CTL 0x078
#define MYKONOS_ADDR_FRAMER_DATA_SAMPLE_CTL 0x079
/* Mykonos Deframer Sub Address Map */
#define MYKONOS_SUBADDR_DEFRAMER_LANE0_ILAS_RECVD 0x00
#define MYKONOS_SUBADDR_DEFRAMER_LANE0_ILAS_CFG 0x50
/* Mykonos Deframer Registers */
#define MYKONOS_ADDR_DEFRAMER_RESET 0x07A
#define MYKONOS_ADDR_DEFRAMER_CLK_EN 0x07B
#define MYKONOS_ADDR_DEFRAMER_ADDR 0x07C
#define MYKONOS_ADDR_DEFRAMER_DATA 0x07D
#define MYKONOS_ADDR_DEFRAMER_WR_EN 0x07E
#define MYKONOS_ADDR_DEFRAMER_SYSREF_FIFO_EN 0x07F
#define MYKONOS_ADDR_DEFRAMER_CONFIG_F 0x080
#define MYKONOS_ADDR_DEFRAMER_LANE_FIFO_CTL 0x081
#define MYKONOS_ADDR_DEFRAMER_DAC_XBAR_SEL 0x082
#define MYKONOS_ADDR_DEFRAMER_LANE_XBAR_SEL 0x083
#define MYKONOS_ADDR_DEFRAMER_LMFC_F_OFFSET 0x084
#define MYKONOS_ADDR_DEFRAMER_LMFC_K_OFFSET 0x085
#define MYKONOS_ADDR_DEFRAMER_CONFIG_SYNC_USER_DATA_CTL 0x086
#define MYKONOS_ADDR_DEFRAMER_SYNC_REQ_RETIME 0x087
#define MYKONOS_ADDR_DEFRAMER_TEST 0x088
#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_WR_STRT_DAC_XBAR_REV 0x089
#define MYKONOS_ADDR_DEFRAMER_STAT_STRB 0x08A
#define MYKONOS_ADDR_DEFRAMER_STAT 0x08B
#define MYKONOS_ADDR_DEFRAMER_TEST_ERR_CNT_STAT 0x08C
#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_RD_ADDR 0x08D
#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_WR_ADDR 0x08E
#define MYKONOS_ADDR_DEFRAMER_QBLMFC_VS_EXTLMFC_CNTR_STAT 0x08F
#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_STAT 0x090
#define MYKONOS_ADDR_DEFRAMER_STRT_RD_DEL_STOP_WR 0x091
#define MYKONOS_ADDR_DEFRAMER_FIFO_SAMPLE_SPI_ADDR_RD 0x092
#define MYKONOS_ADDR_DEFRAMER_FIFO_BYTE_SPI_ADDR_RD 0x093
#define MYKONOS_ADDR_DEFRAMER_FIFO_BYTE_SPI_DATA_RD 0x094
#define MYKONOS_ADDR_DEFRAMER_SAMPLE0_7_TO_0 0x095
#define MYKONOS_ADDR_DEFRAMER_SAMPLE0_15_TO_8 0x096
#define MYKONOS_ADDR_DEFRAMER_SAMPLE1_7_TO_0 0x097
#define MYKONOS_ADDR_DEFRAMER_SAMPLE1_15_TO_8 0x098
#define MYKONOS_ADDR_DEFRAMER_SAMPLE2_7_TO_0 0x099
#define MYKONOS_ADDR_DEFRAMER_SAMPLE2_15_TO_8 0x09A
#define MYKONOS_ADDR_DEFRAMER_SAMPLE3_7_TO_0 0x09B
#define MYKONOS_ADDR_DEFRAMER_SAMPLE3_15_TO_8 0x09C
#define MYKONOS_ADDR_DEFRAMER_LANE_FIFO_STRB 0x09D
#define MYKONOS_ADDR_DEFRAMER_LANE0_FIFO_RDWR_ADDR 0x09E
#define MYKONOS_ADDR_DEFRAMER_LANE1_FIFO_RDWR_ADDR 0x09F
#define MYKONOS_ADDR_DEFRAMER_LANE2_FIFO_RDWR_ADDR 0x0A0
#define MYKONOS_ADDR_DEFRAMER_LANE3_FIFO_RDWR_ADDR 0x0A1
#define MYKONOS_ADDR_DEFRAMER_SYSREF_TO_LMFC_CNTR_STAT 0x0A2
#define MYKONOS_ADDR_DEFRAMER_SYSREF_TO_LMFC_ERR_MARGIN 0x0A3
#define MYKONOS_ADDR_DEFRAMER_PRBS10_CTL 0x0A4
#define MYKONOS_ADDR_DEFRAMER_PRBS20_CTL 0x0A5
#define MYKONOS_ADDR_DEFRAMER_PRBS20_STRB_CHKSUM_TYPE 0x0A6
#define MYKONOS_ADDR_DEFRAMER_PRBS20_ERR_CNTR_7_TO_0 0x0A7
#define MYKONOS_ADDR_DEFRAMER_PRBS20_ERR_CNTR_15_TO_8 0x0A8
#define MYKONOS_ADDR_DEFRAMER_PRBS20_ERR_CNTR_23_TO_16 0x0A9
#define MYKONOS_ADDR_DEFRAMER_LANE_DATA_CTL 0x0AA
#define MYKONOS_ADDR_DEFRAMER_STATUS_2 0x0AB
#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_PHASE 0x0AC
/* Mykonos Serializer Registers */
#define MYKONOS_ADDR_SERIALIZER_CTL_0 0x0B0
#define MYKONOS_ADDR_SERIALIZER_CTL_1 0x0B1
#define MYKONOS_ADDR_SERIALIZER_CTL_2 0x0B2
#define MYKONOS_ADDR_SERIALIZER_CTL_3 0x0B3
#define MYKONOS_ADDR_SERIALIZER_HS_DIV_TXSER_CLK_EN 0x0B4
#define MYKONOS_ADDR_SERIALIZER_SPECIAL 0x0B5
/* Mykonos Deserializer Registers */
#define MYKONOS_ADDR_DESERIALIZER_PDET_CTL 0x0BC
#define MYKONOS_ADDR_DESERIALIZER_CTL_0 0x0BD
#define MYKONOS_ADDR_DESERIALIZER_SIN_SHAPE_0 0x0BE
#define MYKONOS_ADDR_DESERIALIZER_SIN_SHAPE_1 0x0BF
#define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_0 0x0C1
#define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_1 0x0C2
#define MYKONOS_ADDR_DESERIALIZER_MISC_CTL 0x0C3
#define MYKONOS_ADDR_DESERIALIZER_EQ_HP_EN 0x0C4
#define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_1_TO_0 0x0C5
#define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_3_TO_2 0x0C6
#define MYKONOS_ADDR_DESERIALIZER_HS_DIV_RXCDR_CLK_EN 0x0CD
#define MYKONOS_ADDR_DESERIALIZER_SPECIAL 0x0CE
#define MYKONOS_ADDR_DESERIALIZER_CDR_CAL_CTL 0x0D0
#define MYKONOS_ADDR_CONFIGURATION_CONTROL_1 0x100
#define MYKONOS_ADDR_CONFIGURATION_CONTROL_2 0x101
#define MYKONOS_ADDR_CONFIGURATION_CONTROL_4 0x102
#define MYKONOS_ADDR_CONFIGURATION_CONTROL_5 0x103
#define MYKONOS_ADDR_DPD_SNIFFER_CONFIGURATION_CONTROL_1 0x104
#define MYKONOS_ADDR_DPD_SNIFFER_CONFIGURATION_CONTROL_2 0x105
#define MYKONOS_ADDR_DPD_SNIFFER_GPIO_SELECT 0x106
#define MYKONOS_ADDR_SNIFFER_CONFIGURATION_CONTROL 0x107
#define MYKONOS_ADDR_DPD_CONFIGURATION_CONTROL 0x108
#define MYKONOS_ADDR_LOOPBACK_CONFIGURATION_CONTROL 0x109
#define MYKONOS_ADDR_CLOCK_CONTROL_0 0x117
#define MYKONOS_ADDR_CLOCK_CONTROL_1 0x118
#define MYKONOS_ADDR_CLOCK_CONTROL_2 0x119
#define MYKONOS_ADDR_CLOCK_CONTROL_3 0x11A
#define MYKONOS_ADDR_CLOCK_CONTROL_4 0x11B
#define MYKONOS_ADDR_CLOCK_CONTROL_5 0x11C
#define MYKONOS_ADDR_MCS_CONTROL 0x120
#define MYKONOS_ADDR_MCS_STATUS 0x121
/* CLK PLL Registers */
#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_INT_BYTE0 0x141
#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_INT_BYTE1 0x142
#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE0 0x143
#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE1 0x144
#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE2 0x145
#define MYKONOS_ADDR_CLK_SYNTH_F_VCOTN_BYTE1 0x148
#define MYKONOS_ADDR_CLK_SYNTH_BYTE1 0x149
#define MYKONOS_ADDR_CLK_SYNTH_BYTE2 0x14A
#define MYKONOS_ADDR_CLK_SYNTH_BYTE3 0x14B
#define MYKONOS_ADDR_CLK_SYNTH_BYTE5 0x14D
#define MYKONOS_ADDR_CLK_SYNTH_BYTE6 0x14E
#define MYKONOS_ADDR_CLK_SYNTH_BYTE7 0x14F
#define MYKONOS_ADDR_CLK_SYNTH_LF_R3 0x150
#define MYKONOS_ADDR_CLK_SYNTH_BYTE9 0x152
#define MYKONOS_ADDR_CLK_SYNTH_CAL_STAT 0x154
#define MYKONOS_ADDR_CLK_SYNTH_VCO_CAL_REF 0x155
#define MYKONOS_ADDR_CLK_SYNTH_VCO_BAND_BYTE1 0x157
#define MYKONOS_ADDR_CLK_SYNTH_CAL_CONTROL 0x159
#define MYKONOS_ADDR_CLK_SYNTH_VCO_VAR_CTL1 0x15E
#define MYKONOS_ADDR_CLK_SYNTH_VCO_VAR_CTL2 0x15F
/* DPD Registers */
#define MYKONOS_ADDR_TX1_DPD_MODEL_INDIRECT_PTR 0x178
#define MYKONOS_ADDR_TX2_DPD_MODEL_INDIRECT_PTR 0x17C
#define MYKONOS_ADDR_DPD_RMS_BUF_SIZE 0x180
#define MYKONOS_ADDR_TX1_DPD_MODEL_WORKING_PTR 0x188
#define MYKONOS_ADDR_TX2_DPD_MODEL_WORKING_PTR 0x18C
/* Rx NCO Control registers */
#define MYKONOS_ADDR_CALPLL_SDM_CONTROL 0x17F
#define MYKONOS_ADDR_RX_NCO_CONTROL 0x190
#define MYKONOS_ADDR_RX_NCO_CH1_FTW_BYTE_3 0x191
#define MYKONOS_ADDR_RX_NCO_CH1_FTW_BYTE_2 0x192
#define MYKONOS_ADDR_RX_NCO_CH1_FTW_BYTE_1 0x193
#define MYKONOS_ADDR_RX_NCO_CH2_FTW_BYTE_3 0x194
#define MYKONOS_ADDR_RX_NCO_CH2_FTW_BYTE_2 0x195
#define MYKONOS_ADDR_RX_NCO_CH2_FTW_BYTE_1 0x196
#define MYKONOS_ADDR_RX_NCO_DPD_SNIFFER_FTW_BYTE_3 0x197
#define MYKONOS_ADDR_RX_NCO_DPD_SNIFFER_FTW_BYTE_2 0x198
#define MYKONOS_ADDR_RX_NCO_DPD_SNIFFER_FTW_BYTE_1 0x199
#define MYKONOS_ADDR_ENSM_CONFIG_7_0 0x1B0
#define MYKONOS_ADDR_CALIBRATION_CONTROL 0x1B2
#define MYKONOS_ADDR_ENSM_MANUAL_GAIN_LOCK_GPIO_SELECT 0x1B5
#define MYKONOS_ADDR_REFERENCE_CLOCK_CYCLES 0x1C0
#define MYKONOS_ADDR_TX_PD_OVERIDE_7_0 0x209
#define MYKONOS_ADDR_RCAL_CONTROL 0x224
#define MYKONOS_ADDR_REF_PAD_CONFIG1 0x230
#define MYKONOS_ADDR_REF_PAD_CONFIG2 0x231
#define MYKONOS_ADDR_RXSYNTH_CP_CAL_STAT 0x254
#define MYKONOS_ADDR_RXSYNTH_VCO_BAND_BYTE1 0x257
#define MYKONOS_ADDR_TXSYNTH_CP_CAL_STAT 0x2C4
#define MYKONOS_ADDR_TXSYNTH_VCO_BAND_BYTE1 0x2C7
#define MYKONOS_ADDR_SNIFF_RXSYNTH_CP_CAL_STAT 0x354
#define MYKONOS_ADDR_SNIFF_RXSYNTH_VCO_BAND_BYTE1 0x357
#define MYKONOS_ADDR_SNIFF_RXLOGEN_BYTE1 0x380
#define MYKONOS_ADDR_RX_FILTER_CONFIGURATION 0x410
#define MYKONOS_ADDR_RX_FILTER_GAIN 0x411
#define MYKONOS_ADDR_DPD_SNIFFER_RX_FILTER_GAIN 0x412
/* Mykonos Temperature Gain Compensation Registers */
#define MYKONOS_ADDR_RX1_TEMP_GAIN_COMP 0x420
#define MYKONOS_ADDR_RX2_TEMP_GAIN_COMP 0x421
#define MYKONOS_ADDR_OBS_TEMP_GAIN_COMP 0x422
/* Mykonos AGC General Registers */
#define MYKONOS_ADDR_AGC_CFG_1 0x42E
#define MYKONOS_ADDR_AGC_CFG_2 0x42F
#define MYKONOS_ADDR_AGC_GAIN_CHANGE_GPIO_SEL 0x430
#define MYKONOS_ADDR_AGC_RX1_MAX_GAIN_INDEX 0x431
#define MYKONOS_ADDR_AGC_RX1_MIN_GAIN_INDEX 0x432
#define MYKONOS_ADDR_AGC_MANUAL_GAIN_CFG 0x433
#define MYKONOS_ADDR_AGC_MANUAL_GAIN_GPIO_SEL 0x434
#define MYKONOS_ADDR_AGC_MANUAL_GAIN_INDEX_CH_1 0x435
#define MYKONOS_ADDR_AGC_MANUAL_GAIN_INDEX_CH_2 0x436
#define MYKONOS_ADDR_AGC_LOCK_LEVEL 0x437
#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_1 0x438
#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_2 0x439
#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_3 0x43A
#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_4 0x43B
#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_5 0x43C
#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_6 0x43D
#define MYKONOS_ADDR_AGC_RX1_GAIN_LOCK_DELAY 0x43E
#define MYKONOS_ADDR_AGC_RX2_GAIN_LOCK_DELAY 0x43F
#define MYKONOS_ADDR_AGC_RX1_ATTACK_DELAY 0x440
#define MYKONOS_ADDR_AGC_RX2_ATTACK_DELAY 0x441
#define MYKONOS_ADDR_AGC_ULB_THRSH 0x442
#define MYKONOS_ADDR_AGC_LLB_THRSH 0x443
#define MYKONOS_ADDR_AGC_RX_BLOCK_DET_DECAY 0x444
#define MYKONOS_ADDR_AGC_RESET_PD_HIGH_CNT 0x445
#define MYKONOS_ADDR_AGC_RX2_MAX_GAIN_INDEX 0x446
#define MYKONOS_ADDR_AGC_RX2_MIN_GAIN_INDEX 0x447
#define MYKONOS_ADDR_AGC_ORX_SNRX_CFG_1 0x448
#define MYKONOS_ADDR_AGC_ORX_SNRX_CFG_2 0x449
#define MYKONOS_ADDR_AGC_ORX_SNRX_MAX_GAIN_INDEX 0x44A
#define MYKONOS_ADDR_AGC_ORX_SNRX_MIN_GAIN_INDEX 0x44B
#define MYKONOS_ADDR_AGC_ORX_SNRX_MANUAL_GAIN_CFG 0x44C
#define MYKONOS_ADDR_AGC_ORX_SNRX_GPIO_SEL 0x44D
#define MYKONOS_ADDR_AGC_ORX_SNRX_LOCK_LEVEL 0x44E
#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_1 0x44F
#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_2 0x450
#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_3 0x451
#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_4 0x452
#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_5 0x453
#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_6 0x454
#define MYKONOS_ADDR_AGC_ORX_SNRX_GAIN_LOCK_DELAY 0x455
#define MYKONOS_ADDR_AGC_ORX_SNRX_ATTACK_DELAY 0x456
#define MYKONOS_ADDR_AGC_ORX_SNRX_ULB_THRSH 0x457
#define MYKONOS_ADDR_AGC_ORX_SNRX_LLB_THRSH 0x458
#define MYKONOS_ADDR_AGC_ORX_SNRX_BLOCK_DET_DECAY 0x459
#define MYKONOS_ADDR_AGC_ORX_SNRX_RESET_PD_HIGH_CNT 0x45A
#define MYKONOS_ADDR_AGC_ORX1_MANUAL_GAIN_INDEX 0x45B
#define MYKONOS_ADDR_AGC_ORX2_MANUAL_GAIN_INDEX 0x45C
#define MYKONOS_ADDR_AGC_SNRX_MANUAL_GAIN_INDEX 0x45D
#define MYKONOS_ADDR_AGC_LOOPBACK1_MANUAL_GAIN_INDEX 0x45E
#define MYKONOS_ADDR_AGC_LOOPBACK2_MANUAL_GAIN_INDEX 0x45F
#define MYKONOS_ADDR_AGC_ORX_SNRX_ACTIVE 0x460
/* Mykonos Fast Attack AGC Registers */
#define MYKONOS_ADDR_AGC_FAST_CFG_1 0x468
#define MYKONOS_ADDR_AGC_FAST_CFG_2 0x469
#define MYKONOS_ADDR_AGC_FAST_ENRGY_LOST_THRSH 0x46A
#define MYKONOS_ADDR_AGC_FAST_STRONG_SIG_THRSH 0x46B
#define MYKONOS_ADDR_AGC_FAST_SETTING_DELAY 0x46C
#define MYKONOS_ADDR_AGC_FAST_OPT_MAX_GAIN 0x46D
#define MYKONOS_ADDR_AGC_FAST_ENRGY_DET_CNT 0x46E
#define MYKONOS_ADDR_AGC_FAST_AGCLL_UPPER_LIMIT 0x46F
#define MYKONOS_ADDR_AGC_FAST_GAIN_LOCK_EXIT_CNT 0x470
#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_CFG_1 0x471
#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_CFG_2 0x472
#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_ENRGY_LOST_THRSH 0x473
#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_STRONG_SIG_THRSH 0x474
#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_SET_DELAY 0x475
#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_OPT_MAX_GAIN 0x476
#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_ENRGY_DET_CNT 0x477
#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_AGCLL_UPPER_LIMIT 0x478
#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_GAIN_LOCK_EXIT_CNT 0x479
/* Mykonos Slow Loop - Hybrid AGC Registers */
#define MYKONOS_ADDR_AGC_SLOW_LOCK_LEV_THRSH 0x480
#define MYKONOS_ADDR_AGC_SLOW_ULB_CNT_THRSH 0x481
#define MYKONOS_ADDR_AGC_SLOW_LLB_CNT_THRSH 0x482
#define MYKONOS_ADDR_AGC_SLOW_HIGH_OVRG_CNT_THRSH 0x483
#define MYKONOS_ADDR_AGC_SLOW_LOW_OVRG_CNT_THRSH 0x484
#define MYKONOS_ADDR_AGC_SLOW_VERYLOW_OVRG_CNT_THRSH 0x485
#define MYKONOS_ADDR_AGC_SLOW_DIG_SAT_CNT_THRSH 0x486
#define MYKONOS_ADDR_AGC_SLOW_UPPER0_THRSH_GAIN_STEP 0x487
#define MYKONOS_ADDR_AGC_SLOW_LOWER0_THRSH_GAIN_STEP 0x488
#define MYKONOS_ADDR_AGC_SLOW_UPPER1_THRSH_GAIN_STEP 0x489
#define MYKONOS_ADDR_AGC_SLOW_LOWER1_THRSH_GAIN_STEP 0x48A
#define MYKONOS_ADDR_AGC_SLOW_GAIN_UPDATE_CNT_1 0x48B
#define MYKONOS_ADDR_AGC_SLOW_GAIN_UPDATE_CNT_2 0x48C
#define MYKONOS_ADDR_AGC_SLOW_GAIN_UPDATE_CNT_3 0x48D
#define MYKONOS_ADDR_AGC_SLOW_LOOP_CFG 0x48E
#define MYKONOS_ADDR_AGC_SLOW_POWER_THRSH 0x48F
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOCK_LEV_THRSH 0x490
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ULB_CNT_THRSH 0x491
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LLB_CNT_THRSH 0x492
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ADC_HIGH_OVRG_CNT_THRSH 0x493
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ADC_LOW_OVRG_CNT_THRSH 0x494
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ADC_VERYLOW_OVRG_CNT_THRSH 0x495
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_DIG_SAT_CNT_THRSH 0x496
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UPPER0_THRSH_GAIN_STEP 0x497
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOWER0_THRSH_GAIN_STEP 0x498
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UPPER1_THRSH_GAIN_STEP 0x499
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOWER1_THRSH_GAIN_STEP 0x49A
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_GAIN_UPDATE_CTR_1 0x49B
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_GAIN_UPDATE_CTR_2 0x49C
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_GAIN_UPDATE_CTR_3 0x49D
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOOP_CFG 0x49E
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_POWER_THRSH 0x49F
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DEL_1 0x4A0
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DEL_2 0x4A1
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DUR_1 0x4A2
#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DUR_2 0x4A3
/* Mykonos Gain Control Read Registers */
#define MYKONOS_ADDR_GAIN_CTL_CHANNEL_1 0x4B0
#define MYKONOS_ADDR_GAIN_CTL_FAST_ATTK_STATE 0x4B1
#define MYKONOS_ADDR_GAIN_CTL_SLOW_LOOP_STATE 0x4B2
#define MYKONOS_ADDR_GAIN_CTL_CHANNEL_2 0x4B3
#define MYKONOS_ADDR_GAIN_CTL_OVRG_SIGS_CHANNEL_1 0x4B4
#define MYKONOS_ADDR_GAIN_CTL_OVRG_SIGS_CHANNEL_2 0x4B5
#define MYKONOS_ADDR_GAIN_CTL_ORX_SNRX_GAIN 0x4B6
#define MYKONOS_ADDR_GAIN_CTL_ORX_SNRX_LOOP_STATE 0x4B7
#define MYKONOS_ADDR_GAIN_CTL_ORX_SNRX_OVRG_SIGS 0x4B8
/* Mykonos Rx Data Path Overrange Registers */
#define MYKONOS_ADDR_RX_OVRG_DATAPATH_OVRFLW 0x4B9
#define MYKONOS_ADDR_RX_OVRG_ORX_SNRX_DATAPATH_OVRFLW 0x4BA
/* Mykonos RSSI Measurement Registers and Dec Power Measurement Registers*/
#define MYKONOS_ADDR_RSSI_MEAS_DURATION_0_1 0x4C0
#define MYKONOS_ADDR_RSSI_MEAS_DURATION_2_3 0x4C1
#define MYKONOS_ADDR_RSSI_CFG 0x4C6
#define MYKONOS_DEC_POWER_CONFIG_1 0x4C7
#define MYKONOS_DEC_POWER_CONFIG_2 0x4C8
#define MYKONOS_ADDR_DPD_SNF_RSSI_CFG 0x4CF
#define MYKONOS_ADDR_DPD_RSSI_CFG 0x4D6
#define MYKONOS_SNIFFER_DEC_POWER_CONFIG_1 0x4D7
#define MYKONOS_SNIFFER_DEC_POWER_CONFIG_2 0x4D8
#define MYKONOS_CH1_DECIMATED_PWR 0x4DE
#define MYKONOS_CH2_DECIMATED_PWR 0x4DF
#define MYKONOS_SNIFFER_DECIMATED_PWR 0x4E6
#define MYKONOS_ADDR_DIGITAL_GAIN_CONFIG 0x4F0
#define MYKONOS_ADDR_DPD_SNIFFER_DIGITAL_GAIN_CONFIG 0x4F1
#define MYKONOS_ADDR_GAIN_TABLE_ADDR 0x500
#define MYKONOS_ADDR_GAIN_TABLE_RX1_FE_GAIN 0x501
#define MYKONOS_ADDR_GAIN_TABLE_RX1_EXT_CTL 0x502
#define MYKONOS_ADDR_GAIN_TABLE_RX1_DIG_GAIN 0x503
#define MYKONOS_ADDR_GAIN_TABLE_RX2_FE_GAIN 0x504
#define MYKONOS_ADDR_GAIN_TABLE_RX2_EXT_CTL 0x505
#define MYKONOS_ADDR_GAIN_TABLE_RX2_DIG_GAIN 0x506
#define MYKONOS_ADDR_GAIN_TABLE_RX3_FE_GAIN 0x507
#define MYKONOS_ADDR_GAIN_TABLE_RX3_LNA_ENAB 0x508
#define MYKONOS_ADDR_GAIN_TABLE_RX3_DIG_GAIN 0x509
#define MYKONOS_ADDR_GAIN_TABLE_CONFIGURATION 0x516
#define MYKONOS_ADDR_CH3_GAIN_TABLE_CONFIGURATION 0x517
#define MYKONOS_ADDR_RXFE1_LOCM 0x520
#define MYKONOS_ADDR_RXFE2_LOCM 0x521
#define MYKONOS_ADDR_RXLOOPBACK1_CNTRL_1 0x540
#define MYKONOS_ADDR_RXLOOPBACK2_CNTRL_1 0x541
#define MYKONOS_ADDR_RX_LOOPBACK1_CNTRL_4 0x546
#define MYKONOS_ADDR_RX_LOOPBACK2_CNTRL_4 0x547
/* Mykonos Overload/Peak Detection Registers */
#define MYKONOS_ADDR_OVRLD_ADC_OVRLD_CFG 0x580
#define MYKONOS_ADDR_OVRLD_ADC_OVRLD_UPPER_THRSH 0x581
#define MYKONOS_ADDR_OVRLD_ADC_OVRLD_LOWER_THRSH 0x582
#define MYKONOS_ADDR_OVRLD_PD_DEC_OVRLD_CFG 0x583
#define MYKONOS_ADDR_OVRLD_PD_DEC_OVRLD_UPPER_THRSH 0x584
#define MYKONOS_ADDR_OVRLD_PD_DEC_OVRLD_LOWER_THRSH 0x585
#define MYKONOS_ADDR_OVRLD_PD_DEC_VERYLOW_THRSH 0x586
#define MYKONOS_ADDR_ORX_SNRX_OVRLD_ADC_OVRLD_CFG 0x587
#define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_CFG 0x58A
#define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_UPPER_THRSH 0x58B
#define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_LOWER_THRSH 0x58C
#define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_VERYLOW_THRSH 0x58D
#define MYKONOS_ADDR_RX_ADC_FLASH_DELAY 0x5B6
#define MYKONOS_ADDR_RX_ADC_FLASH_CTRL 0x5B7
#define MYKONOS_ADDR_RX_ADC1_PRFL 0x5DD
#define MYKONOS_ADDR_RX_ADC2_PRFL 0x5DE
#define MYKONOS_ADDR_ORX_ADC_PRFL 0x5DF
#define MYKONOS_ADDR_RFDC_MEASURE_COUNT_1 0x631
#define MYKONOS_ADDR_RFDC_MEASURE_COUNT_2 0x632
#define MYKONOS_ADDR_RFDC_PROGRAM_SHIFT 0x635
#define MYKONOS_ADDR_RFDC_CONFIG2 0x636
#define MYKONOS_DPD_Sniffer_RFDC_CAL_TRACK_EN 0x642
#define MYKONOS_ADDR_RFDC_SNF_MEASURE_COUNT_1 0x644
#define MYKONOS_ADDR_RFDC_SNF_MEASURE_COUNT_2 0x645
#define MYKONOS_ADDR_RFDC_ORX_MEASURE_COUNT_1 0x650
#define MYKONOS_ADDR_RFDC_ORX_MEASURE_COUNT_2 0x651
#define MYKONOS_ADDR_DIGITAL_DC_MIN_CAL_IDX 0x63A
#define MYKONOS_ADDR_DIGITAL_DC_OFFSET_SHIFT 0x674
#define MYKONOS_ADDR_DIGITAL_DC_OFFSET_CONFIG 0x676
#define MYKONOS_DIGITAL_DC_OFFSET_CH3_TRACKING 0x67A
#define MYKONOS_ADDR_DIGITAL_DC_OFFSET_SNF 0x67C
#define MYKONOS_ADDR_DIGITAL_DC_OFFSET_CH3_DPD_M_SHIFT 0x67D
#define MYKONOS_ADDR_RX_GAIN_COMP_DELAY 0x710
#define MYKONOS_ADDR_RX1_GAIN_COMP_OFFSET 0x711
#define MYKONOS_ADDR_RX2_GAIN_COMP_OFFSET 0x712
#define MYKONOS_ADDR_RX_GAIN_COMP_CFG 0x713
#define MYKONOS_ADDR_RX_SLCR_PIN_CFG 0x714
#define MYKONOS_ADDR_DPD_SNF_RX_GAIN_COMP_DELAY 0x715
#define MYKONOS_ADDR_DPD_SNF_RX_GAIN_COMP_OFFSET 0x716
#define MYKONOS_ADDR_DPD_SNF_RX_GAIN_COMP_CFG 0x717
#define MYKONOS_ADDR_DPD_SNF_RX_SLCR_PIN_CFG 0x718
#define MYKONOS_ADDR_FLOATING_POINT_CFG 0x750
#define MYKONOS_ADDR_FLOATING_POINT_RX_CTRL 0x751
#define MYKONOS_ADDR_FLOATING_POINT_ORX_CTRL 0x752
#define MYKONOS_ADDR_SNRX_LNA_BIAS_C 0x81B
#define MYKONOS_ADDR_ORX_ADC_FLASH_DELAY 0x846
#define MYKONOS_ADDR_ORX_ADC_FLASH_CTRL 0x847
#define MYKONOS_ADDR_TX_FILTER_CONFIGURATION 0x910
#define MYKONOS_ADDR_TX1_ATTENUATION_0_READBACK 0x940
#define MYKONOS_ADDR_TX1_ATTENUATION_1_READBACK 0x941
#define MYKONOS_ADDR_TX2_ATTENUATION_0_READBACK 0x942
#define MYKONOS_ADDR_TX2_ATTENUATION_1_READBACK 0x943
#define MYKONOS_ADDR_TX_FILTER_OVERFLOW 0x950
/* Mykonos PA Protection Block Registers */
#define MYKONOS_ADDR_PA_PROTECTION_CONFIGURATION 0x955
#define MYKONOS_ADDR_PA_PROTECTION_ATTEN_CONTROL 0x956
#define MYKONOS_ADDR_PA_PROTECTION_THRESHOLD_LSB 0x957
#define MYKONOS_ADDR_PA_PROTECTION_THRESHOLD_MSB 0x958
#define MYKONOS_ADDR_PA_PROTECTION_POWER_READBACK_LSB 0x959
#define MYKONOS_ADDR_PA_PROTECTION_POWER_READBACK_MSB 0x95A
#define MYKONOS_ADDR_TX1_ATTENUATION_0 0x960
#define MYKONOS_ADDR_TX1_ATTENUATION_1 0x961
#define MYKONOS_ADDR_TX2_ATTENUATION_0 0x962
#define MYKONOS_ADDR_TX2_ATTENUATION_1 0x963
#define MYKONOS_ADDR_TX1_GAIN_0 0x967
#define MYKONOS_ADDR_TX1_GAIN_1 0x968
#define MYKONOS_ADDR_TX1_GAIN_2 0x969
#define MYKONOS_ADDR_TX2_GAIN_0 0x96A
#define MYKONOS_ADDR_TX2_GAIN_1 0x96B
#define MYKONOS_ADDR_TX2_GAIN_2 0x96C
#define MYKONOS_ADDR_TX_INCR_DECR_WORD 0x96D
#define MYKONOS_ADDR_TX_TPC_CONFIG 0x96E
#define MYKONOS_ADDR_TX_TPC_GPIO_CFG 0x96F
#define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_I_MSB 0x9CB
#define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_I_LSB 0x9CC
#define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_Q_MSB 0x9CD
#define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_Q_LSB 0x9CE
/* Mykonos GPIO Registers */
#define MYKONOS_ADDR_GPIO_3V3_DIR_CTL_7_0 0xB00
#define MYKONOS_ADDR_GPIO_3V3_DIR_CTL_15_8 0xB01
#define MYKONOS_ADDR_GPIO_3V3_SPI_SRC_7_0 0xB02
#define MYKONOS_ADDR_GPIO_3V3_SPI_SRC_15_8 0xB03
#define MYKONOS_ADDR_GPIO_3V3_SPI_READ_7_0 0xB04
#define MYKONOS_ADDR_GPIO_3V3_SPI_READ_15_8 0xB05
#define MYKONOS_ADDR_GPIO_3V3_LSB_SRC_CTL 0xB06
#define MYKONOS_ADDR_GPIO_3V3_MSB_SRC_CTL 0xB07
#define MYKONOS_ADDR_GPIO_DIR_CTL_7_0 0xB20
#define MYKONOS_ADDR_GPIO_DIR_CTL_15_8 0xB21
#define MYKONOS_ADDR_GPIO_DIR_CTL_18_16 0xB22
#define MYKONOS_ADDR_GPIO_SPI_SRC_7_0 0xB23
#define MYKONOS_ADDR_GPIO_SPI_SRC_15_8 0xB24
#define MYKONOS_ADDR_GPIO_SPI_SRC_18_16 0xB25
#define MYKONOS_ADDR_GPIO_SPI_READ_7_0 0xB26
#define MYKONOS_ADDR_GPIO_SPI_READ_15_8 0xB27
#define MYKONOS_ADDR_GPIO_SPI_READ_18_16 0xB28
#define MYKONOS_ADDR_SOURCE_CONTROL_LOWER_BYTE 0xB29
#define MYKONOS_ADDR_SOURCE_CONTROL_UPPER_BYTE 0xB2A
#define MYKONOS_ADDR_SOURCE_CONTROL_EXTRA_BITS 0xB2B
#define MYKONOS_ADDR_GPIO_MONITOR_INDEX 0xB40
#define MYKONOS_ADDR_GPIO_MONITOR_ENABLE 0xB41
#define MYKONOS_ADDR_GP_INTERRUPT_MASK_1 0xB42
#define MYKONOS_ADDR_GP_INTERRUPT_MASK_0 0xB43
#define MYKONOS_ADDR_GP_INTERRUPT_READ_1 0xB44
#define MYKONOS_ADDR_GP_INTERRUPT_READ_0 0xB45
#define MYKONOS_ADDR_PDAUXDAC_MANUAL_CONTROL_5_0 0xB73
#define MYKONOS_ADDR_PDAUXDAC_MANUAL_CONTROL_9_6 0xB74
#define MYKONOS_ADDR_PDAUXDAC_MANUAL_IN_5_0 0xB75
#define MYKONOS_ADDR_PDAUXDAC_MANUAL_IN_9_6 0xB76
#define MYKONOS_ADDR_AUX_DAC_LATCH_CONTROL 0xB9F
#define MYKONOS_ADDR_AUXDAC_0_WORD_MSB 0xBA0
#define MYKONOS_ADR_AUX_ADC_CLOCK_DIVIDE 0xBC0
#define MYKONOS_ADDR_AUX_ADC_CFG 0xBC1
#define MYKONOS_ADDR_AUX_ADC_READ_MSB 0xBC2
#define MYKONOS_ADDR_AUX_ADC_READ_LSB 0xBC3
#define MYKONOS_ADDR_AUX_ADC_SEL 0xBC4
#define MYKONOS_ADDR_AUX_ADC_BUFFER_CONFIG_0 0xBC5
#define MYKONOS_ADDR_AUX_ADC_BUFFER_CONFIG_1 0xBC6
#define MYKONOS_ADDR_TEMP_SENSOR_OFFSET 0xBE0
#define MYKONOS_ADDR_TEMP_SENSOR_CONTROL_LSB 0xBE1
#define MYKONOS_ADDR_TEMP_SENSOR_CONTROL_MSB 0xBE2
#define MYKONOS_ADDR_TEMP_SENSOR_READ 0xBE3
#define MYKONOS_ADDR_TEMP_SENSOR_CONFIG 0xBE4
#define MYKONOS_ADDR_DIGITAL_TEST_BYTE_0 0xC40
/* ARM subsystem registers */
#define MYKONOS_ADDR_ARM_CTL_1 0xD00
#define MYKONOS_ADDR_ARM_CTL_2 0xD01
#define MYKONOS_ADDR_ARM_ADDR_BYTE_0 0xD02
#define MYKONOS_ADDR_ARM_ADDR_BYTE_1 0xD03
#define MYKONOS_ADDR_ARM_DATA_BYTE_0 0xD04
#define MYKONOS_ADDR_ARM_DATA_BYTE_1 0xD05
#define MYKONOS_ADDR_ARM_DATA_BYTE_2 0xD06
#define MYKONOS_ADDR_ARM_DATA_BYTE_3 0xD07
#define MYKONOS_ADDR_ARM_CLK_CTL 0xD08
#define MYKONOS_ADDR_AHB_SPI_BRIDGE 0xD09
#define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_0 0xD0A
#define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_1 0xD0B
#define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_2 0xD0C
#define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_3 0xD0D
#define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_0 0xD0E
#define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_1 0xD0F
#define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_2 0xD10
#define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_3 0xD11
#define MYKONOS_ADDR_ARM_BRIDGE_CLK_CTL 0xD14
/* ARM mailbox registers */
#define MYKONOS_ADDR_ARM_CMD 0xD30
#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_1 0xD31
#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_2 0xD32
#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_3 0xD33
#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_4 0xD34
#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_5 0xD35
#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_6 0xD36
#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_7 0xD37
#define MYKONOS_ADDR_ARM_CMD_STATUS_0 0xD38
#define MYKONOS_ADDR_ARM_CMD_STATUS_1 0xD39
#define MYKONOS_ADDR_ARM_CMD_STATUS_2 0xD3A
#define MYKONOS_ADDR_ARM_CMD_STATUS_3 0xD3B
#define MYKONOS_ADDR_ARM_CMD_STATUS_4 0xD3C
#define MYKONOS_ADDR_ARM_CMD_STATUS_5 0xD3D
#define MYKONOS_ADDR_ARM_CMD_STATUS_6 0xD3E
#define MYKONOS_ADDR_ARM_CMD_STATUS_7 0xD3F
#define MYKONOS_ADDR_ARM_OPCODE_STATE_0 0xD40
#define MYKONOS_ADDR_ARM_OPCODE_STATE_1 0xD41
#define MYKONOS_ADDR_ARM_OPCODE_STATE_2 0xD42
#define MYKONOS_ADDR_ARM_OPCODE_STATE_3 0xD43
#define MYKONOS_ADDR_ARM_OPCODE_STATE_4 0xD44
#define MYKONOS_ADDR_ARM_OPCODE_STATE_5 0xD45
#define MYKONOS_ADDR_ARM_OPCODE_STATE_6 0xD46
#define MYKONOS_ADDR_ARM_OPCODE_STATE_7 0xD47
/* Mykonos Power-Down Override Control Registers */
#define MYKONOS_ADDR_TX_PD_OVERRIDE_CONTROL_7_0 0xD89
/* Mykonos Observation Framer Registers */
#define MYKONOS_ADDR_OBS_FRAMER_RESET 0xDC0
#define MYKONOS_ADDR_OBS_FRAMER_CLK_EN 0xDC1
#define MYKONOS_ADDR_OBS_FRAMER_ADDR 0xDC2
#define MYKONOS_ADDR_OBS_FRAMER_DATA 0xDC3
#define MYKONOS_ADDR_OBS_FRAMER_WRITE_EN 0xDC4
#define MYKONOS_ADDR_OBS_FRAMER_SYSREF_FIFO_EN 0xDC5
#define MYKONOS_ADDR_OBS_FRAMER_CONFIG_F 0xDC6
#define MYKONOS_ADDR_OBS_FRAMER_LANE_CTL 0xDC7
#define MYKONOS_ADDR_OBS_FRAMER_ADC_XBAR_SEL 0xDC8
#define MYKONOS_ADDR_OBS_FRAMER_LANE_XBAR_SEL 0xDC9
#define MYKONOS_ADDR_OBS_FRAMER_CONFIG_LOOPBACK_XBAR_REV 0xDCA
#define MYKONOS_ADDR_OBS_FRAMER_SYNCN_FILT 0xDCB
#define MYKONOS_ADDR_OBS_FRAMER_LMFC_F_OFFSET 0xDCC
#define MYKONOS_ADDR_OBS_FRAMER_LMFC_K_OFFSET 0xDCD
#define MYKONOS_ADDR_OBS_FRAMER_TEST_CNTR_CTL 0xDCE
#define MYKONOS_ADDR_OBS_FRAMER_STATUS_STRB 0xDCF
#define MYKONOS_ADDR_OBS_FRAMER_STATUS 0xDD0
#define MYKONOS_ADDR_OBS_FRAMER_SYSREF_TO_LMFC_CNTR_STAT 0xDD1
#define MYKONOS_ADDR_OBS_FRAMER_SYSREF_TO_LMFC_ERR_MARGIN 0xDD2
#define MYKONOS_ADDR_OBS_FRAMER_LANE_FIFO_STRB 0xDD3
#define MYKONOS_ADDR_OBS_FRAMER_LANE0_FIFO_RDWR_ADDR 0xDD4
#define MYKONOS_ADDR_OBS_FRAMER_LANE1_FIFO_RDWR_ADDR 0xDD5
#define MYKONOS_ADDR_OBS_FRAMER_LANE2_FIFO_RDWR_ADDR 0xDD6
#define MYKONOS_ADDR_OBS_FRAMER_LANE3_FIFO_RDWR_ADDR 0xDD7
#define MYKONOS_ADDR_OBS_FRAMER_PRBS10_CTL 0xDD8
#define MYKONOS_ADDR_OBS_FRAMER_PRBS20_CTL 0xDD9
#define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_EN 0xDDA
#define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_7_TO_0 0xDDB
#define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_15_TO_8 0xDDC
#define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_19_TO_16 0xDDD
#define MYKONOS_ADDR_OBS_FRAMER_CONFIG_JTX_GEN 0xDDE
#define MYKONOS_ADDR_OBS_FRAMER_LANE_DATA_CTL 0xDDF
#define MYKONOS_ADDR_OBS_FRAMER_DATA_SAMPLE_CTL 0xDE0
#define MYKONOS_ADDR_PFIR_COEFF_CTL 0xDFF
#define MYKONOS_ADDR_PFIR_COEFF_DATA 0xE00
#define MYKONOS_ADDR_PFIR_COEFF_ADDR 0xE01
/* ARM memory */
#define MYKONOS_ADDR_ARM_START_PROG_ADDR 0x01000000
#define MYKONOS_ADDR_ARM_END_PROG_ADDR 0x01017FFF
#define MYKONOS_ADDR_ARM_START_DATA_ADDR 0x20000000
#define MYKONOS_ADDR_ARM_END_DATA_ADDR 0x2000FFFF
#define MYKONOS_ADDR_ARM_BUILD_CHKSUM_ADDR 0x01017FE0
#define MYKONOS_ADDR_ARM_CALC_CHKSUM_ADDR 0x01017FE4
#define MYKONOS_ADDR_ARM_VERSION 0x01000128
#define MYKONOS_ARM_ABORT_OPCODE 0x00
#define MYKONOS_ARM_RUNINIT_OPCODE 0x02
#define MYKONOS_ARM_RADIOON_OPCODE 0x04
#define MYKONOS_ARM_WRITECFG_OPCODE 0x06
#define MYKONOS_ARM_READCFG_OPCODE 0x08
#define MYKONOS_ARM_SET_OPCODE 0x0A
#define MYKONOS_ARM_GET_OPCODE 0x0C
#define MYKONOS_ARM_OBJECTID_DPDINIT_CONFIG 0x0F
#define MYKONOS_ARM_OBJECTID_CLGCINIT_CONFIG 0x10
#define MYKONOS_ARM_OBJECTID_VSWRINIT_CONFIG 0x11
#define MYKONOS_ARM_OBJECTID_DPDCONFIG 0x24
#define MYKONOS_ARM_DPD_RESET 0x02
#define MYKONOS_ARM_OBJECTID_GS_TRACKCALS 0x66
#define MYKONOS_ARM_OBJECTID_RXQEC_TRACKING 0x20
#define MYKONOS_ARM_OBJECTID_ORXQEC_TRACKING 0x21
#define MYKONOS_ARM_OBJECTID_TXLOL_TRACKING 0x22
#define MYKONOS_ARM_OBJECTID_TXQEC_TRACKING 0x23
#define MYKONOS_ARM_OBJECTID_CLGCCONFIG 0x25
#define MYKONOS_ARM_OBJECTID_VSWRCONFIG 0x26
#define MYKONOS_ARM_OBJECTID_CAL_STATUS 0x42
#define MYKONOS_ARM_OBJECTID_INIT_CAL_DONE 0x43
#define MYKONOS_ARM_OBJECTID_ORX_MODE 0x61
#define MYKONOS_ARM_OBJECTID_TRACKING_CAL_SUSPEND_RESUME 0x65
#define MYKONOS_ARM_OBJECTID_TRACKING_CAL_CONTROL 0x66
#define MYKONOS_ARM_OBJECTID_TRACKING_CAL_PENDING 0x67
#define MYKONOS_ARM_OBJECTID_RADIO_CONTROL 0x81
#define MYKONOS_ARM_OBJECTID_CALSCHEDULER 0x83
#define MYKONOS_ARM_SYSTEMSTATE_POWERUP 0x00
#define MYKONOS_ARM_SYSTEMSTATE_READY 0x01
#define MYKONOS_ARM_SYSTEMSTATE_IDLE 0x02
#define MYKONOS_ARM_SYSTEMSTATE_RADIO_ON 0x03
#define ORX_TRIGGER_SIGNALID 0x00
#define ORX_MODE_0_SIGNALID 0x01
#define ORX_MODE_1_SIGNALID 0x02
#define ORX_MODE_2_SIGNALID 0x03
#define RX1_ENABLE_ACK_SIGNALID 0x04
#define RX2_ENABLE_ACK_SIGNALID 0x05
#define TX1_ENABLE_ACK_SIGNALID 0x06
#define TX2_ENABLE_ACK_SIGNALID 0x07
#define ORX1_ENABLE_ACK_SIGNALID 0x08
#define ORX2_ENABLE_ACK_SIGNALID 0x09
#define SRX_ENABLE_ACK_SIGNALID 0x0A
#define TX_OBS_SELECT_SIGNALID 0x0B
#define DISABLE_DPD_ACTUATOR 0x03
#define ENABLE_DPD_ACTUATOR 0x04
#define SET_CLGC_DESIRED_GAIN_1 0x05
#define SET_CLGC_DESIRED_GAIN_2 0x06
#define SET_PATH_DELAY 0x08
#ifdef __cplusplus
}
#endif
#endif
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/mykonos/mykonos_user.c
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/**
* \file mykonos_user.c
* \brief Contains Mykonos default gain table values for Rx, ObsRx, and SnRx
*
* Mykonos API version: 1.5.2.3566
*/
/**
* \page Disclaimer Legal Disclaimer
* Copyright 2015-2017 Analog Devices Inc.
* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
*
*/
#include <stdint.h>
#include "t_mykonos.h"
#include "mykonos_user.h"
/**
* \brief Default Rx gain table settings
*/
uint8_t RxGainTable [61][4] =
{
/* Order: {FE table, External Ctl, Digital Gain/Atten, Enable Atten} */
{0, 0, 0, 0}, /* Gain index 255 */
{3, 0, 2, 1}, /* Gain index 254 */
{6, 0, 3, 1}, /* Gain index 253 */
{10, 0, 0, 0}, /* Gain index 252 */
{13, 0, 1, 1}, /* Gain index 251 */
{16, 0, 0, 0}, /* Gain index 250 */
{18, 0, 3, 1}, /* Gain index 249 */
{21, 0, 1, 1}, /* Gain index 248 */
{23, 0, 3, 1}, /* Gain index 247 */
{25, 0, 4, 1}, /* Gain index 246 */
{28, 0, 0, 0}, /* Gain index 245 */
{30, 0, 0, 0}, /* Gain index 244 */
{31, 0, 5, 1}, /* Gain index 243 */
{33, 0, 4, 1}, /* Gain index 242 */
{35, 0, 2, 1}, /* Gain index 241 */
{37, 0, 0, 0}, /* Gain index 240 */
{38, 0, 4, 1}, /* Gain index 239 */
{39, 0, 7, 1}, /* Gain index 238 */
{41, 0, 2, 1}, /* Gain index 237 */
{42, 0, 4, 1}, /* Gain index 236 */
{43, 0, 6, 1}, /* Gain index 235 */
{44, 0, 8, 1}, /* Gain index 234 */
{45, 0, 9, 1}, /* Gain index 233 */
{46, 0, 10, 1}, /* Gain index 232 */
{47, 0, 10, 1}, /* Gain index 231 */
{48, 0, 9, 1}, /* Gain index 230 */
{49, 0, 8, 1}, /* Gain index 229 */
{50, 0, 6, 1}, /* Gain index 228 */
{51, 0, 3, 1}, /* Gain index 227 */
{51, 0, 13, 1}, /* Gain index 226 */
{52, 0, 9, 1}, /* Gain index 225 */
{53, 0, 5, 1}, /* Gain index 224 */
{53, 0, 15, 1}, /* Gain index 223 */
{54, 0, 9, 1}, /* Gain index 222 */
{54, 0, 19, 1}, /* Gain index 221 */
{55, 0, 11, 1}, /* Gain index 220 */
{55, 0, 21, 1}, /* Gain index 219 */
{56, 0, 11, 1}, /* Gain index 218 */
{56, 0, 21, 1}, /* Gain index 217 */
{57, 0, 9, 1}, /* Gain index 216 */
{57, 0, 19, 1}, /* Gain index 215 */
{57, 0, 29, 1}, /* Gain index 214 */
{58, 0, 12, 1}, /* Gain index 213 */
{58, 0, 22, 1}, /* Gain index 212 */
{58, 0, 32, 1}, /* Gain index 211 */
{59, 0, 11, 1}, /* Gain index 210 */
{59, 0, 21, 1}, /* Gain index 209 */
{59, 0, 31, 1}, /* Gain index 208 */
{59, 0, 41, 1}, /* Gain index 207 */
{60, 0, 13, 1}, /* Gain index 206 */
{60, 0, 23, 1}, /* Gain index 205 */
{60, 0, 33, 1}, /* Gain index 204 */
{60, 0, 43, 1}, /* Gain index 203 */
{60, 0, 53, 1}, /* Gain index 202 */
{61, 0, 14, 1}, /* Gain index 201 */
{61, 0, 24, 1}, /* Gain index 200 */
{61, 0, 34, 1}, /* Gain index 199 */
{61, 0, 44, 1}, /* Gain index 198 */
{61, 0, 54, 1}, /* Gain index 197 */
{61, 0, 64, 1}, /* Gain index 196 */
{61, 0, 74, 1}, /* Gain index 195 */
};
/**
* \brief Default ORx gain table settings
*/
uint8_t ORxGainTable [19][4] =
{
/* Order: {FE table, External Ctl, Digital Gain/Atten, Enable Atten} */
{0, 0, 0, 0}, /* Gain index 255 */
{7, 0, 0, 0}, /* Gain index 254 */
{13, 0, 1, 1}, /* Gain index 253 */
{18, 0, 3, 1}, /* Gain index 252 */
{23, 0, 3, 1}, /* Gain index 251 */
{28, 0, 0, 0}, /* Gain index 250 */
{32, 0, 0, 0}, /* Gain index 249 */
{35, 0, 2, 1}, /* Gain index 248 */
{38, 0, 4, 1}, /* Gain index 247 */
{41, 0, 2, 1}, /* Gain index 246 */
{43, 0, 6, 1}, /* Gain index 245 */
{46, 0, 0, 0}, /* Gain index 244 */
{47, 0, 10, 1}, /* Gain index 243 */
{49, 0, 8, 1}, /* Gain index 242 */
{51, 0, 3, 1}, /* Gain index 241 */
{52, 0, 9, 1}, /* Gain index 240 */
{53, 0, 14, 1}, /* Gain index 239 */
{54, 0, 18, 1}, /* Gain index 238 */
{56, 0, 0, 0} /* Gain index 237 */
};
/**
* \brief Default SnRx gain table settings
*/
uint8_t SnRxGainTable [53][4] =
{
/* Order: {FE table, LNA Bypass, Digital Gain/Atten, Enable Atten} */
{0, 0, 0, 0}, /* Gain index 255 */
{1, 0, 7, 1}, /* Gain index 254 */
{3, 0, 1, 0}, /* Gain index 253 */
{3, 0, 15, 1}, /* Gain index 252 */
{5, 0, 0, 0}, /* Gain index 251 */
{6, 0, 2, 1}, /* Gain index 250 */
{7, 0, 2, 1}, /* Gain index 249 */
{8, 0, 12, 1}, /* Gain index 248 */
{9, 0, 7, 1}, /* Gain index 247 */
{11, 0, 1, 0}, /* Gain index 246 */
{11, 0, 15, 1},/* Gain index 245 */
{13, 0, 1, 0}, /* Gain index 244 */
{14, 0, 2, 0}, /* Gain index 243 */
{14, 0, 10, 1},/* Gain index 242 */
{15, 0, 0, 0}, /* Gain index 241 */
{15, 0, 20, 1},/* Gain index 240 */
{16, 0, 2, 1}, /* Gain index 239 */
{16, 0, 22, 1},/* Gain index 238 */
{17, 0, 1, 0}, /* Gain index 237 */
{17, 0, 15, 1},/* Gain index 236 */
{17, 0, 35, 1},/* Gain index 235 */
{17, 0, 55, 1},/* Gain index 234 */
{18, 0, 7, 1}, /* Gain index 233 */
{18, 0, 27, 1},/* Gain index 232 */
{ 6, 1, 7, 1}, /* Gain index 231 */
{ 7, 1, 7, 1}, /* Gain index 230 */
{ 8, 1, 17, 1}, /* Gain index 229 */
{ 9, 1, 12, 1}, /* Gain index 228 */
{11, 1, 0, 0}, /* Gain index 227 */
{12, 1, 3, 1}, /* Gain index 226 */
{13, 1, 0, 0}, /* Gain index 225 */
{14, 1, 1, 0}, /* Gain index 224 */
{14, 1, 15, 1},/* Gain index 223 */
{15, 1, 5, 1}, /* Gain index 222 */
{15, 1, 25, 1},/* Gain index 221 */
{16, 1, 7, 1}, /* Gain index 220 */
{16, 1, 27, 1},/* Gain index 219 */
{17, 1, 0, 0}, /* Gain index 218 */
{17, 1, 20, 1},/* Gain index 217 */
{17, 1, 40, 1},/* Gain index 216 */
{17, 1, 60, 1},/* Gain index 215 */
{18, 1, 12, 1},/* Gain index 214 */
{18, 1, 32, 1},/* Gain index 213 */
{18, 1, 52, 1},/* Gain index 212 */
{18, 1, 72, 1},/* Gain index 211 */
{18, 1, 92, 1},/* Gain index 210 */
{19, 1, 1, 0}, /* Gain index 209 */
{19, 1, 15, 1},/* Gain index 208 */
{19, 1, 35, 1},/* Gain index 207 */
{19, 1, 55, 1},/* Gain index 206 */
{19, 1, 75, 1},/* Gain index 205 */
{19, 1, 95, 1},/* Gain index 204 */
{19, 1, 115, 1}/* Gain index 203 */
};
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/mykonos/mykonos_user.h
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/**
* \file mykonos_user.h
*
* \brief Contains macro definitions and global structure declarations for mykonos_user.c
*
* Mykonos API version: 1.5.2.3566
*/
/**
* \page Disclaimer Legal Disclaimer
* Copyright 2015-2017 Analog Devices Inc.
* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
*
*/
#ifndef _MYKONOSPROFILES_H_
#define _MYKONOSPROFILES_H_
#ifdef __cplusplus
extern "C" {
#endif
/* turns verbose messaging on */
#define MYKONOS_VERBOSE 1
#define MYK_ENABLE_SPIWRITEARRAY 1
/* 3 Bytes per SPI transaction * 341 transactions = ~1024 byte buffer size */
/* Minimum MYK_SPIWRITEARRAY_BUFFERSIZE = 27 */
#define MYK_SPIWRITEARRAY_BUFFERSIZE 341
/*
*****************************************
* Rx, ObsRx, and Sniffer gain tables
******************************************
*/
#define MAX_GAIN_TABLE_INDEX 255
#define START_RX_GAIN_INDEX 255
#define MAX_RX_GAIN_TABLE_NUMINDEXES (START_RX_GAIN_INDEX + 1)
#define MIN_RX_GAIN_TABLE_INDEX 0
#define START_ORX_GAIN_INDEX 47
#define MAX_ORX_GAIN_TABLE_NUMINDEXES (START_ORX_GAIN_INDEX + 1)
#define MIN_ORX_GAIN_TABLE_INDEX (MAX_GAIN_TABLE_INDEX - START_ORX_GAIN_INDEX)
#define START_SNRX_GAIN_INDEX 127
#define MAX_SNRX_GAIN_TABLE_NUMINDEXES (START_SNRX_GAIN_INDEX + 1)
#define MIN_SNRX_GAIN_TABLE_INDEX (MAX_GAIN_TABLE_INDEX - START_SNRX_GAIN_INDEX)
#define START_LOOPBACK_GAIN_INDEX 47
#define MAX_LOOPBACK_GAIN_TABLE_NUMINDEXES (START_LOOPBACK_GAIN_INDEX + 1)
#define MIN_LOOPBACK_GAIN_TABLE_INDEX (MAX_GAIN_TABLE_INDEX - START_SNRX_GAIN_INDEX)
extern uint8_t RxGainTable [61][4];
extern uint8_t ORxGainTable [19][4];
extern uint8_t SnRxGainTable [53][4];
/*
********************************************
* Rx, Sniffer, ObsRx and Tx Profiles limits
********************************************
*/
#define MIN_RX_IQRATE_KHZ 15000 /*!< Mykonos minimum IQ rate for the Rx channel, expressed in KHz */
#define MAX_RX_IQRATE_KHZ 320000 /*!< Mykonos maximum IQ rate for the Rx channel, expressed in KHz */
#define MIN_TX_IQRATE_KHZ 15000 /*!< Mykonos minimum IQ rate for the Tx channel, expressed in KHz */
#define MAX_TX_IQRATE_KHZ 492000 /*!< Mykonos maximum IQ rate for the Tx channel, expressed in KHz */
#define MIN_SNIFFER_RFBW_HZ 5000000 /*!< Mykonos minimum Sniffer channel bandwidth expressed in Hz */
#define MAX_SNIFFER_RFBW_HZ 20000000 /*!< Mykonos maximum Sniffer channel bandwidth expressed in Hz */
#define MIN_ORX_RFBW_HZ 5000000 /*!< Mykonos minimum Observation channel bandwidth expressed in Hz */
#define MAX_ORX_RFBW_HZ 250000000 /*!< Mykonos maximum Observation channel bandwidth expressed in Hz */
#define MIN_RX_RFBW_HZ 5000000 /*!< Mykonos minimum Rx channel bandwidth expressed in Hz */
#define MAX_RX_RFBW_HZ 100000000 /*!< Mykonos maximum Rx channel bandwidth expressed in Hz */
#define MIN_TX_RFBW_HZ 20000000 /*!< Mykonos minimum Tx channel bandwidth expressed in Hz */
#define MAX_TX_RFBW_HZ 250000000 /*!< Mykonos maximum Tx channel bandwidth expressed in Hz */
#ifdef __cplusplus
}
#endif
#endif
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/mykonos/mykonos_version.h
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/**
* \file mykonos_version.h
* \brief Contains the version number for the Mykonos API
*
* Mykonos API version: 1.5.2.3566
*/
/**
* \page Disclaimer Legal Disclaimer
* Copyright 2015-2017 Analog Devices Inc.
* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in * this zip file.
*
*/
#ifndef MYKONOS_VERSION_H_
#define MYKONOS_VERSION_H_
#ifdef __cplusplus
extern "C" {
#endif
#define MYKONOS_CURRENT_SI_VERSION 1 /*!< Mykonos current silicon version */
#define MYKONOS_CURRENT_MAJOR_VERSION 5 /*!< Mykonos current ARM major version */
#define MYKONOS_CURRENT_MINOR_VERSION 2 /*!< Mykonos current ARM minor version */
#define MYKONOS_CURRENT_BUILD_VERSION 3566 /*!< Mykonos current API build version */
#ifdef __cplusplus
}
#endif
#endif /* MYKONOS_VERSION_H_ */
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/mykonos/t_ad9528.h
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/**
* \file t_ad9528.h
* \brief Contains enum and structure data types for all AD9528 function calls
*/
/**
* \page Disclaimer Legal Disclaimer
* Copyright 2015-2017 Analog Devices Inc.
* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
*
*/
#ifndef _AD9528_TYPES_H_
#define _AD9528_TYPES_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "../common.h"
/* AD9528 SPI Address defines */
#define AD9528_ADDR_ADI_SPI_CONFIG_A 0x000
#define AD9528_ADDR_ADI_SPI_CONFIG_B 0x001
#define AD9528_ADDR_IO_UPDATE 0x00F
#define AD9528_ADDR_REF_A_DIVIDER_LSB 0x100
#define AD9528_ADDR_REF_A_DIVIDER_MSB 0x101
#define AD9528_ADDR_REF_B_DIVIDER_LSB 0x102
#define AD9528_ADDR_REF_B_DIVIDER_MSB 0x103
#define AD9528_ADDR_PLL1_N_DIV_LSB 0x104
#define AD9528_ADDR_PLL1_N_DIV_MSB 0x105
#define AD9528_ADDR_PLL1_CHARGEPUMP 0x106
#define AD9528_ADDR_PLL1_CP_CTRL2 0x107
#define AD9528_ADDR_INPUT_RECEIVERS1 0x108
#define AD9528_ADDR_INPUT_RECEIVERS2 0x109
#define AD9528_ADDR_INPUT_RECEIVERS3 0x10A
#define AD9528_ADDR_PLL1_FASTLOCK 0x10B
#define AD9528_ADDR_PLL2_CHARGEPUMP 0x200
#define AD9528_ADDR_PLL2_N_DIV 0x201
#define AD9528_ADDR_PLL2_CTRL 0x202
#define AD9528_ADDR_PLL2_VCO_CTRL 0x203
#define AD9528_ADDR_PLL2_VCO_DIV 0x204
#define AD9528_ADDR_PLL2_LF_CTRL1 0x205
#define AD9528_ADDR_PLL2_LF_CTRL2 0x206
#define AD9528_ADDR_PLL2_RDIV 0x207
#define AD9528_ADDR_PLL2_REPLICA_CHDIV 0x208
#define AD9528_ADDR_PLL2_REPLICA_DIV_PHASE 0x209
#define AD9528_ADDR_CH_OUT0_CTRL1 0x300
#define AD9528_ADDR_CH_OUT0_CTRL2 0x301
#define AD9528_ADDR_CH_OUT0_CHDIV 0x302
#define AD9528_ADDR_OUTPUT_SYNC 0x32A
#define AD9528_ADDR_MASK_SYNC1 0x32B
#define AD9528_ADDR_MASK_SYNC2 0x32C
#define AD9528_ADDR_EN_OUTPUT_PATH_SEL1 0x32D
#define AD9528_ADDR_EN_OUTPUT_PATH_SEL2 0x32E
#define AD9528_ADDR_SYSERF_DIV_LSB 0x400
#define AD9528_ADDR_SYSERF_DIV_MSB 0x401
#define AD9528_ADDR_SYSREF_CTRL3 0x402
#define AD9528_ADDR_SYSREF_CTRL4 0x403
#define AD9528_ADDR_SYSREF_CTRL5 0x404
#define AD9528_ADDR_POWERDOWN_CTRL 0x500
#define AD9528_ADDR_CH_POWERDOWN1 0x501
#define AD9528_ADDR_CH_POWERDOWN2 0x502
#define AD9528_ADDR_LDO_ENABLES1 0x503
#define AD9528_ADDR_LDO_ENABLES2 0x504
#define AD9528_ADDR_STATUS0_CTRL 0x505
#define AD9528_ADDR_STATUS1_CTRL 0x506
#define AD9528_ADDR_STATUS_OE 0x507
#define AD9528_ADDR_STATUS_READBACK0 0x508
#define AD9528_ADDR_STATUS_READBACK1 0x509
///Enum to select what source outputs from each AD9528 output channel
typedef enum
{
CHANNEL_DIV = 0, PLL1_OUTPUT = 1, //VCXO frequency
SYSREF = 2,
INV_PLL1_OUTPUT = 5 //VCXO inverted
} ad9528outSourceSel_t;
///Enum to select what output buffer standard is used for the clock outputs
typedef enum
{
LVDS = 0, LVDS_BOOST = 1, HSTL = 2
} ad9528outBufferControl_t;
///Enum to select the clock input buffer mode.
typedef enum
{
DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL
} ad9528RefBuffer_t;
/// Structure to hold AD9528 PLL1 settings
typedef struct
{
uint32_t refA_Frequency_Hz;
uint16_t refA_Divider;
ad9528RefBuffer_t refA_bufferCtrl;
uint32_t refB_Frequency_Hz;
uint16_t refB_Divider;
ad9528RefBuffer_t refB_bufferCtrl;
uint32_t vcxo_Frequency_Hz;
ad9528RefBuffer_t vcxoBufferCtrl;
uint16_t nDivider;
uint8_t bypassPll1;
} ad9528pll1Settings_t;
/// Structure to hold AD9528 PLL2 settings
typedef struct
{
uint8_t rfDivider; //VCO divider: Valid range (3,4,5)
uint8_t n2Divider; //PLL2 N2 Divider
uint8_t totalNdiv; //NDiv = 4*Bdiv + Adiv //Bdiv valid range (3 to 63), Adiv valid range (0-3)
} ad9528pll2Settings_t;
/// Structure to hold AD9528 Output Clock settings
typedef struct
{
uint16_t outPowerDown; //bit per output, if 1 power down that output.
ad9528outSourceSel_t outSource[14]; //CHANNEL_DIV, PLL1_OUTPUT, SYSREF, INV_PLL1_OUTPUT
ad9528outBufferControl_t outBufferCtrl[14]; //LVDS, LVDS_BOOST, HSTL
uint8_t outAnalogDelay[14]; //5 bits
uint8_t outDigitalDelay[14]; //6 bits, 1/2 clock resolution @ channel div input frequency
uint8_t outChannelDiv[14]; //8 bit channel divider
uint32_t outFrequency_Hz[14]; //output clock frequency per clock output
} ad9528outputSettings_t;
///Enum to select the SYSREF output source
typedef enum
{
EXTERNAL = 0, EXT_RESAMPLED = 1, INTERNAL = 2
} sysrefSourceSelection_t;
///Enum to choose the SYSREF pattern mode.
typedef enum
{
NSHOT = 0, CONTINUOUS = 1, PRBS = 2, STOP = 3
} sysrefPatternMode_t;
///Enum to select the SYSREF input pin mode.
typedef enum
{
LEVEL_ACTIVE_HIGH = 0, LEVEL_ACTIVE_LOW = 1, RISING_EDGE = 2, FALLING_EDGE = 3
} sysrefPinEdgeMode_t;
///Enum to select the SYSREF output # of pulses for NSHOT mode.
typedef enum
{
ONE_PULSE = 0, TWO_PULSES = 2, FOUR_PULSES = 3, SIX_PULSES = 4, EIGHT_PULSES = 5
} sysrefNshotMode_t;
//Enum to select how a SYSREF is requested.
typedef enum
{
SPI = 0, PIN = 1
} sysrefRequestMethod_t;
/// Structure to hold AD9528 SYSREF output settings
typedef struct
{
sysrefRequestMethod_t sysrefRequestMethod;
sysrefSourceSelection_t sysrefSource;
sysrefPinEdgeMode_t sysrefPinEdgeMode;
ad9528RefBuffer_t sysrefPinBufferMode;
sysrefPatternMode_t sysrefPatternMode;
sysrefNshotMode_t sysrefNshotMode;
uint16_t sysrefDivide;
} ad9528sysrefSettings_t;
/// Structure to hold AD9528 settings
typedef struct
{
spiSettings_t *spiSettings;
ad9528pll1Settings_t *pll1Settings;
ad9528pll2Settings_t *pll2Settings;
ad9528outputSettings_t *outputSettings;
ad9528sysrefSettings_t *sysrefSettings;
} ad9528Device_t;
#ifdef __cplusplus
}
#endif
#endif
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/mykonos/t_mykonos.h
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projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/mykonos/t_mykonos_gpio.h
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/*!
* \file t_mykonos_gpio.h
* \brief Mykonos GPIO error handling and type defines
*
* Mykonos API version: 1.5.2.3566
*/
/**
* \page Disclaimer Legal Disclaimer
* Copyright 2015-2017 Analog Devices Inc.
* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
*
*/
#ifndef T_MYKONOSGPIO_H_
#define T_MYKONOSGPIO_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "../common.h"
/**
* \brief Enum of unique error codes from the Mykonos GPIO API functions.
* Each error condition in the library should get its own enum value to allow
* easy debug of errors.
*/
typedef enum
{
MYKONOS_ERR_GPIO_OK = 0,
MYKONOS_ERR_EN_MONITOR_OUT_NOT_ENABLED,
MYKONOS_ERR_EN_MONITOR_OUT_SRC_CTRL,
MYKONOS_ERR_MONITOR_OUT_INDEX_RANGE,
MYKONOS_ERR_GETGPIOMON_INDEX_NULL_PARM,
MYKONOS_ERR_GETGPIOMON_MONITORMASK_NULL_PARM,
MYKONOS_ERR_MGCRX2_GPIO_DECPIN_INV_PARAM,
MYKONOS_ERR_MGCRX2_GPIO_INCPIN_INV_PARAM,
MYKONOS_ERR_MGCRX2_SOURCE_CONFIG,
MYKONOS_ERR_MGCRX2_STEP_INV_PARAM,
MYKONOS_ERR_MGCRX1_GPIO_DECPIN_INV_PARAM,
MYKONOS_ERR_MGCRX1_GPIO_INCPIN_INV_PARAM,
MYKONOS_ERR_MGCRX1_STEP_INV_PARAM,
MYKONOS_ERR_GETRX2PIN_INCSTEP_NULL_PARM,
MYKONOS_ERR_GETRX2PIN_DECSTEP_NULL_PARM,
MYKONOS_ERR_GETRX2PIN_INCPIN_NULL_PARM,
MYKONOS_ERR_GETRX2PIN_DECPIN_NULL_PARM,
MYKONOS_ERR_GETRX2PIN_EN_NULL_PARM,
MYKONOS_ERR_GETRX1PIN_INCSTEP_NULL_PARM,
MYKONOS_ERR_GETRX1PIN_DECSTEP_NULL_PARM,
MYKONOS_ERR_GETRX1PIN_INCPIN_NULL_PARM,
MYKONOS_ERR_GETRX1PIN_DECPIN_NULL_PARM,
MYKONOS_ERR_GETRX1PIN_EN_NULL_PARM,
MYKONOS_ERR_TPCTX2_GPIO_DECPIN_INV_PARAM,
MYKONOS_ERR_TPCTX2_GPIO_INCPIN_INV_PARAM,
MYKONOS_ERR_TPCTX2_GPIO_STEP_INV_PARAM,
MYKONOS_ERR_TPCTX1_GPIO_DECPIN_INV_PARAM,
MYKONOS_ERR_TPCTX1_GPIO_INCPIN_INV_PARAM,
MYKONOS_ERR_TPCTX1_GPIO_STEP_INV_PARAM,
MYKONOS_ERR_GETTX2PIN_STEP_NULL_PARM,
MYKONOS_ERR_GETTX2PIN_INC_NULL_PARM,
MYKONOS_ERR_GETTX2PIN_DEC_NULL_PARM,
MYKONOS_ERR_GETTX2PIN_EN_NULL_PARM,
MYKONOS_ERR_GETTX2PIN_TX1TX2_NULL_PARM,
MYKONOS_ERR_GETTX1PIN_STEP_NULL_PARM,
MYKONOS_ERR_GETTX1PIN_INC_NULL_PARM,
MYKONOS_ERR_GETTX1PIN_DEC_NULL_PARM,
MYKONOS_ERR_GETTX1PIN_EN_NULL_PARM,
MYKONOS_ERR_GETTX1PIN_TX1TX2_NULL_PARM,
MYKONOS_ERR_SPI2_INV_GPIO,
MYKONOS_ERR_SPI2_INV_SETUP,
MYKONOS_ERR_SET_GPIO_1V8_INV_POINTER,
MYKONOS_ERR_GETGPIOSETLEVEL_NULL_PARM,
MYKONOS_ERR_READGPIOSPI_NULL_PARM,
MYKONOS_ERR_SET_GPIO_1V8_INV_MODE,
MYKONOS_ERR_GETGPIO_OE_NULL_PARM,
MYKONOS_ERR_GPIO_OE_INV_PARAM,
MYKONOS_ERR_GPIO_SRC_PARAM_INV,
MYKONOS_ERR_GET_GPIO_SOURCE_CONTROL_NULL_PARM,
MYKONOS_ERR_INV_GP_INT_MASK_PARM,
MYKONOS_ERR_GP_INT_STATUS_NULL_PARAM,
MYKONOS_ERR_GETGPIO3V3OUT_NULL_PARM,
MYKONOS_ERR_SET_GPIO_3V3_INV_POINTER,
MYKONOS_ERR_GETGPIO3V3SPI_NULL_PARM,
MYKONOS_ERR_GPIO3V3OUTEN_NULL_PARM,
MYKONOS_ERR_SET_GPIO_3V3_INV_MODE,
MYKONOS_ERR_SET_GPIO_3V3_INV_SRC_CTRL,
MYKONOS_ERR_SET_ARMGPIO_INV_POINTER,
MYKONOS_ERR_SET_ARMGPIO_PINS_ARMERROR,
MYKONOS_ERR_SET_ARMGPIO_PINS_INV_SIGNALID,
MYKONOS_ERR_SET_ARMGPIO_PINS_INV_GPIOPIN,
MYKONOS_ERR_SETUPAUXDAC_NULL_PARAM,
MYKONOS_ERR_WRITEAUXDAC_NULL_AUXIO,
MYKONOS_ERR_READAUXADC_NULL_PARAM,
MYKONOS_ERR_SETUPAUXDAC_INV_AUXDACCODE,
MYKONOS_ERR_WRITEAUXDAC_INV_AUXDACCODE,
MYKONOS_ERR_WRITEAUXDAC_INV_AUXDACINDEX,
MYKONOS_ERR_INV_AUX_ADC_CHAN_PARM,
MYKONOS_ERR_SETUPAUXADC_INV_VCODIV,
MYKONOS_ERR_INV_AUX_ADC_DEC_PARM,
MYKONOS_ERR_GAINCOMP_NULL_STRUCT,
MYKONOS_ERR_GAINCOMP_EN_NULL_PARM,
MYKONOS_ERR_GAINCOMP_SET_NULL_STRUCT,
MYKONOS_ERR_GAINCOMP_INV_RX1_OFFSET,
MYKONOS_ERR_GAINCOMP_INV_RX2_OFFSET,
MYKONOS_ERR_GAINCOMP_INV_STEP,
MYKONOS_ERR_GAINCOMP_INV_EN,
MYKONOS_ERR_OBS_RX_GAINCOMP_SET_NULL_STRUCT,
MYKONOS_ERR_OBS_RX_GAINCOMP_EN_NULL_PARAM,
MYKONOS_ERR_OBS_RX_GAINCOMP_INV_EN,
MYKONOS_ERR_OBS_RX_GAINCOMP_INV_OFFSET,
MYKONOS_ERR_OBS_RX_GAINCOMP_INV_STEP,
MYKONOS_ERR_OBS_RX_GAINCOMP_NULL_STRUCT,
MYKONOS_ERR_SLICER_STEP_OUT_OF_RANGE,
MYKONOS_ERR_SLICER_INV_RX1_SEL,
MYKONOS_ERR_SLICER_INV_RX2_SEL,
MYKONOS_ERR_SLICER_EN_INV,
MYKONOS_ERR_SLICER_RX1PIN_NULL_PARM,
MYKONOS_ERR_SLICER_RX2PIN_NULL_PARM,
MYKONOS_ERR_SLICER_STEP_NULL_PARM,
MYKONOS_ERR_SLICER_EN_NULL_PARM,
MYKONOS_ERR_SLICER_INV_OBS_RX_SEL,
MYKONOS_ERR_SLICER_OBS_RX_STEP_OUT_OF_RANGE,
MYKONOS_ERR_SLICER_OBS_RX_EN_INV,
MYKONOS_ERR_SLICER_OBS_RX_EN_NULL_PARM,
MYKONOS_ERR_SLICER_OBS_RX_STEP_NULL_PARM,
MYKONOS_ERR_SLICER_OBS_RXPIN_NULL_PARM,
MYKONOS_ERR_FLOATFRMT_NULL_STRUCT,
MYKONOS_ERR_FLOATFRMT_SET_NULL_STRUCT,
MYKONOS_ERR_FLOATFRMT_INV_ROUND_MODE,
MYKONOS_ERR_FLOATFRMT_INV_DATA_FORMAT,
MYKONOS_ERR_FLOATFRMT_INV_ENC_NAN,
MYKONOS_ERR_FLOATFRMT_INV_EXP_BITS,
MYKONOS_ERR_FLOATFRMT_INV_LEADING,
MYKONOS_ERR_FLOATFRMT_INV_RX1ATT,
MYKONOS_ERR_FLOATFRMT_INV_RX2ATT,
MYKONOS_ERR_FLOATFRMT_INV_EN,
MYKONOS_ERR_FLOATFRMT_NULL_RX1ATT,
MYKONOS_ERR_FLOATFRMT_NULL_RX2ATT,
MYKONOS_ERR_FLOATFRMT_NULL_ENABLE,
MYKONOS_ERR_FLOATFRMT_SET_INV_EN,
MYKONOS_ERR_FLOATFRMT_SET_INV_RX1ATT,
MYKONOS_ERR_FLOATFRMT_SET_INV_RX2ATT,
MYKONOS_ERR_FLOATFRMT_INV_ORXATT,
MYKONOS_ERR_FLOATFRMT_INV_ORXEN,
MYKONOS_ERR_FLOATFRMT_NULL_ORXATT,
MYKONOS_ERR_FLOATFRMT_NULL_ORXENABLE,
MYKONOS_ERR_SETUPTEMPSENSOR_NULL_PARAM,
MYKONOS_ERR_SETUPTEMPSENSOR_INV_TEMPDECIMATION,
MYKONOS_ERR_SETUPTEMPSENSOR_INV_OFFSET,
MYKONOS_ERR_SETUPTEMPSENSOR_INV_TEMPWINDOW,
MYKONOS_ERR_GETTEMPSENSORCFG_NULL_PARAM,
MYKONOS_ERR_READTEMPSENSOR_NULL_PARAM,
MYKONOS_ERR_READTEMPSENSOR_NOT_LOCKED,
MYKONOS_ERR_GAIN_CONTROL_NOT_HYBRID,
MYKONOS_ERR_GPIO_HYBRID_RX1_PIN,
MYKONOS_ERR_GPIO_HYBRID_RX2_PIN,
MYKONOS_ERR_GPIO_HYBRID_RX1_PIN_NULL_PARM,
MYKONOS_ERR_GPIO_HYBRID_RX2_PIN_NULL_PARM,
MYKONOS_ERR_GPIO_HYBRID_RX1_PIN_READ,
MYKONOS_ERR_GPIO_HYBRID_RX2_PIN_READ,
MYKONOS_ERR_AGC_OBS_NOT_IN_HYBRID,
MYKONOS_ERR_GPIO_HYBRID_ORX_PIN,
MYKONOS_ERR_GPIO_HYBRID_ORX_PIN_NULL_PARM,
MYKONOS_ERR_GAIN_CONTROL_NOT_AGC,
MYKONOS_ERR_GPIO_AGC_SYNC_RX1_PIN,
MYKONOS_ERR_GPIO_AGC_SYNC_RX2_PIN,
MYKONOS_ERR_GPIO_AGC_SYNC_RX1_PIN_NULL_PARM,
MYKONOS_ERR_GPIO_AGC_SYNC_RX2_PIN_NULL_PARM,
MYKONOS_ERR_OBS_GAIN_CONTROL_NOT_AGC,
MYKONOS_ERR_GPIO_AGC_SYNC_ORX_PIN,
MYKONOS_ERR_GPIO_AGC_SYNC_ORX_PIN_NULL_PARM,
MYKONOS_ERR_GETGPIODRV_NULL_PARAM,
MYKONOS_ERR_GPIO_DRV_INV_PARAM,
MYKONOS_ERR_GPIO_SLEW_RATE_INV_PARAM,
MYKONOS_ERR_GPIO_GETSLEW_NULL_PARAM,
MYKONOS_ERR_CMOS_DRV_INV_PARAM,
MYKONOS_ERR_CMOS_DRV_NULL_PARAM
} mykonosGpioErr_t;
/**
* \brief Enum of possible Rx Slicer pin combinations
*/
typedef enum
{
GPIO_0_1_2 = 0, /*!< GPIO combination for RX1 */
GPIO_5_6_7 = 1, /*!< GPIO combination for RX1 or RX2 */
GPIO_8_9_10 = 2, /*!< GPIO combination for RX1 */
GPIO_11_12_13 = 3 /*!< GPIO combination for RX2 */
} mykonosRxSlicer_t;
/**
* \brief Enum of possible observation channel Slicer pin combinations
*/
typedef enum
{
GPIO_18_17_16 = 0, /*!< GPIO combination for observation channel */
GPIO_16_15_14 = 1 /*!< GPIO combination for observation channel */
} mykonosObsRxSlicer_t;
/**
* \brief Enum of possible GPIO slew rate settings
*/
typedef enum
{
MYK_SLEWRATE_NONE = 0, /*!< Lower slew rate for the GPIO */
MYK_SLEWRATE_LOW = 1, /*!< Low slew rate for the GPIO */
MYK_SLEWRATE_MEDIUM = 2, /*!< Medium slew rate for the GPIO */
MYK_SLEWRATE_HIGH = 3 /*!< High slew rate for the GPIO */
} mykonosGpioSlewRate_t;
/**
* \brief Enumerated list of CMOS pads drive strength options
*/
typedef enum
{
MYK_CMOSPAD_DRV_1X = 0x00, /*!< 2.5pF load @ 65MHz */
MYK_CMOSPAD_DRV_2X = 0x01, /*!< 5pF load @ 65MHz */
MYK_CMOSPAD_DRV_3X = 0x03, /*!< 7.5pF load @ 65MHz */
MYK_CMOSPAD_DRV_4X = 0x07, /*!< 10pF load @ 65MHz */
MYK_CMOSPAD_DRV_5X = 0x0F /*!< 12.5pF load @ 65MHz */
} mykonosCmosPadDrvStr_t;
/**
* \brief Enumerated list for Aux ADCs
*/
typedef enum
{
MYK_AUXADC_0 = 0x00, /*!< Aux ADC channel 0 */
MYK_AUXADC_1 = 0x01, /*!< Aux ADC channel 1 */
MYK_AUXADC_2 = 0x02, /*!< Aux ADC channel 2 */
MYK_AUXADC_3 = 0x03, /*!< Aux ADC channel 3 */
MYK_AUXADC_0_DIV2 = 0x04, /*!< Aux ADC channel 0 with the divider by 2 set */
MYK_TEMPSENSOR = 0x10 /*!< Temperature sensor channel */
} mykonosAuxAdcChannels_t;
/**
* \brief Data structure to hold Gain compensation settings for the main receive channels
**/
typedef struct
{
uint8_t rx1Offset; /*!< These parameter contains the Rx1 offset word used for the gain compensation
when the gain index is at its maximum setting.
It has a range of 0 to 0x1F with a resolution is 0.5dB per LSB. */
uint8_t rx2Offset; /*!< These parameter contains the Rx2 offset word used for the gain compensation
when the gain index is at its maximum setting.
It has a range of 0 to 0x1F with a resolution is 0.5dB per LSB. */
uint8_t compStep; /*!< These bits contains the value in dB that the total Rx gain changes
when there is an LSB change in the gain index according to the following settings:
compStep | dB ramp
---------|------------
0 | 0.25dB
1 | 0.5dB
2 | 1.0dB
3 | 2.0dB
4 | 3.0dB
5 | 4.0dB
6 | 6.0dB
7 | Not valid defaulted to 0.25dB */
} mykonosGainComp_t;
/**
* \brief Data structure to hold Gain compensation settings for the observation channel
**/
typedef struct
{
uint8_t obsRxOffset; /*!< These parameter contains the Rx1 offset word used for the gain compensation
when the gain index is at its maximum setting.
It has a range of 0 to 0x1F with a resolution is 0.5dB per LSB. */
uint8_t compStep; /*!< These bits contains the value in dB that the total Rx gain changes
when there is an LSB change in the gain index according to the following settings:
compStep | dB ramp
---------|------------
0 | 0.25dB
1 | 0.5dB
2 | 1.0dB
3 | 2.0dB
4 | 3.0dB
5 | 4.0dB
6 | 6.0dB
7 | Not valid defaulted to 0.25dB */
} mykonosObsRxGainComp_t;
/**
* \brief Data structure to hold floating point formatter settings for the floating point
* number generation
**/
typedef struct
{
uint8_t roundMode; /*!<These parameter set the round modes for the significand.
The following settings are defined in the IEEE754 specification:
roundMode | Round type
----------|-----------------
0 | RoundTiesToEven
1 | RoundTowardsPositive
2 | RoundTowardsNegative
3 | RoundTowardsZero
4 | RoundTiesToAway*/
uint8_t dataFormat; /*!< These parameter sets the format of the 16-bit output on the JESD interface:
Setting this to 1 then the format is from MSB to LSB to {sign, significand, exponent}.
Clearing this bit sets the format to {sign, exponent, significand}.*/
uint8_t encNan; /*!< if this parameter is set to 1 then the floating point formatter reserves the highest value
of exponent for NaN to be compatible to the IEEE754 specification.
Clearing this parameter increases the range of the exponent by one.*/
uint8_t expBits; /*!<These parameter is used to indicate the number of exponent bits in the floating point number
according to the following settings:
expBits| Round type
--------|------------------------------------------------
0 | 2 bit exponent, 13 bit significand, 1 bit sign
1 | 3 bit exponent, 12 bit significand, 1 bit sign
2 | 4 bit exponent, 11 bit significand, 1 bit sign
3 | 5 bit exponent, 10 bit significand, 1 bit sign */
uint8_t leading; /*!< Setting this parameter hides the leading one in the the significand to be compatible to the IEEE754 specification.
Clearing this parameter causes the leading one to be at the MSB of the significand.*/
}mykonosFloatPntFrmt_t;
/**
* \brief Data structure used to configure the on-die Temperature Sensor
*/
typedef struct
{
uint8_t tempDecimation; /*!<3-bit value that controls the AuxADC decimation factor when used for temp sensor calculations;
AuxADC_decimation = 256 * 2^tempDecimation */
uint8_t offset; /*!< 8-bit offset that gets added to temp sensor code internally */
uint8_t overrideFusedOffset; /*!< This bit overrides the factory-calibrated fuse offset
and uses the value stored in the offset member */
uint8_t tempWindow; /*!< 4-bit code with a resolution of 1?C/LSB, each time a temperature measurement is performed,
the device compares the current temperature against the previous value.*/
}mykonosTempSensorConfig_t;
/**
* \brief Data structure used to store Temperature Sensor related values
*/
typedef struct
{
int16_t tempCode; /*!< 16-bit signed temperature value (in deg C) that is read back */
uint8_t windowExceeded; /*!< If the absolute value of the difference is greater than the value in temperature configuration
tempWindow, the windowExceeded flag is set.*/
uint8_t windowHiLo; /*!<when windowExceeded member gets set,
this bit is set to 1 if current value is greater than previous value, else reset */
uint8_t tempValid; /*!< When the reading is complete and a valid temperature value stored in tempCode*/
}mykonosTempSensorStatus_t;
#ifdef __cplusplus
}
#endif
#endif /* T_MYKONOSGPIO_H_ */
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/parameters.h
+82
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@@ -0,0 +1,82 @@
/***************************************************************************//**
* @file ad9371/src/devices/adi_hal/parameters.h
* @brief Platform dependent parameters.
* @author DBogdan ([email protected])
********************************************************************************
* Copyright 2019(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef _PARAMETERS_H_
#define _PARAMETERS_H_
/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
#include "platform_drivers.h"
#include "xparameters.h"
/******************************************************************************/
/********************** Macros and Constants Definitions **********************/
/******************************************************************************/
#define DDR_MEM_BASEADDR XPAR_DDR_MEM_BASEADDR
#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
#define GPIO_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
//#define FREQ_CTRL_DEVICE_ID XPAR_AXI_9731_FREQ_CTRL_DEVICE_ID
//#define GAIN_CTRL_DEVICE_ID XPAR_AXI_9731_RX_GAIN_DEVICE_ID
//#define ATTN_CTRL_DEVICE_ID XPAR_AXI_9731_TX_ATTN_DEVICE_ID
//
//#define FREQ_CTRL_INTR_ID XPAR_FABRIC_AXI_9731_FREQ_CTRL_IP2INTC_IRPT_INTR
//#define GAIN_CTRL_INTR_ID XPAR_FABRIC_AXI_9731_RX_GAIN_IP2INTC_IRPT_INTR
//#define ATTN_CTRL_INTR_ID XPAR_FABRIC_AXI_9731_TX_ATTN_IP2INTC_IRPT_INTR
#define GPIO_OFFSET 54
#define AD9528_CS 1
#define AD9371_CS 2
#define TX_FREQ_INTR_MASK XGPIO_IR_CH1_MASK
#define RX_FREQ_INTR_MASK XGPIO_IR_CH2_MASK
#define TX1_ATTN_INTR_MASK XGPIO_IR_CH1_MASK
#define TX2_ATTN_INTR_MASK XGPIO_IR_CH2_MASK
#define RX1_ATTN_INTR_MASK XGPIO_IR_CH1_MASK
#define RX2_ATTN_INTR_MASK XGPIO_IR_CH2_MASK
#define AXI_GPIO_BANK_1 1
#define AXI_GPIO_BANK_2 2
//#define DAC_GPIO_PLDDR_BYPASS GPIO_OFFSET + 60
#define AD9528_RESET_B GPIO_OFFSET + 4
#define AD9528_SYSREF_REQ GPIO_OFFSET + 3
#define AD9371_RESET_B GPIO_OFFSET + 1
#endif
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/platform_drivers.c
+497
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@@ -0,0 +1,497 @@
/***************************************************************************//**
* @file platform_drivers.c
* @brief Implementation of Xilinx Platform Drivers.
* @author DBogdan ([email protected])
********************************************************************************
* Copyright 2018(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
#include <stdlib.h>
#include <sleep.h>
#include "platform_drivers.h"
/******************************************************************************/
/************************ Functions Definitions *******************************/
/******************************************************************************/
/**
* @brief Initialize the I2C communication peripheral.
* @param desc - The I2C descriptor.
* @param init_param - The structure that contains the I2C parameters.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t i2c_init(struct i2c_desc **desc,
const struct i2c_init_param *param)
{
if (desc) {
// Unused variable - fix compiler warning
}
if (param->type) {
// Unused variable - fix compiler warning
}
return SUCCESS;
}
/**
* @brief Free the resources allocated by i2c_init().
* @param desc - The I2C descriptor.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t i2c_remove(struct i2c_desc *desc)
{
if (desc) {
// Unused variable - fix compiler warning
}
return SUCCESS;
}
/**
* @brief Write data to a slave device.
* @param desc - The I2C descriptor.
* @param data - Buffer that stores the transmission data.
* @param bytes_number - Number of bytes to write.
* @param stop_bit - Stop condition control.
* Example: 0 - A stop condition will not be generated;
* 1 - A stop condition will be generated.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t i2c_write(struct i2c_desc *desc,
uint8_t *data,
uint8_t bytes_number,
uint8_t stop_bit)
{
if (desc) {
// Unused variable - fix compiler warning
}
if (data) {
// Unused variable - fix compiler warning
}
if (bytes_number) {
// Unused variable - fix compiler warning
}
if (stop_bit) {
// Unused variable - fix compiler warning
}
return SUCCESS;
}
/**
* @brief Read data from a slave device.
* @param desc - The I2C descriptor.
* @param data - Buffer that will store the received data.
* @param bytes_number - Number of bytes to read.
* @param stop_bit - Stop condition control.
* Example: 0 - A stop condition will not be generated;
* 1 - A stop condition will be generated.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t i2c_read(struct i2c_desc *desc,
uint8_t *data,
uint8_t bytes_number,
uint8_t stop_bit)
{
if (desc) {
// Unused variable - fix compiler warning
}
if (data) {
// Unused variable - fix compiler warning
}
if (bytes_number) {
// Unused variable - fix compiler warning
}
if (stop_bit) {
// Unused variable - fix compiler warning
}
return SUCCESS;
}
/**
* @brief Initialize the SPI communication peripheral.
* @param desc - The SPI descriptor.
* @param init_param - The structure that contains the SPI parameters.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t spi_init(struct spi_desc **desc,
const struct spi_init_param *param)
{
spi_desc *descriptor;
int32_t ret;
descriptor = (struct spi_desc *) calloc(1, sizeof(*descriptor));
if (!descriptor)
return FAILURE;
descriptor->mode = param->mode;
descriptor->chip_select = param->chip_select;
descriptor->flags = param->flags;
#ifdef _XPARAMETERS_PS_H_
descriptor->config = XSpiPs_LookupConfig(param->id);
if (descriptor->config == NULL)
goto error;
ret = XSpiPs_CfgInitialize(&descriptor->instance,
descriptor->config, descriptor->config->BaseAddress);
if (ret != 0)
goto error;
XSpiPs_SetOptions(&descriptor->instance,
XSPIPS_MASTER_OPTION |
((descriptor->flags & SPI_CS_DECODE) ?
XSPIPS_DECODE_SSELECT_OPTION : 0) |
XSPIPS_FORCE_SSELECT_OPTION |
((descriptor->mode & SPI_CPOL) ?
XSPIPS_CLK_ACTIVE_LOW_OPTION : 0) |
((descriptor->mode & SPI_CPHA) ?
XSPIPS_CLK_PHASE_1_OPTION : 0));
XSpiPs_SetClkPrescaler(&descriptor->instance,
XSPIPS_CLK_PRESCALE_64);
XSpiPs_SetSlaveSelect(&descriptor->instance, 0xf);
#else
ret = XSpi_Initialize(&descriptor->instance, param->id);
if (ret != 0)
goto error;
XSpi_SetOptions(&descriptor->instance,
XSP_MASTER_OPTION |
((descriptor->mode & SPI_CPOL) ?
XSP_CLK_ACTIVE_LOW_OPTION : 0) |
((descriptor->mode & SPI_CPHA) ?
XSP_CLK_PHASE_1_OPTION : 0));
XSpi_Start(&descriptor->instance);
XSpi_IntrGlobalDisable(&descriptor->instance);
#endif
*desc = descriptor;
return SUCCESS;
error:
free(descriptor);
return FAILURE;
}
/**
* @brief Free the resources allocated by spi_init().
* @param desc - The SPI descriptor.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t spi_remove(struct spi_desc *desc)
{
if (desc) {
// Unused variable - fix compiler warning
}
return SUCCESS;
}
/**
* @brief Write and read data to/from SPI.
* @param desc - The SPI descriptor.
* @param data - The buffer with the transmitted/received data.
* @param bytes_number - Number of bytes to write/read.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t spi_write_and_read(struct spi_desc *desc,
uint8_t *data,
uint8_t bytes_number)
{
#ifdef _XPARAMETERS_PS_H_
XSpiPs_SetOptions(&desc->instance,
XSPIPS_MASTER_OPTION |
((desc->flags & SPI_CS_DECODE) ?
XSPIPS_DECODE_SSELECT_OPTION : 0) |
XSPIPS_FORCE_SSELECT_OPTION |
((desc->mode & SPI_CPOL) ?
XSPIPS_CLK_ACTIVE_LOW_OPTION : 0) |
((desc->mode & SPI_CPHA) ?
XSPIPS_CLK_PHASE_1_OPTION : 0));
XSpiPs_SetSlaveSelect(&desc->instance, desc->chip_select);
// 0xf & ~desc->chip_select);
XSpiPs_PolledTransfer(&desc->instance,
data, data, bytes_number);
#else
XSpi_SetOptions(&desc->instance,
XSP_MASTER_OPTION |
((desc->mode & SPI_CPOL) ?
XSP_CLK_ACTIVE_LOW_OPTION : 0) |
((desc->mode & SPI_CPHA) ?
XSP_CLK_PHASE_1_OPTION : 0));
XSpi_SetSlaveSelect(&desc->instance,
desc->chip_select);
XSpi_Transfer(&desc->instance,
data, data, bytes_number);
#endif
return 0;
}
/**
* @brief Obtain the GPIO decriptor.
* @param desc - The GPIO descriptor.
* @param gpio_number - The number of the GPIO.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t gpio_get(struct gpio_desc **desc,
uint8_t gpio_number)
{
gpio_desc *descriptor;
int32_t ret;
descriptor = (struct gpio_desc *) malloc(sizeof(*descriptor));
if (!descriptor)
return FAILURE;
#ifdef _XPARAMETERS_PS_H_
descriptor->config = XGpioPs_LookupConfig(0);
if (descriptor->config == NULL)
goto error;
ret = XGpioPs_CfgInitialize(&descriptor->instance,
descriptor->config, descriptor->config->BaseAddr);
if (ret != 0)
goto error;
#else
ret = XGpio_Initialize(&descriptor->instance, 0);
if (ret != 0)
goto error;
#endif
descriptor->number = gpio_number;
*desc = descriptor;
return SUCCESS;
error:
free(descriptor);
return FAILURE;
}
/**
* @brief Free the resources allocated by gpio_get().
* @param desc - The SPI descriptor.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t gpio_remove(struct gpio_desc *desc)
{
if (desc) {
// Unused variable - fix compiler warning
}
return SUCCESS;
}
/**
* @brief Enable the input direction of the specified GPIO.
* @param desc - The GPIO descriptor.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t gpio_direction_input(struct gpio_desc *desc)
{
if (desc) {
// Unused variable - fix compiler warning
}
return 0;
}
/**
* @brief Enable the output direction of the specified GPIO.
* @param desc - The GPIO descriptor.
* @param value - The value.
* Example: GPIO_HIGH
* GPIO_LOW
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t gpio_direction_output(struct gpio_desc *desc,
uint8_t value)
{
#ifdef _XPARAMETERS_PS_H_
XGpioPs_SetDirectionPin(&desc->instance, desc->number, 1);
XGpioPs_SetOutputEnablePin(&desc->instance, desc->number, 1);
XGpioPs_WritePin(&desc->instance, desc->number, value);
#else
uint8_t pin = desc->number;
uint8_t channel;
uint32_t reg_val;
if (pin >= 32) {
channel = 2;
pin -= 32;
} else
channel = 1;
reg_val = XGpio_GetDataDirection(&desc->instance, channel);
reg_val &= ~(1 << pin);
XGpio_SetDataDirection(&desc->instance, channel, reg_val);
reg_val = XGpio_DiscreteRead(&desc->instance, channel);
if(value)
reg_val |= (1 << pin);
else
reg_val &= ~(1 << pin);
XGpio_DiscreteWrite(&desc->instance, channel, reg_val);
#endif
return SUCCESS;
}
/**
* @brief Get the direction of the specified GPIO.
* @param desc - The GPIO descriptor.
* @param direction - The direction.
* Example: GPIO_OUT
* GPIO_IN
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t gpio_get_direction(struct gpio_desc *desc,
uint8_t *direction)
{
if (desc) {
// Unused variable - fix compiler warning
}
if (direction) {
// Unused variable - fix compiler warning
}
return 0;
}
/**
* @brief Set the value of the specified GPIO.
* @param desc - The GPIO descriptor.
* @param value - The value.
* Example: GPIO_HIGH
* GPIO_LOW
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t gpio_set_value(struct gpio_desc *desc,
uint8_t value)
{
#ifdef _XPARAMETERS_PS_H_
XGpioPs_WritePin(&desc->instance, desc->number, value);
#else
uint8_t pin = desc->number;
uint8_t channel;
uint32_t reg_val;
if (pin >= 32) {
channel = 2;
pin -= 32;
} else
channel = 1;
reg_val = XGpio_DiscreteRead(&desc->instance, channel);
if(value)
reg_val |= (1 << pin);
else
reg_val &= ~(1 << pin);
XGpio_DiscreteWrite(&desc->instance, channel, reg_val);
#endif
return 0;
}
/**
* @brief Get the value of the specified GPIO.
* @param desc - The GPIO descriptor.
* @param value - The value.
* Example: GPIO_HIGH
* GPIO_LOW
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t gpio_get_value(struct gpio_desc *desc,
uint8_t *value)
{
if (desc) {
// Unused variable - fix compiler warning
}
if (value) {
// Unused variable - fix compiler warning
}
return 0;
}
/**
* @brief Generate microseconds delay.
* @param usecs - Delay in microseconds.
* @return None.
*/
void udelay(uint32_t usecs)
{
usleep(usecs);
}
/**
* @brief Generate miliseconds delay.
* @param msecs - Delay in miliseconds.
* @return None.
*/
void mdelay(uint32_t msecs)
{
#ifdef _XPARAMETERS_PS_H_
usleep(msecs * 1000);
#else
usleep(msecs * 50); // FIXME
#endif
}
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/hardware/platform_drivers.h
+223
View File
@@ -0,0 +1,223 @@
/***************************************************************************//**
* @file platform_drivers.h
* @brief Header file of Xilinx Platform Drivers.
* @author DBogdan ([email protected])
********************************************************************************
* Copyright 2018(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef PLATFORM_DRIVERS_H_
#define PLATFORM_DRIVERS_H_
/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
#include <stdint.h>
#include <xparameters.h>
#ifdef _XPARAMETERS_PS_H_
#include <xspips.h>
#include <xgpiops.h>
#else
#include <xspi.h>
#include <xgpio.h>
#endif
/******************************************************************************/
/********************** Macros and Constants Definitions **********************/
/******************************************************************************/
#define SUCCESS 0
#define FAILURE -1
#define SPI_CPHA 0x01
#define SPI_CPOL 0x02
#define SPI_CS_DECODE 0x01
#define SPI_CS_DECODE_DISABLE 0x00
#define GPIO_OUT 0x01
#define GPIO_IN 0x00
#define GPIO_HIGH 0x01
#define GPIO_LOW 0x00
/******************************************************************************/
/*************************** Types Declarations *******************************/
/******************************************************************************/
typedef enum i2c_type {
XILINX_I2C
} i2c_type;
typedef struct i2c_init_param {
enum i2c_type type;
uint32_t id;
uint32_t max_speed_hz;
uint8_t slave_address;
} i2c_init_param;
typedef struct i2c_desc {
enum i2c_type type;
uint32_t id;
uint32_t max_speed_hz;
uint8_t slave_address;
} i2c_desc;
typedef enum spi_type {
XILINX_SPI
} spi_type;
/**
* @enum spi_mode
* @brief SPI configuration for clock phase and polarity.
*/
typedef enum spi_mode {
/** Data on rising, shift out on falling */
SPI_MODE_0 = (0 | 0),
/** Data on falling, shift out on rising */
SPI_MODE_1 = (0 | SPI_CPHA),
/** Data on falling, shift out on rising */
SPI_MODE_2 = (SPI_CPOL | 0),
/** Data on rising, shift out on falling */
SPI_MODE_3 = (SPI_CPOL | SPI_CPHA)
} spi_mode;
typedef struct spi_init_param {
enum spi_type type;
uint32_t id;
uint32_t max_speed_hz;
enum spi_mode mode;
uint8_t chip_select;
uint32_t flags;
} spi_init_param;
typedef struct spi_desc {
enum spi_type type;
uint32_t id;
uint32_t max_speed_hz;
enum spi_mode mode;
uint8_t chip_select;
uint32_t flags;
#ifdef _XPARAMETERS_PS_H_
XSpiPs_Config *config;
XSpiPs instance;
#else
XSpi instance;
#endif
} spi_desc;
typedef enum gpio_type {
XILINX_GPIO
} gpio_type;
typedef struct gpio_desc {
enum gpio_type type;
uint32_t id;
uint8_t number;
#ifdef _XPARAMETERS_PS_H_
XGpioPs_Config *config;
XGpioPs instance;
#else
XGpio instance;
#endif
} gpio_desc;
/******************************************************************************/
/************************ Functions Declarations ******************************/
/******************************************************************************/
/* Initialize the I2C communication peripheral. */
int32_t i2c_init(struct i2c_desc **desc,
const struct i2c_init_param *param);
/* Free the resources allocated by i2c_init(). */
int32_t i2c_remove(struct i2c_desc *desc);
/* Write data to a slave device. */
int32_t i2c_write(struct i2c_desc *desc,
uint8_t *data,
uint8_t bytes_number,
uint8_t stop_bit);
/* Read data from a slave device. */
int32_t i2c_read(struct i2c_desc *desc,
uint8_t *data,
uint8_t bytes_number,
uint8_t stop_bit);
/* Initialize the SPI communication peripheral. */
int32_t spi_init(struct spi_desc **desc,
const struct spi_init_param *param);
/* Free the resources allocated by spi_init() */
int32_t spi_remove(struct spi_desc *desc);
/* Write and read data to/from SPI. */
int32_t spi_write_and_read(struct spi_desc *desc,
uint8_t *data,
uint8_t bytes_number);
/* Obtain the GPIO decriptor. */
int32_t gpio_get(struct gpio_desc **desc,
uint8_t gpio_number);
/* Free the resources allocated by gpio_get() */
int32_t gpio_remove(struct gpio_desc *desc);
/* Enable the input direction of the specified GPIO. */
int32_t gpio_direction_input(struct gpio_desc *desc);
/* Enable the output direction of the specified GPIO. */
int32_t gpio_direction_output(struct gpio_desc *desc,
uint8_t value);
/* Get the direction of the specified GPIO. */
int32_t gpio_get_direction(struct gpio_desc *desc,
uint8_t *direction);
/* Set the value of the specified GPIO. */
int32_t gpio_set_value(struct gpio_desc *desc,
uint8_t value);
/* Get the value of the specified GPIO. */
int32_t gpio_get_value(struct gpio_desc *desc,
uint8_t *value);
/* Generate microseconds delay. */
void udelay(uint32_t usecs);
/* Generate miliseconds delay. */
void mdelay(uint32_t msecs);
#endif // PLATFORM_DRIVERS_H_
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/lscript.ld
+288
View File
@@ -0,0 +1,288 @@
/*******************************************************************/
/* */
/* This file is automatically generated by linker script generator.*/
/* */
/* Version: 2019.1.3 */
/* */
/* Copyright (c) 2010-2016 Xilinx, Inc. All rights reserved. */
/* */
/* Description : Cortex-A9 Linker Script */
/* */
/*******************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
/* Define Memories in the system */
MEMORY
{
ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x1FF00000
ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x1000000
ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
}
/* Specify the default entry point to the program */
ENTRY(_vector_table)
/* Define the sections, and where they are mapped in memory */
SECTIONS
{
.text : {
KEEP (*(.vectors))
*(.boot)
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
*(.plt)
*(.gnu_warning)
*(.gcc_execpt_table)
*(.glue_7)
*(.glue_7t)
*(.vfp11_veneer)
*(.ARM.extab)
*(.gnu.linkonce.armextab.*)
} > ps7_ddr_0
.init : {
KEEP (*(.init))
} > ps7_ddr_0
.fini : {
KEEP (*(.fini))
} > ps7_ddr_0
.rodata : {
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
} > ps7_ddr_0
.rodata1 : {
__rodata1_start = .;
*(.rodata1)
*(.rodata1.*)
__rodata1_end = .;
} > ps7_ddr_0
.sdata2 : {
__sdata2_start = .;
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
__sdata2_end = .;
} > ps7_ddr_0
.sbss2 : {
__sbss2_start = .;
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
__sbss2_end = .;
} > ps7_ddr_0
.data : {
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.jcr)
*(.got)
*(.got.plt)
__data_end = .;
} > ps7_ddr_0
.data1 : {
__data1_start = .;
*(.data1)
*(.data1.*)
__data1_end = .;
} > ps7_ddr_0
.got : {
*(.got)
} > ps7_ddr_0
.ctors : {
__CTOR_LIST__ = .;
___CTORS_LIST___ = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
} > ps7_ddr_0
.dtors : {
__DTOR_LIST__ = .;
___DTORS_LIST___ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
___DTORS_END___ = .;
} > ps7_ddr_0
.fixup : {
__fixup_start = .;
*(.fixup)
__fixup_end = .;
} > ps7_ddr_0
.eh_frame : {
*(.eh_frame)
} > ps7_ddr_0
.eh_framehdr : {
__eh_framehdr_start = .;
*(.eh_framehdr)
__eh_framehdr_end = .;
} > ps7_ddr_0
.gcc_except_table : {
*(.gcc_except_table)
} > ps7_ddr_0
.mmu_tbl (ALIGN(16384)) : {
__mmu_tbl_start = .;
*(.mmu_tbl)
__mmu_tbl_end = .;
} > ps7_ddr_0
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidix.*.*)
__exidx_end = .;
} > ps7_ddr_0
.preinit_array : {
__preinit_array_start = .;
KEEP (*(SORT(.preinit_array.*)))
KEEP (*(.preinit_array))
__preinit_array_end = .;
} > ps7_ddr_0
.init_array : {
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
} > ps7_ddr_0
.fini_array : {
__fini_array_start = .;
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
__fini_array_end = .;
} > ps7_ddr_0
.ARM.attributes : {
__ARM.attributes_start = .;
*(.ARM.attributes)
__ARM.attributes_end = .;
} > ps7_ddr_0
.sdata : {
__sdata_start = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
} > ps7_ddr_0
.sbss (NOLOAD) : {
__sbss_start = .;
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
__sbss_end = .;
} > ps7_ddr_0
.tdata : {
__tdata_start = .;
*(.tdata)
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
} > ps7_ddr_0
.tbss : {
__tbss_start = .;
*(.tbss)
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
} > ps7_ddr_0
.bss (NOLOAD) : {
__bss_start = .;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
__bss_end = .;
} > ps7_ddr_0
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
/* Generate Stack and Heap definitions */
.heap (NOLOAD) : {
. = ALIGN(16);
_heap = .;
HeapBase = .;
_heap_start = .;
. += _HEAP_SIZE;
_heap_end = .;
HeapLimit = .;
} > ps7_ddr_0
.stack (NOLOAD) : {
. = ALIGN(16);
_stack_end = .;
. += _STACK_SIZE;
. = ALIGN(16);
_stack = .;
__stack = _stack;
. = ALIGN(16);
_irq_stack_end = .;
. += _IRQ_STACK_SIZE;
. = ALIGN(16);
__irq_stack = .;
_supervisor_stack_end = .;
. += _SUPERVISOR_STACK_SIZE;
. = ALIGN(16);
__supervisor_stack = .;
_abort_stack_end = .;
. += _ABORT_STACK_SIZE;
. = ALIGN(16);
__abort_stack = .;
_fiq_stack_end = .;
. += _FIQ_STACK_SIZE;
. = ALIGN(16);
__fiq_stack = .;
_undef_stack_end = .;
. += _UNDEF_STACK_SIZE;
. = ALIGN(16);
__undef_stack = .;
} > ps7_ddr_0
_end = .;
}
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj/src/main.c
+60
View File
@@ -0,0 +1,60 @@
/*****************************************************************************/
/**
* Description: main.c
*
* Author: Fan Hao
* Date: 2021-11-13 13:19
* Last Editors: Fan Hao
* Last Edit Time: [2022-03-28 20:32]
*
* Revisions: Rev 0.0
* History:
* [2021-11-13]: Initial edition.
* [2022-03-28]: Add bit error test mode.
*
* Copyright(c) 2021 Beijing Institute of Technology.
* Lab of Communication and Networking
*
******************************************************************************/
/***************************** Include Files *********************************/
#include <stdint.h>
#include "xscugic.h" // The generic interrupt controller driver component
#include "xil_exception.h" // ARM Cortex A9 specific exception related APIs
#include "sleep.h" // Sleep APIs for Cortex A9
#include "xil_cache.h"
#include "hardware/headless.h"
/************************** Constant Definitions *****************************/
/************************** Function Prototypes ******************************/
/*********************** Driver Instance Definitions **************************/
/*****************************************************************************/
/**
* @brief Main function, initialize all the device needed, initialize
* interrupt system, halt in while(1) wait for event interrupt.
*
* @param None.
*
* @return
*
******************************************************************************/
int main(void) {
int Status;
Xil_ICacheEnable();
Xil_DCacheDisable();
Status = HARDWARE_initialize();
if (Status == SUCCESS) {
xil_printf("Hardware Init SUCCESS! \r\n");
}
else {
xil_printf("Hardware Init FAILED! \r\n");
}
return Status;
} // main
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj_bsp/.cproject
+13
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@@ -0,0 +1,13 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="org.eclipse.cdt.core.default.config.764086390">
<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.764086390" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
<externalSettings/>
<extensions/>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
</cproject>
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj_bsp/.project
+75
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@@ -0,0 +1,75 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>dl814_dj_bsp</name>
<comment>Created by SDK v2019.1</comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.make.core.makeBuilder</name>
<arguments>
<dictionary>
<key>org.eclipse.cdt.core.errorOutputParser</key>
<value>org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.append_environment</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.arguments</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.command</key>
<value>make</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.target.auto</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.target.clean</key>
<value>clean</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.target.inc</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.environment</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.stopOnError</key>
<value>false</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
<value>true</value>
</dictionary>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.xilinx.sdk.sw.SwProjectNature</nature>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.make.core.makeNature</nature>
</natures>
</projectDescription>
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj_bsp/.sdkproject
+4
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@@ -0,0 +1,4 @@
THIRPARTY=false
HW_PROJECT_REFERENCE=system_top_hw_platform_0
PROCESSOR=ps7_cortexa9_0
MSS_FILE=system.mss
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj_bsp/Makefile
+35
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@@ -0,0 +1,35 @@
# Makefile generated by Xilinx.
PROCESSOR = ps7_cortexa9_0
LIBRARIES = ${PROCESSOR}/lib/libxil.a
BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)
SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES))
ifneq (,$(findstring win,$(RDI_PLATFORM)))
SHELL = CMD
endif
all: libs
@echo 'Finished building libraries'
include: $(addsuffix /make.include,$(SUBDIRS))
libs: $(addsuffix /make.libs,$(SUBDIRS))
clean: $(addsuffix /make.clean,$(SUBDIRS))
$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
cp -f $< $@
%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
@echo "Running Make include in $(subst /make.include,,$@)"
$(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
%/make.libs: include
@echo "Running Make libs in $(subst /make.libs,,$@)"
$(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
%/make.clean:
$(MAKE) -C $(subst /make.clean,,$@) -s clean
clean:
rm -f ${PROCESSOR}/lib/libxil.a
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/dl814_dj_bsp/system.mss
+225
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@@ -0,0 +1,225 @@
PARAMETER VERSION = 2.2.0
BEGIN OS
PARAMETER OS_NAME = standalone
PARAMETER OS_VER = 7.0
PARAMETER PROC_INSTANCE = ps7_cortexa9_0
PARAMETER stdin = ps7_uart_1
PARAMETER stdout = ps7_uart_1
END
BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu_cortexa9
PARAMETER DRIVER_VER = 2.7
PARAMETER HW_INSTANCE = ps7_cortexa9_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = jesd204b_jesd204_phy
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = jesd204b_jesd204_rx
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = jesd204b_jesd204_tx
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_afi_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_afi_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_afi_2
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_afi_3
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = coresightps_dcc
PARAMETER DRIVER_VER = 1.5
PARAMETER HW_INSTANCE = ps7_coresight_comp_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ddrps
PARAMETER DRIVER_VER = 1.0
PARAMETER HW_INSTANCE = ps7_ddr_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_ddrc_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = devcfg
PARAMETER DRIVER_VER = 3.5
PARAMETER HW_INSTANCE = ps7_dev_cfg_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = dmaps
PARAMETER DRIVER_VER = 2.4
PARAMETER HW_INSTANCE = ps7_dma_ns
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = dmaps
PARAMETER DRIVER_VER = 2.4
PARAMETER HW_INSTANCE = ps7_dma_s
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_globaltimer_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpiops
PARAMETER DRIVER_VER = 3.5
PARAMETER HW_INSTANCE = ps7_gpio_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_gpv_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_intc_dist_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_iop_bus_config_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_l2cachec_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_ocmc_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_pl310_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_pmu_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = qspips
PARAMETER DRIVER_VER = 3.6
PARAMETER HW_INSTANCE = ps7_qspi_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_qspi_linear_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_ram_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_ram_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_scuc_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = scugic
PARAMETER DRIVER_VER = 4.0
PARAMETER HW_INSTANCE = ps7_scugic_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = scutimer
PARAMETER DRIVER_VER = 2.1
PARAMETER HW_INSTANCE = ps7_scutimer_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = scuwdt
PARAMETER DRIVER_VER = 2.1
PARAMETER HW_INSTANCE = ps7_scuwdt_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 2.0
PARAMETER HW_INSTANCE = ps7_slcr_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = spips
PARAMETER DRIVER_VER = 3.2
PARAMETER HW_INSTANCE = ps7_spi_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartps
PARAMETER DRIVER_VER = 3.7
PARAMETER HW_INSTANCE = ps7_uart_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = xadcps
PARAMETER DRIVER_VER = 2.3
PARAMETER HW_INSTANCE = ps7_xadc_0
END
projects/datalink_814/dl814_dj_48m/project/dl814_dj_48m/dl814_dj_48m.sdk/system_top.hdf
BIN
View File
Binary file not shown.
projects/datalink_814/dl814_dj_48m/rtl/system_top.v
+8 -10
View File
@@ -343,24 +343,22 @@ assign tx_2_q = tx_data_q;
// <--------------------------------------------------------------------------->
// <--------------------- insert transmitter logic below ---------------------->
// <--------------------------------------------------------------------------->
wire [ 1:0] waveform_sel;
wire [ 2:0] waveform_sel;
wire sweep_on ;
wire [31:0] freq_set ;
wire [ 1:0] iq_sel ;
wire [ 3:0] bb_rshift ;
tx_qpsk #(
.DATA_WIDTH (16 ),
.CLK_FREQ (122880000 ),
.SQUARE_INTERP (32 )
) u_tx_qpsk
tx_control u_tx_wave
(
.clk (sys_clk ), // input clk
.rst (sys_rst ), // input rst
.sys_clk (sys_clk ), // input sys_clk
.sys_rst (sys_rst ), // input sys_rst
.sig_clk (sig_clk ), // input sig_clk
.sig_rst (sig_rst ), // input sig_rst
.tx_data_i (tx_data_i ), // output [15:0] tx_data_i
.tx_data_q (tx_data_q ), // output [15:0] tx_data_q
// debug ports
.waveform_sel (waveform_sel ), // input [ 1:0] waveform_sel
.waveform_sel (waveform_sel ), // input [ 2:0] waveform_sel
.sweep_on (sweep_on ), // input sweep_on
.freq_set (freq_set ), // input [31:0] freq_set
.iq_sel (iq_sel ), // input [ 1:0] iq_sel
@@ -418,7 +416,7 @@ ila_ctrl_signal u_ila_ctrl_signal
vio_manual_ctrl u_vio_manual_ctrl
(
.clk (sys_clk ), // input wire clk
.probe_out0 (waveform_sel ), // output wire [1 : 0] probe_out0
.probe_out0 (waveform_sel ), // output wire [2 : 0] probe_out0
.probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1
.probe_out2 (freq_set ), // output wire [31 : 0] probe_out2
.probe_out3 (iq_sel ), // output wire [1 : 0] probe_out3
projects/datalink_814/dl814_dj_48m/rtl/tx_control.v
+101
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@@ -0,0 +1,101 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/03/21 18:35:38
// Design Name:
// Module Name: tx_control
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tx_control
(
input sys_clk , // 122.88MHz
input sys_rst ,
input sig_clk , // 48MHz
input sig_rst ,
output [15:0] tx_data_i ,
output [15:0] tx_data_q ,
// debug ports
input [ 2:0] waveform_sel ,
input sweep_on ,
input [31:0] freq_set ,
input [ 1:0] iq_sel ,
input [ 3:0] bb_rshift
);
// pn seq
wire [15:0] tx_pn_seq_i;
wire [15:0] tx_pn_seq_q;
tx_pn_seq_6mcps #(
.DATA_WIDTH (16)
) u_tx_pn_seq
(
.sys_clk (sys_clk ), // 122.88MHz
.sys_rst (sys_rst ),
.sig_clk (sig_clk ), // 48MHz
.sig_rst (sig_rst ),
.tx_data_i (tx_pn_seq_i),
.tx_data_q (tx_pn_seq_q)
);
// qpsk
wire [15:0] tx_qpsk_i;
wire [15:0] tx_qpsk_q;
tx_qpsk #(
.DATA_WIDTH (16 ),
.SQUARE_INTERP (32 ),
.CLK_FREQ (122880000 )
) u_tx_qpsk
(
.clk (sys_clk ),
.rst (sys_rst ),
.tx_data_i (tx_qpsk_i ),
.tx_data_q (tx_qpsk_q ),
// debug ports
.waveform_sel (waveform_sel[1:0] ),
.sweep_on (sweep_on ),
.freq_set (freq_set ),
.iq_sel (iq_sel ),
.bb_rshift (bb_rshift )
);
// output
reg [15:0] tx_data_buf_i = 'b0;
reg [15:0] tx_data_buf_q = 'b0;
assign tx_data_i = tx_data_buf_i;
assign tx_data_q = tx_data_buf_q;
always @(posedge sys_clk) begin
if (sys_rst) begin
tx_data_buf_i <= 'b0;
tx_data_buf_q <= 'b0;
end
else if (waveform_sel) begin
tx_data_buf_i <= tx_pn_seq_i;
tx_data_buf_q <= tx_pn_seq_q;
end
else begin
tx_data_buf_i <= tx_qpsk_i;
tx_data_buf_q <= tx_qpsk_q;
end
end
endmodule
projects/datalink_814/dl814_dj_48m/rtl/tx_pn_seq_6mcps.v
+3 -3
View File
@@ -93,7 +93,7 @@ always @(posedge sig_clk) begin
end
end
else begin
hsq_wave[0] <= hsq_data ? {1'b0,{(MAX_DATA_WIDTH-2){1'b1}},1'b1} : {1'b1,{(MAX_DATA_WIDTH-2){1'b0}},1'b0};
hsq_wave[0] <= hsq_data ? {1'b0,{(MAX_DATA_WIDTH-2){1'b1}},1'b1} : {1'b1,{(MAX_DATA_WIDTH-2){1'b0}},1'b1};
hsq_wave[1] <= hsq_data ? {1'b1,{(MAX_DATA_WIDTH-2){1'b0}},1'b1} : {1'b0,{(MAX_DATA_WIDTH-2){1'b1}},1'b1};
end
end
@@ -122,8 +122,8 @@ fifo_48m_to_122p88m u_fifo_cdc
(
.wr_rst_busy ( ), // output wire wr_rst_busy
.rd_rst_busy ( ), // output wire rd_rst_busy
.m_aclk (sig_clk ), // input wire m_aclk
.s_aclk (sys_clk ), // input wire s_aclk
.m_aclk (sys_clk ), // input wire m_aclk
.s_aclk (sig_clk ), // input wire s_aclk
.s_aresetn (~sig_rst ), // input wire s_aresetn
.s_axis_tvalid (cdc_fifo_s_axis_valid[m] ), // input wire s_axis_tvalid
.s_axis_tready (cdc_fifo_s_axis_ready[m] ), // output wire s_axis_tready
projects/datalink_814/dl814_k7_cal_coarse/constraints/k7401t_ad9516_2ad9361_physical.xdc
+220
View File
@@ -0,0 +1,220 @@
# smq7k410t_b9361
## Timing Assertions Section
## Physical Constraints Section
# Clocks
set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS33} [get_ports clk_25m ] ;# CLK_25M
set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25 } [get_ports clk_250m_p ] ;# CLK_250M_P
set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_buffer_clk ] ;# B9361_1_CLK_OUT
set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_buffer_clk ] ;# B9361_2_CLK_OUT
# HMC7044-1 Interface
set_property -dict {PACKAGE_PIN J23 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_clk ] ;# GM4526C_SPI_SCLK
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_csn ] ;# GM4526C_SPI_CSB
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_mosi ] ;# GM4526C_SPI_SDIO
set_property -dict {PACKAGE_PIN K23 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_miso ] ;# GM4526C_SPI_SDO
set_property -dict {PACKAGE_PIN L23 IOSTANDARD LVCMOS33} [get_ports ad9516_refmon ] ;# GM4526C_REFMON
set_property -dict {PACKAGE_PIN K24 IOSTANDARD LVCMOS33} [get_ports ad9516_ld ] ;# GM4526C_LD
set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS33} [get_ports ad9516_status ] ;# GM4526C_STATUS
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS33} [get_ports ad9516_pd_b ] ;# GM4526C_PDB
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS33} [get_ports ad9516_reset_b ] ;# GM4526C_RESETB
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS33} [get_ports ad9516_sync_b ] ;# GM4526C_SYNCB
# AD9361-1 Interface
set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data_clk ] ;# B9361_1_DATA_CLK
set_property -dict {PACKAGE_PIN B27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_frame ] ;# B9361_1_RX_FRAME
set_property -dict {PACKAGE_PIN A23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[0] ] ;# B9361_1_P0_00_TX0_N
set_property -dict {PACKAGE_PIN B23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[1] ] ;# B9361_1_P0_01_TX0_P
set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[2] ] ;# B9361_1_P0_02_TX1_N
set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[3] ] ;# B9361_1_P0_03_TX1_P
set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[4] ] ;# B9361_1_P0_04_TX2_N
set_property -dict {PACKAGE_PIN E24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[5] ] ;# B9361_1_P0_05_TX2_P
set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[6] ] ;# B9361_1_P0_06_TX3_N
set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[7] ] ;# B9361_1_P0_07_TX3_P
set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[8] ] ;# B9361_1_P0_08_TX4_N
set_property -dict {PACKAGE_PIN F26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[9] ] ;# B9361_1_P0_09_TX4_P
set_property -dict {PACKAGE_PIN G24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[10] ] ;# B9361_1_P0_10_TX5_N
set_property -dict {PACKAGE_PIN G23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[11] ] ;# B9361_1_P0_11_TX5_P
set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_fb_clk ] ;# B9361_1_FB_CLK
set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_frame ] ;# B9361_1_TX_FRAME
set_property -dict {PACKAGE_PIN E30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[0] ] ;# B9361_1_P1_00_RX0_N
set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[1] ] ;# B9361_1_P1_01_RX0_P
set_property -dict {PACKAGE_PIN C30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[2] ] ;# B9361_1_P1_02_RX1_N
set_property -dict {PACKAGE_PIN D29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[3] ] ;# B9361_1_P1_03_RX1_P
set_property -dict {PACKAGE_PIN A30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[4] ] ;# B9361_1_P1_04_RX2_N
set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[5] ] ;# B9361_1_P1_05_RX2_P
set_property -dict {PACKAGE_PIN B29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[6] ] ;# B9361_1_P1_06_RX3_N
set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[7] ] ;# B9361_1_P1_07_RX3_P
set_property -dict {PACKAGE_PIN F28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[8] ] ;# B9361_1_P1_08_RX4_N
set_property -dict {PACKAGE_PIN G28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[9] ] ;# B9361_1_P1_09_RX4_P
set_property -dict {PACKAGE_PIN H25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[10] ] ;# B9361_1_P1_10_RX5_N
set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[11] ] ;# B9361_1_P1_11_RX5_P
set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_clk ] ;# B9361_1_SPI_CLK
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_csn ] ;# B9361_1_SPI_ENB
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_mosi ] ;# B9361_1_SPI_DI
set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_miso ] ;# B9361_1_SPI_DO
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_reset_b ] ;# B9361_1_RESETB
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_en_agc ] ;# B9361_1_EN_AGC
set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_enable ] ;# B9361_1_ENABLE
set_property -dict {PACKAGE_PIN A27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_txnrx ] ;# B9361_1_TXNRX
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[0] ] ;# B9361_1_CTRL_IN0
set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[1] ] ;# B9361_1_CTRL_IN1
set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[2] ] ;# B9361_1_CTRL_IN2
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[3] ] ;# B9361_1_CTRL_IN3
set_property -dict {PACKAGE_PIN H21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[0] ] ;# B9361_1_CTRL_OUT0
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[1] ] ;# B9361_1_CTRL_OUT1
set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[2] ] ;# B9361_1_CTRL_OUT2
set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[3] ] ;# B9361_1_CTRL_OUT3
set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[4] ] ;# B9361_1_CTRL_OUT4
set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[5] ] ;# B9361_1_CTRL_OUT5
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[6] ] ;# B9361_1_CTRL_OUT6
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[7] ] ;# B9361_1_CTRL_OUT7
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS18} [get_ports ad9361_sync ] ;# B9361_SYNC
# AD9361-2 Interface
set_property -dict {PACKAGE_PIN D12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data_clk ] ;# B9361_2_DATA_CLK
set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_frame ] ;# B9361_2_RX_FRAME
set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[0] ] ;# B9361_2_P0_00_TX0_N
set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[1] ] ;# B9361_2_P0_01_TX0_P
set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[2] ] ;# B9361_2_P0_02_TX1_N
set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[3] ] ;# B9361_2_P0_03_TX1_P
set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[4] ] ;# B9361_2_P0_04_TX2_N
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[5] ] ;# B9361_2_P0_05_TX2_P
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[6] ] ;# B9361_2_P0_06_TX3_N
set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[7] ] ;# B9361_2_P0_07_TX3_P
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[8] ] ;# B9361_2_P0_08_TX4_N
set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[9] ] ;# B9361_2_P0_09_TX4_P
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[10] ] ;# B9361_2_P0_10_TX5_N
set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[11] ] ;# B9361_2_P0_11_TX5_P
set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_fb_clk ] ;# B9361_2_FB_CLK
set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_frame ] ;# B9361_2_TX_FRAME
set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[0] ] ;# B9361_2_P1_00_RX0_N
set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[1] ] ;# B9361_2_P1_01_RX0_P
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[2] ] ;# B9361_2_P1_02_RX1_N
set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[3] ] ;# B9361_2_P1_03_RX1_P
set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[4] ] ;# B9361_2_P1_04_RX2_N
set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[5] ] ;# B9361_2_P1_05_RX2_P
set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[6] ] ;# B9361_2_P1_06_RX3_N
set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[7] ] ;# B9361_2_P1_07_RX3_P
set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[8] ] ;# B9361_2_P1_08_RX4_N
set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[9] ] ;# B9361_2_P1_09_RX4_P
set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[10] ] ;# B9361_2_P1_10_RX5_N
set_property -dict {PACKAGE_PIN F11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[11] ] ;# B9361_2_P1_11_RX5_P
set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_clk ] ;# B9361_2_SPI_CLK
set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_csn ] ;# B9361_2_SPI_ENB
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_mosi ] ;# B9361_2_SPI_DI
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_miso ] ;# B9361_2_SPI_DO
set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_reset_b ] ;# B9361_2_RESETB
set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS18} [get_ports ad9361_2_en_agc ] ;# B9361_2_EN_AGC
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18} [get_ports ad9361_2_enable ] ;# B9361_2_ENABLE
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_txnrx ] ;# B9361_2_TXNRX
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[0] ] ;# B9361_2_CTRL_IN0
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[1] ] ;# B9361_2_CTRL_IN1
set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[2] ] ;# B9361_2_CTRL_IN2
set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[3] ] ;# B9361_2_CTRL_IN3
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[0] ] ;# B9361_2_CTRL_OUT0
set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[1] ] ;# B9361_2_CTRL_OUT1
set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[2] ] ;# B9361_2_CTRL_OUT2
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[3] ] ;# B9361_2_CTRL_OUT3
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[4] ] ;# B9361_2_CTRL_OUT4
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[5] ] ;# B9361_2_CTRL_OUT5
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[6] ] ;# B9361_2_CTRL_OUT6
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[7] ] ;# B9361_2_CTRL_OUT7
# Phased-Array Control
set_property -dict {PACKAGE_PIN T26 IOSTANDARD LVTTL } [get_ports ant_cin ] ;# ANT_CIN0
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVTTL } [get_ports ant_din0 ] ;# ANT_DIN0
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVTTL } [get_ports ant_din1 ] ;# ANT_DIN1
set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVTTL } [get_ports ant_cout ] ;# ANT_COUT0
set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVTTL } [get_ports ant_dout0 ] ;# ANT_DOUT0
set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVTTL } [get_ports ant_dout1 ] ;# ANT_DOUT1
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVTTL } [get_ports ant_tr ] ;# ANT_TR_IN
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVTTL } [get_ports ant_dary ] ;# ANT_DARY_IN
# RF Synthesizer Control
set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVTTL } [get_ports rf_standby ] ;# RF_STANDBY
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVTTL } [get_ports rf_sw_pll ] ;# RF_SW_PLL
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVTTL } [get_ports rf_t ] ;# RF_T
set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVTTL } [get_ports rf_r ] ;# RF_R
set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVTTL } [get_ports rf_sw_bpf ] ;# RF_SW_BPF
set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVTTL } [get_ports rf_sclk1 ] ;# RF_SCLK1
set_property -dict {PACKAGE_PIN AA26 IOSTANDARD LVTTL } [get_ports rf_sdio1 ] ;# RF_SDIO1
set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVTTL } [get_ports rf_cs1 ] ;# RF_CS1
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVTTL } [get_ports rf_ld1 ] ;# RF_LD1
set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVTTL } [get_ports rf_sclk2 ] ;# RF_SCLK2
set_property -dict {PACKAGE_PIN AD27 IOSTANDARD LVTTL } [get_ports rf_sdio2 ] ;# RF_SDIO2
set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVTTL } [get_ports rf_cs2 ] ;# RF_CS2
set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVTTL } [get_ports rf_ld2 ] ;# RF_LD2
set_property -dict {PACKAGE_PIN AC30 IOSTANDARD LVTTL } [get_ports rf_sclk3 ] ;# RF_SCLK3
set_property -dict {PACKAGE_PIN AE29 IOSTANDARD LVTTL } [get_ports rf_sdio3 ] ;# RF_SDIO3
set_property -dict {PACKAGE_PIN AB28 IOSTANDARD LVTTL } [get_ports rf_cs3 ] ;# RF_CS3
set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVTTL } [get_ports rf_ld3 ] ;# RF_LD3
set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVTTL } [get_ports rf_tmgc_16 ] ;# RF_TMGC_16
set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVTTL } [get_ports rf_tmgc_8 ] ;# RF_TMGC_8
set_property -dict {PACKAGE_PIN AA27 IOSTANDARD LVTTL } [get_ports rf_tmgc_4 ] ;# RF_TMGC_4
set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVTTL } [get_ports rf_tmgc_2 ] ;# RF_TMGC_2
set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVTTL } [get_ports rf_tmgc_1 ] ;# RF_TMGC_1
set_property -dict {PACKAGE_PIN AA28 IOSTANDARD LVTTL } [get_ports rf_rmgc_16 ] ;# RF_RMGC_16
set_property -dict {PACKAGE_PIN Y28 IOSTANDARD LVTTL } [get_ports rf_rmgc_8 ] ;# RF_RMGC_8
set_property -dict {PACKAGE_PIN Y29 IOSTANDARD LVTTL } [get_ports rf_rmgc_4 ] ;# RF_RMGC_4
set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVTTL } [get_ports rf_rmgc_2 ] ;# RF_RMGC_2
set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVTTL } [get_ports rf_rmgc_1 ] ;# RF_RMGC_1
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVTTL } [get_ports rf_enable ] ;# RF_ENABLE
set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVTTL } [get_ports rf_sc ] ;# RF_SC
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVTTL } [get_ports rf_sd ] ;# RF_SD
set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVTTL } [get_ports rf_endsyn ] ;# RF_END_SYN
set_property -dict {PACKAGE_PIN W27 IOSTANDARD LVTTL } [get_ports rf_sdout ] ;# RF_SDOUT
set_property -dict {PACKAGE_PIN AF28 IOSTANDARD LVTTL } [get_ports rf_dq_wd ] ;# RF_DQ_WD
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVTTL } [get_ports rf_sw_rx ] ;# RF_SW_RX
# LVDS for Time Synchronization
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS33} [get_ports lvds_in_1 ] ;# LVDS_IN1
set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS33} [get_ports lvds_out_1 ] ;# LVDS_OUT1
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports lvds_in_2 ] ;# LVDS_IN2
set_property -dict {PACKAGE_PIN J29 IOSTANDARD LVCMOS33} [get_ports lvds_out_2 ] ;# LVDS_OUT2
# Debug IO
set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports uart1_txd ] ;# UART_1_TXD
set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports uart1_rxd ] ;# UART_1_RXD
set_property -dict {PACKAGE_PIN U23 IOSTANDARD LVCMOS33} [get_ports uart2_txd ] ;# UART_2_TXD
set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports uart2_rxd ] ;# UART_2_RXD
set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS33} [get_ports uart3_txd ] ;# UART_3_TXD
set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS33} [get_ports uart3_rxd ] ;# UART_3_RXD
set_property -dict {PACKAGE_PIN V25 IOSTANDARD LVCMOS33} [get_ports debug_io_1 ] ;# DEBUG_IO_1
set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports debug_io_2 ] ;# DEBUG_IO_2
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS33} [get_ports debug_io_3 ] ;# DEBUG_IO_3
set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports debug_io_4 ] ;# DEBUG_IO_4
set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS33} [get_ports debug_io_5 ] ;# DEBUG_IO_5
set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports debug_io_6 ] ;# DEBUG_IO_6
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS33} [get_ports debug_io_7 ] ;# DEBUG_IO_7
set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports debug_io_8 ] ;# DEBUG_IO_8
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVDS_25 } [get_ports debug_io_00_p ] ;# DEBUG_IO_00_P
set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVDS_25 } [get_ports debug_io_01_p ] ;# DEBUG_IO_01_P
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVDS_25 } [get_ports debug_io_02_p ] ;# DEBUG_IO_02_P
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVDS_25 } [get_ports debug_io_03_p ] ;# DEBUG_IO_03_P
set_property -dict {PACKAGE_PIN AC20 IOSTANDARD LVDS_25 } [get_ports debug_io_04_p ] ;# DEBUG_IO_04_P
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25 } [get_ports debug_io_05_p ] ;# DEBUG_IO_05_P
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVDS_25 } [get_ports debug_io_06_p ] ;# DEBUG_IO_06_P
set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVDS_25 } [get_ports debug_io_07_p ] ;# DEBUG_IO_07_P
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVDS_25 } [get_ports debug_io_08_p ] ;# DEBUG_IO_08_P
# FLASH
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
projects/datalink_814/dl814_k7_cal_coarse/constraints/k7410t_ad9516_2ad9361_timing.xdc
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set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[8]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_recal_d1_reg/D]
set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[10]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_1_cal_start_d1_reg/D]
set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[7]/C}] -to [get_pins u_tx_pre_process/ad9361_tx_switch_d1_reg/D]
set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[9]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_2_cal_start_d1_reg/D]
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The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/COSLUT_10_16bit.veo
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// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
// IP Revision: 3
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
COSLUT_10_16bit your_instance_name (
.clka(clka), // input wire clka
.addra(addra), // input wire [12 : 0] addra
.douta(douta), // output wire [17 : 0] douta
.clkb(clkb), // input wire clkb
.addrb(addrb), // input wire [12 : 0] addrb
.doutb(doutb) // output wire [17 : 0] doutb
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file COSLUT_10_16bit.v when simulating
// the core, COSLUT_10_16bit. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
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-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
-- IP Revision: 3
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT COSLUT_10_16bit
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : COSLUT_10_16bit
PORT MAP (
clka => clka,
addra => addra,
douta => douta,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file COSLUT_10_16bit.vhd when simulating
-- the core, COSLUT_10_16bit. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:34:22 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_stub.v
// Design : COSLUT_10_16bit
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
module COSLUT_10_16bit(clka, addra, douta, clkb, addrb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,addra[12:0],douta[17:0],clkb,addrb[12:0],doutb[17:0]" */;
input clka;
input [12:0]addra;
output [17:0]douta;
input clkb;
input [12:0]addrb;
output [17:0]doutb;
endmodule
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/COSLUT_10_16bit_stub.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:34:22 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_stub.vhdl
-- Design : COSLUT_10_16bit
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity COSLUT_10_16bit is
Port (
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
douta : out STD_LOGIC_VECTOR ( 17 downto 0 );
clkb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 17 downto 0 )
);
end COSLUT_10_16bit;
architecture stub of COSLUT_10_16bit is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,addra[12:0],douta[17:0],clkb,addrb[12:0],doutb[17:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
begin
end;
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v
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// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
// IP Revision: 3
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module COSLUT_10_16bit (
clka,
addra,
douta,
clkb,
addrb,
doutb
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [12 : 0] addra;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [17 : 0] douta;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
input wire clkb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
input wire [12 : 0] addrb;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
output wire [17 : 0] doutb;
blk_mem_gen_v8_4_3 #(
.C_FAMILY("kintex7"),
.C_XDEVICEFAMILY("kintex7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(4),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("COSLUT_10_16bit.mif"),
.C_INIT_FILE("COSLUT_10_16bit.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(18),
.C_READ_WIDTH_A(18),
.C_WRITE_DEPTH_A(8192),
.C_READ_DEPTH_A(8192),
.C_ADDRA_WIDTH(13),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(18),
.C_READ_WIDTH_B(18),
.C_WRITE_DEPTH_B(8192),
.C_READ_DEPTH_B(8192),
.C_ADDRB_WIDTH(13),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(1),
.C_HAS_MUX_OUTPUT_REGS_A(1),
.C_HAS_MUX_OUTPUT_REGS_B(1),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_READ_LATENCY_A(1),
.C_READ_LATENCY_B(1),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("4"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 9.414399 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(1'B0),
.addra(addra),
.dina(18'B0),
.douta(douta),
.clkb(clkb),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(addrb),
.dinb(18'B0),
.doutb(doutb),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(18'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_12m/GaussFir_12m.veo
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// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fir_compiler:7.2
// IP Revision: 12
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
GaussFir_12m your_instance_name (
.aclk(aclk), // input wire aclk
.s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid
.s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready
.s_axis_data_tdata(s_axis_data_tdata), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid
.m_axis_data_tdata(m_axis_data_tdata) // output wire [15 : 0] m_axis_data_tdata
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file GaussFir_12m.v when simulating
// the core, GaussFir_12m. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
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-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 12
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT GaussFir_12m
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : GaussFir_12m
PORT MAP (
aclk => aclk,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tdata => m_axis_data_tdata
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file GaussFir_12m.vhd when simulating
-- the core, GaussFir_12m. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:33:48 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_stub.v
// Design : GaussFir_12m
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *)
module GaussFir_12m(aclk, s_axis_data_tvalid, s_axis_data_tready,
s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
input aclk;
input s_axis_data_tvalid;
output s_axis_data_tready;
input [7:0]s_axis_data_tdata;
output m_axis_data_tvalid;
output [15:0]m_axis_data_tdata;
endmodule
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:33:48 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_stub.vhdl
-- Design : GaussFir_12m
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity GaussFir_12m is
Port (
aclk : in STD_LOGIC;
s_axis_data_tvalid : in STD_LOGIC;
s_axis_data_tready : out STD_LOGIC;
s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end GaussFir_12m;
architecture stub of GaussFir_12m is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3";
begin
end;
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--------------------------------------------------------------------------------
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the FIR Compiler IP core.
-- The testbench has been generated by Vivado to accompany the IP core
-- instance you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with your core.
--
-- See the FIR Compiler product guide for further information
-- about this core.
--
--------------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated FIR Compiler core
-- instance named "GaussFir_12m".
--
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
-- documentation for details.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_GaussFir_12m is
end tb_GaussFir_12m;
architecture tb of tb_GaussFir_12m is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
-----------------------------------------------------------------------
-- DUT signals
-----------------------------------------------------------------------
-- General signals
signal aclk : std_logic := '0'; -- the master clock
-- Data slave channel signals
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal s_axis_data_tready : std_logic := '1'; -- slave is ready
signal s_axis_data_tdata : std_logic_vector(7 downto 0) := (others => '0'); -- data payload
-- Data master channel signals
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA and TUSER fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
-- Data slave channel alias signals
signal s_axis_data_tdata_data : std_logic_vector(1 downto 0) := (others => '0');
-- Data master channel alias signals
signal m_axis_data_tdata_data : std_logic_vector(14 downto 0) := (others => '0');
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.GaussFir_12m
port map (
aclk => aclk,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tdata => m_axis_data_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
-- Procedure to drive a number of input samples with specific data
-- data is the data value to drive on the tdata signal
-- samples is the number of zero-data input samples to drive
procedure drive_data ( data : std_logic_vector(7 downto 0);
samples : natural := 1 ) is
variable ip_count : integer := 0;
begin
ip_count := 0;
loop
s_axis_data_tvalid <= '1';
s_axis_data_tdata <= data;
loop
wait until rising_edge(aclk);
exit when s_axis_data_tready = '1';
end loop;
ip_count := ip_count + 1;
wait for T_HOLD;
-- Input rate is 1 input each 4 clock cycles: drive valid inputs at this rate
s_axis_data_tvalid <= '0';
wait for CLOCK_PERIOD * 3;
exit when ip_count >= samples;
end loop;
end procedure drive_data;
-- Procedure to drive a number of zero-data input samples
-- samples is the number of zero-data input samples to drive
procedure drive_zeros ( samples : natural := 1 ) is
begin
drive_data((others => '0'), samples);
end procedure drive_zeros;
-- Procedure to drive an impulse and let the impulse response emerge on the data master channel
-- samples is the number of input samples to drive; default is enough for impulse response output to emerge
procedure drive_impulse ( samples : natural := 27 ) is
variable impulse : std_logic_vector(7 downto 0);
begin
impulse := (others => '0'); -- initialize unused bits to zero
impulse(1 downto 0) := "01";
drive_data(impulse);
if samples > 1 then
drive_zeros(samples-1);
end if;
end procedure drive_impulse;
begin
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Drive a single impulse and let the impulse response emerge
drive_impulse;
-- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
drive_impulse(2); -- start of impulse; data is now zero
s_axis_data_tvalid <= '0';
wait for CLOCK_PERIOD * 20; -- provide no data for 5 input samples worth
drive_zeros(2); -- 2 normal input samples
s_axis_data_tvalid <= '1';
wait for CLOCK_PERIOD * 20; -- provide data as fast as the core can accept it for 5 input samples worth
drive_zeros(18); -- back to normal operation
-- End of test
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
wait;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the master DATA channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_data_tvalid = '1' then
if is_x(m_axis_data_tdata) then
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
-- Data slave channel alias signals
s_axis_data_tdata_data <= s_axis_data_tdata(1 downto 0);
-- Data master channel alias signals: update these only when they are valid
m_axis_data_tdata_data <= m_axis_data_tdata(14 downto 0) when m_axis_data_tvalid = '1';
end tb;
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-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_2_12;
USE fir_compiler_v7_2_12.fir_compiler_v7_2_12;
ENTITY GaussFir_12m IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END GaussFir_12m;
ARCHITECTURE GaussFir_12m_arch OF GaussFir_12m IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF GaussFir_12m_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_2_12 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_PX_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_2_12;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
BEGIN
U0 : fir_compiler_v7_2_12
GENERIC MAP (
C_XDEVICEFAMILY => "kintex7",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "GaussFir_12m",
C_COEF_FILE => "GaussFir_12m.mif",
C_COEF_FILE_LINES => 20,
C_FILTER_TYPE => 2,
C_INTERP_RATE => 4,
C_DECIM_RATE => 1,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 0,
C_NUM_FILTS => 1,
C_NUM_TAPS => 17,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 0,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "5",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "2",
C_DATA_IP_PATH_WIDTHS => "2",
C_DATA_PX_PATH_WIDTHS => "2",
C_DATA_WIDTH => 2,
C_COEF_PATH_WIDTHS => "14",
C_COEF_WIDTH => 14,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_PX_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "1",
C_ACCUM_PATH_WIDTHS => "15",
C_OUTPUT_WIDTH => 15,
C_OUTPUT_PATH_WIDTHS => "15",
C_ACCUM_OP_PATH_WIDTHS => "15",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 5,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 4,
C_OUTPUT_RATE => 1,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 0,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 0,
C_MEM_ARRANGEMENT => 2,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 11,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 0,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 8,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 16,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END GaussFir_12m_arch;
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// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fir_compiler:7.2
// IP Revision: 12
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
GaussFir_1mp5 your_instance_name (
.aclk(aclk), // input wire aclk
.s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid
.s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready
.s_axis_data_tdata(s_axis_data_tdata), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid
.m_axis_data_tdata(m_axis_data_tdata) // output wire [15 : 0] m_axis_data_tdata
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file GaussFir_1mp5.v when simulating
// the core, GaussFir_1mp5. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
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-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 12
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT GaussFir_1mp5
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : GaussFir_1mp5
PORT MAP (
aclk => aclk,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tdata => m_axis_data_tdata
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file GaussFir_1mp5.vhd when simulating
-- the core, GaussFir_1mp5. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:33:47 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_stub.v
// Design : GaussFir_1mp5
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *)
module GaussFir_1mp5(aclk, s_axis_data_tvalid, s_axis_data_tready,
s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
input aclk;
input s_axis_data_tvalid;
output s_axis_data_tready;
input [7:0]s_axis_data_tdata;
output m_axis_data_tvalid;
output [15:0]m_axis_data_tdata;
endmodule
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/GaussFir_1mp5/GaussFir_1mp5_stub.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:33:47 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_stub.vhdl
-- Design : GaussFir_1mp5
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity GaussFir_1mp5 is
Port (
aclk : in STD_LOGIC;
s_axis_data_tvalid : in STD_LOGIC;
s_axis_data_tready : out STD_LOGIC;
s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end GaussFir_1mp5;
architecture stub of GaussFir_1mp5 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3";
begin
end;
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--------------------------------------------------------------------------------
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the FIR Compiler IP core.
-- The testbench has been generated by Vivado to accompany the IP core
-- instance you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with your core.
--
-- See the FIR Compiler product guide for further information
-- about this core.
--
--------------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated FIR Compiler core
-- instance named "GaussFir_1mp5".
--
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
-- documentation for details.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_GaussFir_1mp5 is
end tb_GaussFir_1mp5;
architecture tb of tb_GaussFir_1mp5 is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
-----------------------------------------------------------------------
-- DUT signals
-----------------------------------------------------------------------
-- General signals
signal aclk : std_logic := '0'; -- the master clock
-- Data slave channel signals
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal s_axis_data_tready : std_logic := '1'; -- slave is ready
signal s_axis_data_tdata : std_logic_vector(7 downto 0) := (others => '0'); -- data payload
-- Data master channel signals
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA and TUSER fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
-- Data slave channel alias signals
signal s_axis_data_tdata_data : std_logic_vector(1 downto 0) := (others => '0');
-- Data master channel alias signals
signal m_axis_data_tdata_data : std_logic_vector(12 downto 0) := (others => '0');
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.GaussFir_1mp5
port map (
aclk => aclk,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tdata => m_axis_data_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
-- Procedure to drive a number of input samples with specific data
-- data is the data value to drive on the tdata signal
-- samples is the number of zero-data input samples to drive
procedure drive_data ( data : std_logic_vector(7 downto 0);
samples : natural := 1 ) is
variable ip_count : integer := 0;
begin
ip_count := 0;
loop
s_axis_data_tvalid <= '1';
s_axis_data_tdata <= data;
loop
wait until rising_edge(aclk);
exit when s_axis_data_tready = '1';
end loop;
ip_count := ip_count + 1;
wait for T_HOLD;
-- Input rate is 1 input each 32 clock cycles: drive valid inputs at this rate
s_axis_data_tvalid <= '0';
wait for CLOCK_PERIOD * 31;
exit when ip_count >= samples;
end loop;
end procedure drive_data;
-- Procedure to drive a number of zero-data input samples
-- samples is the number of zero-data input samples to drive
procedure drive_zeros ( samples : natural := 1 ) is
begin
drive_data((others => '0'), samples);
end procedure drive_zeros;
-- Procedure to drive an impulse and let the impulse response emerge on the data master channel
-- samples is the number of input samples to drive; default is enough for impulse response output to emerge
procedure drive_impulse ( samples : natural := 165 ) is
variable impulse : std_logic_vector(7 downto 0);
begin
impulse := (others => '0'); -- initialize unused bits to zero
impulse(1 downto 0) := "01";
drive_data(impulse);
if samples > 1 then
drive_zeros(samples-1);
end if;
end procedure drive_impulse;
begin
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Drive a single impulse and let the impulse response emerge
drive_impulse;
-- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
drive_impulse(2); -- start of impulse; data is now zero
s_axis_data_tvalid <= '0';
wait for CLOCK_PERIOD * 160; -- provide no data for 5 input samples worth
drive_zeros(2); -- 2 normal input samples
s_axis_data_tvalid <= '1';
wait for CLOCK_PERIOD * 160; -- provide data as fast as the core can accept it for 5 input samples worth
drive_zeros(156); -- back to normal operation
-- End of test
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
wait;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the master DATA channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_data_tvalid = '1' then
if is_x(m_axis_data_tdata) then
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
-- Data slave channel alias signals
s_axis_data_tdata_data <= s_axis_data_tdata(1 downto 0);
-- Data master channel alias signals: update these only when they are valid
m_axis_data_tdata_data <= m_axis_data_tdata(12 downto 0) when m_axis_data_tvalid = '1';
end tb;
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-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_2_12;
USE fir_compiler_v7_2_12.fir_compiler_v7_2_12;
ENTITY GaussFir_1mp5 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END GaussFir_1mp5;
ARCHITECTURE GaussFir_1mp5_arch OF GaussFir_1mp5 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF GaussFir_1mp5_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_2_12 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_PX_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_2_12;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
BEGIN
U0 : fir_compiler_v7_2_12
GENERIC MAP (
C_XDEVICEFAMILY => "kintex7",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "GaussFir_1mp5",
C_COEF_FILE => "GaussFir_1mp5.mif",
C_COEF_FILE_LINES => 160,
C_FILTER_TYPE => 2,
C_INTERP_RATE => 32,
C_DECIM_RATE => 1,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 0,
C_NUM_FILTS => 1,
C_NUM_TAPS => 129,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 0,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "5",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "2",
C_DATA_IP_PATH_WIDTHS => "2",
C_DATA_PX_PATH_WIDTHS => "2",
C_DATA_WIDTH => 2,
C_COEF_PATH_WIDTHS => "14",
C_COEF_WIDTH => 14,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_PX_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "1",
C_ACCUM_PATH_WIDTHS => "13",
C_OUTPUT_WIDTH => 13,
C_OUTPUT_PATH_WIDTHS => "13",
C_ACCUM_OP_PATH_WIDTHS => "13",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 5,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 32,
C_OUTPUT_RATE => 1,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 0,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 0,
C_MEM_ARRANGEMENT => 2,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 11,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 0,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 8,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 16,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END GaussFir_1mp5_arch;
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/ad9361_clk_gen/ad9361_clk_gen.v
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// file: ad9361_clk_gen.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____48.000______0.000______50.0______139.139_____89.958
// clk_out2____96.000______0.000______50.0______120.859_____89.958
// clk_out3___144.000______0.000______50.0______112.241_____89.958
// clk_out4___192.000______0.000______50.0______106.524_____89.958
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary______________96____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "ad9361_clk_gen,clk_wiz_v6_0_3_0_0,{component_name=ad9361_clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=10.417,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module ad9361_clk_gen
(
// Clock out ports
output clk_out1,
output clk_out2,
output clk_out3,
output clk_out4,
// Status and control signals
output locked,
// Clock in ports
input clk_in1
);
ad9361_clk_gen_clk_wiz inst
(
// Clock out ports
.clk_out1(clk_out1),
.clk_out2(clk_out2),
.clk_out3(clk_out3),
.clk_out4(clk_out4),
// Status and control signals
.locked(locked),
// Clock in ports
.clk_in1(clk_in1)
);
endmodule
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/ad9361_clk_gen/ad9361_clk_gen.veo
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//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____48.000______0.000______50.0______139.139_____89.958
// clk_out2____96.000______0.000______50.0______120.859_____89.958
// clk_out3___144.000______0.000______50.0______112.241_____89.958
// clk_out4___192.000______0.000______50.0______106.524_____89.958
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary______________96____________0.010
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
ad9361_clk_gen instance_name
(
// Clock out ports
.clk_out1(clk_out1), // output clk_out1
.clk_out2(clk_out2), // output clk_out2
.clk_out3(clk_out3), // output clk_out3
.clk_out4(clk_out4), // output clk_out4
// Status and control signals
.locked(locked), // output locked
// Clock in ports
.clk_in1(clk_in1)); // input clk_in1
// INST_TAG_END ------ End INSTANTIATION Template ---------
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/ad9361_clk_gen/ad9361_clk_gen_clk_wiz.v
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// file: ad9361_clk_gen.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____48.000______0.000______50.0______139.139_____89.958
// clk_out2____96.000______0.000______50.0______120.859_____89.958
// clk_out3___144.000______0.000______50.0______112.241_____89.958
// clk_out4___192.000______0.000______50.0______106.524_____89.958
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary______________96____________0.010
`timescale 1ps/1ps
module ad9361_clk_gen_clk_wiz
(// Clock in ports
// Clock out ports
output clk_out1,
output clk_out2,
output clk_out3,
output clk_out4,
// Status and control signals
output locked,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_ad9361_clk_gen;
wire clk_in2_ad9361_clk_gen;
IBUF clkin1_ibufg
(.O (clk_in1_ad9361_clk_gen),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire clk_out1_ad9361_clk_gen;
wire clk_out2_ad9361_clk_gen;
wire clk_out3_ad9361_clk_gen;
wire clk_out4_ad9361_clk_gen;
wire clk_out5_ad9361_clk_gen;
wire clk_out6_ad9361_clk_gen;
wire clk_out7_ad9361_clk_gen;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_ad9361_clk_gen;
wire clkfbout_buf_ad9361_clk_gen;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (12.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (24.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (12),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (8),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (6),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.417))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_ad9361_clk_gen),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_ad9361_clk_gen),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clk_out2_ad9361_clk_gen),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clk_out3_ad9361_clk_gen),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clk_out4_ad9361_clk_gen),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_ad9361_clk_gen),
.CLKIN1 (clk_in1_ad9361_clk_gen),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
assign locked = locked_int;
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_ad9361_clk_gen),
.I (clkfbout_ad9361_clk_gen));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_ad9361_clk_gen));
BUFG clkout2_buf
(.O (clk_out2),
.I (clk_out2_ad9361_clk_gen));
BUFG clkout3_buf
(.O (clk_out3),
.I (clk_out3_ad9361_clk_gen));
BUFG clkout4_buf
(.O (clk_out4),
.I (clk_out4_ad9361_clk_gen));
endmodule
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/ad9361_clk_gen/ad9361_clk_gen_sim_netlist.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:33:33 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/ad9361_clk_gen_synth_1/ad9361_clk_gen_sim_netlist.v
// Design : ad9361_clk_gen
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module ad9361_clk_gen
(clk_out1,
clk_out2,
clk_out3,
clk_out4,
locked,
clk_in1);
output clk_out1;
output clk_out2;
output clk_out3;
output clk_out4;
output locked;
input clk_in1;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
wire clk_out2;
wire clk_out3;
wire clk_out4;
wire locked;
ad9361_clk_gen_ad9361_clk_gen_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.clk_out2(clk_out2),
.clk_out3(clk_out3),
.clk_out4(clk_out4),
.locked(locked));
endmodule
(* ORIG_REF_NAME = "ad9361_clk_gen_clk_wiz" *)
module ad9361_clk_gen_ad9361_clk_gen_clk_wiz
(clk_out1,
clk_out2,
clk_out3,
clk_out4,
locked,
clk_in1);
output clk_out1;
output clk_out2;
output clk_out3;
output clk_out4;
output locked;
input clk_in1;
wire clk_in1;
wire clk_in1_ad9361_clk_gen;
wire clk_out1;
wire clk_out1_ad9361_clk_gen;
wire clk_out2;
wire clk_out2_ad9361_clk_gen;
wire clk_out3;
wire clk_out3_ad9361_clk_gen;
wire clk_out4;
wire clk_out4_ad9361_clk_gen;
wire clkfbout_ad9361_clk_gen;
wire clkfbout_buf_ad9361_clk_gen;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_ad9361_clk_gen),
.O(clkfbout_buf_ad9361_clk_gen));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_ad9361_clk_gen));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_ad9361_clk_gen),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout2_buf
(.I(clk_out2_ad9361_clk_gen),
.O(clk_out2));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout3_buf
(.I(clk_out3_ad9361_clk_gen),
.O(clk_out3));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout4_buf
(.I(clk_out4_ad9361_clk_gen),
.O(clk_out4));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(12.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.417000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(24.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(12),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(8),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(6),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_ad9361_clk_gen),
.CLKFBOUT(clkfbout_ad9361_clk_gen),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_ad9361_clk_gen),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_ad9361_clk_gen),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(clk_out2_ad9361_clk_gen),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(clk_out3_ad9361_clk_gen),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(clk_out4_ad9361_clk_gen),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/ad9361_clk_gen/ad9361_clk_gen_sim_netlist.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:33:33 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/ad9361_clk_gen_synth_1/ad9361_clk_gen_sim_netlist.vhdl
-- Design : ad9361_clk_gen
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ad9361_clk_gen_ad9361_clk_gen_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
clk_out3 : out STD_LOGIC;
clk_out4 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ad9361_clk_gen_ad9361_clk_gen_clk_wiz : entity is "ad9361_clk_gen_clk_wiz";
end ad9361_clk_gen_ad9361_clk_gen_clk_wiz;
architecture STRUCTURE of ad9361_clk_gen_ad9361_clk_gen_clk_wiz is
signal clk_in1_ad9361_clk_gen : STD_LOGIC;
signal clk_out1_ad9361_clk_gen : STD_LOGIC;
signal clk_out2_ad9361_clk_gen : STD_LOGIC;
signal clk_out3_ad9361_clk_gen : STD_LOGIC;
signal clk_out4_ad9361_clk_gen : STD_LOGIC;
signal clkfbout_ad9361_clk_gen : STD_LOGIC;
signal clkfbout_buf_ad9361_clk_gen : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout3_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout4_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_ad9361_clk_gen,
O => clkfbout_buf_ad9361_clk_gen
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_ad9361_clk_gen
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_ad9361_clk_gen,
O => clk_out1
);
clkout2_buf: unisim.vcomponents.BUFG
port map (
I => clk_out2_ad9361_clk_gen,
O => clk_out2
);
clkout3_buf: unisim.vcomponents.BUFG
port map (
I => clk_out3_ad9361_clk_gen,
O => clk_out3
);
clkout4_buf: unisim.vcomponents.BUFG
port map (
I => clk_out4_ad9361_clk_gen,
O => clk_out4
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 12.000000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.417000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 24.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 12,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 8,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 6,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_ad9361_clk_gen,
CLKFBOUT => clkfbout_ad9361_clk_gen,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_ad9361_clk_gen,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_ad9361_clk_gen,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => clk_out2_ad9361_clk_gen,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => clk_out3_ad9361_clk_gen,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => clk_out4_ad9361_clk_gen,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ad9361_clk_gen is
port (
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
clk_out3 : out STD_LOGIC;
clk_out4 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of ad9361_clk_gen : entity is true;
end ad9361_clk_gen;
architecture STRUCTURE of ad9361_clk_gen is
begin
inst: entity work.ad9361_clk_gen_ad9361_clk_gen_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
clk_out2 => clk_out2,
clk_out3 => clk_out3,
clk_out4 => clk_out4,
locked => locked
);
end STRUCTURE;
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/ad9361_clk_gen/ad9361_clk_gen_stub.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:33:33 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/ad9361_clk_gen_synth_1/ad9361_clk_gen_stub.v
// Design : ad9361_clk_gen
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module ad9361_clk_gen(clk_out1, clk_out2, clk_out3, clk_out4, locked,
clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_out2,clk_out3,clk_out4,locked,clk_in1" */;
output clk_out1;
output clk_out2;
output clk_out3;
output clk_out4;
output locked;
input clk_in1;
endmodule
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/ad9361_clk_gen/ad9361_clk_gen_stub.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:33:33 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/ad9361_clk_gen_synth_1/ad9361_clk_gen_stub.vhdl
-- Design : ad9361_clk_gen
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ad9361_clk_gen is
Port (
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
clk_out3 : out STD_LOGIC;
clk_out4 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end ad9361_clk_gen;
architecture stub of ad9361_clk_gen is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,clk_out3,clk_out4,locked,clk_in1";
begin
end;
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/add_s24_s32_s32/add_s24_s32_s32.veo
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// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:c_addsub:12.0
// IP Revision: 13
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
add_s24_s32_s32 your_instance_name (
.A(A), // input wire [23 : 0] A
.B(B), // input wire [31 : 0] B
.CLK(CLK), // input wire CLK
.CE(CE), // input wire CE
.SCLR(SCLR), // input wire SCLR
.S(S) // output wire [31 : 0] S
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file add_s24_s32_s32.v when simulating
// the core, add_s24_s32_s32. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/add_s24_s32_s32/add_s24_s32_s32.vho
+85
View File
@@ -0,0 +1,85 @@
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:c_addsub:12.0
-- IP Revision: 13
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT add_s24_s32_s32
PORT (
A : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
CLK : IN STD_LOGIC;
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : add_s24_s32_s32
PORT MAP (
A => A,
B => B,
CLK => CLK,
CE => CE,
SCLR => SCLR,
S => S
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file add_s24_s32_s32.vhd when simulating
-- the core, add_s24_s32_s32. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/add_s24_s32_s32/add_s24_s32_s32_sim_netlist.v
+737
View File
@@ -0,0 +1,737 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:33:37 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/add_s24_s32_s32_synth_1/add_s24_s32_s32_sim_netlist.v
// Design : add_s24_s32_s32
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "add_s24_s32_s32,c_addsub_v12_0_13,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "c_addsub_v12_0_13,Vivado 2019.1.3" *)
(* NotValidForBitStream *)
module add_s24_s32_s32
(A,
B,
CLK,
CE,
SCLR,
S);
(* x_interface_info = "xilinx.com:signal:data:1.0 a_intf DATA" *) (* x_interface_parameter = "XIL_INTERFACENAME a_intf, LAYERED_METADATA undef" *) input [23:0]A;
(* x_interface_info = "xilinx.com:signal:data:1.0 b_intf DATA" *) (* x_interface_parameter = "XIL_INTERFACENAME b_intf, LAYERED_METADATA undef" *) input [31:0]B;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clk_intf, ASSOCIATED_BUSIF s_intf:c_out_intf:sinit_intf:sset_intf:bypass_intf:c_in_intf:add_intf:b_intf:a_intf, ASSOCIATED_RESET SCLR, ASSOCIATED_CLKEN CE, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *) input CLK;
(* x_interface_info = "xilinx.com:signal:clockenable:1.0 ce_intf CE" *) (* x_interface_parameter = "XIL_INTERFACENAME ce_intf, POLARITY ACTIVE_LOW" *) input CE;
(* x_interface_info = "xilinx.com:signal:reset:1.0 sclr_intf RST" *) (* x_interface_parameter = "XIL_INTERFACENAME sclr_intf, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input SCLR;
(* x_interface_info = "xilinx.com:signal:data:1.0 s_intf DATA" *) (* x_interface_parameter = "XIL_INTERFACENAME s_intf, LAYERED_METADATA undef" *) output [31:0]S;
wire [23:0]A;
wire [31:0]B;
wire CE;
wire CLK;
wire [31:0]S;
wire SCLR;
wire NLW_U0_C_OUT_UNCONNECTED;
(* C_AINIT_VAL = "0" *)
(* C_BORROW_LOW = "1" *)
(* C_CE_OVERRIDES_BYPASS = "1" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "1" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_SINIT = "0" *)
(* C_HAS_SSET = "0" *)
(* C_IMPLEMENTATION = "0" *)
(* C_SCLR_OVERRIDES_SSET = "1" *)
(* C_SINIT_VAL = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "kintex7" *)
(* c_a_type = "0" *)
(* c_a_width = "24" *)
(* c_add_mode = "0" *)
(* c_b_constant = "0" *)
(* c_b_type = "0" *)
(* c_b_value = "00000000000000000000000000000000" *)
(* c_b_width = "32" *)
(* c_bypass_low = "0" *)
(* c_has_bypass = "0" *)
(* c_has_c_in = "0" *)
(* c_has_c_out = "0" *)
(* c_latency = "1" *)
(* c_out_width = "32" *)
(* downgradeipidentifiedwarnings = "yes" *)
add_s24_s32_s32_c_addsub_v12_0_13 U0
(.A(A),
.ADD(1'b1),
.B(B),
.BYPASS(1'b0),
.CE(CE),
.CLK(CLK),
.C_IN(1'b0),
.C_OUT(NLW_U0_C_OUT_UNCONNECTED),
.S(S),
.SCLR(SCLR),
.SINIT(1'b0),
.SSET(1'b0));
endmodule
(* C_ADD_MODE = "0" *) (* C_AINIT_VAL = "0" *) (* C_A_TYPE = "0" *)
(* C_A_WIDTH = "24" *) (* C_BORROW_LOW = "1" *) (* C_BYPASS_LOW = "0" *)
(* C_B_CONSTANT = "0" *) (* C_B_TYPE = "0" *) (* C_B_VALUE = "00000000000000000000000000000000" *)
(* C_B_WIDTH = "32" *) (* C_CE_OVERRIDES_BYPASS = "1" *) (* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_BYPASS = "0" *) (* C_HAS_CE = "1" *) (* C_HAS_C_IN = "0" *)
(* C_HAS_C_OUT = "0" *) (* C_HAS_SCLR = "1" *) (* C_HAS_SINIT = "0" *)
(* C_HAS_SSET = "0" *) (* C_IMPLEMENTATION = "0" *) (* C_LATENCY = "1" *)
(* C_OUT_WIDTH = "32" *) (* C_SCLR_OVERRIDES_SSET = "1" *) (* C_SINIT_VAL = "0" *)
(* C_VERBOSITY = "0" *) (* C_XDEVICEFAMILY = "kintex7" *) (* ORIG_REF_NAME = "c_addsub_v12_0_13" *)
(* downgradeipidentifiedwarnings = "yes" *)
module add_s24_s32_s32_c_addsub_v12_0_13
(A,
B,
CLK,
ADD,
C_IN,
CE,
BYPASS,
SCLR,
SSET,
SINIT,
C_OUT,
S);
input [23:0]A;
input [31:0]B;
input CLK;
input ADD;
input C_IN;
input CE;
input BYPASS;
input SCLR;
input SSET;
input SINIT;
output C_OUT;
output [31:0]S;
wire \<const0> ;
wire [23:0]A;
wire [31:0]B;
wire CE;
wire CLK;
wire [31:0]S;
wire SCLR;
wire NLW_xst_addsub_C_OUT_UNCONNECTED;
assign C_OUT = \<const0> ;
GND GND
(.G(\<const0> ));
(* C_AINIT_VAL = "0" *)
(* C_BORROW_LOW = "1" *)
(* C_CE_OVERRIDES_BYPASS = "1" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "1" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_SINIT = "0" *)
(* C_HAS_SSET = "0" *)
(* C_IMPLEMENTATION = "0" *)
(* C_SCLR_OVERRIDES_SSET = "1" *)
(* C_SINIT_VAL = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "kintex7" *)
(* c_a_type = "0" *)
(* c_a_width = "24" *)
(* c_add_mode = "0" *)
(* c_b_constant = "0" *)
(* c_b_type = "0" *)
(* c_b_value = "00000000000000000000000000000000" *)
(* c_b_width = "32" *)
(* c_bypass_low = "0" *)
(* c_has_bypass = "0" *)
(* c_has_c_in = "0" *)
(* c_has_c_out = "0" *)
(* c_latency = "1" *)
(* c_out_width = "32" *)
(* downgradeipidentifiedwarnings = "yes" *)
add_s24_s32_s32_c_addsub_v12_0_13_viv xst_addsub
(.A(A),
.ADD(1'b0),
.B(B),
.BYPASS(1'b0),
.CE(CE),
.CLK(CLK),
.C_IN(1'b0),
.C_OUT(NLW_xst_addsub_C_OUT_UNCONNECTED),
.S(S),
.SCLR(SCLR),
.SINIT(1'b0),
.SSET(1'b0));
endmodule
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`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/add_s24_s32_s32/add_s24_s32_s32_sim_netlist.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:33:37 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/add_s24_s32_s32_synth_1/add_s24_s32_s32_sim_netlist.vhdl
-- Design : add_s24_s32_s32
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
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GbxZxhG/OFq9gzNP5B2i4any8Edqug==
`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity add_s24_s32_s32_c_addsub_v12_0_13 is
port (
A : in STD_LOGIC_VECTOR ( 23 downto 0 );
B : in STD_LOGIC_VECTOR ( 31 downto 0 );
CLK : in STD_LOGIC;
ADD : in STD_LOGIC;
C_IN : in STD_LOGIC;
CE : in STD_LOGIC;
BYPASS : in STD_LOGIC;
SCLR : in STD_LOGIC;
SSET : in STD_LOGIC;
SINIT : in STD_LOGIC;
C_OUT : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ADD_MODE : integer;
attribute C_ADD_MODE of add_s24_s32_s32_c_addsub_v12_0_13 : entity is 0;
attribute C_AINIT_VAL : string;
attribute C_AINIT_VAL of add_s24_s32_s32_c_addsub_v12_0_13 : entity is "0";
attribute C_A_TYPE : integer;
attribute C_A_TYPE of add_s24_s32_s32_c_addsub_v12_0_13 : entity is 0;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of add_s24_s32_s32_c_addsub_v12_0_13 : entity is 24;
attribute C_BORROW_LOW : integer;
attribute C_BORROW_LOW of add_s24_s32_s32_c_addsub_v12_0_13 : entity is 1;
attribute C_BYPASS_LOW : integer;
attribute C_BYPASS_LOW of add_s24_s32_s32_c_addsub_v12_0_13 : entity is 0;
attribute C_B_CONSTANT : integer;
attribute C_B_CONSTANT of add_s24_s32_s32_c_addsub_v12_0_13 : entity is 0;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of add_s24_s32_s32_c_addsub_v12_0_13 : entity is 0;
attribute C_B_VALUE : string;
attribute C_B_VALUE of add_s24_s32_s32_c_addsub_v12_0_13 : entity is "00000000000000000000000000000000";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of add_s24_s32_s32_c_addsub_v12_0_13 : entity is 32;
attribute C_CE_OVERRIDES_BYPASS : integer;
attribute C_CE_OVERRIDES_BYPASS of add_s24_s32_s32_c_addsub_v12_0_13 : entity is 1;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of add_s24_s32_s32_c_addsub_v12_0_13 : entity is 0;
attribute C_HAS_BYPASS : integer;
attribute C_HAS_BYPASS of add_s24_s32_s32_c_addsub_v12_0_13 : entity is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of add_s24_s32_s32_c_addsub_v12_0_13 : entity is 1;
attribute C_HAS_C_IN : integer;
attribute C_HAS_C_IN of add_s24_s32_s32_c_addsub_v12_0_13 : entity is 0;
attribute C_HAS_C_OUT : integer;
attribute C_HAS_C_OUT of add_s24_s32_s32_c_addsub_v12_0_13 : entity is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of add_s24_s32_s32_c_addsub_v12_0_13 : entity is 1;
attribute C_HAS_SINIT : integer;
attribute C_HAS_SINIT of add_s24_s32_s32_c_addsub_v12_0_13 : entity is 0;
attribute C_HAS_SSET : integer;
attribute C_HAS_SSET of add_s24_s32_s32_c_addsub_v12_0_13 : entity is 0;
attribute C_IMPLEMENTATION : integer;
attribute C_IMPLEMENTATION of add_s24_s32_s32_c_addsub_v12_0_13 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of add_s24_s32_s32_c_addsub_v12_0_13 : entity is 1;
attribute C_OUT_WIDTH : integer;
attribute C_OUT_WIDTH of add_s24_s32_s32_c_addsub_v12_0_13 : entity is 32;
attribute C_SCLR_OVERRIDES_SSET : integer;
attribute C_SCLR_OVERRIDES_SSET of add_s24_s32_s32_c_addsub_v12_0_13 : entity is 1;
attribute C_SINIT_VAL : string;
attribute C_SINIT_VAL of add_s24_s32_s32_c_addsub_v12_0_13 : entity is "0";
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of add_s24_s32_s32_c_addsub_v12_0_13 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of add_s24_s32_s32_c_addsub_v12_0_13 : entity is "kintex7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of add_s24_s32_s32_c_addsub_v12_0_13 : entity is "c_addsub_v12_0_13";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of add_s24_s32_s32_c_addsub_v12_0_13 : entity is "yes";
end add_s24_s32_s32_c_addsub_v12_0_13;
architecture STRUCTURE of add_s24_s32_s32_c_addsub_v12_0_13 is
signal \<const0>\ : STD_LOGIC;
signal NLW_xst_addsub_C_OUT_UNCONNECTED : STD_LOGIC;
attribute C_AINIT_VAL of xst_addsub : label is "0";
attribute C_BORROW_LOW of xst_addsub : label is 1;
attribute C_CE_OVERRIDES_BYPASS of xst_addsub : label is 1;
attribute C_CE_OVERRIDES_SCLR of xst_addsub : label is 0;
attribute C_HAS_CE of xst_addsub : label is 1;
attribute C_HAS_SCLR of xst_addsub : label is 1;
attribute C_HAS_SINIT of xst_addsub : label is 0;
attribute C_HAS_SSET of xst_addsub : label is 0;
attribute C_IMPLEMENTATION of xst_addsub : label is 0;
attribute C_SCLR_OVERRIDES_SSET of xst_addsub : label is 1;
attribute C_SINIT_VAL of xst_addsub : label is "0";
attribute C_VERBOSITY of xst_addsub : label is 0;
attribute C_XDEVICEFAMILY of xst_addsub : label is "kintex7";
attribute c_a_type of xst_addsub : label is 0;
attribute c_a_width of xst_addsub : label is 24;
attribute c_add_mode of xst_addsub : label is 0;
attribute c_b_constant of xst_addsub : label is 0;
attribute c_b_type of xst_addsub : label is 0;
attribute c_b_value of xst_addsub : label is "00000000000000000000000000000000";
attribute c_b_width of xst_addsub : label is 32;
attribute c_bypass_low of xst_addsub : label is 0;
attribute c_has_bypass of xst_addsub : label is 0;
attribute c_has_c_in of xst_addsub : label is 0;
attribute c_has_c_out of xst_addsub : label is 0;
attribute c_latency of xst_addsub : label is 1;
attribute c_out_width of xst_addsub : label is 32;
attribute downgradeipidentifiedwarnings of xst_addsub : label is "yes";
begin
C_OUT <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
xst_addsub: entity work.add_s24_s32_s32_c_addsub_v12_0_13_viv
port map (
A(23 downto 0) => A(23 downto 0),
ADD => '0',
B(31 downto 0) => B(31 downto 0),
BYPASS => '0',
CE => CE,
CLK => CLK,
C_IN => '0',
C_OUT => NLW_xst_addsub_C_OUT_UNCONNECTED,
S(31 downto 0) => S(31 downto 0),
SCLR => SCLR,
SINIT => '0',
SSET => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity add_s24_s32_s32 is
port (
A : in STD_LOGIC_VECTOR ( 23 downto 0 );
B : in STD_LOGIC_VECTOR ( 31 downto 0 );
CLK : in STD_LOGIC;
CE : in STD_LOGIC;
SCLR : in STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of add_s24_s32_s32 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of add_s24_s32_s32 : entity is "add_s24_s32_s32,c_addsub_v12_0_13,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of add_s24_s32_s32 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of add_s24_s32_s32 : entity is "c_addsub_v12_0_13,Vivado 2019.1.3";
end add_s24_s32_s32;
architecture STRUCTURE of add_s24_s32_s32 is
signal NLW_U0_C_OUT_UNCONNECTED : STD_LOGIC;
attribute C_AINIT_VAL : string;
attribute C_AINIT_VAL of U0 : label is "0";
attribute C_BORROW_LOW : integer;
attribute C_BORROW_LOW of U0 : label is 1;
attribute C_CE_OVERRIDES_BYPASS : integer;
attribute C_CE_OVERRIDES_BYPASS of U0 : label is 1;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of U0 : label is 1;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of U0 : label is 1;
attribute C_HAS_SINIT : integer;
attribute C_HAS_SINIT of U0 : label is 0;
attribute C_HAS_SSET : integer;
attribute C_HAS_SSET of U0 : label is 0;
attribute C_IMPLEMENTATION : integer;
attribute C_IMPLEMENTATION of U0 : label is 0;
attribute C_SCLR_OVERRIDES_SSET : integer;
attribute C_SCLR_OVERRIDES_SSET of U0 : label is 1;
attribute C_SINIT_VAL : string;
attribute C_SINIT_VAL of U0 : label is "0";
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "kintex7";
attribute c_a_type : integer;
attribute c_a_type of U0 : label is 0;
attribute c_a_width : integer;
attribute c_a_width of U0 : label is 24;
attribute c_add_mode : integer;
attribute c_add_mode of U0 : label is 0;
attribute c_b_constant : integer;
attribute c_b_constant of U0 : label is 0;
attribute c_b_type : integer;
attribute c_b_type of U0 : label is 0;
attribute c_b_value : string;
attribute c_b_value of U0 : label is "00000000000000000000000000000000";
attribute c_b_width : integer;
attribute c_b_width of U0 : label is 32;
attribute c_bypass_low : integer;
attribute c_bypass_low of U0 : label is 0;
attribute c_has_bypass : integer;
attribute c_has_bypass of U0 : label is 0;
attribute c_has_c_in : integer;
attribute c_has_c_in of U0 : label is 0;
attribute c_has_c_out : integer;
attribute c_has_c_out of U0 : label is 0;
attribute c_latency : integer;
attribute c_latency of U0 : label is 1;
attribute c_out_width : integer;
attribute c_out_width of U0 : label is 32;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute x_interface_info : string;
attribute x_interface_info of CE : signal is "xilinx.com:signal:clockenable:1.0 ce_intf CE";
attribute x_interface_parameter : string;
attribute x_interface_parameter of CE : signal is "XIL_INTERFACENAME ce_intf, POLARITY ACTIVE_LOW";
attribute x_interface_info of CLK : signal is "xilinx.com:signal:clock:1.0 clk_intf CLK";
attribute x_interface_parameter of CLK : signal is "XIL_INTERFACENAME clk_intf, ASSOCIATED_BUSIF s_intf:c_out_intf:sinit_intf:sset_intf:bypass_intf:c_in_intf:add_intf:b_intf:a_intf, ASSOCIATED_RESET SCLR, ASSOCIATED_CLKEN CE, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
attribute x_interface_info of SCLR : signal is "xilinx.com:signal:reset:1.0 sclr_intf RST";
attribute x_interface_parameter of SCLR : signal is "XIL_INTERFACENAME sclr_intf, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
attribute x_interface_info of A : signal is "xilinx.com:signal:data:1.0 a_intf DATA";
attribute x_interface_parameter of A : signal is "XIL_INTERFACENAME a_intf, LAYERED_METADATA undef";
attribute x_interface_info of B : signal is "xilinx.com:signal:data:1.0 b_intf DATA";
attribute x_interface_parameter of B : signal is "XIL_INTERFACENAME b_intf, LAYERED_METADATA undef";
attribute x_interface_info of S : signal is "xilinx.com:signal:data:1.0 s_intf DATA";
attribute x_interface_parameter of S : signal is "XIL_INTERFACENAME s_intf, LAYERED_METADATA undef";
begin
U0: entity work.add_s24_s32_s32_c_addsub_v12_0_13
port map (
A(23 downto 0) => A(23 downto 0),
ADD => '1',
B(31 downto 0) => B(31 downto 0),
BYPASS => '0',
CE => CE,
CLK => CLK,
C_IN => '0',
C_OUT => NLW_U0_C_OUT_UNCONNECTED,
S(31 downto 0) => S(31 downto 0),
SCLR => SCLR,
SINIT => '0',
SSET => '0'
);
end STRUCTURE;
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/add_s24_s32_s32/add_s24_s32_s32_stub.v
+25
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@@ -0,0 +1,25 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:33:37 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/add_s24_s32_s32_synth_1/add_s24_s32_s32_stub.v
// Design : add_s24_s32_s32
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "c_addsub_v12_0_13,Vivado 2019.1.3" *)
module add_s24_s32_s32(A, B, CLK, CE, SCLR, S)
/* synthesis syn_black_box black_box_pad_pin="A[23:0],B[31:0],CLK,CE,SCLR,S[31:0]" */;
input [23:0]A;
input [31:0]B;
input CLK;
input CE;
input SCLR;
output [31:0]S;
endmodule
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/add_s24_s32_s32/add_s24_s32_s32_stub.vhdl
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@@ -0,0 +1,35 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:33:37 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/add_s24_s32_s32_synth_1/add_s24_s32_s32_stub.vhdl
-- Design : add_s24_s32_s32
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity add_s24_s32_s32 is
Port (
A : in STD_LOGIC_VECTOR ( 23 downto 0 );
B : in STD_LOGIC_VECTOR ( 31 downto 0 );
CLK : in STD_LOGIC;
CE : in STD_LOGIC;
SCLR : in STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end add_s24_s32_s32;
architecture stub of add_s24_s32_s32 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "A[23:0],B[31:0],CLK,CE,SCLR,S[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "c_addsub_v12_0_13,Vivado 2019.1.3";
begin
end;
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/add_s24_s32_s32/sim/add_s24_s32_s32.vhd
+174
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@@ -0,0 +1,174 @@
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:c_addsub:12.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY c_addsub_v12_0_13;
USE c_addsub_v12_0_13.c_addsub_v12_0_13;
ENTITY add_s24_s32_s32 IS
PORT (
A : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
CLK : IN STD_LOGIC;
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END add_s24_s32_s32;
ARCHITECTURE add_s24_s32_s32_arch OF add_s24_s32_s32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF add_s24_s32_s32_arch: ARCHITECTURE IS "yes";
COMPONENT c_addsub_v12_0_13 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_XDEVICEFAMILY : STRING;
C_IMPLEMENTATION : INTEGER;
C_A_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_OUT_WIDTH : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_A_TYPE : INTEGER;
C_B_TYPE : INTEGER;
C_LATENCY : INTEGER;
C_ADD_MODE : INTEGER;
C_B_CONSTANT : INTEGER;
C_B_VALUE : STRING;
C_AINIT_VAL : STRING;
C_SINIT_VAL : STRING;
C_CE_OVERRIDES_BYPASS : INTEGER;
C_BYPASS_LOW : INTEGER;
C_SCLR_OVERRIDES_SSET : INTEGER;
C_HAS_C_IN : INTEGER;
C_HAS_C_OUT : INTEGER;
C_BORROW_LOW : INTEGER;
C_HAS_CE : INTEGER;
C_HAS_BYPASS : INTEGER;
C_HAS_SCLR : INTEGER;
C_HAS_SSET : INTEGER;
C_HAS_SINIT : INTEGER
);
PORT (
A : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
CLK : IN STD_LOGIC;
ADD : IN STD_LOGIC;
C_IN : IN STD_LOGIC;
CE : IN STD_LOGIC;
BYPASS : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
SSET : IN STD_LOGIC;
SINIT : IN STD_LOGIC;
C_OUT : OUT STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT c_addsub_v12_0_13;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF S: SIGNAL IS "XIL_INTERFACENAME s_intf, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF S: SIGNAL IS "xilinx.com:signal:data:1.0 s_intf DATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF SCLR: SIGNAL IS "XIL_INTERFACENAME sclr_intf, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF SCLR: SIGNAL IS "xilinx.com:signal:reset:1.0 sclr_intf RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF CE: SIGNAL IS "XIL_INTERFACENAME ce_intf, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF CE: SIGNAL IS "xilinx.com:signal:clockenable:1.0 ce_intf CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME clk_intf, ASSOCIATED_BUSIF s_intf:c_out_intf:sinit_intf:sset_intf:bypass_intf:c_in_intf:add_intf:b_intf:a_intf, ASSOCIATED_RESET SCLR, ASSOCIATED_CLKEN CE, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF B: SIGNAL IS "XIL_INTERFACENAME b_intf, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF A: SIGNAL IS "XIL_INTERFACENAME a_intf, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
BEGIN
U0 : c_addsub_v12_0_13
GENERIC MAP (
C_VERBOSITY => 0,
C_XDEVICEFAMILY => "kintex7",
C_IMPLEMENTATION => 0,
C_A_WIDTH => 24,
C_B_WIDTH => 32,
C_OUT_WIDTH => 32,
C_CE_OVERRIDES_SCLR => 0,
C_A_TYPE => 0,
C_B_TYPE => 0,
C_LATENCY => 1,
C_ADD_MODE => 0,
C_B_CONSTANT => 0,
C_B_VALUE => "00000000000000000000000000000000",
C_AINIT_VAL => "0",
C_SINIT_VAL => "0",
C_CE_OVERRIDES_BYPASS => 1,
C_BYPASS_LOW => 0,
C_SCLR_OVERRIDES_SSET => 1,
C_HAS_C_IN => 0,
C_HAS_C_OUT => 0,
C_BORROW_LOW => 1,
C_HAS_CE => 1,
C_HAS_BYPASS => 0,
C_HAS_SCLR => 1,
C_HAS_SSET => 0,
C_HAS_SINIT => 0
)
PORT MAP (
A => A,
B => B,
CLK => CLK,
ADD => '1',
C_IN => '0',
CE => CE,
BYPASS => '0',
SCLR => SCLR,
SSET => '0',
SINIT => '0',
S => S
);
END add_s24_s32_s32_arch;
projects/datalink_814/dl814_k7_cal_coarse/ip/ip_user_files/ip/ant_clk_gen_stg1/ant_clk_gen_stg1.v
+92
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// file: ant_clk_gen_stg1.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____96.000______0.000______50.0______168.397____161.614
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_____________250____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "ant_clk_gen_stg1,clk_wiz_v6_0_3_0_0,{component_name=ant_clk_gen_stg1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=4.000,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module ant_clk_gen_stg1
(
// Clock out ports
output clk_out1,
// Status and control signals
output locked,
// Clock in ports
input clk_in1_p,
input clk_in1_n
);
ant_clk_gen_stg1_clk_wiz inst
(
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
.locked(locked),
// Clock in ports
.clk_in1_p(clk_in1_p),
.clk_in1_n(clk_in1_n)
);
endmodule

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