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archive dl814_dj_48m, add dl814_k7_cal_coarse

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This commit is contained in:
josh
2023-03-21 20:20:28 +08:00
parent fa4d745322
commit 0832a08d3d
3264 changed files with 9610614 additions and 13 deletions
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projects/datalink_814/dl814_dj_48m/rtl/system_top.v
+8 -10
View File
@@ -343,24 +343,22 @@ assign tx_2_q = tx_data_q;
// <--------------------------------------------------------------------------->
// <--------------------- insert transmitter logic below ---------------------->
// <--------------------------------------------------------------------------->
wire [ 1:0] waveform_sel;
wire [ 2:0] waveform_sel;
wire sweep_on ;
wire [31:0] freq_set ;
wire [ 1:0] iq_sel ;
wire [ 3:0] bb_rshift ;
tx_qpsk #(
.DATA_WIDTH (16 ),
.CLK_FREQ (122880000 ),
.SQUARE_INTERP (32 )
) u_tx_qpsk
tx_control u_tx_wave
(
.clk (sys_clk ), // input clk
.rst (sys_rst ), // input rst
.sys_clk (sys_clk ), // input sys_clk
.sys_rst (sys_rst ), // input sys_rst
.sig_clk (sig_clk ), // input sig_clk
.sig_rst (sig_rst ), // input sig_rst
.tx_data_i (tx_data_i ), // output [15:0] tx_data_i
.tx_data_q (tx_data_q ), // output [15:0] tx_data_q
// debug ports
.waveform_sel (waveform_sel ), // input [ 1:0] waveform_sel
.waveform_sel (waveform_sel ), // input [ 2:0] waveform_sel
.sweep_on (sweep_on ), // input sweep_on
.freq_set (freq_set ), // input [31:0] freq_set
.iq_sel (iq_sel ), // input [ 1:0] iq_sel
@@ -418,7 +416,7 @@ ila_ctrl_signal u_ila_ctrl_signal
vio_manual_ctrl u_vio_manual_ctrl
(
.clk (sys_clk ), // input wire clk
.probe_out0 (waveform_sel ), // output wire [1 : 0] probe_out0
.probe_out0 (waveform_sel ), // output wire [2 : 0] probe_out0
.probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1
.probe_out2 (freq_set ), // output wire [31 : 0] probe_out2
.probe_out3 (iq_sel ), // output wire [1 : 0] probe_out3
projects/datalink_814/dl814_dj_48m/rtl/tx_control.v
+101
View File
@@ -0,0 +1,101 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/03/21 18:35:38
// Design Name:
// Module Name: tx_control
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tx_control
(
input sys_clk , // 122.88MHz
input sys_rst ,
input sig_clk , // 48MHz
input sig_rst ,
output [15:0] tx_data_i ,
output [15:0] tx_data_q ,
// debug ports
input [ 2:0] waveform_sel ,
input sweep_on ,
input [31:0] freq_set ,
input [ 1:0] iq_sel ,
input [ 3:0] bb_rshift
);
// pn seq
wire [15:0] tx_pn_seq_i;
wire [15:0] tx_pn_seq_q;
tx_pn_seq_6mcps #(
.DATA_WIDTH (16)
) u_tx_pn_seq
(
.sys_clk (sys_clk ), // 122.88MHz
.sys_rst (sys_rst ),
.sig_clk (sig_clk ), // 48MHz
.sig_rst (sig_rst ),
.tx_data_i (tx_pn_seq_i),
.tx_data_q (tx_pn_seq_q)
);
// qpsk
wire [15:0] tx_qpsk_i;
wire [15:0] tx_qpsk_q;
tx_qpsk #(
.DATA_WIDTH (16 ),
.SQUARE_INTERP (32 ),
.CLK_FREQ (122880000 )
) u_tx_qpsk
(
.clk (sys_clk ),
.rst (sys_rst ),
.tx_data_i (tx_qpsk_i ),
.tx_data_q (tx_qpsk_q ),
// debug ports
.waveform_sel (waveform_sel[1:0] ),
.sweep_on (sweep_on ),
.freq_set (freq_set ),
.iq_sel (iq_sel ),
.bb_rshift (bb_rshift )
);
// output
reg [15:0] tx_data_buf_i = 'b0;
reg [15:0] tx_data_buf_q = 'b0;
assign tx_data_i = tx_data_buf_i;
assign tx_data_q = tx_data_buf_q;
always @(posedge sys_clk) begin
if (sys_rst) begin
tx_data_buf_i <= 'b0;
tx_data_buf_q <= 'b0;
end
else if (waveform_sel) begin
tx_data_buf_i <= tx_pn_seq_i;
tx_data_buf_q <= tx_pn_seq_q;
end
else begin
tx_data_buf_i <= tx_qpsk_i;
tx_data_buf_q <= tx_qpsk_q;
end
end
endmodule
projects/datalink_814/dl814_dj_48m/rtl/tx_pn_seq_6mcps.v
+3 -3
View File
@@ -93,7 +93,7 @@ always @(posedge sig_clk) begin
end
end
else begin
hsq_wave[0] <= hsq_data ? {1'b0,{(MAX_DATA_WIDTH-2){1'b1}},1'b1} : {1'b1,{(MAX_DATA_WIDTH-2){1'b0}},1'b0};
hsq_wave[0] <= hsq_data ? {1'b0,{(MAX_DATA_WIDTH-2){1'b1}},1'b1} : {1'b1,{(MAX_DATA_WIDTH-2){1'b0}},1'b1};
hsq_wave[1] <= hsq_data ? {1'b1,{(MAX_DATA_WIDTH-2){1'b0}},1'b1} : {1'b0,{(MAX_DATA_WIDTH-2){1'b1}},1'b1};
end
end
@@ -122,8 +122,8 @@ fifo_48m_to_122p88m u_fifo_cdc
(
.wr_rst_busy ( ), // output wire wr_rst_busy
.rd_rst_busy ( ), // output wire rd_rst_busy
.m_aclk (sig_clk ), // input wire m_aclk
.s_aclk (sys_clk ), // input wire s_aclk
.m_aclk (sys_clk ), // input wire m_aclk
.s_aclk (sig_clk ), // input wire s_aclk
.s_aresetn (~sig_rst ), // input wire s_aresetn
.s_axis_tvalid (cdc_fifo_s_axis_valid[m] ), // input wire s_axis_tvalid
.s_axis_tready (cdc_fifo_s_axis_ready[m] ), // output wire s_axis_tready