archive dl814_dj_48m, add dl814_k7_cal_coarse

projects/datalink_814/dl814_dj_48m/rtl/tx_control.v

@@ -0,0 +1,101 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 2023/03/21 18:35:38
+// Design Name:
+// Module Name: tx_control
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tx_control
+(
+    input           sys_clk         , // 122.88MHz
+    input           sys_rst         ,
+    input           sig_clk         , // 48MHz
+    input           sig_rst         ,
+
+    output  [15:0]  tx_data_i       ,
+    output  [15:0]  tx_data_q       ,
+    // debug ports
+    input   [ 2:0]  waveform_sel    ,
+    input           sweep_on        ,
+    input   [31:0]  freq_set        ,
+    input   [ 1:0]  iq_sel          ,
+    input   [ 3:0]  bb_rshift
+);
+
+// pn seq
+wire [15:0] tx_pn_seq_i;
+wire [15:0] tx_pn_seq_q;
+
+tx_pn_seq_6mcps #(
+    .DATA_WIDTH (16)
+) u_tx_pn_seq
+(
+    .sys_clk    (sys_clk    ), // 122.88MHz
+    .sys_rst    (sys_rst    ),
+    .sig_clk    (sig_clk    ), // 48MHz
+    .sig_rst    (sig_rst    ),
+
+    .tx_data_i  (tx_pn_seq_i),
+    .tx_data_q  (tx_pn_seq_q)
+);
+
+// qpsk
+wire [15:0] tx_qpsk_i;
+wire [15:0] tx_qpsk_q;
+
+tx_qpsk #(
+    .DATA_WIDTH     (16         ),
+    .SQUARE_INTERP  (32         ),
+    .CLK_FREQ       (122880000  )
+) u_tx_qpsk
+(
+    .clk            (sys_clk            ),
+    .rst            (sys_rst            ),
+    .tx_data_i      (tx_qpsk_i          ),
+    .tx_data_q      (tx_qpsk_q          ),
+    // debug ports
+    .waveform_sel   (waveform_sel[1:0]  ),
+    .sweep_on       (sweep_on           ),
+    .freq_set       (freq_set           ),
+    .iq_sel         (iq_sel             ),
+    .bb_rshift      (bb_rshift          )
+);
+
+// output
+reg [15:0] tx_data_buf_i = 'b0;
+reg [15:0] tx_data_buf_q = 'b0;
+
+assign tx_data_i = tx_data_buf_i;
+assign tx_data_q = tx_data_buf_q;
+
+always @(posedge sys_clk) begin
+    if (sys_rst) begin
+        tx_data_buf_i <= 'b0;
+        tx_data_buf_q <= 'b0;
+    end
+    else if (waveform_sel) begin
+        tx_data_buf_i <= tx_pn_seq_i;
+        tx_data_buf_q <= tx_pn_seq_q;
+    end
+    else begin
+        tx_data_buf_i <= tx_qpsk_i;
+        tx_data_buf_q <= tx_qpsk_q;
+    end
+end
+
+endmodule