josh/vivado-202304
Archived
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fix dl814_k7_cal_coarse.tcl, former cannot use

Browse Source
This commit is contained in:
josh
2023-03-21 20:49:47 +08:00
parent 0832a08d3d
commit 59ab22f92c
5 changed files with 129 additions and 166 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/datalink_814/dl814_k7_cal_coarse/project/dl814_k7_cal_coarse.tcl
+107 -144
View File
@@ -3,7 +3,7 @@
#
# dl814_k7_cal_coarse.tcl: Tcl script for re-creating project 'dl814_k7_cal_coarse'
#
# Generated by Vivado on Tue Mar 21 20:18:34 +0800 2023
# Generated by Vivado on Tue Mar 21 20:47:28 +0800 2023
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -27,91 +27,91 @@
#
# 3. The following remote source files that were added to the original project:-
#
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_manual_ctrl/vio_manual_ctrl.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_rx/ila_rx.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_tx/ila_tx.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_ant_rd/vio_ant_rd.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_rf_rd/vio_rf_rd.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_ant_test/vio_ant_test.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_rfcontrl/vio_rfcontrl.xci"
# "D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci"
# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci"
# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci"
# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci"
# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/GaussFir_12m/GaussFir_12m.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/data_1p5m/data_1p5m.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/GaussFir_1mp5/GaussFir_1mp5.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ant_rf_interface/fifo_AntCtrl/fifo_AntCtrl.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ipi-bds/system_bd/system_bd.bd"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ant_clk_gen_stg2/ant_clk_gen_stg2.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ant_clk_gen_stg1/ant_clk_gen_stg1.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ad9361_clk_gen/ad9361_clk_gen.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/ADF4351_2.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/transmitter/AddrtoWaveform.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/FRAC1.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/transmitter/GMSK_send.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/INT_ROMb.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/R_CAL_1.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/R_CAL_2.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/R_CAL_3.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/R_CAL_4.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/Sisyif.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/T_CAL.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/ad9361_phase_cal_coarse.v"
# "D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_dual.v"
# "D:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_dual.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/adf4371_a.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/adf4371_b.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/ant_rf_ctrl.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/band_rom_a.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/band_rom_b.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/clk_dist.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/ds18b20_temp.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/frac2_rom.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/fre_caliatt.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/mgc_ctrl.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/mod2_rom.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/spi_master.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/spi_salve.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/spi_tx.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ipi-bds/system_bd/hdl/system_bd_wrapper.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/transmitter/tx_control.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/tx_pre_process.v"
# "D:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/rtl/tx_qpsk.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/system_top.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_cal/vio_cal.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_rx_pre/ila_rx_pre.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_cal/ila_cal.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/ram_hop_data/ram_hop_data.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/atan2_16b/atan2_16b.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rotate_16b/rotate_16b.xci"
# "D:/vivado-git/common/ApproxModuli_26bit.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/accor_mat_formatting.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/accum_cmplx_mat.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/acorr_cmplx_col_vec.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/ad9361_phase_cal_fine.v"
# "D:/vivado-git/common/adder_tree_ppl.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_process.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/spatial_filter.v"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/weight_vec_formatting.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_manual_ctrl/vio_manual_ctrl.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_rx/ila_rx.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_tx/ila_tx.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_ant_rd/vio_ant_rd.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_rf_rd/vio_rf_rd.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_AntCtrl/ila_AntCtrl.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_rfcontrl/ila_rfcontrl.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_ant_test/vio_ant_test.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_rfcontrl/vio_rfcontrl.xci"
# "d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci"
# "d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci"
# "d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci"
# "d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci"
# "d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/COSLUT_10_16bit/COSLUT_10_16bit.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/GaussFir_12m/GaussFir_12m.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/data_1p5m/data_1p5m.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/GaussFir_1mp5/GaussFir_1mp5.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ant_rf_interface/fifo_AntCtrl/fifo_AntCtrl.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ipi-bds/system_bd/system_bd.bd"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ant_clk_gen_stg2/ant_clk_gen_stg2.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ant_clk_gen_stg1/ant_clk_gen_stg1.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ad9361_clk_gen/ad9361_clk_gen.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/ADF4351_2.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/transmitter/AddrtoWaveform.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/FRAC1.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/transmitter/GMSK_send.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/INT_ROMb.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/R_CAL_1.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/R_CAL_2.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/R_CAL_3.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/R_CAL_4.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/Sisyif.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/T_CAL.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/ad9361_phase_cal_coarse.v"
# "d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_dual.v"
# "d:/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_dual.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/adf4371_a.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/adf4371_b.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/ant_rf_ctrl.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/band_rom_a.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/band_rom_b.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/clk_dist.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/ds18b20_temp.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/frac2_rom.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/fre_caliatt.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/mgc_ctrl.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/mod2_rom.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/spi_master.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/spi_salve.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/Sisyif_src/spi_tx.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ipi-bds/system_bd/hdl/system_bd_wrapper.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/transmitter/tx_control.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/tx_pre_process.v"
# "d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/rtl/tx_qpsk.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/system_top.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_cal/vio_cal.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_rx_pre/ila_rx_pre.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_cal/ila_cal.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/vio_clk_ld_rd/vio_clk_ld_rd.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/ram_hop_data/ram_hop_data.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/atan2_16b/atan2_16b.xci"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/rx_pre_process/rotate_16b/rotate_16b.xci"
# "d:/vivado-git/common/ApproxModuli_26bit.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/accor_mat_formatting.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/accum_cmplx_mat.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/acorr_cmplx_col_vec.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/ad9361_phase_cal_fine.v"
# "d:/vivado-git/common/adder_tree_ppl.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_process.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/spatial_filter.v"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/rtl/rx_pre_process/weight_vec_formatting.v"
# "d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe"
# "d:/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/coe/cos_8192_18bit.coe"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/coe/GaussFir_12m.coe"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/coe/data_1m5.coe"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/transmitter/coe/Gaussfir_1p5m.coe"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_rfcontrl/ila_rfcontrl.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/ila_AntCtrl/ila_AntCtrl.xci"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/constraints/k7401t_ad9516_2ad9361_physical.xdc"
# "D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/constraints/k7410t_ad9516_2ad9361_timing.xdc"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/constraints/k7401t_ad9516_2ad9361_physical.xdc"
# "d:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/constraints/k7410t_ad9516_2ad9361_timing.xdc"
#
#*****************************************************************************************
@@ -216,14 +216,13 @@ set_property -name "part" -value "xc7k410tffg900-2" -objects $obj
set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "43" -objects $obj
set_property -name "webtalk.ies_export_sim" -value "43" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "43" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "43" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "43" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "43" -objects $obj
set_property -name "webtalk.xcelium_export_sim" -value "4" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "43" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "45" -objects $obj
set_property -name "webtalk.ies_export_sim" -value "45" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "45" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "45" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "45" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "45" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "45" -objects $obj
set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
# Create 'sources_1' fileset (if not found)
@@ -246,6 +245,8 @@ set files [list \
[file normalize "${origin_dir}/../ip/ila_tx/ila_tx.xci"] \
[file normalize "${origin_dir}/../ip/vio_ant_rd/vio_ant_rd.xci"] \
[file normalize "${origin_dir}/../ip/vio_rf_rd/vio_rf_rd.xci"] \
[file normalize "${origin_dir}/../ip/ila_AntCtrl/ila_AntCtrl.xci"] \
[file normalize "${origin_dir}/../ip/ila_rfcontrl/ila_rfcontrl.xci"] \
[file normalize "${origin_dir}/../ip/vio_ant_test/vio_ant_test.xci"] \
[file normalize "${origin_dir}/../ip/vio_rfcontrl/vio_rfcontrl.xci"] \
[file normalize "${origin_dir}/../../../../modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci"] \
@@ -371,6 +372,24 @@ if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../ip/ila_AntCtrl/ila_AntCtrl.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
set_property -name "registered_with_manager" -value "1" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../ip/ila_rfcontrl/ila_rfcontrl.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
set_property -name "registered_with_manager" -value "1" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../ip/vio_ant_test/vio_ant_test.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
@@ -628,62 +647,6 @@ set obj [get_filesets sources_1]
set_property -name "top" -value "system_top" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
# Set IP repository paths
set obj [get_filesets ila_rfcontrl]
set_property "ip_repo_paths" "[file normalize "$origin_dir/../../../../adi_library"]" $obj
# Rebuild user ip_repo's index before adding any source files
update_ip_catalog -rebuild
# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
set files [list \
[file normalize "${origin_dir}/../ip/ila_rfcontrl/ila_rfcontrl.xci"] \
]
add_files -norecurse -fileset $obj $files
# Set 'sources_1' fileset file properties for remote files
set file "$origin_dir/../ip/ila_rfcontrl/ila_rfcontrl.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
set_property -name "registered_with_manager" -value "1" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
# Set 'sources_1' fileset file properties for local files
# None
# Set IP repository paths
set obj [get_filesets ila_AntCtrl]
set_property "ip_repo_paths" "[file normalize "$origin_dir/../../../../adi_library"]" $obj
# Rebuild user ip_repo's index before adding any source files
update_ip_catalog -rebuild
# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
set files [list \
[file normalize "${origin_dir}/../ip/ila_AntCtrl/ila_AntCtrl.xci"] \
]
add_files -norecurse -fileset $obj $files
# Set 'sources_1' fileset file properties for remote files
set file "$origin_dir/../ip/ila_AntCtrl/ila_AntCtrl.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
set_property -name "registered_with_manager" -value "1" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
# Set 'sources_1' fileset file properties for local files
# None
# Create 'constrs_1' fileset (if not found)
if {[string equal [get_filesets -quiet constrs_1] ""]} {
create_fileset -constrset constrs_1