update dl814_k7_cal_coarse

now rf control and lcmv autocorrelation data shares the same signal line by simply 'or' operation, so the two must be transmitted at different time, otherwise the data will collapse

projects/datalink_814/dl814_k7_cal_coarse/rtl/system_top.v

@@ -392,24 +392,48 @@ system_bd_wrapper u_system_bd_wrapper
 ///////////////// Phased-Array & RF Synthesizer Control & C2C //////////////////
 ////////////////////////////////////////////////////////////////////////////////
 // antenna & rf interface
-wire            rf_clk ;
-wire            rf_en  ;
-wire            rf_data;
-wire            rf_tr  ;
-wire            rf_dary;
-wire            rf_dout;
+wire rf_clk ;
+wire rf_en  ;
+wire rf_data;
+wire rf_tr  ;
+wire rf_dary;
+wire rf_dout;
 
-// output data
-assign ant_cin = rf_clk;
-// assign ant_din0 = accor_stream_data; // assigned afterwards
-assign ant_din1 = rf_data;
-assign ant_tr   = rf_tr;
-assign ant_dary = rf_dary;
+// nulling algorithm
+wire accor_stream_data;
+wire weight_stream_data;
+
+// buffer output data
+reg ant_cin_buf  = 'b0;
+reg ant_din1_buf = 'b0;
+reg ant_tr_buf   = 'b0;
+reg ant_dary_buf = 'b0;
+
+assign ant_cin  = ant_cin_buf ;
+assign ant_din1 = ant_din1_buf;
+assign ant_tr   = ant_tr_buf  ;
+assign ant_dary = ant_dary_buf;
+
+always @(posedge clk_96m) begin
+    if (ant_rst) begin
+        ant_cin_buf  <= 'b0;
+        ant_din1_buf <= 'b0;
+        ant_tr_buf   <= 'b0;
+        ant_dary_buf <= 'b0;
+    end
+    else begin
+        ant_cin_buf  <= rf_clk;
+        ant_din1_buf <= rf_data | accor_stream_data;
+        ant_tr_buf   <= rf_tr;
+        ant_dary_buf <= rf_dary;
+    end
+end
 
 // input data
 wire ant_dout0_cdc, ant_dout1_cdc;
 
 assign rf_dout = ant_dout1_cdc;
+assign weight_stream_data = ant_dout1_cdc;
 
 xpm_cdc_single u_cdc_ant_dout0
 (
@@ -576,14 +600,11 @@ wire    [29:0]  rx_data_i, rx_data_q;
 
 wire            hop_start_flag      ;
 wire            accor_stream_valid  ;
-wire            accor_stream_data   ;
-wire            weight_stream_data  ;
+// wire            accor_stream_data   ;
+// wire            weight_stream_data  ;
 
 wire    [11:0]  rx_data;
 
-assign weight_stream_data = ant_dout1_cdc;
-assign ant_din0 = accor_stream_data;
-
 ad9361_rx_map_cmos_dual u_ad9361_1_rx_map
 (
     .clk_2x_in      (ad9361_1_clk_2x    ), // input           clk_2x_in