Archived
Modify: k7 rf interface; dj tx interp
This commit is contained in:
+89
@@ -0,0 +1,89 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>1ad2c59fcdfd22ab</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>selectio_lvds_tx</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="selectio_wiz" spirit:version="5.1"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_OUT.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACTIVE_EDGE">RISING</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_DIR">OUTPUTS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_IN_DELAY">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_IN_TAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_IO_STD">LVCMOS33</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_OUT_DELAY">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_OUT_TAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_SIG_TYPE">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_TAP_RESET">NOT_APP</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_TAP_WRAP">NOT_APP</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_BUF">BUFIO2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_DELAY">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_EN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_FWD">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_FWD_IO_STD">LVCMOS33</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_FWD_SER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_FWD_SIG_TYPE">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IO_STD">LVCMOS18</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_SIG_TYPE">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_TAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONFIG_CLK_FWD">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">selectio_lvds_tx</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DDR_ALIGNMENT">C0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DDR_CLK_BUF">BUFR</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_BITSLIP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TRAIN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IDDR_RST_TYPE">ASYNC</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IDELAY_HIGH_PERF_MODE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_IDELAYCTRL">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_IDELAYCTRL_BUFG">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">NETWORKING</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NOTES">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_ACTIVE_EDGE">SDR</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_BUS_IN_DELAY">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_BUS_IN_TAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_BUS_OUT_DELAY">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_BUS_OUT_TAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_CLK_BUF">BUFIO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_CLK_IO_STD">LVCMOS33</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_CLK_SIG_TYPE">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_DDR_ALIGNMENT">SAME_EDGE_PIPELINED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_IDDR_RST_TYPE">ASYNC</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_INTERFACE_TYPE">NETWORKING</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_ODDR_ALIGNMENT">SAME_EDGE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SERIALIZATION_FACTOR">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYSTEM_DATA_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRAIN_CONSTANT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_DETECTOR">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SERIALIZATION">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_TEMPLATE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">1ad2c59fcdfd22ab</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESPECIALDATA">selectio_lvds_tx</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">af96b0bc</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">20</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">13</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
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||||
BIN
Binary file not shown.
+227
@@ -0,0 +1,227 @@
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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||||
// --------------------------------------------------------------------------------
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||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
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||||
// Date : Sun Mar 19 17:32:20 2023
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||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
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||||
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_sim_netlist.v
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// Design : selectio_lvds_tx
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// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
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// or synthesized. This netlist cannot be used for SDF annotated simulation.
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// Device : xc7k410tffg900-2
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// --------------------------------------------------------------------------------
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`timescale 1 ps / 1 ps
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(* DEV_W = "4" *) (* SYS_W = "4" *)
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(* NotValidForBitStream *)
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module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
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(data_out_from_device,
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data_out_to_pins,
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clk_in,
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||||
clk_out,
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||||
io_reset);
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||||
input [3:0]data_out_from_device;
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output [3:0]data_out_to_pins;
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input clk_in;
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output clk_out;
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input io_reset;
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||||
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(* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire clk_in;
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wire clk_out;
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wire [3:0]data_out_from_device;
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||||
(* DRIVE = "12" *) (* IOSTANDARD = "LVCMOS33" *) (* SLEW = "SLOW" *) wire [3:0]data_out_to_pins;
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wire io_reset;
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(* DEV_W = "4" *)
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(* SYS_W = "4" *)
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||||
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz inst
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||||
(.clk_in(clk_in),
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||||
.clk_out(clk_out),
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||||
.data_out_from_device(data_out_from_device),
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||||
.data_out_to_pins(data_out_to_pins),
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||||
.io_reset(io_reset));
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||||
endmodule
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||||
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||||
(* DEV_W = "4" *) (* SYS_W = "4" *)
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||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz
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(data_out_from_device,
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data_out_to_pins,
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clk_in,
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||||
clk_out,
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io_reset);
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||||
input [3:0]data_out_from_device;
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output [3:0]data_out_to_pins;
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||||
input clk_in;
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||||
output clk_out;
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||||
input io_reset;
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||||
|
||||
wire clk_in;
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||||
wire clk_in_int;
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||||
wire clk_out;
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||||
wire [3:0]data_out_from_device;
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||||
wire [3:0]data_out_to_pins;
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||||
wire io_reset;
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||||
wire \pins[0].data_out_from_device_q ;
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||||
wire \pins[1].data_out_from_device_q ;
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||||
wire \pins[2].data_out_from_device_q ;
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wire \pins[3].data_out_from_device_q ;
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||||
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||||
(* BOX_TYPE = "PRIMITIVE" *)
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BUFR #(
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.BUFR_DIVIDE("BYPASS"),
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.SIM_DEVICE("7SERIES"))
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clkout_buf_inst
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(.CE(1'b1),
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.CLR(1'b0),
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||||
.I(clk_in_int),
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.O(clk_out));
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||||
(* BOX_TYPE = "PRIMITIVE" *)
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||||
(* CAPACITANCE = "DONT_CARE" *)
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||||
(* IBUF_DELAY_VALUE = "0" *)
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||||
(* IFD_DELAY_VALUE = "AUTO" *)
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||||
IBUF ibuf_clk_inst
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||||
(.I(clk_in),
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||||
.O(clk_in_int));
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||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* IOB = "TRUE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
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||||
.IS_C_INVERTED(1'b0),
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||||
.IS_D_INVERTED(1'b0),
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||||
.IS_R_INVERTED(1'b0))
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||||
\pins[0].fdre_out_inst
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||||
(.C(clk_out),
|
||||
.CE(1'b1),
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||||
.D(data_out_from_device[0]),
|
||||
.Q(\pins[0].data_out_from_device_q ),
|
||||
.R(io_reset));
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||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* CAPACITANCE = "DONT_CARE" *)
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||||
OBUF \pins[0].obuf_inst
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||||
(.I(\pins[0].data_out_from_device_q ),
|
||||
.O(data_out_to_pins[0]));
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||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* IOB = "TRUE" *)
|
||||
FDRE #(
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||||
.INIT(1'b0),
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||||
.IS_C_INVERTED(1'b0),
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||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
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||||
\pins[1].fdre_out_inst
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||||
(.C(clk_out),
|
||||
.CE(1'b1),
|
||||
.D(data_out_from_device[1]),
|
||||
.Q(\pins[1].data_out_from_device_q ),
|
||||
.R(io_reset));
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||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
OBUF \pins[1].obuf_inst
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||||
(.I(\pins[1].data_out_from_device_q ),
|
||||
.O(data_out_to_pins[1]));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* IOB = "TRUE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\pins[2].fdre_out_inst
|
||||
(.C(clk_out),
|
||||
.CE(1'b1),
|
||||
.D(data_out_from_device[2]),
|
||||
.Q(\pins[2].data_out_from_device_q ),
|
||||
.R(io_reset));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
OBUF \pins[2].obuf_inst
|
||||
(.I(\pins[2].data_out_from_device_q ),
|
||||
.O(data_out_to_pins[2]));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* IOB = "TRUE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\pins[3].fdre_out_inst
|
||||
(.C(clk_out),
|
||||
.CE(1'b1),
|
||||
.D(data_out_from_device[3]),
|
||||
.Q(\pins[3].data_out_from_device_q ),
|
||||
.R(io_reset));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
OBUF \pins[3].obuf_inst
|
||||
(.I(\pins[3].data_out_from_device_q ),
|
||||
.O(data_out_to_pins[3]));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+191
@@ -0,0 +1,191 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sun Mar 19 17:32:20 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_sim_netlist.vhdl
|
||||
-- Design : selectio_lvds_tx
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz is
|
||||
port (
|
||||
data_out_from_device : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
data_out_to_pins : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
clk_in : in STD_LOGIC;
|
||||
clk_out : out STD_LOGIC;
|
||||
io_reset : in STD_LOGIC
|
||||
);
|
||||
attribute DEV_W : integer;
|
||||
attribute DEV_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz : entity is 4;
|
||||
attribute SYS_W : integer;
|
||||
attribute SYS_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz : entity is 4;
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz is
|
||||
signal clk_in_int : STD_LOGIC;
|
||||
signal \^clk_out\ : STD_LOGIC;
|
||||
signal \pins[0].data_out_from_device_q\ : STD_LOGIC;
|
||||
signal \pins[1].data_out_from_device_q\ : STD_LOGIC;
|
||||
signal \pins[2].data_out_from_device_q\ : STD_LOGIC;
|
||||
signal \pins[3].data_out_from_device_q\ : STD_LOGIC;
|
||||
attribute BOX_TYPE : string;
|
||||
attribute BOX_TYPE of clkout_buf_inst : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of ibuf_clk_inst : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE : string;
|
||||
attribute CAPACITANCE of ibuf_clk_inst : label is "DONT_CARE";
|
||||
attribute IBUF_DELAY_VALUE : string;
|
||||
attribute IBUF_DELAY_VALUE of ibuf_clk_inst : label is "0";
|
||||
attribute IFD_DELAY_VALUE : string;
|
||||
attribute IFD_DELAY_VALUE of ibuf_clk_inst : label is "AUTO";
|
||||
attribute BOX_TYPE of \pins[0].fdre_out_inst\ : label is "PRIMITIVE";
|
||||
attribute IOB : string;
|
||||
attribute IOB of \pins[0].fdre_out_inst\ : label is "TRUE";
|
||||
attribute BOX_TYPE of \pins[0].obuf_inst\ : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE of \pins[0].obuf_inst\ : label is "DONT_CARE";
|
||||
attribute BOX_TYPE of \pins[1].fdre_out_inst\ : label is "PRIMITIVE";
|
||||
attribute IOB of \pins[1].fdre_out_inst\ : label is "TRUE";
|
||||
attribute BOX_TYPE of \pins[1].obuf_inst\ : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE of \pins[1].obuf_inst\ : label is "DONT_CARE";
|
||||
attribute BOX_TYPE of \pins[2].fdre_out_inst\ : label is "PRIMITIVE";
|
||||
attribute IOB of \pins[2].fdre_out_inst\ : label is "TRUE";
|
||||
attribute BOX_TYPE of \pins[2].obuf_inst\ : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE of \pins[2].obuf_inst\ : label is "DONT_CARE";
|
||||
attribute BOX_TYPE of \pins[3].fdre_out_inst\ : label is "PRIMITIVE";
|
||||
attribute IOB of \pins[3].fdre_out_inst\ : label is "TRUE";
|
||||
attribute BOX_TYPE of \pins[3].obuf_inst\ : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE of \pins[3].obuf_inst\ : label is "DONT_CARE";
|
||||
begin
|
||||
clk_out <= \^clk_out\;
|
||||
clkout_buf_inst: unisim.vcomponents.BUFR
|
||||
generic map(
|
||||
BUFR_DIVIDE => "BYPASS",
|
||||
SIM_DEVICE => "7SERIES"
|
||||
)
|
||||
port map (
|
||||
CE => '1',
|
||||
CLR => '0',
|
||||
I => clk_in_int,
|
||||
O => \^clk_out\
|
||||
);
|
||||
ibuf_clk_inst: unisim.vcomponents.IBUF
|
||||
port map (
|
||||
I => clk_in,
|
||||
O => clk_in_int
|
||||
);
|
||||
\pins[0].fdre_out_inst\: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '0',
|
||||
IS_C_INVERTED => '0',
|
||||
IS_D_INVERTED => '0',
|
||||
IS_R_INVERTED => '0'
|
||||
)
|
||||
port map (
|
||||
C => \^clk_out\,
|
||||
CE => '1',
|
||||
D => data_out_from_device(0),
|
||||
Q => \pins[0].data_out_from_device_q\,
|
||||
R => io_reset
|
||||
);
|
||||
\pins[0].obuf_inst\: unisim.vcomponents.OBUF
|
||||
port map (
|
||||
I => \pins[0].data_out_from_device_q\,
|
||||
O => data_out_to_pins(0)
|
||||
);
|
||||
\pins[1].fdre_out_inst\: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '0',
|
||||
IS_C_INVERTED => '0',
|
||||
IS_D_INVERTED => '0',
|
||||
IS_R_INVERTED => '0'
|
||||
)
|
||||
port map (
|
||||
C => \^clk_out\,
|
||||
CE => '1',
|
||||
D => data_out_from_device(1),
|
||||
Q => \pins[1].data_out_from_device_q\,
|
||||
R => io_reset
|
||||
);
|
||||
\pins[1].obuf_inst\: unisim.vcomponents.OBUF
|
||||
port map (
|
||||
I => \pins[1].data_out_from_device_q\,
|
||||
O => data_out_to_pins(1)
|
||||
);
|
||||
\pins[2].fdre_out_inst\: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '0',
|
||||
IS_C_INVERTED => '0',
|
||||
IS_D_INVERTED => '0',
|
||||
IS_R_INVERTED => '0'
|
||||
)
|
||||
port map (
|
||||
C => \^clk_out\,
|
||||
CE => '1',
|
||||
D => data_out_from_device(2),
|
||||
Q => \pins[2].data_out_from_device_q\,
|
||||
R => io_reset
|
||||
);
|
||||
\pins[2].obuf_inst\: unisim.vcomponents.OBUF
|
||||
port map (
|
||||
I => \pins[2].data_out_from_device_q\,
|
||||
O => data_out_to_pins(2)
|
||||
);
|
||||
\pins[3].fdre_out_inst\: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '0',
|
||||
IS_C_INVERTED => '0',
|
||||
IS_D_INVERTED => '0',
|
||||
IS_R_INVERTED => '0'
|
||||
)
|
||||
port map (
|
||||
C => \^clk_out\,
|
||||
CE => '1',
|
||||
D => data_out_from_device(3),
|
||||
Q => \pins[3].data_out_from_device_q\,
|
||||
R => io_reset
|
||||
);
|
||||
\pins[3].obuf_inst\: unisim.vcomponents.OBUF
|
||||
port map (
|
||||
I => \pins[3].data_out_from_device_q\,
|
||||
O => data_out_to_pins(3)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
port (
|
||||
data_out_from_device : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
data_out_to_pins : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
clk_in : in STD_LOGIC;
|
||||
clk_out : out STD_LOGIC;
|
||||
io_reset : in STD_LOGIC
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
|
||||
attribute DEV_W : integer;
|
||||
attribute DEV_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is 4;
|
||||
attribute SYS_W : integer;
|
||||
attribute SYS_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is 4;
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute DEV_W of inst : label is 4;
|
||||
attribute SYS_W of inst : label is 4;
|
||||
begin
|
||||
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_tx_selectio_wiz
|
||||
port map (
|
||||
clk_in => clk_in,
|
||||
clk_out => clk_out,
|
||||
data_out_from_device(3 downto 0) => data_out_from_device(3 downto 0),
|
||||
data_out_to_pins(3 downto 0) => data_out_to_pins(3 downto 0),
|
||||
io_reset => io_reset
|
||||
);
|
||||
end STRUCTURE;
|
||||
+24
@@ -0,0 +1,24 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sun Mar 19 17:32:20 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_stub.v
|
||||
// Design : selectio_lvds_tx
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(data_out_from_device, data_out_to_pins,
|
||||
clk_in, clk_out, io_reset)
|
||||
/* synthesis syn_black_box black_box_pad_pin="data_out_from_device[3:0],data_out_to_pins[3:0],clk_in,clk_out,io_reset" */;
|
||||
input [3:0]data_out_from_device;
|
||||
output [3:0]data_out_to_pins;
|
||||
input clk_in;
|
||||
output clk_out;
|
||||
input io_reset;
|
||||
endmodule
|
||||
+32
@@ -0,0 +1,32 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sun Mar 19 17:32:20 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_stub.vhdl
|
||||
-- Design : selectio_lvds_tx
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
data_out_from_device : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
data_out_to_pins : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
clk_in : in STD_LOGIC;
|
||||
clk_out : out STD_LOGIC;
|
||||
io_reset : in STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "data_out_from_device[3:0],data_out_to_pins[3:0],clk_in,clk_out,io_reset";
|
||||
begin
|
||||
end;
|
||||
+89
@@ -0,0 +1,89 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>9a6afb606ad4ce08</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>selectio_lvds_rx</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="selectio_wiz" spirit:version="5.1"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_OUT.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACTIVE_EDGE">RISING</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_DIR">INPUTS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_IN_DELAY">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_IN_TAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_IO_STD">LVCMOS33</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_OUT_DELAY">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_OUT_TAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_SIG_TYPE">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_TAP_RESET">NOT_APP</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_TAP_WRAP">NOT_APP</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_BUF">BUFIO2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_DELAY">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_EN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_FWD">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_FWD_IO_STD">LVCMOS33</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_FWD_SER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_FWD_SIG_TYPE">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IO_STD">LVCMOS18</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_SIG_TYPE">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_TAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONFIG_CLK_FWD">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">selectio_lvds_rx</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DDR_ALIGNMENT">C0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DDR_CLK_BUF">BUFR</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_BITSLIP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TRAIN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IDDR_RST_TYPE">ASYNC</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IDELAY_HIGH_PERF_MODE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_IDELAYCTRL">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_IDELAYCTRL_BUFG">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">NETWORKING</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NOTES">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_ACTIVE_EDGE">SDR</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_BUS_IN_DELAY">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_BUS_IN_TAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_BUS_OUT_DELAY">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_BUS_OUT_TAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_CLK_BUF">BUFIO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_CLK_IO_STD">LVCMOS33</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_CLK_SIG_TYPE">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_DDR_ALIGNMENT">SAME_EDGE_PIPELINED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_IDDR_RST_TYPE">ASYNC</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_INTERFACE_TYPE">NETWORKING</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_ODDR_ALIGNMENT">SAME_EDGE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SERIALIZATION_FACTOR">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYSTEM_DATA_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRAIN_CONSTANT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_DETECTOR">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SERIALIZATION">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_TEMPLATE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">9a6afb606ad4ce08</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESPECIALDATA">selectio_lvds_rx</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">af96b0bc</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">20</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">13</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
BIN
Binary file not shown.
+172
@@ -0,0 +1,172 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sun Mar 19 17:32:20 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_sim_netlist.v
|
||||
// Design : selectio_lvds_rx
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* DEV_W = "1" *) (* SYS_W = "1" *)
|
||||
(* NotValidForBitStream *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
|
||||
(data_in_from_pins,
|
||||
data_in_to_device,
|
||||
clk_in,
|
||||
clk_out,
|
||||
io_reset);
|
||||
input [0:0]data_in_from_pins;
|
||||
output [0:0]data_in_to_device;
|
||||
input clk_in;
|
||||
output clk_out;
|
||||
input io_reset;
|
||||
|
||||
(* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire clk_in;
|
||||
wire clk_out;
|
||||
(* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire [0:0]data_in_from_pins;
|
||||
wire [0:0]data_in_to_device;
|
||||
wire io_reset;
|
||||
|
||||
(* DEV_W = "1" *)
|
||||
(* SYS_W = "1" *)
|
||||
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz inst
|
||||
(.clk_in(clk_in),
|
||||
.clk_out(clk_out),
|
||||
.data_in_from_pins(data_in_from_pins),
|
||||
.data_in_to_device(data_in_to_device),
|
||||
.io_reset(io_reset));
|
||||
endmodule
|
||||
|
||||
(* DEV_W = "1" *) (* SYS_W = "1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz
|
||||
(data_in_from_pins,
|
||||
data_in_to_device,
|
||||
clk_in,
|
||||
clk_out,
|
||||
io_reset);
|
||||
input [0:0]data_in_from_pins;
|
||||
output [0:0]data_in_to_device;
|
||||
input clk_in;
|
||||
output clk_out;
|
||||
input io_reset;
|
||||
|
||||
wire clk_in;
|
||||
wire clk_in_int;
|
||||
wire clk_out;
|
||||
wire [0:0]data_in_from_pins;
|
||||
wire data_in_from_pins_int;
|
||||
wire [0:0]data_in_to_device;
|
||||
wire io_reset;
|
||||
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFR #(
|
||||
.BUFR_DIVIDE("BYPASS"),
|
||||
.SIM_DEVICE("7SERIES"))
|
||||
clkout_buf_inst
|
||||
(.CE(1'b1),
|
||||
.CLR(1'b0),
|
||||
.I(clk_in_int),
|
||||
.O(clk_out));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
(* IBUF_DELAY_VALUE = "0" *)
|
||||
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||
IBUF ibuf_clk_inst
|
||||
(.I(clk_in),
|
||||
.O(clk_in_int));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* IOB = "TRUE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\pins[0].fdre_in_inst
|
||||
(.C(clk_out),
|
||||
.CE(1'b1),
|
||||
.D(data_in_from_pins_int),
|
||||
.Q(data_in_to_device),
|
||||
.R(io_reset));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
(* IBUF_DELAY_VALUE = "0" *)
|
||||
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||
IBUF \pins[0].ibuf_inst
|
||||
(.I(data_in_from_pins),
|
||||
.O(data_in_from_pins_int));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+121
@@ -0,0 +1,121 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sun Mar 19 17:32:20 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_sim_netlist.vhdl
|
||||
-- Design : selectio_lvds_rx
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz is
|
||||
port (
|
||||
data_in_from_pins : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
data_in_to_device : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
clk_in : in STD_LOGIC;
|
||||
clk_out : out STD_LOGIC;
|
||||
io_reset : in STD_LOGIC
|
||||
);
|
||||
attribute DEV_W : integer;
|
||||
attribute DEV_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz : entity is 1;
|
||||
attribute SYS_W : integer;
|
||||
attribute SYS_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz : entity is 1;
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz is
|
||||
signal clk_in_int : STD_LOGIC;
|
||||
signal \^clk_out\ : STD_LOGIC;
|
||||
signal data_in_from_pins_int : STD_LOGIC;
|
||||
attribute BOX_TYPE : string;
|
||||
attribute BOX_TYPE of clkout_buf_inst : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of ibuf_clk_inst : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE : string;
|
||||
attribute CAPACITANCE of ibuf_clk_inst : label is "DONT_CARE";
|
||||
attribute IBUF_DELAY_VALUE : string;
|
||||
attribute IBUF_DELAY_VALUE of ibuf_clk_inst : label is "0";
|
||||
attribute IFD_DELAY_VALUE : string;
|
||||
attribute IFD_DELAY_VALUE of ibuf_clk_inst : label is "AUTO";
|
||||
attribute BOX_TYPE of \pins[0].fdre_in_inst\ : label is "PRIMITIVE";
|
||||
attribute IOB : string;
|
||||
attribute IOB of \pins[0].fdre_in_inst\ : label is "TRUE";
|
||||
attribute BOX_TYPE of \pins[0].ibuf_inst\ : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE of \pins[0].ibuf_inst\ : label is "DONT_CARE";
|
||||
attribute IBUF_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "0";
|
||||
attribute IFD_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "AUTO";
|
||||
begin
|
||||
clk_out <= \^clk_out\;
|
||||
clkout_buf_inst: unisim.vcomponents.BUFR
|
||||
generic map(
|
||||
BUFR_DIVIDE => "BYPASS",
|
||||
SIM_DEVICE => "7SERIES"
|
||||
)
|
||||
port map (
|
||||
CE => '1',
|
||||
CLR => '0',
|
||||
I => clk_in_int,
|
||||
O => \^clk_out\
|
||||
);
|
||||
ibuf_clk_inst: unisim.vcomponents.IBUF
|
||||
port map (
|
||||
I => clk_in,
|
||||
O => clk_in_int
|
||||
);
|
||||
\pins[0].fdre_in_inst\: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '0',
|
||||
IS_C_INVERTED => '0',
|
||||
IS_D_INVERTED => '0',
|
||||
IS_R_INVERTED => '0'
|
||||
)
|
||||
port map (
|
||||
C => \^clk_out\,
|
||||
CE => '1',
|
||||
D => data_in_from_pins_int,
|
||||
Q => data_in_to_device(0),
|
||||
R => io_reset
|
||||
);
|
||||
\pins[0].ibuf_inst\: unisim.vcomponents.IBUF
|
||||
port map (
|
||||
I => data_in_from_pins(0),
|
||||
O => data_in_from_pins_int
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
port (
|
||||
data_in_from_pins : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
data_in_to_device : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
clk_in : in STD_LOGIC;
|
||||
clk_out : out STD_LOGIC;
|
||||
io_reset : in STD_LOGIC
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
|
||||
attribute DEV_W : integer;
|
||||
attribute DEV_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is 1;
|
||||
attribute SYS_W : integer;
|
||||
attribute SYS_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is 1;
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute DEV_W of inst : label is 1;
|
||||
attribute SYS_W of inst : label is 1;
|
||||
begin
|
||||
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz
|
||||
port map (
|
||||
clk_in => clk_in,
|
||||
clk_out => clk_out,
|
||||
data_in_from_pins(0) => data_in_from_pins(0),
|
||||
data_in_to_device(0) => data_in_to_device(0),
|
||||
io_reset => io_reset
|
||||
);
|
||||
end STRUCTURE;
|
||||
+24
@@ -0,0 +1,24 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sun Mar 19 17:32:20 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_stub.v
|
||||
// Design : selectio_lvds_rx
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(data_in_from_pins, data_in_to_device, clk_in,
|
||||
clk_out, io_reset)
|
||||
/* synthesis syn_black_box black_box_pad_pin="data_in_from_pins[0:0],data_in_to_device[0:0],clk_in,clk_out,io_reset" */;
|
||||
input [0:0]data_in_from_pins;
|
||||
output [0:0]data_in_to_device;
|
||||
input clk_in;
|
||||
output clk_out;
|
||||
input io_reset;
|
||||
endmodule
|
||||
+32
@@ -0,0 +1,32 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sun Mar 19 17:32:20 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_stub.vhdl
|
||||
-- Design : selectio_lvds_rx
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
data_in_from_pins : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
data_in_to_device : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
clk_in : in STD_LOGIC;
|
||||
clk_out : out STD_LOGIC;
|
||||
io_reset : in STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "data_in_from_pins[0:0],data_in_to_device[0:0],clk_in,clk_out,io_reset";
|
||||
begin
|
||||
end;
|
||||
+2
@@ -0,0 +1,2 @@
|
||||
NumberHits:1
|
||||
Timestamp: Sun Mar 19 09:31:54 UTC 2023
|
||||
+89
@@ -0,0 +1,89 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>c2b0e4781c06dae9</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>selectio_lvds_rx</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="selectio_wiz" spirit:version="5.1"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_OUT.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACTIVE_EDGE">RISING</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_DIR">INPUTS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_IN_DELAY">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_IN_TAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_IO_STD">LVCMOS33</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_OUT_DELAY">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_OUT_TAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_SIG_TYPE">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_TAP_RESET">NOT_APP</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_TAP_WRAP">NOT_APP</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_BUF">BUFIO2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_DELAY">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_EN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_FWD">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_FWD_IO_STD">LVCMOS33</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_FWD_SER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_FWD_SIG_TYPE">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IO_STD">LVCMOS18</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_SIG_TYPE">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_TAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONFIG_CLK_FWD">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">selectio_lvds_rx</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DDR_ALIGNMENT">C0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DDR_CLK_BUF">BUFR</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_BITSLIP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TRAIN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IDDR_RST_TYPE">ASYNC</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IDELAY_HIGH_PERF_MODE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_IDELAYCTRL">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_IDELAYCTRL_BUFG">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">NETWORKING</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NOTES">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_ACTIVE_EDGE">SDR</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_BUS_IN_DELAY">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_BUS_IN_TAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_BUS_OUT_DELAY">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_BUS_OUT_TAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_CLK_BUF">BUFIO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_CLK_IO_STD">LVCMOS33</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_CLK_SIG_TYPE">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_DDR_ALIGNMENT">SAME_EDGE_PIPELINED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_IDDR_RST_TYPE">ASYNC</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_INTERFACE_TYPE">NETWORKING</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_ODDR_ALIGNMENT">SAME_EDGE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SERIALIZATION_FACTOR">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYSTEM_DATA_WIDTH">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRAIN_CONSTANT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_DETECTOR">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SERIALIZATION">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_TEMPLATE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">c2b0e4781c06dae9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESPECIALDATA">selectio_lvds_rx</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">af96b0bc</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">19</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">13</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
BIN
Binary file not shown.
+192
@@ -0,0 +1,192 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sun Mar 19 18:02:10 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_sim_netlist.v
|
||||
// Design : selectio_lvds_rx
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* DEV_W = "2" *) (* SYS_W = "2" *)
|
||||
(* NotValidForBitStream *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
|
||||
(data_in_from_pins,
|
||||
data_in_to_device,
|
||||
clk_in,
|
||||
clk_out,
|
||||
io_reset);
|
||||
input [1:0]data_in_from_pins;
|
||||
output [1:0]data_in_to_device;
|
||||
input clk_in;
|
||||
output clk_out;
|
||||
input io_reset;
|
||||
|
||||
(* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire clk_in;
|
||||
wire clk_out;
|
||||
(* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire [1:0]data_in_from_pins;
|
||||
wire [1:0]data_in_to_device;
|
||||
wire io_reset;
|
||||
|
||||
(* DEV_W = "2" *)
|
||||
(* SYS_W = "2" *)
|
||||
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz inst
|
||||
(.clk_in(clk_in),
|
||||
.clk_out(clk_out),
|
||||
.data_in_from_pins(data_in_from_pins),
|
||||
.data_in_to_device(data_in_to_device),
|
||||
.io_reset(io_reset));
|
||||
endmodule
|
||||
|
||||
(* DEV_W = "2" *) (* SYS_W = "2" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz
|
||||
(data_in_from_pins,
|
||||
data_in_to_device,
|
||||
clk_in,
|
||||
clk_out,
|
||||
io_reset);
|
||||
input [1:0]data_in_from_pins;
|
||||
output [1:0]data_in_to_device;
|
||||
input clk_in;
|
||||
output clk_out;
|
||||
input io_reset;
|
||||
|
||||
wire clk_in;
|
||||
wire clk_in_int;
|
||||
wire clk_out;
|
||||
wire [1:0]data_in_from_pins;
|
||||
wire [1:0]data_in_from_pins_int;
|
||||
wire [1:0]data_in_to_device;
|
||||
wire io_reset;
|
||||
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFR #(
|
||||
.BUFR_DIVIDE("BYPASS"),
|
||||
.SIM_DEVICE("7SERIES"))
|
||||
clkout_buf_inst
|
||||
(.CE(1'b1),
|
||||
.CLR(1'b0),
|
||||
.I(clk_in_int),
|
||||
.O(clk_out));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
(* IBUF_DELAY_VALUE = "0" *)
|
||||
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||
IBUF ibuf_clk_inst
|
||||
(.I(clk_in),
|
||||
.O(clk_in_int));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* IOB = "TRUE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\pins[0].fdre_in_inst
|
||||
(.C(clk_out),
|
||||
.CE(1'b1),
|
||||
.D(data_in_from_pins_int[0]),
|
||||
.Q(data_in_to_device[0]),
|
||||
.R(io_reset));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
(* IBUF_DELAY_VALUE = "0" *)
|
||||
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||
IBUF \pins[0].ibuf_inst
|
||||
(.I(data_in_from_pins[0]),
|
||||
.O(data_in_from_pins_int[0]));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* IOB = "TRUE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\pins[1].fdre_in_inst
|
||||
(.C(clk_out),
|
||||
.CE(1'b1),
|
||||
.D(data_in_from_pins_int[1]),
|
||||
.Q(data_in_to_device[1]),
|
||||
.R(io_reset));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
(* IBUF_DELAY_VALUE = "0" *)
|
||||
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||
IBUF \pins[1].ibuf_inst
|
||||
(.I(data_in_from_pins[1]),
|
||||
.O(data_in_from_pins_int[1]));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+146
@@ -0,0 +1,146 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sun Mar 19 18:02:10 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_sim_netlist.vhdl
|
||||
-- Design : selectio_lvds_rx
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz is
|
||||
port (
|
||||
data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
clk_in : in STD_LOGIC;
|
||||
clk_out : out STD_LOGIC;
|
||||
io_reset : in STD_LOGIC
|
||||
);
|
||||
attribute DEV_W : integer;
|
||||
attribute DEV_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz : entity is 2;
|
||||
attribute SYS_W : integer;
|
||||
attribute SYS_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz : entity is 2;
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz is
|
||||
signal clk_in_int : STD_LOGIC;
|
||||
signal \^clk_out\ : STD_LOGIC;
|
||||
signal data_in_from_pins_int : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
attribute BOX_TYPE : string;
|
||||
attribute BOX_TYPE of clkout_buf_inst : label is "PRIMITIVE";
|
||||
attribute BOX_TYPE of ibuf_clk_inst : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE : string;
|
||||
attribute CAPACITANCE of ibuf_clk_inst : label is "DONT_CARE";
|
||||
attribute IBUF_DELAY_VALUE : string;
|
||||
attribute IBUF_DELAY_VALUE of ibuf_clk_inst : label is "0";
|
||||
attribute IFD_DELAY_VALUE : string;
|
||||
attribute IFD_DELAY_VALUE of ibuf_clk_inst : label is "AUTO";
|
||||
attribute BOX_TYPE of \pins[0].fdre_in_inst\ : label is "PRIMITIVE";
|
||||
attribute IOB : string;
|
||||
attribute IOB of \pins[0].fdre_in_inst\ : label is "TRUE";
|
||||
attribute BOX_TYPE of \pins[0].ibuf_inst\ : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE of \pins[0].ibuf_inst\ : label is "DONT_CARE";
|
||||
attribute IBUF_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "0";
|
||||
attribute IFD_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "AUTO";
|
||||
attribute BOX_TYPE of \pins[1].fdre_in_inst\ : label is "PRIMITIVE";
|
||||
attribute IOB of \pins[1].fdre_in_inst\ : label is "TRUE";
|
||||
attribute BOX_TYPE of \pins[1].ibuf_inst\ : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE of \pins[1].ibuf_inst\ : label is "DONT_CARE";
|
||||
attribute IBUF_DELAY_VALUE of \pins[1].ibuf_inst\ : label is "0";
|
||||
attribute IFD_DELAY_VALUE of \pins[1].ibuf_inst\ : label is "AUTO";
|
||||
begin
|
||||
clk_out <= \^clk_out\;
|
||||
clkout_buf_inst: unisim.vcomponents.BUFR
|
||||
generic map(
|
||||
BUFR_DIVIDE => "BYPASS",
|
||||
SIM_DEVICE => "7SERIES"
|
||||
)
|
||||
port map (
|
||||
CE => '1',
|
||||
CLR => '0',
|
||||
I => clk_in_int,
|
||||
O => \^clk_out\
|
||||
);
|
||||
ibuf_clk_inst: unisim.vcomponents.IBUF
|
||||
port map (
|
||||
I => clk_in,
|
||||
O => clk_in_int
|
||||
);
|
||||
\pins[0].fdre_in_inst\: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '0',
|
||||
IS_C_INVERTED => '0',
|
||||
IS_D_INVERTED => '0',
|
||||
IS_R_INVERTED => '0'
|
||||
)
|
||||
port map (
|
||||
C => \^clk_out\,
|
||||
CE => '1',
|
||||
D => data_in_from_pins_int(0),
|
||||
Q => data_in_to_device(0),
|
||||
R => io_reset
|
||||
);
|
||||
\pins[0].ibuf_inst\: unisim.vcomponents.IBUF
|
||||
port map (
|
||||
I => data_in_from_pins(0),
|
||||
O => data_in_from_pins_int(0)
|
||||
);
|
||||
\pins[1].fdre_in_inst\: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '0',
|
||||
IS_C_INVERTED => '0',
|
||||
IS_D_INVERTED => '0',
|
||||
IS_R_INVERTED => '0'
|
||||
)
|
||||
port map (
|
||||
C => \^clk_out\,
|
||||
CE => '1',
|
||||
D => data_in_from_pins_int(1),
|
||||
Q => data_in_to_device(1),
|
||||
R => io_reset
|
||||
);
|
||||
\pins[1].ibuf_inst\: unisim.vcomponents.IBUF
|
||||
port map (
|
||||
I => data_in_from_pins(1),
|
||||
O => data_in_from_pins_int(1)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
port (
|
||||
data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
clk_in : in STD_LOGIC;
|
||||
clk_out : out STD_LOGIC;
|
||||
io_reset : in STD_LOGIC
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
|
||||
attribute DEV_W : integer;
|
||||
attribute DEV_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is 2;
|
||||
attribute SYS_W : integer;
|
||||
attribute SYS_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is 2;
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute DEV_W of inst : label is 2;
|
||||
attribute SYS_W of inst : label is 2;
|
||||
begin
|
||||
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz
|
||||
port map (
|
||||
clk_in => clk_in,
|
||||
clk_out => clk_out,
|
||||
data_in_from_pins(1 downto 0) => data_in_from_pins(1 downto 0),
|
||||
data_in_to_device(1 downto 0) => data_in_to_device(1 downto 0),
|
||||
io_reset => io_reset
|
||||
);
|
||||
end STRUCTURE;
|
||||
+24
@@ -0,0 +1,24 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sun Mar 19 18:02:10 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_stub.v
|
||||
// Design : selectio_lvds_rx
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(data_in_from_pins, data_in_to_device, clk_in,
|
||||
clk_out, io_reset)
|
||||
/* synthesis syn_black_box black_box_pad_pin="data_in_from_pins[1:0],data_in_to_device[1:0],clk_in,clk_out,io_reset" */;
|
||||
input [1:0]data_in_from_pins;
|
||||
output [1:0]data_in_to_device;
|
||||
input clk_in;
|
||||
output clk_out;
|
||||
input io_reset;
|
||||
endmodule
|
||||
+32
@@ -0,0 +1,32 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sun Mar 19 18:02:10 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_stub.vhdl
|
||||
-- Design : selectio_lvds_rx
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
clk_in : in STD_LOGIC;
|
||||
clk_out : out STD_LOGIC;
|
||||
io_reset : in STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "data_in_from_pins[1:0],data_in_to_device[1:0],clk_in,clk_out,io_reset";
|
||||
begin
|
||||
end;
|
||||
+88
@@ -0,0 +1,88 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>fffcbdb43410d449</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>selectio_lvds_rx</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="selectio_wiz" spirit:version="5.1"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACTIVE_EDGE">RISING</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_DIR">INPUTS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_IN_DELAY">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_IN_TAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_IO_STD">LVCMOS33</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_OUT_DELAY">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_OUT_TAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_SIG_TYPE">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_TAP_RESET">NOT_APP</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUS_TAP_WRAP">NOT_APP</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_BUF">BUFIO2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_DELAY">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_EN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_FWD">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_FWD_IO_STD">LVCMOS33</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_FWD_SER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_FWD_SIG_TYPE">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IO_STD">LVCMOS18</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_SIG_TYPE">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_TAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONFIG_CLK_FWD">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">selectio_lvds_rx</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DDR_ALIGNMENT">C0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DDR_CLK_BUF">BUFR</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_BITSLIP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TRAIN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IDDR_RST_TYPE">ASYNC</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IDELAY_HIGH_PERF_MODE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_IDELAYCTRL">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_IDELAYCTRL_BUFG">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">NETWORKING</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NOTES">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_ACTIVE_EDGE">SDR</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_BUS_IN_DELAY">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_BUS_IN_TAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_BUS_OUT_DELAY">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_BUS_OUT_TAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_CLK_BUF">MMCM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_CLK_IO_STD">LVCMOS33</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_CLK_SIG_TYPE">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_DDR_ALIGNMENT">SAME_EDGE_PIPELINED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_IDDR_RST_TYPE">ASYNC</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_INTERFACE_TYPE">NETWORKING</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SELIO_ODDR_ALIGNMENT">SAME_EDGE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SERIALIZATION_FACTOR">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYSTEM_DATA_WIDTH">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRAIN_CONSTANT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_DETECTOR">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SERIALIZATION">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_TEMPLATE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">fffcbdb43410d449</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESPECIALDATA">selectio_lvds_rx</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">af96b0bc</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">19</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">13</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
BIN
Binary file not shown.
+168
@@ -0,0 +1,168 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sun Mar 19 18:25:55 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_sim_netlist.v
|
||||
// Design : selectio_lvds_rx
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* DEV_W = "2" *) (* SYS_W = "2" *)
|
||||
(* NotValidForBitStream *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
|
||||
(data_in_from_pins,
|
||||
data_in_to_device,
|
||||
clk_in,
|
||||
io_reset);
|
||||
input [1:0]data_in_from_pins;
|
||||
output [1:0]data_in_to_device;
|
||||
input clk_in;
|
||||
input io_reset;
|
||||
|
||||
wire clk_in;
|
||||
(* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire [1:0]data_in_from_pins;
|
||||
wire [1:0]data_in_to_device;
|
||||
wire io_reset;
|
||||
|
||||
(* DEV_W = "2" *)
|
||||
(* SYS_W = "2" *)
|
||||
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz inst
|
||||
(.clk_in(clk_in),
|
||||
.data_in_from_pins(data_in_from_pins),
|
||||
.data_in_to_device(data_in_to_device),
|
||||
.io_reset(io_reset));
|
||||
endmodule
|
||||
|
||||
(* DEV_W = "2" *) (* SYS_W = "2" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz
|
||||
(data_in_from_pins,
|
||||
data_in_to_device,
|
||||
clk_in,
|
||||
io_reset);
|
||||
input [1:0]data_in_from_pins;
|
||||
output [1:0]data_in_to_device;
|
||||
input clk_in;
|
||||
input io_reset;
|
||||
|
||||
wire clk_in;
|
||||
wire [1:0]data_in_from_pins;
|
||||
wire [1:0]data_in_from_pins_int;
|
||||
wire [1:0]data_in_to_device;
|
||||
wire io_reset;
|
||||
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* IOB = "TRUE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\pins[0].fdre_in_inst
|
||||
(.C(clk_in),
|
||||
.CE(1'b1),
|
||||
.D(data_in_from_pins_int[0]),
|
||||
.Q(data_in_to_device[0]),
|
||||
.R(io_reset));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
(* IBUF_DELAY_VALUE = "0" *)
|
||||
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||
IBUF \pins[0].ibuf_inst
|
||||
(.I(data_in_from_pins[0]),
|
||||
.O(data_in_from_pins_int[0]));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* IOB = "TRUE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\pins[1].fdre_in_inst
|
||||
(.C(clk_in),
|
||||
.CE(1'b1),
|
||||
.D(data_in_from_pins_int[1]),
|
||||
.Q(data_in_to_device[1]),
|
||||
.R(io_reset));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
(* IBUF_DELAY_VALUE = "0" *)
|
||||
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||
IBUF \pins[1].ibuf_inst
|
||||
(.I(data_in_from_pins[1]),
|
||||
.O(data_in_from_pins_int[1]));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+119
@@ -0,0 +1,119 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sun Mar 19 18:25:55 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_sim_netlist.vhdl
|
||||
-- Design : selectio_lvds_rx
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz is
|
||||
port (
|
||||
data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
clk_in : in STD_LOGIC;
|
||||
io_reset : in STD_LOGIC
|
||||
);
|
||||
attribute DEV_W : integer;
|
||||
attribute DEV_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz : entity is 2;
|
||||
attribute SYS_W : integer;
|
||||
attribute SYS_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz : entity is 2;
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz is
|
||||
signal data_in_from_pins_int : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
attribute BOX_TYPE : string;
|
||||
attribute BOX_TYPE of \pins[0].fdre_in_inst\ : label is "PRIMITIVE";
|
||||
attribute IOB : string;
|
||||
attribute IOB of \pins[0].fdre_in_inst\ : label is "TRUE";
|
||||
attribute BOX_TYPE of \pins[0].ibuf_inst\ : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE : string;
|
||||
attribute CAPACITANCE of \pins[0].ibuf_inst\ : label is "DONT_CARE";
|
||||
attribute IBUF_DELAY_VALUE : string;
|
||||
attribute IBUF_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "0";
|
||||
attribute IFD_DELAY_VALUE : string;
|
||||
attribute IFD_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "AUTO";
|
||||
attribute BOX_TYPE of \pins[1].fdre_in_inst\ : label is "PRIMITIVE";
|
||||
attribute IOB of \pins[1].fdre_in_inst\ : label is "TRUE";
|
||||
attribute BOX_TYPE of \pins[1].ibuf_inst\ : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE of \pins[1].ibuf_inst\ : label is "DONT_CARE";
|
||||
attribute IBUF_DELAY_VALUE of \pins[1].ibuf_inst\ : label is "0";
|
||||
attribute IFD_DELAY_VALUE of \pins[1].ibuf_inst\ : label is "AUTO";
|
||||
begin
|
||||
\pins[0].fdre_in_inst\: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '0',
|
||||
IS_C_INVERTED => '0',
|
||||
IS_D_INVERTED => '0',
|
||||
IS_R_INVERTED => '0'
|
||||
)
|
||||
port map (
|
||||
C => clk_in,
|
||||
CE => '1',
|
||||
D => data_in_from_pins_int(0),
|
||||
Q => data_in_to_device(0),
|
||||
R => io_reset
|
||||
);
|
||||
\pins[0].ibuf_inst\: unisim.vcomponents.IBUF
|
||||
port map (
|
||||
I => data_in_from_pins(0),
|
||||
O => data_in_from_pins_int(0)
|
||||
);
|
||||
\pins[1].fdre_in_inst\: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '0',
|
||||
IS_C_INVERTED => '0',
|
||||
IS_D_INVERTED => '0',
|
||||
IS_R_INVERTED => '0'
|
||||
)
|
||||
port map (
|
||||
C => clk_in,
|
||||
CE => '1',
|
||||
D => data_in_from_pins_int(1),
|
||||
Q => data_in_to_device(1),
|
||||
R => io_reset
|
||||
);
|
||||
\pins[1].ibuf_inst\: unisim.vcomponents.IBUF
|
||||
port map (
|
||||
I => data_in_from_pins(1),
|
||||
O => data_in_from_pins_int(1)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
port (
|
||||
data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
clk_in : in STD_LOGIC;
|
||||
io_reset : in STD_LOGIC
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
|
||||
attribute DEV_W : integer;
|
||||
attribute DEV_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is 2;
|
||||
attribute SYS_W : integer;
|
||||
attribute SYS_W of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is 2;
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute DEV_W of inst : label is 2;
|
||||
attribute SYS_W of inst : label is 2;
|
||||
begin
|
||||
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_selectio_lvds_rx_selectio_wiz
|
||||
port map (
|
||||
clk_in => clk_in,
|
||||
data_in_from_pins(1 downto 0) => data_in_from_pins(1 downto 0),
|
||||
data_in_to_device(1 downto 0) => data_in_to_device(1 downto 0),
|
||||
io_reset => io_reset
|
||||
);
|
||||
end STRUCTURE;
|
||||
+23
@@ -0,0 +1,23 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sun Mar 19 18:25:55 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_stub.v
|
||||
// Design : selectio_lvds_rx
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(data_in_from_pins, data_in_to_device, clk_in,
|
||||
io_reset)
|
||||
/* synthesis syn_black_box black_box_pad_pin="data_in_from_pins[1:0],data_in_to_device[1:0],clk_in,io_reset" */;
|
||||
input [1:0]data_in_from_pins;
|
||||
output [1:0]data_in_to_device;
|
||||
input clk_in;
|
||||
input io_reset;
|
||||
endmodule
|
||||
+31
@@ -0,0 +1,31 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sun Mar 19 18:25:55 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_stub.vhdl
|
||||
-- Design : selectio_lvds_rx
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
clk_in : in STD_LOGIC;
|
||||
io_reset : in STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "data_in_from_pins[1:0],data_in_to_device[1:0],clk_in,io_reset";
|
||||
begin
|
||||
end;
|
||||
+29
-11
@@ -1,19 +1,37 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6d6d616e6473696e7075745f747970655f74636c5f636f6d6d616e645f68657265:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3332:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6d616e6167655f6970:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6f70656e5f70726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3639:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6d616e6167655f6970:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6f70656e5f70726f6a656374:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f73746172745f7573696e675f76697661646f5f776974685f69705f636174616c6f67:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6861636763636f6566696c657769646765745f62726f777365:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68706f7075707469746c655f636c6f7365:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f65646974:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f7265706f727473:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746f6f6c73:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f77696e646f77:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e77696e6d656e756d67725f6c61796f7574:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f696e666f726d6174696f6e5f6d65737361676573:31:00:00
|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
eof:256007650
|
||||
eof:3417462915
|
||||
|
||||
+9
-5
@@ -1,7 +1,11 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6164646578697374696e67697068616e646c6572:31:00:00
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
eof:1295650939
|
||||
|
||||
+1
-1
@@ -1,3 +1,3 @@
|
||||
version:1
|
||||
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|
||||
6d6f64655f636f756e7465727c4755494d6f6465:6
|
||||
eof:
|
||||
|
||||
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-7
@@ -1,7 +1,7 @@
|
||||
version:1
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
@@ -33,9 +33,7 @@ version:1
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
33
|
||||
0935
|
||||
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|
||||
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|
||||
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|
||||
eof:1985685470
|
||||
|
||||
+39
-17
@@ -3,7 +3,7 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Sat Mar 18 23:40:32 2023">
|
||||
<application name="pa" timeStamp="Sun Mar 19 18:26:21 2023">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="dd2c041edc1245f6938f6800e430db6c" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||
@@ -17,35 +17,57 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddExistingIPHandler" value="1" type="JavaHandler"/>
|
||||
<property name="ManageCompositeTargets" value="3" type="JavaHandler"/>
|
||||
<property name="AddExistingIPHandler" value="2" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="1" type="JavaHandler"/>
|
||||
<property name="ManageCompositeTargets" value="5" type="JavaHandler"/>
|
||||
<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
|
||||
<property name="OpenProject" value="1" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="5" type="JavaHandler"/>
|
||||
<property name="OpenIPLocationHandler" value="1" type="JavaHandler"/>
|
||||
<property name="OpenPreviousIPHandler" value="4" type="JavaHandler"/>
|
||||
<property name="OpenProject" value="2" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="12" type="JavaHandler"/>
|
||||
<property name="ShowView" value="3" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="BaseDialog_CANCEL" value="1" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="5" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_CANCEL" value="6" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="9" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_OK" value="1" type="GuiHandlerData"/>
|
||||
<property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="1" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="1" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="32" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_MANAGE_IP" value="1" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="3" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="69" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_MANAGE_IP" value="2" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_OPEN_PROJECT" value="2" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="1" type="GuiHandlerData"/>
|
||||
<property name="HACGCCoeFileWidget_BROWSE" value="3" type="GuiHandlerData"/>
|
||||
<property name="HPopupTitle_CLOSE" value="1" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_EDIT" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FILE" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_REPORTS" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_TOOLS" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_WINDOW" value="8" type="GuiHandlerData"/>
|
||||
<property name="MainWinMenuMgr_LAYOUT" value="2" type="GuiHandlerData"/>
|
||||
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="11" type="GuiHandlerData"/>
|
||||
<property name="MsgView_INFORMATION_MESSAGES" value="1" type="GuiHandlerData"/>
|
||||
<property name="MsgView_WARNING_MESSAGES" value="1" type="GuiHandlerData"/>
|
||||
<property name="NewIPProjectWizard_IP_LOCATION" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_EXISTING_IP" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_EXISTING_IP" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_FILESET_WINDOW" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_IP_LOCATION" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_PROPERTIES_WINDOW" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RESET_COMPOSITE_FILE" value="2" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_BACKGROUND" value="2" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_CLOSE_DIALOG_UNSAVED_CHANGES_WILL" value="5" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="1" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="1" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="3" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="4" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="2" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="4" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="4" type="GuiHandlerData"/>
|
||||
<property name="XPG_CoeFileWidgdet_BROWSE" value="2" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="53" type="GuiMode"/>
|
||||
<property name="GuiMode" value="65" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="36" type="TclMode"/>
|
||||
<property name="TclMode" value="44" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="selectio_lvds_rx_synth_1" LaunchDir="D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Run Id="selectio_lvds_tx_synth_1" LaunchDir="D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+8
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="selectio_lvds_rx_synth_1" LaunchDir="D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+8
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="selectio_lvds_rx_synth_1" LaunchDir="D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+1
-6
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="COSLUT_10_16bit_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
|
||||
<File Type="PA-TCL" Name="COSLUT_10_16bit.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="COSLUT_10_16bit_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="COSLUT_10_16bit_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="COSLUT_10_16bit.vds"/>
|
||||
<File Type="RDS-UTIL" Name="COSLUT_10_16bit_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="COSLUT_10_16bit_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="COSLUT_10_16bit.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="COSLUT_10_16bit_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="COSLUT_10_16bit_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/COSLUT_10_16bit">
|
||||
<File Path="$PPRDIR/../transmitter/COSLUT_10_16bit/COSLUT_10_16bit.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+1
-6
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="GaussFir_12m_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153568">
|
||||
<File Type="PA-TCL" Name="GaussFir_12m.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="GaussFir_12m_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="GaussFir_12m_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="GaussFir_12m.vds"/>
|
||||
<File Type="RDS-UTIL" Name="GaussFir_12m_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="GaussFir_12m_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="GaussFir_12m.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="GaussFir_12m_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="GaussFir_12m_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/GaussFir_12m">
|
||||
<File Path="$PPRDIR/../transmitter/GaussFir_12m/GaussFir_12m.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+1
-6
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="GaussFir_1mp5_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153568">
|
||||
<File Type="PA-TCL" Name="GaussFir_1mp5.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="GaussFir_1mp5_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="GaussFir_1mp5_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="GaussFir_1mp5.vds"/>
|
||||
<File Type="RDS-UTIL" Name="GaussFir_1mp5_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="GaussFir_1mp5_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="GaussFir_1mp5.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="GaussFir_1mp5_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="GaussFir_1mp5_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/GaussFir_1mp5">
|
||||
<File Path="$PPRDIR/../transmitter/GaussFir_1mp5/GaussFir_1mp5.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+1
-6
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ad9361_clk_gen_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153566">
|
||||
<File Type="PA-TCL" Name="ad9361_clk_gen.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ad9361_clk_gen_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="ad9361_clk_gen_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ad9361_clk_gen.vds"/>
|
||||
<File Type="RDS-UTIL" Name="ad9361_clk_gen_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ad9361_clk_gen_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="ad9361_clk_gen.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ad9361_clk_gen_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="ad9361_clk_gen_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ad9361_clk_gen">
|
||||
<File Path="$PPRDIR/../ad9361_clk_gen/ad9361_clk_gen.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+1
-6
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="add_s24_s32_s32_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
|
||||
<File Type="PA-TCL" Name="add_s24_s32_s32.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="add_s24_s32_s32_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="add_s24_s32_s32_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="add_s24_s32_s32.vds"/>
|
||||
<File Type="RDS-UTIL" Name="add_s24_s32_s32_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="add_s24_s32_s32_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="add_s24_s32_s32.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="add_s24_s32_s32_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="add_s24_s32_s32_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/add_s24_s32_s32">
|
||||
<File Path="$PPRDIR/../rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+1
-6
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ant_clk_gen_stg1_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
|
||||
<File Type="PA-TCL" Name="ant_clk_gen_stg1.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ant_clk_gen_stg1_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="ant_clk_gen_stg1_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ant_clk_gen_stg1.vds"/>
|
||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg1_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ant_clk_gen_stg1_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="ant_clk_gen_stg1.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ant_clk_gen_stg1_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="ant_clk_gen_stg1_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ant_clk_gen_stg1">
|
||||
<File Path="$PPRDIR/../ant_clk_gen_stg1/ant_clk_gen_stg1.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+1
-6
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ant_clk_gen_stg2_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
|
||||
<File Type="PA-TCL" Name="ant_clk_gen_stg2.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ant_clk_gen_stg2_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="ant_clk_gen_stg2_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ant_clk_gen_stg2.vds"/>
|
||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg2_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ant_clk_gen_stg2_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="ant_clk_gen_stg2.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ant_clk_gen_stg2_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="ant_clk_gen_stg2_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ant_clk_gen_stg2">
|
||||
<File Path="$PPRDIR/../ant_clk_gen_stg2/ant_clk_gen_stg2.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+1
-6
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="atan2_16b_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
|
||||
<File Type="PA-TCL" Name="atan2_16b.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="atan2_16b_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="atan2_16b_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="atan2_16b.vds"/>
|
||||
<File Type="RDS-UTIL" Name="atan2_16b_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="atan2_16b_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="atan2_16b.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="atan2_16b_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="atan2_16b_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/atan2_16b">
|
||||
<File Path="$PPRDIR/../rx_pre_process/atan2_16b/atan2_16b.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+1
-6
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="cmpy_12x12_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
|
||||
<File Type="PA-TCL" Name="cmpy_12x12.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="cmpy_12x12_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="cmpy_12x12_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="cmpy_12x12.vds"/>
|
||||
<File Type="RDS-UTIL" Name="cmpy_12x12_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="cmpy_12x12_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="cmpy_12x12.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="cmpy_12x12_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="cmpy_12x12_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cmpy_12x12">
|
||||
<File Path="$PPRDIR/../rx_pre_process/cmpy_12x12/cmpy_12x12.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+1
-6
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="cmpy_16x12_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
|
||||
<File Type="PA-TCL" Name="cmpy_16x12.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="cmpy_16x12_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="cmpy_16x12_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="cmpy_16x12.vds"/>
|
||||
<File Type="RDS-UTIL" Name="cmpy_16x12_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="cmpy_16x12_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="cmpy_16x12.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="cmpy_16x12_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="cmpy_16x12_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cmpy_16x12">
|
||||
<File Path="$PPRDIR/../rx_pre_process/cmpy_16x12/cmpy_16x12.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+1
-6
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="data_1p5m_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
|
||||
<File Type="PA-TCL" Name="data_1p5m.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="data_1p5m_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="data_1p5m_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="data_1p5m.vds"/>
|
||||
<File Type="RDS-UTIL" Name="data_1p5m_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="data_1p5m_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="data_1p5m.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="data_1p5m_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="data_1p5m_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/data_1p5m">
|
||||
<File Path="$PPRDIR/../transmitter/data_1p5m/data_1p5m.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
-32
@@ -1,32 +0,0 @@
|
||||
# This file is automatically generated.
|
||||
# It contains project source information necessary for synthesis and implementation.
|
||||
|
||||
# IP: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xci
|
||||
# IP: The module: 'fifo_AntCtrl' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'fifo_AntCtrl'. Do not add the DONT_TOUCH constraint.
|
||||
set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
|
||||
# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl_clocks.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'fifo_AntCtrl'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
|
||||
# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'fifo_AntCtrl'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
|
||||
# IP: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xci
|
||||
# IP: The module: 'fifo_AntCtrl' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'fifo_AntCtrl'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
|
||||
# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl_clocks.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'fifo_AntCtrl'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
|
||||
# XDC: d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'fifo_AntCtrl'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
BIN
Binary file not shown.
-158
@@ -1,158 +0,0 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param general.maxThreads 20
|
||||
set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
create_project -in_memory -part xc7k410tffg900-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.cache/wt [current_project]
|
||||
set_property parent.project_path D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.xpr [current_project]
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo d:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_ip -quiet D:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xci
|
||||
set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl_clocks.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl_ooc.xdc]
|
||||
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc dont_touch.xdc
|
||||
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
|
||||
set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1 -new_name fifo_AntCtrl -ip [get_ips fifo_AntCtrl]]
|
||||
|
||||
if { $cached_ip eq {} } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top fifo_AntCtrl -part xc7k410tffg900-2 -mode out_of_context
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix fifo_AntCtrl_ fifo_AntCtrl.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_AntCtrl_stub.v
|
||||
lappend ipCachedFiles fifo_AntCtrl_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_AntCtrl_stub.vhdl
|
||||
lappend ipCachedFiles fifo_AntCtrl_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_AntCtrl_sim_netlist.v
|
||||
lappend ipCachedFiles fifo_AntCtrl_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_AntCtrl_sim_netlist.vhdl
|
||||
lappend ipCachedFiles fifo_AntCtrl_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
config_ip_cache -add -dcp fifo_AntCtrl.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips fifo_AntCtrl]
|
||||
}
|
||||
|
||||
rename_ref -prefix_all fifo_AntCtrl_
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef fifo_AntCtrl.dcp
|
||||
create_report "fifo_AntCtrl_synth_1_synth_report_utilization_0" "report_utilization -file fifo_AntCtrl_utilization_synth.rpt -pb fifo_AntCtrl_utilization_synth.pb"
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
}; # end if cached_ip
|
||||
|
||||
add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xci]
|
||||
|
||||
add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xci]
|
||||
|
||||
add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_sim_netlist.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xci]
|
||||
|
||||
add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xci]
|
||||
|
||||
add_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl.dcp -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xci]
|
||||
|
||||
if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/fifo_AntCtrl]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_sim_netlist.v D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/fifo_AntCtrl
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/fifo_AntCtrl]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_sim_netlist.vhdl D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/fifo_AntCtrl
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/fifo_AntCtrl]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.v D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/fifo_AntCtrl
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/fifo_AntCtrl]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.vhdl D:/vivado-git/projects/datalink_814/dl814_cmos/ip/ip_user_files/ip/fifo_AntCtrl
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
-742
@@ -1,742 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Sat Mar 18 23:32:54 2023
|
||||
# Process ID: 26592
|
||||
# Current directory: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1
|
||||
# Command line: vivado.exe -log fifo_AntCtrl.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source fifo_AntCtrl.tcl
|
||||
# Log file: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl.vds
|
||||
# Journal file: D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
Sourcing tcl script 'C:/Users/Josh/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl'
|
||||
source fifo_AntCtrl.tcl -notrace
|
||||
Command: synth_design -top fifo_AntCtrl -part xc7k410tffg900-2 -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Device 21-403] Loading part xc7k410tffg900-2
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 33764
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 886.301 ; gain = 177.375
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'fifo_AntCtrl' [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/synth/fifo_AntCtrl.vhd:73]
|
||||
Parameter C_COMMON_CLOCK bound to: 0 - type: integer
|
||||
Parameter C_SELECT_XPM bound to: 0 - type: integer
|
||||
Parameter C_COUNT_TYPE bound to: 0 - type: integer
|
||||
Parameter C_DATA_COUNT_WIDTH bound to: 10 - type: integer
|
||||
Parameter C_DEFAULT_VALUE bound to: BlankString - type: string
|
||||
Parameter C_DIN_WIDTH bound to: 4 - type: integer
|
||||
Parameter C_DOUT_RST_VAL bound to: 0 - type: string
|
||||
Parameter C_DOUT_WIDTH bound to: 4 - type: integer
|
||||
Parameter C_ENABLE_RLOCS bound to: 0 - type: integer
|
||||
Parameter C_FAMILY bound to: kintex7 - type: string
|
||||
Parameter C_FULL_FLAGS_RST_VAL bound to: 1 - type: integer
|
||||
Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer
|
||||
Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer
|
||||
Parameter C_HAS_BACKUP bound to: 0 - type: integer
|
||||
Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer
|
||||
Parameter C_HAS_INT_CLK bound to: 0 - type: integer
|
||||
Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer
|
||||
Parameter C_HAS_OVERFLOW bound to: 0 - type: integer
|
||||
Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer
|
||||
Parameter C_HAS_RD_RST bound to: 0 - type: integer
|
||||
Parameter C_HAS_RST bound to: 1 - type: integer
|
||||
Parameter C_HAS_SRST bound to: 0 - type: integer
|
||||
Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer
|
||||
Parameter C_HAS_VALID bound to: 0 - type: integer
|
||||
Parameter C_HAS_WR_ACK bound to: 0 - type: integer
|
||||
Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer
|
||||
Parameter C_HAS_WR_RST bound to: 0 - type: integer
|
||||
Parameter C_IMPLEMENTATION_TYPE bound to: 2 - type: integer
|
||||
Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer
|
||||
Parameter C_MEMORY_TYPE bound to: 2 - type: integer
|
||||
Parameter C_MIF_FILE_NAME bound to: BlankString - type: string
|
||||
Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer
|
||||
Parameter C_OVERFLOW_LOW bound to: 0 - type: integer
|
||||
Parameter C_PRELOAD_LATENCY bound to: 1 - type: integer
|
||||
Parameter C_PRELOAD_REGS bound to: 0 - type: integer
|
||||
Parameter C_PRIM_FIFO_TYPE bound to: 1kx18 - type: string
|
||||
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 2 - type: integer
|
||||
Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 3 - type: integer
|
||||
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
|
||||
Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 1021 - type: integer
|
||||
Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 1020 - type: integer
|
||||
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
|
||||
Parameter C_RD_DATA_COUNT_WIDTH bound to: 10 - type: integer
|
||||
Parameter C_RD_DEPTH bound to: 1024 - type: integer
|
||||
Parameter C_RD_FREQ bound to: 1 - type: integer
|
||||
Parameter C_RD_PNTR_WIDTH bound to: 10 - type: integer
|
||||
Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer
|
||||
Parameter C_USE_DOUT_RST bound to: 1 - type: integer
|
||||
Parameter C_USE_ECC bound to: 0 - type: integer
|
||||
Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
|
||||
Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer
|
||||
Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer
|
||||
Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer
|
||||
Parameter C_USE_FWFT_DATA_COUNT bound to: 0 - type: integer
|
||||
Parameter C_VALID_LOW bound to: 0 - type: integer
|
||||
Parameter C_WR_ACK_LOW bound to: 0 - type: integer
|
||||
Parameter C_WR_DATA_COUNT_WIDTH bound to: 10 - type: integer
|
||||
Parameter C_WR_DEPTH bound to: 1024 - type: integer
|
||||
Parameter C_WR_FREQ bound to: 1 - type: integer
|
||||
Parameter C_WR_PNTR_WIDTH bound to: 10 - type: integer
|
||||
Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer
|
||||
Parameter C_MSGON_VAL bound to: 1 - type: integer
|
||||
Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer
|
||||
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
|
||||
Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer
|
||||
Parameter C_SYNCHRONIZER_STAGE bound to: 2 - type: integer
|
||||
Parameter C_INTERFACE_TYPE bound to: 0 - type: integer
|
||||
Parameter C_AXI_TYPE bound to: 1 - type: integer
|
||||
Parameter C_HAS_AXI_WR_CHANNEL bound to: 1 - type: integer
|
||||
Parameter C_HAS_AXI_RD_CHANNEL bound to: 1 - type: integer
|
||||
Parameter C_HAS_SLAVE_CE bound to: 0 - type: integer
|
||||
Parameter C_HAS_MASTER_CE bound to: 0 - type: integer
|
||||
Parameter C_ADD_NGC_CONSTRAINT bound to: 0 - type: integer
|
||||
Parameter C_USE_COMMON_OVERFLOW bound to: 0 - type: integer
|
||||
Parameter C_USE_COMMON_UNDERFLOW bound to: 0 - type: integer
|
||||
Parameter C_USE_DEFAULT_SETTINGS bound to: 0 - type: integer
|
||||
Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
|
||||
Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer
|
||||
Parameter C_AXI_LEN_WIDTH bound to: 8 - type: integer
|
||||
Parameter C_AXI_LOCK_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_HAS_AXI_ID bound to: 0 - type: integer
|
||||
Parameter C_HAS_AXI_AWUSER bound to: 0 - type: integer
|
||||
Parameter C_HAS_AXI_WUSER bound to: 0 - type: integer
|
||||
Parameter C_HAS_AXI_BUSER bound to: 0 - type: integer
|
||||
Parameter C_HAS_AXI_ARUSER bound to: 0 - type: integer
|
||||
Parameter C_HAS_AXI_RUSER bound to: 0 - type: integer
|
||||
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_HAS_AXIS_TDATA bound to: 1 - type: integer
|
||||
Parameter C_HAS_AXIS_TID bound to: 0 - type: integer
|
||||
Parameter C_HAS_AXIS_TDEST bound to: 0 - type: integer
|
||||
Parameter C_HAS_AXIS_TUSER bound to: 1 - type: integer
|
||||
Parameter C_HAS_AXIS_TREADY bound to: 1 - type: integer
|
||||
Parameter C_HAS_AXIS_TLAST bound to: 0 - type: integer
|
||||
Parameter C_HAS_AXIS_TSTRB bound to: 0 - type: integer
|
||||
Parameter C_HAS_AXIS_TKEEP bound to: 0 - type: integer
|
||||
Parameter C_AXIS_TDATA_WIDTH bound to: 8 - type: integer
|
||||
Parameter C_AXIS_TID_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_AXIS_TDEST_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_AXIS_TUSER_WIDTH bound to: 4 - type: integer
|
||||
Parameter C_AXIS_TSTRB_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_AXIS_TKEEP_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_WACH_TYPE bound to: 0 - type: integer
|
||||
Parameter C_WDCH_TYPE bound to: 0 - type: integer
|
||||
Parameter C_WRCH_TYPE bound to: 0 - type: integer
|
||||
Parameter C_RACH_TYPE bound to: 0 - type: integer
|
||||
Parameter C_RDCH_TYPE bound to: 0 - type: integer
|
||||
Parameter C_AXIS_TYPE bound to: 0 - type: integer
|
||||
Parameter C_IMPLEMENTATION_TYPE_WACH bound to: 1 - type: integer
|
||||
Parameter C_IMPLEMENTATION_TYPE_WDCH bound to: 1 - type: integer
|
||||
Parameter C_IMPLEMENTATION_TYPE_WRCH bound to: 1 - type: integer
|
||||
Parameter C_IMPLEMENTATION_TYPE_RACH bound to: 1 - type: integer
|
||||
Parameter C_IMPLEMENTATION_TYPE_RDCH bound to: 1 - type: integer
|
||||
Parameter C_IMPLEMENTATION_TYPE_AXIS bound to: 1 - type: integer
|
||||
Parameter C_APPLICATION_TYPE_WACH bound to: 0 - type: integer
|
||||
Parameter C_APPLICATION_TYPE_WDCH bound to: 0 - type: integer
|
||||
Parameter C_APPLICATION_TYPE_WRCH bound to: 0 - type: integer
|
||||
Parameter C_APPLICATION_TYPE_RACH bound to: 0 - type: integer
|
||||
Parameter C_APPLICATION_TYPE_RDCH bound to: 0 - type: integer
|
||||
Parameter C_APPLICATION_TYPE_AXIS bound to: 0 - type: integer
|
||||
Parameter C_PRIM_FIFO_TYPE_WACH bound to: 512x36 - type: string
|
||||
Parameter C_PRIM_FIFO_TYPE_WDCH bound to: 1kx36 - type: string
|
||||
Parameter C_PRIM_FIFO_TYPE_WRCH bound to: 512x36 - type: string
|
||||
Parameter C_PRIM_FIFO_TYPE_RACH bound to: 512x36 - type: string
|
||||
Parameter C_PRIM_FIFO_TYPE_RDCH bound to: 1kx36 - type: string
|
||||
Parameter C_PRIM_FIFO_TYPE_AXIS bound to: 1kx18 - type: string
|
||||
Parameter C_USE_ECC_WACH bound to: 0 - type: integer
|
||||
Parameter C_USE_ECC_WDCH bound to: 0 - type: integer
|
||||
Parameter C_USE_ECC_WRCH bound to: 0 - type: integer
|
||||
Parameter C_USE_ECC_RACH bound to: 0 - type: integer
|
||||
Parameter C_USE_ECC_RDCH bound to: 0 - type: integer
|
||||
Parameter C_USE_ECC_AXIS bound to: 0 - type: integer
|
||||
Parameter C_ERROR_INJECTION_TYPE_WACH bound to: 0 - type: integer
|
||||
Parameter C_ERROR_INJECTION_TYPE_WDCH bound to: 0 - type: integer
|
||||
Parameter C_ERROR_INJECTION_TYPE_WRCH bound to: 0 - type: integer
|
||||
Parameter C_ERROR_INJECTION_TYPE_RACH bound to: 0 - type: integer
|
||||
Parameter C_ERROR_INJECTION_TYPE_RDCH bound to: 0 - type: integer
|
||||
Parameter C_ERROR_INJECTION_TYPE_AXIS bound to: 0 - type: integer
|
||||
Parameter C_DIN_WIDTH_WACH bound to: 1 - type: integer
|
||||
Parameter C_DIN_WIDTH_WDCH bound to: 64 - type: integer
|
||||
Parameter C_DIN_WIDTH_WRCH bound to: 2 - type: integer
|
||||
Parameter C_DIN_WIDTH_RACH bound to: 32 - type: integer
|
||||
Parameter C_DIN_WIDTH_RDCH bound to: 64 - type: integer
|
||||
Parameter C_DIN_WIDTH_AXIS bound to: 1 - type: integer
|
||||
Parameter C_WR_DEPTH_WACH bound to: 16 - type: integer
|
||||
Parameter C_WR_DEPTH_WDCH bound to: 1024 - type: integer
|
||||
Parameter C_WR_DEPTH_WRCH bound to: 16 - type: integer
|
||||
Parameter C_WR_DEPTH_RACH bound to: 16 - type: integer
|
||||
Parameter C_WR_DEPTH_RDCH bound to: 1024 - type: integer
|
||||
Parameter C_WR_DEPTH_AXIS bound to: 1024 - type: integer
|
||||
Parameter C_WR_PNTR_WIDTH_WACH bound to: 4 - type: integer
|
||||
Parameter C_WR_PNTR_WIDTH_WDCH bound to: 10 - type: integer
|
||||
Parameter C_WR_PNTR_WIDTH_WRCH bound to: 4 - type: integer
|
||||
Parameter C_WR_PNTR_WIDTH_RACH bound to: 4 - type: integer
|
||||
Parameter C_WR_PNTR_WIDTH_RDCH bound to: 10 - type: integer
|
||||
Parameter C_WR_PNTR_WIDTH_AXIS bound to: 10 - type: integer
|
||||
Parameter C_HAS_DATA_COUNTS_WACH bound to: 0 - type: integer
|
||||
Parameter C_HAS_DATA_COUNTS_WDCH bound to: 0 - type: integer
|
||||
Parameter C_HAS_DATA_COUNTS_WRCH bound to: 0 - type: integer
|
||||
Parameter C_HAS_DATA_COUNTS_RACH bound to: 0 - type: integer
|
||||
Parameter C_HAS_DATA_COUNTS_RDCH bound to: 0 - type: integer
|
||||
Parameter C_HAS_DATA_COUNTS_AXIS bound to: 0 - type: integer
|
||||
Parameter C_HAS_PROG_FLAGS_WACH bound to: 0 - type: integer
|
||||
Parameter C_HAS_PROG_FLAGS_WDCH bound to: 0 - type: integer
|
||||
Parameter C_HAS_PROG_FLAGS_WRCH bound to: 0 - type: integer
|
||||
Parameter C_HAS_PROG_FLAGS_RACH bound to: 0 - type: integer
|
||||
Parameter C_HAS_PROG_FLAGS_RDCH bound to: 0 - type: integer
|
||||
Parameter C_HAS_PROG_FLAGS_AXIS bound to: 0 - type: integer
|
||||
Parameter C_PROG_FULL_TYPE_WACH bound to: 0 - type: integer
|
||||
Parameter C_PROG_FULL_TYPE_WDCH bound to: 0 - type: integer
|
||||
Parameter C_PROG_FULL_TYPE_WRCH bound to: 0 - type: integer
|
||||
Parameter C_PROG_FULL_TYPE_RACH bound to: 0 - type: integer
|
||||
Parameter C_PROG_FULL_TYPE_RDCH bound to: 0 - type: integer
|
||||
Parameter C_PROG_FULL_TYPE_AXIS bound to: 0 - type: integer
|
||||
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH bound to: 1023 - type: integer
|
||||
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH bound to: 1023 - type: integer
|
||||
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH bound to: 1023 - type: integer
|
||||
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH bound to: 1023 - type: integer
|
||||
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH bound to: 1023 - type: integer
|
||||
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS bound to: 1023 - type: integer
|
||||
Parameter C_PROG_EMPTY_TYPE_WACH bound to: 0 - type: integer
|
||||
Parameter C_PROG_EMPTY_TYPE_WDCH bound to: 0 - type: integer
|
||||
Parameter C_PROG_EMPTY_TYPE_WRCH bound to: 0 - type: integer
|
||||
Parameter C_PROG_EMPTY_TYPE_RACH bound to: 0 - type: integer
|
||||
Parameter C_PROG_EMPTY_TYPE_RDCH bound to: 0 - type: integer
|
||||
Parameter C_PROG_EMPTY_TYPE_AXIS bound to: 0 - type: integer
|
||||
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH bound to: 1022 - type: integer
|
||||
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH bound to: 1022 - type: integer
|
||||
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH bound to: 1022 - type: integer
|
||||
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH bound to: 1022 - type: integer
|
||||
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH bound to: 1022 - type: integer
|
||||
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS bound to: 1022 - type: integer
|
||||
Parameter C_REG_SLICE_MODE_WACH bound to: 0 - type: integer
|
||||
Parameter C_REG_SLICE_MODE_WDCH bound to: 0 - type: integer
|
||||
Parameter C_REG_SLICE_MODE_WRCH bound to: 0 - type: integer
|
||||
Parameter C_REG_SLICE_MODE_RACH bound to: 0 - type: integer
|
||||
Parameter C_REG_SLICE_MODE_RDCH bound to: 0 - type: integer
|
||||
Parameter C_REG_SLICE_MODE_AXIS bound to: 0 - type: integer
|
||||
INFO: [Synth 8-3491] module 'fifo_generator_v13_2_4' declared at 'd:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd:38586' bound to instance 'U0' of component 'fifo_generator_v13_2_4' [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/synth/fifo_AntCtrl.vhd:543]
|
||||
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_async_rst' [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175]
|
||||
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1226]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_async_rst' (1#1) [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175]
|
||||
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single' [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153]
|
||||
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:205]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single' (2#1) [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153]
|
||||
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
|
||||
INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:358]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (7#1) [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
|
||||
INFO: [Synth 8-256] done synthesizing module 'fifo_AntCtrl' (21#1) [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/synth/fifo_AntCtrl.vhd:73]
|
||||
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_RST
|
||||
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port SRST
|
||||
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port SAFETY_CKT_WR_RST
|
||||
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[9]
|
||||
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[8]
|
||||
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[7]
|
||||
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[6]
|
||||
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[5]
|
||||
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[4]
|
||||
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[3]
|
||||
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[2]
|
||||
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[1]
|
||||
WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[0]
|
||||
WARNING: [Synth 8-3331] design wr_bin_cntr has unconnected port SRST
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port WR_EN_INTO_LOGIC
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port WR_RST_INTO_LOGIC
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port RD_EN
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port SRST_FULL_FF
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port WR_RST_BUSY
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port EMPTY
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port RAM_RD_EN
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port ALMOST_EMPTY
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[9]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[8]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[7]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[6]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[5]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[4]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[3]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[2]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[1]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[0]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[9]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[8]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[7]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[6]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[5]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[4]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[3]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[2]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[1]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[0]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[9]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[8]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[7]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[6]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[5]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[4]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[3]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[2]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[1]
|
||||
WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[0]
|
||||
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port SRST
|
||||
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port SAFETY_CKT_RD_RST
|
||||
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[9]
|
||||
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[8]
|
||||
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[7]
|
||||
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[6]
|
||||
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[5]
|
||||
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[4]
|
||||
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[3]
|
||||
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[2]
|
||||
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[1]
|
||||
WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[0]
|
||||
WARNING: [Synth 8-3331] design rd_bin_cntr has unconnected port SRST
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port RD_EN_INTO_LOGIC
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port RD_RST_INTO_LOGIC
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port RD_RST_BUSY
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port RAM_WR_EN
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port RST_FULL_FF
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port ALMOST_FULL_FB
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port FULL
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[9]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[8]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[7]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[6]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[5]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[4]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[3]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[2]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[1]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[0]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[9]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[8]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[7]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[6]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[5]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[4]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[3]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[2]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[1]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[0]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[9]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[8]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[7]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[6]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[5]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[4]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[3]
|
||||
WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[2]
|
||||
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 1056.262 ; gain = 347.336
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1056.262 ; gain = 347.336
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1056.262 ; gain = 347.336
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Netlist 29-17] Analyzing 20 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl_ooc.xdc] for cell 'U0'
|
||||
Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl_ooc.xdc] for cell 'U0'
|
||||
Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xdc] for cell 'U0'
|
||||
Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl.xdc] for cell 'U0'
|
||||
Parsing XDC File [D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/dont_touch.xdc]
|
||||
Finished Parsing XDC File [D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/dont_touch.xdc]
|
||||
Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl_clocks.xdc] for cell 'U0'
|
||||
Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl_clocks.xdc] for cell 'U0'
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/vivado-git/projects/datalink_814/dl814_cmos/ip/fifo_AntCtrl/fifo_AntCtrl_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fifo_AntCtrl_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/fifo_AntCtrl_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
||||
Finished Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
|
||||
Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
||||
Finished Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fifo_AntCtrl_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/fifo_AntCtrl_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
||||
Finished Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
|
||||
Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
||||
Finished Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fifo_AntCtrl_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/fifo_AntCtrl_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
||||
Finished Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
|
||||
Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
||||
Finished Sourcing Tcl File [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fifo_AntCtrl_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/fifo_AntCtrl_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1078.977 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1089.344 ; gain = 10.367
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1089.344 ; gain = 380.418
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k410tffg900-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1089.344 ; gain = 380.418
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property DONT_TOUCH = true for U0. (constraint file D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/dont_touch.xdc, line 9).
|
||||
Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint, line ).
|
||||
Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint, line ).
|
||||
Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint, line ).
|
||||
Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint, line ).
|
||||
Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint, line ).
|
||||
Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint, line ).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1089.344 ; gain = 380.418
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 1089.344 ; gain = 380.418
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 10 Bit Adders := 2
|
||||
+---XORs :
|
||||
2 Input 10 Bit XORs := 2
|
||||
2 Input 1 Bit XORs := 58
|
||||
+---Registers :
|
||||
10 Bit Registers := 13
|
||||
4 Bit Registers := 4
|
||||
2 Bit Registers := 3
|
||||
1 Bit Registers := 10
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module xpm_cdc_async_rst
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
2 Bit Registers := 1
|
||||
Module xpm_cdc_single
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
4 Bit Registers := 1
|
||||
Module reset_blk_ramfifo
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
4 Bit Registers := 1
|
||||
2 Bit Registers := 1
|
||||
1 Bit Registers := 6
|
||||
Module dmem
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
4 Bit Registers := 1
|
||||
Module xpm_cdc_gray
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 10 Bit XORs := 1
|
||||
2 Input 1 Bit XORs := 9
|
||||
+---Registers :
|
||||
10 Bit Registers := 4
|
||||
Module rd_bin_cntr
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 10 Bit Adders := 1
|
||||
+---Registers :
|
||||
10 Bit Registers := 2
|
||||
Module compare
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 10
|
||||
Module rd_status_flags_as
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
1 Bit Registers := 2
|
||||
Module wr_bin_cntr
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 10 Bit Adders := 1
|
||||
+---Registers :
|
||||
10 Bit Registers := 3
|
||||
Module wr_status_flags_as
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
1 Bit Registers := 2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 1540 (col length:140)
|
||||
BRAMs: 1590 (col length: RAMB18 140 RAMB36 70)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 1089.344 ; gain = 380.418
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP and Shift Register Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Distributed RAM: Preliminary Mapping Report (see note below)
|
||||
+------------+-------------------------------------------------------------------------------+----------------+----------------------+------------------------------+
|
||||
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
|
||||
+------------+-------------------------------------------------------------------------------+----------------+----------------------+------------------------------+
|
||||
|U0 | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 1 K x 4 | RAM64X1D x 16 RAM64M x 16 |
|
||||
+------------+-------------------------------------------------------------------------------+----------------+----------------------+------------------------------+
|
||||
|
||||
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished ROM, RAM, DSP and Shift Register Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:34 . Memory (MB): peak = 1089.344 ; gain = 380.418
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:26 ; elapsed = 00:00:34 . Memory (MB): peak = 1089.344 ; gain = 380.418
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP and Shift Register Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Distributed RAM: Final Mapping Report
|
||||
+------------+-------------------------------------------------------------------------------+----------------+----------------------+------------------------------+
|
||||
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
|
||||
+------------+-------------------------------------------------------------------------------+----------------+----------------------+------------------------------+
|
||||
|U0 | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 1 K x 4 | RAM64X1D x 16 RAM64M x 16 |
|
||||
+------------+-------------------------------------------------------------------------------+----------------+----------------------+------------------------------+
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
Finished ROM, RAM, DSP and Shift Register Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:26 ; elapsed = 00:00:34 . Memory (MB): peak = 1089.344 ; gain = 380.418
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 1089.344 ; gain = 380.418
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 1089.344 ; gain = 380.418
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 1089.344 ; gain = 380.418
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 1089.344 ; gain = 380.418
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 1089.344 ; gain = 380.418
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 1089.344 ; gain = 380.418
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+---------+------+
|
||||
| |Cell |Count |
|
||||
+------+---------+------+
|
||||
|1 |LUT1 | 2|
|
||||
|2 |LUT2 | 30|
|
||||
|3 |LUT3 | 9|
|
||||
|4 |LUT4 | 29|
|
||||
|5 |LUT5 | 10|
|
||||
|6 |LUT6 | 38|
|
||||
|7 |MUXCY | 20|
|
||||
|8 |MUXF7 | 8|
|
||||
|9 |MUXF8 | 4|
|
||||
|10 |RAM64M | 16|
|
||||
|11 |RAM64X1D | 16|
|
||||
|12 |FDCE | 57|
|
||||
|13 |FDPE | 17|
|
||||
|14 |FDRE | 88|
|
||||
+------+---------+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+-------------------------------------------------------------------------------------+-----------------------------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+-------------------------------------------------------------------------------------+-----------------------------+------+
|
||||
|1 |top | | 344|
|
||||
|2 | U0 |fifo_generator_v13_2_4 | 344|
|
||||
|3 | inst_fifo_gen |fifo_generator_v13_2_4_synth | 344|
|
||||
|4 | \gconvfifo.rf |fifo_generator_top | 344|
|
||||
|5 | \grf.rf |fifo_generator_ramfifo | 344|
|
||||
|6 | \gntv_or_sync_fifo.gcx.clkx |clk_x_pntrs | 126|
|
||||
|7 | wr_pntr_cdc_inst |xpm_cdc_gray__2 | 58|
|
||||
|8 | rd_pntr_cdc_inst |xpm_cdc_gray | 58|
|
||||
|9 | \gntv_or_sync_fifo.gl0.rd |rd_logic | 55|
|
||||
|10 | \gras.rsts |rd_status_flags_as | 14|
|
||||
|11 | c0 |compare_1 | 6|
|
||||
|12 | c1 |compare_2 | 5|
|
||||
|13 | rpntr |rd_bin_cntr | 41|
|
||||
|14 | \gntv_or_sync_fifo.gl0.wr |wr_logic | 71|
|
||||
|15 | \gwas.wsts |wr_status_flags_as | 14|
|
||||
|16 | c1 |compare | 5|
|
||||
|17 | c2 |compare_0 | 6|
|
||||
|18 | wpntr |wr_bin_cntr | 57|
|
||||
|19 | \gntv_or_sync_fifo.mem |memory | 64|
|
||||
|20 | \gdm.dm_gen.dm |dmem | 64|
|
||||
|21 | rstblk |reset_blk_ramfifo | 28|
|
||||
|22 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst |xpm_cdc_async_rst__2 | 2|
|
||||
|23 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst |xpm_cdc_async_rst | 2|
|
||||
|24 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd |xpm_cdc_single__2 | 4|
|
||||
|25 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr |xpm_cdc_single | 4|
|
||||
+------+-------------------------------------------------------------------------------------+-----------------------------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 1089.344 ; gain = 380.418
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 475 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:00:33 . Memory (MB): peak = 1089.344 ; gain = 347.336
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 1089.344 ; gain = 380.418
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 64 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1102.047 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 40 instances were transformed.
|
||||
(MUXCY,XORCY) => CARRY4: 8 instances
|
||||
RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 16 instances
|
||||
RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 16 instances
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
30 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:45 . Memory (MB): peak = 1102.047 ; gain = 713.664
|
||||
INFO: [Common 17-600] The following parameters have non-default value.
|
||||
general.maxThreads
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1102.047 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl.dcp' has been generated.
|
||||
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP fifo_AntCtrl, cache-ID = a60812ed144d9d97
|
||||
INFO: [Coretcl 2-1174] Renamed 24 cell refs.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1102.047 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file fifo_AntCtrl_utilization_synth.rpt -pb fifo_AntCtrl_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Sat Mar 18 23:33:47 2023...
|
||||
-6225
File diff suppressed because it is too large
Load Diff
-7376
File diff suppressed because it is too large
Load Diff
-38
@@ -1,38 +0,0 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:33:47 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.vhdl
|
||||
-- Design : fifo_AntCtrl
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity fifo_AntCtrl is
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
wr_clk : in STD_LOGIC;
|
||||
rd_clk : in STD_LOGIC;
|
||||
din : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
wr_en : in STD_LOGIC;
|
||||
rd_en : in STD_LOGIC;
|
||||
dout : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
full : out STD_LOGIC;
|
||||
empty : out STD_LOGIC
|
||||
);
|
||||
|
||||
end fifo_AntCtrl;
|
||||
|
||||
architecture stub of fifo_AntCtrl is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[3:0],wr_en,rd_en,dout[3:0],full,empty";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "fifo_generator_v13_2_4,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+1
-6
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="fifo_accor_cdc_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153567">
|
||||
<File Type="PA-TCL" Name="fifo_accor_cdc.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="fifo_accor_cdc_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="fifo_accor_cdc_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="fifo_accor_cdc.vds"/>
|
||||
<File Type="RDS-UTIL" Name="fifo_accor_cdc_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="fifo_accor_cdc_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="fifo_accor_cdc.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="fifo_accor_cdc_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="fifo_accor_cdc_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_accor_cdc">
|
||||
<File Path="$PPRDIR/../rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+1
-6
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="fifo_weight_cdc_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153568">
|
||||
<File Type="PA-TCL" Name="fifo_weight_cdc.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="fifo_weight_cdc_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="fifo_weight_cdc_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="fifo_weight_cdc.vds"/>
|
||||
<File Type="RDS-UTIL" Name="fifo_weight_cdc_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="fifo_weight_cdc_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="fifo_weight_cdc.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="fifo_weight_cdc_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="fifo_weight_cdc_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_weight_cdc">
|
||||
<File Path="$PPRDIR/../rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+1
-6
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ila_AntCtrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153568">
|
||||
<File Type="PA-TCL" Name="ila_AntCtrl.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ila_AntCtrl_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="ila_AntCtrl_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ila_AntCtrl.vds"/>
|
||||
<File Type="RDS-UTIL" Name="ila_AntCtrl_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ila_AntCtrl_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="ila_AntCtrl.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ila_AntCtrl_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="ila_AntCtrl_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_AntCtrl">
|
||||
<File Path="$PPRDIR/../ila_AntCtrl/ila_AntCtrl.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+1
-6
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ila_cal_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153569">
|
||||
<File Type="PA-TCL" Name="ila_cal.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ila_cal_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="ila_cal_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ila_cal.vds"/>
|
||||
<File Type="RDS-UTIL" Name="ila_cal_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ila_cal_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="ila_cal.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ila_cal_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="ila_cal_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_cal">
|
||||
<File Path="$PPRDIR/../ila_cal/ila_cal.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+1
-6
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ila_rfcontrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153569">
|
||||
<File Type="PA-TCL" Name="ila_rfcontrl.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ila_rfcontrl_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="ila_rfcontrl_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ila_rfcontrl.vds"/>
|
||||
<File Type="RDS-UTIL" Name="ila_rfcontrl_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ila_rfcontrl_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="ila_rfcontrl.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ila_rfcontrl_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="ila_rfcontrl_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_rfcontrl">
|
||||
<File Path="$PPRDIR/../ila_rfcontrl/ila_rfcontrl.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+1
-6
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ila_rx_pre_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153570">
|
||||
<File Type="PA-TCL" Name="ila_rx_pre.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ila_rx_pre_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="ila_rx_pre_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ila_rx_pre.vds"/>
|
||||
<File Type="RDS-UTIL" Name="ila_rx_pre_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ila_rx_pre_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="ila_rx_pre.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ila_rx_pre_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="ila_rx_pre_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_rx_pre">
|
||||
<File Path="$PPRDIR/../ila_rx_pre/ila_rx_pre.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+1
-6
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ila_tx_rx_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153570">
|
||||
<File Type="PA-TCL" Name="ila_tx_rx.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ila_tx_rx_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="ila_tx_rx_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ila_tx_rx.vds"/>
|
||||
<File Type="RDS-UTIL" Name="ila_tx_rx_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ila_tx_rx_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="ila_tx_rx.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ila_tx_rx_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="ila_tx_rx_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_tx_rx">
|
||||
<File Path="$PPRDIR/../ila_tx_rx/ila_tx_rx.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+1
-6
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ram_hop_data_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153570">
|
||||
<File Type="PA-TCL" Name="ram_hop_data.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ram_hop_data_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="ram_hop_data_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ram_hop_data.vds"/>
|
||||
<File Type="RDS-UTIL" Name="ram_hop_data_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ram_hop_data_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="ram_hop_data.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ram_hop_data_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="ram_hop_data_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ram_hop_data">
|
||||
<File Path="$PPRDIR/../rx_pre_process/ram_hop_data/ram_hop_data.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+1
-6
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="rotate_16b_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153571">
|
||||
<File Type="PA-TCL" Name="rotate_16b.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="rotate_16b_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="rotate_16b_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="rotate_16b.vds"/>
|
||||
<File Type="RDS-UTIL" Name="rotate_16b_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="rotate_16b_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="rotate_16b.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="rotate_16b_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="rotate_16b_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/rotate_16b">
|
||||
<File Path="$PPRDIR/../rx_pre_process/rotate_16b/rotate_16b.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+1
-1
@@ -1,5 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado.bat" Owner="Josh" Host="JOSH-ASUS-Z690" Pid="25208" HostCore="20" HostMemory="068448337920">
|
||||
<Process Command="vivado.bat" Owner="Josh" Host="JOSH-ASUS-Z690" Pid="34076" HostCore="20" HostMemory="068448337920">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
+24
@@ -0,0 +1,24 @@
|
||||
# This file is automatically generated.
|
||||
# It contains project source information necessary for synthesis and implementation.
|
||||
|
||||
# IP: D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci
|
||||
# IP: The module: 'selectio_lvds_rx' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_rx'. Do not add the DONT_TOUCH constraint.
|
||||
set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet
|
||||
|
||||
# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_rx'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet
|
||||
|
||||
# IP: D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci
|
||||
# IP: The module: 'selectio_lvds_rx' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_rx'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet
|
||||
|
||||
# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_rx'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet
|
||||
+62
@@ -0,0 +1,62 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="selectio_lvds_rx_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679221532">
|
||||
<File Type="PA-TCL" Name="selectio_lvds_rx.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="selectio_lvds_rx_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="selectio_lvds_rx_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="selectio_lvds_rx.vds"/>
|
||||
<File Type="RDS-UTIL" Name="selectio_lvds_rx_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="selectio_lvds_rx_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="selectio_lvds_rx.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="selectio_lvds_rx_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="selectio_lvds_rx_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/selectio_lvds_rx">
|
||||
<File Path="$PPRDIR/../ant_rf_interface/selectio_lvds_rx.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="selectio_lvds_rx"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/selectio_lvds_rx">
|
||||
<File Path="$PPRDIR/../ant_rf_interface/selectio_lvds_rx.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="selectio_lvds_rx"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
+1
-1
@@ -6,4 +6,4 @@ REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log fifo_AntCtrl.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fifo_AntCtrl.tcl
|
||||
vivado -log selectio_lvds_rx.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_rx.tcl
|
||||
+13
-11
@@ -1,13 +1,13 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3239:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3239:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3330:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3330:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||
@@ -34,6 +34,8 @@ version:1
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f74785f7278:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c72616d5f686f705f64617461:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636f726469635f76365f305f31355c726f746174655f313662:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c73656c656374696f5f77697a5f76355f315f31335c73656c656374696f5f6c7664735f7278:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c73656c656374696f5f77697a5f76355f315f31335c73656c656374696f5f6c7664735f7478:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f616e745f7264:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f616e745f74657374:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f63616c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
@@ -48,12 +50,12 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3238:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3238:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3238:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3238:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3238:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3238:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3238:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3633:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3633:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3633:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3633:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3633:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3633:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3633:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3661346264366134396337643466636438383330333461376438356536303661:506172656e742050412070726f6a656374204944:00
|
||||
eof:3863841633
|
||||
eof:3953027363
|
||||
+1
-1
@@ -23,7 +23,7 @@ eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log fifo_AntCtrl.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fifo_AntCtrl.tcl" );
|
||||
"-log selectio_lvds_rx.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_rx.tcl" );
|
||||
|
||||
|
||||
|
||||
+2
-2
@@ -24,7 +24,7 @@ else
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1'
|
||||
HD_PWD='D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
@@ -40,4 +40,4 @@ EAStep()
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log fifo_AntCtrl.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fifo_AntCtrl.tcl
|
||||
EAStep vivado -log selectio_lvds_rx.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_rx.tcl
|
||||
BIN
Binary file not shown.
+156
@@ -0,0 +1,156 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
create_project -in_memory -part xc7k410tffg900-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt [current_project]
|
||||
set_property parent.project_path D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.xpr [current_project]
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo d:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_ip -quiet D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci
|
||||
set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xdc]
|
||||
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc dont_touch.xdc
|
||||
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
|
||||
set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1 -new_name selectio_lvds_rx -ip [get_ips selectio_lvds_rx]]
|
||||
|
||||
if { $cached_ip eq {} } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top selectio_lvds_rx -part xc7k410tffg900-2 -mode out_of_context
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix selectio_lvds_rx_ selectio_lvds_rx.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_stub.v
|
||||
lappend ipCachedFiles selectio_lvds_rx_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_stub.vhdl
|
||||
lappend ipCachedFiles selectio_lvds_rx_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_sim_netlist.v
|
||||
lappend ipCachedFiles selectio_lvds_rx_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_rx_sim_netlist.vhdl
|
||||
lappend ipCachedFiles selectio_lvds_rx_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
config_ip_cache -add -dcp selectio_lvds_rx.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips selectio_lvds_rx]
|
||||
}
|
||||
|
||||
rename_ref -prefix_all selectio_lvds_rx_
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef selectio_lvds_rx.dcp
|
||||
create_report "selectio_lvds_rx_synth_1_synth_report_utilization_0" "report_utilization -file selectio_lvds_rx_utilization_synth.rpt -pb selectio_lvds_rx_utilization_synth.pb"
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
}; # end if cached_ip
|
||||
|
||||
add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci]
|
||||
|
||||
add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci]
|
||||
|
||||
add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci]
|
||||
|
||||
add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci]
|
||||
|
||||
add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.dcp -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xci]
|
||||
|
||||
if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.v D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.vhdl D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.v D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.vhdl D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_rx
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
+289
@@ -0,0 +1,289 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Sun Mar 19 18:25:34 2023
|
||||
# Process ID: 30212
|
||||
# Current directory: D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1
|
||||
# Command line: vivado.exe -log selectio_lvds_rx.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_rx.tcl
|
||||
# Log file: D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.vds
|
||||
# Journal file: D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
Sourcing tcl script 'C:/Users/Josh/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl'
|
||||
source selectio_lvds_rx.tcl -notrace
|
||||
Command: synth_design -top selectio_lvds_rx -part xc7k410tffg900-2 -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Device 21-403] Loading part xc7k410tffg900-2
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 26720
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 884.641 ; gain = 176.336
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'selectio_lvds_rx' [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.v:58]
|
||||
Parameter SYS_W bound to: 2 - type: integer
|
||||
Parameter DEV_W bound to: 2 - type: integer
|
||||
INFO: [Synth 8-6157] synthesizing module 'selectio_lvds_rx_selectio_wiz' [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v:56]
|
||||
Parameter SYS_W bound to: 2 - type: integer
|
||||
Parameter DEV_W bound to: 2 - type: integer
|
||||
INFO: [Synth 8-6157] synthesizing module 'IBUF' [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:32856]
|
||||
Parameter CAPACITANCE bound to: DONT_CARE - type: string
|
||||
Parameter IBUF_DELAY_VALUE bound to: 0 - type: string
|
||||
Parameter IBUF_LOW_PWR bound to: TRUE - type: string
|
||||
Parameter IFD_DELAY_VALUE bound to: AUTO - type: string
|
||||
Parameter IOSTANDARD bound to: LVCMOS33 - type: string
|
||||
INFO: [Synth 8-6155] done synthesizing module 'IBUF' (1#1) [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:32856]
|
||||
INFO: [Synth 8-6157] synthesizing module 'FDRE' [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664]
|
||||
Parameter INIT bound to: 1'b0
|
||||
Parameter IS_C_INVERTED bound to: 1'b0
|
||||
Parameter IS_D_INVERTED bound to: 1'b0
|
||||
Parameter IS_R_INVERTED bound to: 1'b0
|
||||
INFO: [Synth 8-6155] done synthesizing module 'FDRE' (2#1) [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'selectio_lvds_rx_selectio_wiz' (3#1) [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_selectio_wiz.v:56]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'selectio_lvds_rx' (4#1) [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.v:58]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 952.234 ; gain = 243.930
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:00 ; elapsed = 00:00:03 . Memory (MB): peak = 952.234 ; gain = 243.930
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:00 ; elapsed = 00:00:03 . Memory (MB): peak = 952.234 ; gain = 243.930
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_ooc.xdc] for cell 'inst'
|
||||
Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_ooc.xdc] for cell 'inst'
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx_ooc.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/selectio_lvds_rx_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/selectio_lvds_rx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xdc] for cell 'inst'
|
||||
Finished Parsing XDC File [d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_rx/selectio_lvds_rx.xdc] for cell 'inst'
|
||||
Parsing XDC File [D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/dont_touch.xdc]
|
||||
Finished Parsing XDC File [D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/dont_touch.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 995.320 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1007.500 ; gain = 12.180
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1007.500 ; gain = 299.195
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k410tffg900-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1007.500 ; gain = 299.195
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property DONT_TOUCH = true for inst. (constraint file D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/dont_touch.xdc, line 9).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1007.500 ; gain = 299.195
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1007.500 ; gain = 299.195
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 1540 (col length:140)
|
||||
BRAMs: 1590 (col length: RAMB18 140 RAMB36 70)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1007.500 ; gain = 299.195
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:02 ; elapsed = 00:00:11 . Memory (MB): peak = 1018.660 ; gain = 310.355
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:02 ; elapsed = 00:00:11 . Memory (MB): peak = 1018.660 ; gain = 310.355
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:02 ; elapsed = 00:00:11 . Memory (MB): peak = 1028.504 ; gain = 320.199
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-----+------+
|
||||
| |Cell |Count |
|
||||
+------+-----+------+
|
||||
|1 |FDRE | 2|
|
||||
|2 |IBUF | 2|
|
||||
+------+-----+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+------------------------------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+------------------------------+------+
|
||||
|1 |top | | 4|
|
||||
|2 | inst |selectio_lvds_rx_selectio_wiz | 4|
|
||||
+------+---------+------------------------------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:01 ; elapsed = 00:00:10 . Memory (MB): peak = 1043.328 ; gain = 279.758
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1043.328 ; gain = 335.023
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1070.727 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
18 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:17 . Memory (MB): peak = 1070.727 ; gain = 683.102
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1070.727 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.dcp' has been generated.
|
||||
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP selectio_lvds_rx, cache-ID = fffcbdb43410d449
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1070.727 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file selectio_lvds_rx_utilization_synth.rpt -pb selectio_lvds_rx_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Sun Mar 19 18:25:55 2023...
|
||||
+168
@@ -0,0 +1,168 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sun Mar 19 18:25:55 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.v
|
||||
// Design : selectio_lvds_rx
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* DEV_W = "2" *) (* SYS_W = "2" *)
|
||||
(* NotValidForBitStream *)
|
||||
module selectio_lvds_rx
|
||||
(data_in_from_pins,
|
||||
data_in_to_device,
|
||||
clk_in,
|
||||
io_reset);
|
||||
input [1:0]data_in_from_pins;
|
||||
output [1:0]data_in_to_device;
|
||||
input clk_in;
|
||||
input io_reset;
|
||||
|
||||
wire clk_in;
|
||||
(* IBUF_LOW_PWR *) (* IOSTANDARD = "LVCMOS33" *) wire [1:0]data_in_from_pins;
|
||||
wire [1:0]data_in_to_device;
|
||||
wire io_reset;
|
||||
|
||||
(* DEV_W = "2" *)
|
||||
(* SYS_W = "2" *)
|
||||
selectio_lvds_rx_selectio_lvds_rx_selectio_wiz inst
|
||||
(.clk_in(clk_in),
|
||||
.data_in_from_pins(data_in_from_pins),
|
||||
.data_in_to_device(data_in_to_device),
|
||||
.io_reset(io_reset));
|
||||
endmodule
|
||||
|
||||
(* DEV_W = "2" *) (* ORIG_REF_NAME = "selectio_lvds_rx_selectio_wiz" *) (* SYS_W = "2" *)
|
||||
module selectio_lvds_rx_selectio_lvds_rx_selectio_wiz
|
||||
(data_in_from_pins,
|
||||
data_in_to_device,
|
||||
clk_in,
|
||||
io_reset);
|
||||
input [1:0]data_in_from_pins;
|
||||
output [1:0]data_in_to_device;
|
||||
input clk_in;
|
||||
input io_reset;
|
||||
|
||||
wire clk_in;
|
||||
wire [1:0]data_in_from_pins;
|
||||
wire [1:0]data_in_from_pins_int;
|
||||
wire [1:0]data_in_to_device;
|
||||
wire io_reset;
|
||||
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* IOB = "TRUE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\pins[0].fdre_in_inst
|
||||
(.C(clk_in),
|
||||
.CE(1'b1),
|
||||
.D(data_in_from_pins_int[0]),
|
||||
.Q(data_in_to_device[0]),
|
||||
.R(io_reset));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
(* IBUF_DELAY_VALUE = "0" *)
|
||||
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||
IBUF \pins[0].ibuf_inst
|
||||
(.I(data_in_from_pins[0]),
|
||||
.O(data_in_from_pins_int[0]));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* IOB = "TRUE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\pins[1].fdre_in_inst
|
||||
(.C(clk_in),
|
||||
.CE(1'b1),
|
||||
.D(data_in_from_pins_int[1]),
|
||||
.Q(data_in_to_device[1]),
|
||||
.R(io_reset));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
(* IBUF_DELAY_VALUE = "0" *)
|
||||
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||
IBUF \pins[1].ibuf_inst
|
||||
(.I(data_in_from_pins[1]),
|
||||
.O(data_in_from_pins_int[1]));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+121
@@ -0,0 +1,121 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sun Mar 19 18:25:55 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim
|
||||
-- D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_sim_netlist.vhdl
|
||||
-- Design : selectio_lvds_rx
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity selectio_lvds_rx_selectio_lvds_rx_selectio_wiz is
|
||||
port (
|
||||
data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
clk_in : in STD_LOGIC;
|
||||
io_reset : in STD_LOGIC
|
||||
);
|
||||
attribute DEV_W : integer;
|
||||
attribute DEV_W of selectio_lvds_rx_selectio_lvds_rx_selectio_wiz : entity is 2;
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of selectio_lvds_rx_selectio_lvds_rx_selectio_wiz : entity is "selectio_lvds_rx_selectio_wiz";
|
||||
attribute SYS_W : integer;
|
||||
attribute SYS_W of selectio_lvds_rx_selectio_lvds_rx_selectio_wiz : entity is 2;
|
||||
end selectio_lvds_rx_selectio_lvds_rx_selectio_wiz;
|
||||
|
||||
architecture STRUCTURE of selectio_lvds_rx_selectio_lvds_rx_selectio_wiz is
|
||||
signal data_in_from_pins_int : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
attribute BOX_TYPE : string;
|
||||
attribute BOX_TYPE of \pins[0].fdre_in_inst\ : label is "PRIMITIVE";
|
||||
attribute IOB : string;
|
||||
attribute IOB of \pins[0].fdre_in_inst\ : label is "TRUE";
|
||||
attribute BOX_TYPE of \pins[0].ibuf_inst\ : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE : string;
|
||||
attribute CAPACITANCE of \pins[0].ibuf_inst\ : label is "DONT_CARE";
|
||||
attribute IBUF_DELAY_VALUE : string;
|
||||
attribute IBUF_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "0";
|
||||
attribute IFD_DELAY_VALUE : string;
|
||||
attribute IFD_DELAY_VALUE of \pins[0].ibuf_inst\ : label is "AUTO";
|
||||
attribute BOX_TYPE of \pins[1].fdre_in_inst\ : label is "PRIMITIVE";
|
||||
attribute IOB of \pins[1].fdre_in_inst\ : label is "TRUE";
|
||||
attribute BOX_TYPE of \pins[1].ibuf_inst\ : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE of \pins[1].ibuf_inst\ : label is "DONT_CARE";
|
||||
attribute IBUF_DELAY_VALUE of \pins[1].ibuf_inst\ : label is "0";
|
||||
attribute IFD_DELAY_VALUE of \pins[1].ibuf_inst\ : label is "AUTO";
|
||||
begin
|
||||
\pins[0].fdre_in_inst\: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '0',
|
||||
IS_C_INVERTED => '0',
|
||||
IS_D_INVERTED => '0',
|
||||
IS_R_INVERTED => '0'
|
||||
)
|
||||
port map (
|
||||
C => clk_in,
|
||||
CE => '1',
|
||||
D => data_in_from_pins_int(0),
|
||||
Q => data_in_to_device(0),
|
||||
R => io_reset
|
||||
);
|
||||
\pins[0].ibuf_inst\: unisim.vcomponents.IBUF
|
||||
port map (
|
||||
I => data_in_from_pins(0),
|
||||
O => data_in_from_pins_int(0)
|
||||
);
|
||||
\pins[1].fdre_in_inst\: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '0',
|
||||
IS_C_INVERTED => '0',
|
||||
IS_D_INVERTED => '0',
|
||||
IS_R_INVERTED => '0'
|
||||
)
|
||||
port map (
|
||||
C => clk_in,
|
||||
CE => '1',
|
||||
D => data_in_from_pins_int(1),
|
||||
Q => data_in_to_device(1),
|
||||
R => io_reset
|
||||
);
|
||||
\pins[1].ibuf_inst\: unisim.vcomponents.IBUF
|
||||
port map (
|
||||
I => data_in_from_pins(1),
|
||||
O => data_in_from_pins_int(1)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity selectio_lvds_rx is
|
||||
port (
|
||||
data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
clk_in : in STD_LOGIC;
|
||||
io_reset : in STD_LOGIC
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of selectio_lvds_rx : entity is true;
|
||||
attribute DEV_W : integer;
|
||||
attribute DEV_W of selectio_lvds_rx : entity is 2;
|
||||
attribute SYS_W : integer;
|
||||
attribute SYS_W of selectio_lvds_rx : entity is 2;
|
||||
end selectio_lvds_rx;
|
||||
|
||||
architecture STRUCTURE of selectio_lvds_rx is
|
||||
attribute DEV_W of inst : label is 2;
|
||||
attribute SYS_W of inst : label is 2;
|
||||
begin
|
||||
inst: entity work.selectio_lvds_rx_selectio_lvds_rx_selectio_wiz
|
||||
port map (
|
||||
clk_in => clk_in,
|
||||
data_in_from_pins(1 downto 0) => data_in_from_pins(1 downto 0),
|
||||
data_in_to_device(1 downto 0) => data_in_to_device(1 downto 0),
|
||||
io_reset => io_reset
|
||||
);
|
||||
end STRUCTURE;
|
||||
+10
-16
@@ -1,11 +1,11 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:33:47 2023
|
||||
// Date : Sun Mar 19 18:25:55 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.v
|
||||
// Design : fifo_AntCtrl
|
||||
// D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.v
|
||||
// Design : selectio_lvds_rx
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
@@ -13,17 +13,11 @@
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "fifo_generator_v13_2_4,Vivado 2019.1.3" *)
|
||||
module fifo_AntCtrl(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
|
||||
empty)
|
||||
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[3:0],wr_en,rd_en,dout[3:0],full,empty" */;
|
||||
input rst;
|
||||
input wr_clk;
|
||||
input rd_clk;
|
||||
input [3:0]din;
|
||||
input wr_en;
|
||||
input rd_en;
|
||||
output [3:0]dout;
|
||||
output full;
|
||||
output empty;
|
||||
module selectio_lvds_rx(data_in_from_pins, data_in_to_device, clk_in,
|
||||
io_reset)
|
||||
/* synthesis syn_black_box black_box_pad_pin="data_in_from_pins[1:0],data_in_to_device[1:0],clk_in,io_reset" */;
|
||||
input [1:0]data_in_from_pins;
|
||||
output [1:0]data_in_to_device;
|
||||
input clk_in;
|
||||
input io_reset;
|
||||
endmodule
|
||||
+31
@@ -0,0 +1,31 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sun Mar 19 18:25:55 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_rx_synth_1/selectio_lvds_rx_stub.vhdl
|
||||
-- Design : selectio_lvds_rx
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity selectio_lvds_rx is
|
||||
Port (
|
||||
data_in_from_pins : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
data_in_to_device : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
clk_in : in STD_LOGIC;
|
||||
io_reset : in STD_LOGIC
|
||||
);
|
||||
|
||||
end selectio_lvds_rx;
|
||||
|
||||
architecture stub of selectio_lvds_rx is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "data_in_from_pins[1:0],data_in_to_device[1:0],clk_in,io_reset";
|
||||
begin
|
||||
end;
|
||||
BIN
Binary file not shown.
+23
-36
@@ -1,13 +1,13 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
| Date : Sat Mar 18 23:33:47 2023
|
||||
| Date : Sun Mar 19 18:25:55 2023
|
||||
| Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file fifo_AntCtrl_utilization_synth.rpt -pb fifo_AntCtrl_utilization_synth.pb
|
||||
| Design : fifo_AntCtrl
|
||||
| Command : report_utilization -file selectio_lvds_rx_utilization_synth.rpt -pb selectio_lvds_rx_utilization_synth.pb
|
||||
| Design : selectio_lvds_rx
|
||||
| Device : 7k410tffg900-2
|
||||
| Design State : Synthesized
|
||||
-------------------------------------------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
@@ -27,20 +27,18 @@ Table of Contents
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 198 | 0 | 254200 | 0.08 |
|
||||
| LUT as Logic | 102 | 0 | 254200 | 0.04 |
|
||||
| LUT as Memory | 96 | 0 | 90600 | 0.11 |
|
||||
| LUT as Distributed RAM | 96 | 0 | | |
|
||||
| LUT as Shift Register | 0 | 0 | | |
|
||||
| Slice Registers | 162 | 0 | 508400 | 0.03 |
|
||||
| Register as Flip Flop | 162 | 0 | 508400 | 0.03 |
|
||||
| Register as Latch | 0 | 0 | 508400 | 0.00 |
|
||||
| F7 Muxes | 8 | 0 | 127100 | <0.01 |
|
||||
| F8 Muxes | 4 | 0 | 63550 | <0.01 |
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 0 | 0 | 254200 | 0.00 |
|
||||
| LUT as Logic | 0 | 0 | 254200 | 0.00 |
|
||||
| LUT as Memory | 0 | 0 | 90600 | 0.00 |
|
||||
| Slice Registers | 2 | 2 | 508400 | <0.01 |
|
||||
| Register as Flip Flop | 2 | 2 | 508400 | <0.01 |
|
||||
| Register as Latch | 0 | 0 | 508400 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 127100 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 63550 | 0.00 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
@@ -56,10 +54,10 @@ Table of Contents
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 17 | Yes | - | Set |
|
||||
| 57 | Yes | - | Reset |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 88 | Yes | Reset | - |
|
||||
| 2 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
@@ -92,7 +90,7 @@ Table of Contents
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 0 | 0 | 500 | 0.00 |
|
||||
| Bonded IOB | 2 | 0 | 500 | 0.40 |
|
||||
| Bonded IPADs | 0 | 0 | 50 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 32 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
|
||||
@@ -153,19 +151,8 @@ Table of Contents
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| RAMD64E | 96 | Distributed Memory |
|
||||
| FDRE | 88 | Flop & Latch |
|
||||
| FDCE | 57 | Flop & Latch |
|
||||
| LUT6 | 38 | LUT |
|
||||
| LUT2 | 30 | LUT |
|
||||
| LUT4 | 29 | LUT |
|
||||
| FDPE | 17 | Flop & Latch |
|
||||
| LUT5 | 10 | LUT |
|
||||
| LUT3 | 9 | LUT |
|
||||
| MUXF7 | 8 | MuxFx |
|
||||
| CARRY4 | 8 | CarryLogic |
|
||||
| MUXF8 | 4 | MuxFx |
|
||||
| LUT1 | 2 | LUT |
|
||||
| IBUF | 2 | IO |
|
||||
| FDRE | 2 | Flop & Latch |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
BIN
Binary file not shown.
+5
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado.bat" Owner="Josh" Host="JOSH-ASUS-Z690" Pid="30700" HostCore="20" HostMemory="068448337920">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
+270
@@ -0,0 +1,270 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
+67
@@ -0,0 +1,67 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
if [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
+24
@@ -0,0 +1,24 @@
|
||||
# This file is automatically generated.
|
||||
# It contains project source information necessary for synthesis and implementation.
|
||||
|
||||
# IP: D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci
|
||||
# IP: The module: 'selectio_lvds_tx' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_tx'. Do not add the DONT_TOUCH constraint.
|
||||
set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet
|
||||
|
||||
# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_tx'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet
|
||||
|
||||
# IP: D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci
|
||||
# IP: The module: 'selectio_lvds_tx' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_tx'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet
|
||||
|
||||
# XDC: d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'selectio_lvds_tx'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet
|
||||
+16
-21
@@ -1,23 +1,20 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="fifo_AntCtrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679153568">
|
||||
<File Type="PA-TCL" Name="fifo_AntCtrl.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="fifo_AntCtrl_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="fifo_AntCtrl_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="fifo_AntCtrl.vds"/>
|
||||
<File Type="RDS-UTIL" Name="fifo_AntCtrl_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="fifo_AntCtrl_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="fifo_AntCtrl.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="fifo_AntCtrl_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="fifo_AntCtrl_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_AntCtrl">
|
||||
<File Path="$PPRDIR/../fifo_AntCtrl/fifo_AntCtrl.xci">
|
||||
<GenRun Id="selectio_lvds_tx_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679218316">
|
||||
<File Type="PA-TCL" Name="selectio_lvds_tx.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="selectio_lvds_tx_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="selectio_lvds_tx.vds"/>
|
||||
<File Type="RDS-UTIL" Name="selectio_lvds_tx_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="selectio_lvds_tx_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="selectio_lvds_tx.dcp"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/selectio_lvds_tx">
|
||||
<File Path="$PPRDIR/../ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../fifo_AntCtrl.xcix">
|
||||
<File Path="$PPRDIR/../ant_rf_interface/selectio_lvds_tx.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
@@ -25,19 +22,19 @@
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="fifo_AntCtrl"/>
|
||||
<Option Name="TopModule" Val="selectio_lvds_tx"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_AntCtrl">
|
||||
<File Path="$PPRDIR/../fifo_AntCtrl/fifo_AntCtrl.xci">
|
||||
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/selectio_lvds_tx">
|
||||
<File Path="$PPRDIR/../ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../fifo_AntCtrl.xcix">
|
||||
<File Path="$PPRDIR/../ant_rf_interface/selectio_lvds_tx.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
@@ -45,7 +42,7 @@
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="fifo_AntCtrl"/>
|
||||
<Option Name="TopModule" Val="selectio_lvds_tx"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log selectio_lvds_tx.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_tx.tcl
|
||||
+61
@@ -0,0 +1,61 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3330:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3330:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c434f534c55545f31305f3136626974:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669725f636f6d70696c65725f76375f325f31325c47617573734669725f31326d:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669725f636f6d70696c65725f76375f325f31325c47617573734669725f316d7035:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f335c6164393336315f636c6b5f67656e:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c635f6164647375625f7631325f305f31335c6164645f7332345f7333325f733332:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f335c616e745f636c6b5f67656e5f73746731:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f335c616e745f636c6b5f67656e5f73746732:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636f726469635f76365f305f31355c6174616e325f313662:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636d70795f76365f305f31375c636d70795f3132783132:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636d70795f76365f305f31375c636d70795f3136783132:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c646174615f3170356d:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669666f5f67656e657261746f725f7631335f325f345c6669666f5f416e744374726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669666f5f67656e657261746f725f7631335f325f345c6669666f5f6163636f725f636463:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669666f5f67656e657261746f725f7631335f325f345c6669666f5f7765696768745f636463:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f416e744374726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f63616c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f7266636f6e74726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f72785f707265:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f74785f7278:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c72616d5f686f705f64617461:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636f726469635f76365f305f31355c726f746174655f313662:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c73656c656374696f5f77697a5f76355f315f31335c73656c656374696f5f6c7664735f7278:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c73656c656374696f5f77697a5f76355f315f31335c73656c656374696f5f6c7664735f7478:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f616e745f7264:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f616e745f74657374:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f63616c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f636c6b5f6c645f7264:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f6d616e75616c5f6374726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f72665f7264:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f7266636f6e74726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3539:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3539:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3539:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3539:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3539:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3539:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3539:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3661346264366134396337643466636438383330333461376438356536303661:506172656e742050412070726f6a656374204944:00
|
||||
eof:1501154971
|
||||
+36
@@ -0,0 +1,36 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;";
|
||||
} else {
|
||||
PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log selectio_lvds_tx.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_tx.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
+43
@@ -0,0 +1,43 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
|
||||
exit
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin
|
||||
else
|
||||
PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log selectio_lvds_tx.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source selectio_lvds_tx.tcl
|
||||
BIN
Binary file not shown.
+156
@@ -0,0 +1,156 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
create_project -in_memory -part xc7k410tffg900-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/wt [current_project]
|
||||
set_property parent.project_path D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.xpr [current_project]
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo d:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_ip -quiet D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci
|
||||
set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xdc]
|
||||
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc dont_touch.xdc
|
||||
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
|
||||
set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1 -new_name selectio_lvds_tx -ip [get_ips selectio_lvds_tx]]
|
||||
|
||||
if { $cached_ip eq {} } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top selectio_lvds_tx -part xc7k410tffg900-2 -mode out_of_context
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix selectio_lvds_tx_ selectio_lvds_tx.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_stub.v
|
||||
lappend ipCachedFiles selectio_lvds_tx_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_stub.vhdl
|
||||
lappend ipCachedFiles selectio_lvds_tx_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_sim_netlist.v
|
||||
lappend ipCachedFiles selectio_lvds_tx_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ selectio_lvds_tx_sim_netlist.vhdl
|
||||
lappend ipCachedFiles selectio_lvds_tx_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
config_ip_cache -add -dcp selectio_lvds_tx.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips selectio_lvds_tx]
|
||||
}
|
||||
|
||||
rename_ref -prefix_all selectio_lvds_tx_
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef selectio_lvds_tx.dcp
|
||||
create_report "selectio_lvds_tx_synth_1_synth_report_utilization_0" "report_utilization -file selectio_lvds_tx_utilization_synth.rpt -pb selectio_lvds_tx_utilization_synth.pb"
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
}; # end if cached_ip
|
||||
|
||||
add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci]
|
||||
|
||||
add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci]
|
||||
|
||||
add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.v -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci]
|
||||
|
||||
add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci]
|
||||
|
||||
add_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx.dcp -of_objects [get_files D:/vivado-git/projects/datalink_814/dl814_k7/ip/ant_rf_interface/selectio_lvds_tx/selectio_lvds_tx.xci]
|
||||
|
||||
if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.v D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_sim_netlist.vhdl D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.v D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/projects/datalink_814/dl814_k7/ip/managed_ip_project/managed_ip_project.runs/selectio_lvds_tx_synth_1/selectio_lvds_tx_stub.vhdl D:/vivado-git/projects/datalink_814/dl814_k7/ip/ip_user_files/ip/selectio_lvds_tx
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user