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Modify: k7 rf interface; dj tx interp

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This commit is contained in:
josh
2023-03-19 19:36:12 +08:00
parent 228b9ac488
commit a8292e95be
297 changed files with 17972 additions and 19805 deletions
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projects/datalink_814/dl814_k7/rtl/rx_pre_process/weight_vec_formatting.v
+1 -1
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@@ -47,7 +47,7 @@ module weight_vec_formatting
parameter WEIGHT_WIDTH = 32,
parameter DATA_O_WIDTH = 16,
parameter FRAME_HEAD = 32'b10110011100011110000111000110010,
parameter FIFO_CDC_DEPTH = 16
parameter FIFO_CDC_DEPTH = 32
)
(
// clock & reset
projects/datalink_814/dl814_k7/rtl/system_top.v
+82 -60
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@@ -84,7 +84,7 @@ module system_top
// control signals
output ad9361_1_reset_b , // ad9361 active-low reset control
output ad9361_1_en_agc , // ad9361 manual agc control
output ad9361_1_enbale , // ad9361 enable state machine pin control (spi control is also allowed)
output ad9361_1_enable , // ad9361 enable state machine pin control (spi control is also allowed)
output ad9361_1_txnrx , // ad9361 enable state machine pin control (spi control is also allowed)
output [ 3:0] ad9361_1_ctrl_in ,
input [ 7:0] ad9361_1_ctrl_out ,
@@ -108,7 +108,7 @@ module system_top
// control signals
output ad9361_2_reset_b , // ad9361 active-low reset control
output ad9361_2_en_agc , // ad9361 manual agc control
output ad9361_2_enbale , // ad9361 enable state machine pin control (spi control is also allowed)
output ad9361_2_enable , // ad9361 enable state machine pin control (spi control is also allowed)
output ad9361_2_txnrx , // ad9361 enable state machine pin control (spi control is also allowed)
output [ 3:0] ad9361_2_ctrl_in ,
input [ 7:0] ad9361_2_ctrl_out ,
@@ -389,63 +389,93 @@ system_bd_wrapper u_system_bd_wrapper
////////////////////////////////////////////////////////////////////////////////
///////////////////////////// Phased-Array Control /////////////////////////////
///////////////// Phased-Array & RF Synthesizer Control & C2C //////////////////
////////////////////////////////////////////////////////////////////////////////
// antenna & rf interface
wire rf_clk ;
wire rf_en ;
wire rf_data;
wire rf_tr ;
wire rf_dary;
wire rf_dout;
// output data
assign ant_cin = clk_96m;
// assign ant_din0 = accor_stream_data; // assigned afterwards
assign ant_din1 = rf_data;
assign ant_tr = rf_tr;
assign ant_dary = rf_dary;
// input data
wire ant_dout0_cdc, ant_dout1_cdc;
assign rf_dout = ant_dout1_cdc;
xpm_cdc_single u_cdc_ant_dout0
(
.dest_out (ant_dout0_cdc ), // 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
.dest_clk (clk_96m ), // 1-bit input: Clock signal for the destination clock domain.
.src_clk (ant_cout ), // 1-bit input: optional; required when SRC_INPUT_REG = 1
.src_in (ant_dout0 ) // 1-bit input: Input signal to be synchronized to dest_clk domain.
);
xpm_cdc_single u_cdc_ant_dout1
(
.dest_out (ant_dout1_cdc ), // 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
.dest_clk (clk_96m ), // 1-bit input: Clock signal for the destination clock domain.
.src_clk (ant_cout ), // 1-bit input: optional; required when SRC_INPUT_REG = 1
.src_in (ant_dout1 ) // 1-bit input: Input signal to be synchronized to dest_clk domain.
);
////////////////////////////////////////////////////////////////////////////////
//////////////////////////// RF Synthesizer Control ////////////////////////////
////////////////////////////////////////////////////////////////////////////////
ant_rf_ctrl u_ant_rf_ctrl
(
.clk_48m (clk_48m ),
.clk_96m (clk_96m ),
.clk_32m (clk_32m ),
.clk_19p2m (clk_19p2m ),
.sys_rst (ant_rst ),
.clk_48m (clk_48m ), // input clk_48m
.clk_96m (clk_96m ), // input clk_96m
.clk_32m (clk_32m ), // input clk_32m
.clk_19p2m (clk_19p2m ), // input clk_19p2m
.sys_rst (ant_rst ), // input sys_rst
.ant_clk (ant_clk ),
.ant_en (ant_en ),
.ant_data (ant_data ),
.ant_tr (ant_tr ),
.ant_dary (ant_dary ),
.ant_dout (ant_dout ),
.ant_clk (rf_clk ), // output ant_clk
.ant_en (rf_en ), // output ant_en
.ant_data (rf_data ), // output ant_data
.ant_tr (rf_tr ), // output ant_tr
.ant_dary (rf_dary ), // output ant_dary
.ant_dout (rf_dout ), // input ant_dout
.rf_standby (rf_standby ),
.rf_sw_pll (rf_sw_pll ),
.rf_t (rf_t ),
.rf_r (rf_r ),
.rf_sw_bpf (rf_sw_bpf ),
.rf_sclk1 (rf_sclk1 ),
.rf_sdio1 (rf_sdio1 ),
.rf_cs1 (rf_cs1 ),
.rf_ld1 (rf_ld1 ),
.rf_sclk2 (rf_sclk2 ),
.rf_sdio2 (rf_sdio2 ),
.rf_cs2 (rf_cs2 ),
.rf_ld2 (rf_ld2 ),
.rf_sclk3 (rf_sclk3 ),
.rf_sdio3 (rf_sdio3 ),
.rf_cs3 (rf_cs3 ),
.rf_ld3 (rf_ld3 ),
.rf_tmgc_16 (rf_tmgc_16 ),
.rf_tmgc_8 (rf_tmgc_8 ),
.rf_tmgc_4 (rf_tmgc_4 ),
.rf_tmgc_2 (rf_tmgc_2 ),
.rf_tmgc_1 (rf_tmgc_1 ),
.rf_rmgc_16 (rf_rmgc_16 ),
.rf_rmgc_8 (rf_rmgc_8 ),
.rf_rmgc_4 (rf_rmgc_4 ),
.rf_rmgc_2 (rf_rmgc_2 ),
.rf_rmgc_1 (rf_rmgc_1 ),
.rf_enable (rf_enable ),
.rf_sc (rf_sc ),
.rf_sd (rf_sd ),
.rf_endsyn (rf_endsyn ),
.rf_sdout (rf_sdout ),
.rf_dq_wd (rf_dq_wd ),
.rf_sw_rx (rf_sw_rx )
.rf_standby (rf_standby ), // output rf_standby
.rf_sw_pll (rf_sw_pll ), // output rf_sw_pll
.rf_t (rf_t ), // output rf_t
.rf_r (rf_r ), // output rf_r
.rf_sw_bpf (rf_sw_bpf ), // output rf_sw_bpf
.rf_sclk1 (rf_sclk1 ), // output rf_sclk1
.rf_sdio1 (rf_sdio1 ), // output rf_sdio1
.rf_cs1 (rf_cs1 ), // output rf_cs1
.rf_ld1 (rf_ld1 ), // input rf_ld1
.rf_sclk2 (rf_sclk2 ), // output rf_sclk2
.rf_sdio2 (rf_sdio2 ), // output rf_sdio2
.rf_cs2 (rf_cs2 ), // output rf_cs2
.rf_ld2 (rf_ld2 ), // input rf_ld2
.rf_sclk3 (rf_sclk3 ), // output rf_sclk3
.rf_sdio3 (rf_sdio3 ), // output rf_sdio3
.rf_cs3 (rf_cs3 ), // output rf_cs3
.rf_ld3 (rf_ld3 ), // input rf_ld3
.rf_tmgc_16 (rf_tmgc_16 ), // output rf_tmgc_16
.rf_tmgc_8 (rf_tmgc_8 ), // output rf_tmgc_8
.rf_tmgc_4 (rf_tmgc_4 ), // output rf_tmgc_4
.rf_tmgc_2 (rf_tmgc_2 ), // output rf_tmgc_2
.rf_tmgc_1 (rf_tmgc_1 ), // output rf_tmgc_1
.rf_rmgc_16 (rf_rmgc_16 ), // output rf_rmgc_16
.rf_rmgc_8 (rf_rmgc_8 ), // output rf_rmgc_8
.rf_rmgc_4 (rf_rmgc_4 ), // output rf_rmgc_4
.rf_rmgc_2 (rf_rmgc_2 ), // output rf_rmgc_2
.rf_rmgc_1 (rf_rmgc_1 ), // output rf_rmgc_1
.rf_enable (rf_enable ), // output rf_enable
.rf_sc (rf_sc ), // output rf_sc
.rf_sd (rf_sd ), // output rf_sd
.rf_endsyn (rf_endsyn ), // output rf_endsyn
.rf_sdout (rf_sdout ), // input rf_sdout
.rf_dq_wd (rf_dq_wd ), // inout rf_dq_wd
.rf_sw_rx (rf_sw_rx ) // output rf_sw_rx
);
@@ -550,17 +580,9 @@ wire weight_stream_data ;
wire [11:0] rx_data;
assign ant_cin = clk_96m;
assign weight_stream_data = ant_dout1_cdc;
assign ant_din0 = accor_stream_data;
xpm_cdc_single u_cdc_ant_dout
(
.dest_out (weight_stream_data ), // 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
.dest_clk (clk_96m ), // 1-bit input: Clock signal for the destination clock domain.
.src_clk (ant_cout ), // 1-bit input: optional; required when SRC_INPUT_REG = 1
.src_in (ant_dout1 ) // 1-bit input: Input signal to be synchronized to dest_clk domain.
);
ad9361_rx_map_cmos_dual u_ad9361_1_rx_map
(
.clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in
projects/datalink_814/dl814_k7/rtl/transmitter/GMSK_send.v
+1 -1
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@@ -197,7 +197,7 @@ module GMSK_send(
.clk ( clk_48M) ,
.rst ( rst ) ,
.Phase_addr ( phase_addr_12M[17:2]) ,
.Phase_addr ( phase_addr_12M[17:3]) ,
.Cos_Wave ( gmsk_send12M_I[17:0] ),
.Sin_Wave ( gmsk_send12M_Q[17:0] )
);
projects/datalink_814/dl814_k7/rtl/tx_pre_process.v
+2 -2
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@@ -114,8 +114,8 @@ always @(posedge clk) begin
else begin
tx_ch1_i_buf <= tx_data_ch1_i;
tx_ch1_q_buf <= tx_data_ch1_q;
tx_ch2_i_buf <= tx_data_ch1_i;
tx_ch2_q_buf <= tx_data_ch1_q;
tx_ch2_i_buf <= tx_data_ch2_i;
tx_ch2_q_buf <= tx_data_ch2_q;
end
end