Archived
update dl814_k7_coarse
This commit is contained in:
@@ -1,4 +1,3 @@
|
||||
set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[8]/C}] -to [get_pins u_ad9361_phase_cal/ad9361_recal_d1_reg/D]
|
||||
set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[10]/C}] -to [get_pins u_ad9361_phase_cal/ad9361_1_cal_start_d1_reg/D]
|
||||
set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[7]/C}] -to [get_pins u_tx_pre_process/ad9361_tx_switch_d1_reg/D]
|
||||
set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[9]/C}] -to [get_pins u_ad9361_phase_cal/ad9361_2_cal_start_d1_reg/D]
|
||||
-70
@@ -1,70 +0,0 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||
// IP Revision: 3
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
COSLUT_10_16bit your_instance_name (
|
||||
.clka(clka), // input wire clka
|
||||
.addra(addra), // input wire [12 : 0] addra
|
||||
.douta(douta), // output wire [17 : 0] douta
|
||||
.clkb(clkb), // input wire clkb
|
||||
.addrb(addrb), // input wire [12 : 0] addrb
|
||||
.doutb(doutb) // output wire [17 : 0] doutb
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file COSLUT_10_16bit.v when simulating
|
||||
// the core, COSLUT_10_16bit. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
-85
@@ -1,85 +0,0 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||
-- IP Revision: 3
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT COSLUT_10_16bit
|
||||
PORT (
|
||||
clka : IN STD_LOGIC;
|
||||
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
douta : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||||
clkb : IN STD_LOGIC;
|
||||
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
doutb : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : COSLUT_10_16bit
|
||||
PORT MAP (
|
||||
clka => clka,
|
||||
addra => addra,
|
||||
douta => douta,
|
||||
clkb => clkb,
|
||||
addrb => addrb,
|
||||
doutb => doutb
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file COSLUT_10_16bit.vhd when simulating
|
||||
-- the core, COSLUT_10_16bit. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
-2445
File diff suppressed because it is too large
Load Diff
-2784
File diff suppressed because it is too large
Load Diff
-35
@@ -1,35 +0,0 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:34:22 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_stub.vhdl
|
||||
-- Design : COSLUT_10_16bit
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity COSLUT_10_16bit is
|
||||
Port (
|
||||
clka : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
|
||||
douta : out STD_LOGIC_VECTOR ( 17 downto 0 );
|
||||
clkb : in STD_LOGIC;
|
||||
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
|
||||
doutb : out STD_LOGIC_VECTOR ( 17 downto 0 )
|
||||
);
|
||||
|
||||
end COSLUT_10_16bit;
|
||||
|
||||
architecture stub of COSLUT_10_16bit is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clka,addra[12:0],douta[17:0],clkb,addrb[12:0],doutb[17:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
-221
@@ -1,221 +0,0 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||
// IP Revision: 3
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module COSLUT_10_16bit (
|
||||
clka,
|
||||
addra,
|
||||
douta,
|
||||
clkb,
|
||||
addrb,
|
||||
doutb
|
||||
);
|
||||
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
|
||||
input wire clka;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
|
||||
input wire [12 : 0] addra;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
|
||||
output wire [17 : 0] douta;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
|
||||
input wire clkb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
|
||||
input wire [12 : 0] addrb;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
|
||||
output wire [17 : 0] doutb;
|
||||
|
||||
blk_mem_gen_v8_4_3 #(
|
||||
.C_FAMILY("kintex7"),
|
||||
.C_XDEVICEFAMILY("kintex7"),
|
||||
.C_ELABORATION_DIR("./"),
|
||||
.C_INTERFACE_TYPE(0),
|
||||
.C_AXI_TYPE(1),
|
||||
.C_AXI_SLAVE_TYPE(0),
|
||||
.C_USE_BRAM_BLOCK(0),
|
||||
.C_ENABLE_32BIT_ADDRESS(0),
|
||||
.C_CTRL_ECC_ALGO("NONE"),
|
||||
.C_HAS_AXI_ID(0),
|
||||
.C_AXI_ID_WIDTH(4),
|
||||
.C_MEM_TYPE(4),
|
||||
.C_BYTE_SIZE(9),
|
||||
.C_ALGORITHM(1),
|
||||
.C_PRIM_TYPE(1),
|
||||
.C_LOAD_INIT_FILE(1),
|
||||
.C_INIT_FILE_NAME("COSLUT_10_16bit.mif"),
|
||||
.C_INIT_FILE("COSLUT_10_16bit.mem"),
|
||||
.C_USE_DEFAULT_DATA(0),
|
||||
.C_DEFAULT_DATA("0"),
|
||||
.C_HAS_RSTA(0),
|
||||
.C_RST_PRIORITY_A("CE"),
|
||||
.C_RSTRAM_A(0),
|
||||
.C_INITA_VAL("0"),
|
||||
.C_HAS_ENA(0),
|
||||
.C_HAS_REGCEA(0),
|
||||
.C_USE_BYTE_WEA(0),
|
||||
.C_WEA_WIDTH(1),
|
||||
.C_WRITE_MODE_A("WRITE_FIRST"),
|
||||
.C_WRITE_WIDTH_A(18),
|
||||
.C_READ_WIDTH_A(18),
|
||||
.C_WRITE_DEPTH_A(8192),
|
||||
.C_READ_DEPTH_A(8192),
|
||||
.C_ADDRA_WIDTH(13),
|
||||
.C_HAS_RSTB(0),
|
||||
.C_RST_PRIORITY_B("CE"),
|
||||
.C_RSTRAM_B(0),
|
||||
.C_INITB_VAL("0"),
|
||||
.C_HAS_ENB(0),
|
||||
.C_HAS_REGCEB(0),
|
||||
.C_USE_BYTE_WEB(0),
|
||||
.C_WEB_WIDTH(1),
|
||||
.C_WRITE_MODE_B("WRITE_FIRST"),
|
||||
.C_WRITE_WIDTH_B(18),
|
||||
.C_READ_WIDTH_B(18),
|
||||
.C_WRITE_DEPTH_B(8192),
|
||||
.C_READ_DEPTH_B(8192),
|
||||
.C_ADDRB_WIDTH(13),
|
||||
.C_HAS_MEM_OUTPUT_REGS_A(1),
|
||||
.C_HAS_MEM_OUTPUT_REGS_B(1),
|
||||
.C_HAS_MUX_OUTPUT_REGS_A(1),
|
||||
.C_HAS_MUX_OUTPUT_REGS_B(1),
|
||||
.C_MUX_PIPELINE_STAGES(0),
|
||||
.C_HAS_SOFTECC_INPUT_REGS_A(0),
|
||||
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
|
||||
.C_USE_SOFTECC(0),
|
||||
.C_USE_ECC(0),
|
||||
.C_EN_ECC_PIPE(0),
|
||||
.C_READ_LATENCY_A(1),
|
||||
.C_READ_LATENCY_B(1),
|
||||
.C_HAS_INJECTERR(0),
|
||||
.C_SIM_COLLISION_CHECK("ALL"),
|
||||
.C_COMMON_CLK(0),
|
||||
.C_DISABLE_WARN_BHV_COLL(0),
|
||||
.C_EN_SLEEP_PIN(0),
|
||||
.C_USE_URAM(0),
|
||||
.C_EN_RDADDRA_CHG(0),
|
||||
.C_EN_RDADDRB_CHG(0),
|
||||
.C_EN_DEEPSLEEP_PIN(0),
|
||||
.C_EN_SHUTDOWN_PIN(0),
|
||||
.C_EN_SAFETY_CKT(0),
|
||||
.C_DISABLE_WARN_BHV_RANGE(0),
|
||||
.C_COUNT_36K_BRAM("4"),
|
||||
.C_COUNT_18K_BRAM("0"),
|
||||
.C_EST_POWER_SUMMARY("Estimated Power for IP : 9.414399 mW")
|
||||
) inst (
|
||||
.clka(clka),
|
||||
.rsta(1'D0),
|
||||
.ena(1'D0),
|
||||
.regcea(1'D0),
|
||||
.wea(1'B0),
|
||||
.addra(addra),
|
||||
.dina(18'B0),
|
||||
.douta(douta),
|
||||
.clkb(clkb),
|
||||
.rstb(1'D0),
|
||||
.enb(1'D0),
|
||||
.regceb(1'D0),
|
||||
.web(1'B0),
|
||||
.addrb(addrb),
|
||||
.dinb(18'B0),
|
||||
.doutb(doutb),
|
||||
.injectsbiterr(1'D0),
|
||||
.injectdbiterr(1'D0),
|
||||
.eccpipece(1'D0),
|
||||
.sbiterr(),
|
||||
.dbiterr(),
|
||||
.rdaddrecc(),
|
||||
.sleep(1'D0),
|
||||
.deepsleep(1'D0),
|
||||
.shutdown(1'D0),
|
||||
.rsta_busy(),
|
||||
.rstb_busy(),
|
||||
.s_aclk(1'H0),
|
||||
.s_aresetn(1'D0),
|
||||
.s_axi_awid(4'B0),
|
||||
.s_axi_awaddr(32'B0),
|
||||
.s_axi_awlen(8'B0),
|
||||
.s_axi_awsize(3'B0),
|
||||
.s_axi_awburst(2'B0),
|
||||
.s_axi_awvalid(1'D0),
|
||||
.s_axi_awready(),
|
||||
.s_axi_wdata(18'B0),
|
||||
.s_axi_wstrb(1'B0),
|
||||
.s_axi_wlast(1'D0),
|
||||
.s_axi_wvalid(1'D0),
|
||||
.s_axi_wready(),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(),
|
||||
.s_axi_bvalid(),
|
||||
.s_axi_bready(1'D0),
|
||||
.s_axi_arid(4'B0),
|
||||
.s_axi_araddr(32'B0),
|
||||
.s_axi_arlen(8'B0),
|
||||
.s_axi_arsize(3'B0),
|
||||
.s_axi_arburst(2'B0),
|
||||
.s_axi_arvalid(1'D0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'D0),
|
||||
.s_axi_injectsbiterr(1'D0),
|
||||
.s_axi_injectdbiterr(1'D0),
|
||||
.s_axi_sbiterr(),
|
||||
.s_axi_dbiterr(),
|
||||
.s_axi_rdaddrecc()
|
||||
);
|
||||
endmodule
|
||||
-70
@@ -1,70 +0,0 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:fir_compiler:7.2
|
||||
// IP Revision: 12
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
GaussFir_12m your_instance_name (
|
||||
.aclk(aclk), // input wire aclk
|
||||
.s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata(s_axis_data_tdata), // input wire [7 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata(m_axis_data_tdata) // output wire [15 : 0] m_axis_data_tdata
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file GaussFir_12m.v when simulating
|
||||
// the core, GaussFir_12m. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
-85
@@ -1,85 +0,0 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
|
||||
-- IP Revision: 12
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT GaussFir_12m
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
s_axis_data_tvalid : IN STD_LOGIC;
|
||||
s_axis_data_tready : OUT STD_LOGIC;
|
||||
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : GaussFir_12m
|
||||
PORT MAP (
|
||||
aclk => aclk,
|
||||
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||
s_axis_data_tready => s_axis_data_tready,
|
||||
s_axis_data_tdata => s_axis_data_tdata,
|
||||
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||
m_axis_data_tdata => m_axis_data_tdata
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file GaussFir_12m.vhd when simulating
|
||||
-- the core, GaussFir_12m. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
-2400
File diff suppressed because it is too large
Load Diff
-3344
File diff suppressed because it is too large
Load Diff
-26
@@ -1,26 +0,0 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:33:48 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_stub.v
|
||||
// Design : GaussFir_12m
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *)
|
||||
module GaussFir_12m(aclk, s_axis_data_tvalid, s_axis_data_tready,
|
||||
s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
|
||||
input aclk;
|
||||
input s_axis_data_tvalid;
|
||||
output s_axis_data_tready;
|
||||
input [7:0]s_axis_data_tdata;
|
||||
output m_axis_data_tvalid;
|
||||
output [15:0]m_axis_data_tdata;
|
||||
endmodule
|
||||
-35
@@ -1,35 +0,0 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:33:48 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_stub.vhdl
|
||||
-- Design : GaussFir_12m
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity GaussFir_12m is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_data_tvalid : in STD_LOGIC;
|
||||
s_axis_data_tready : out STD_LOGIC;
|
||||
s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
m_axis_data_tvalid : out STD_LOGIC;
|
||||
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
);
|
||||
|
||||
end GaussFir_12m;
|
||||
|
||||
architecture stub of GaussFir_12m is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
-261
@@ -1,261 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
-- Description:
|
||||
-- This is an example testbench for the FIR Compiler IP core.
|
||||
-- The testbench has been generated by Vivado to accompany the IP core
|
||||
-- instance you have generated.
|
||||
--
|
||||
-- This testbench is for demonstration purposes only. See note below for
|
||||
-- instructions on how to use it with your core.
|
||||
--
|
||||
-- See the FIR Compiler product guide for further information
|
||||
-- about this core.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Using this testbench
|
||||
--
|
||||
-- This testbench instantiates your generated FIR Compiler core
|
||||
-- instance named "GaussFir_12m".
|
||||
--
|
||||
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
|
||||
-- documentation for details.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity tb_GaussFir_12m is
|
||||
end tb_GaussFir_12m;
|
||||
|
||||
architecture tb of tb_GaussFir_12m is
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Timing constants
|
||||
-----------------------------------------------------------------------
|
||||
constant CLOCK_PERIOD : time := 100 ns;
|
||||
constant T_HOLD : time := 10 ns;
|
||||
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- DUT signals
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- General signals
|
||||
signal aclk : std_logic := '0'; -- the master clock
|
||||
|
||||
-- Data slave channel signals
|
||||
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
|
||||
signal s_axis_data_tready : std_logic := '1'; -- slave is ready
|
||||
signal s_axis_data_tdata : std_logic_vector(7 downto 0) := (others => '0'); -- data payload
|
||||
|
||||
-- Data master channel signals
|
||||
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
|
||||
signal m_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Aliases for AXI channel TDATA and TUSER fields
|
||||
-- These are a convenience for viewing data in a simulator waveform viewer.
|
||||
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
|
||||
-- to prevent the simulator optimizing away these signals.
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- Data slave channel alias signals
|
||||
signal s_axis_data_tdata_data : std_logic_vector(1 downto 0) := (others => '0');
|
||||
|
||||
-- Data master channel alias signals
|
||||
signal m_axis_data_tdata_data : std_logic_vector(14 downto 0) := (others => '0');
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Instantiate the DUT
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
dut : entity work.GaussFir_12m
|
||||
port map (
|
||||
aclk => aclk,
|
||||
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||
s_axis_data_tready => s_axis_data_tready,
|
||||
s_axis_data_tdata => s_axis_data_tdata,
|
||||
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||
m_axis_data_tdata => m_axis_data_tdata
|
||||
);
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Generate clock
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
clock_gen : process
|
||||
begin
|
||||
aclk <= '0';
|
||||
wait for CLOCK_PERIOD;
|
||||
loop
|
||||
aclk <= '0';
|
||||
wait for CLOCK_PERIOD/2;
|
||||
aclk <= '1';
|
||||
wait for CLOCK_PERIOD/2;
|
||||
end loop;
|
||||
end process clock_gen;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Generate inputs
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
stimuli : process
|
||||
|
||||
-- Procedure to drive a number of input samples with specific data
|
||||
-- data is the data value to drive on the tdata signal
|
||||
-- samples is the number of zero-data input samples to drive
|
||||
procedure drive_data ( data : std_logic_vector(7 downto 0);
|
||||
samples : natural := 1 ) is
|
||||
variable ip_count : integer := 0;
|
||||
begin
|
||||
ip_count := 0;
|
||||
loop
|
||||
s_axis_data_tvalid <= '1';
|
||||
s_axis_data_tdata <= data;
|
||||
loop
|
||||
wait until rising_edge(aclk);
|
||||
exit when s_axis_data_tready = '1';
|
||||
end loop;
|
||||
ip_count := ip_count + 1;
|
||||
wait for T_HOLD;
|
||||
-- Input rate is 1 input each 4 clock cycles: drive valid inputs at this rate
|
||||
s_axis_data_tvalid <= '0';
|
||||
wait for CLOCK_PERIOD * 3;
|
||||
exit when ip_count >= samples;
|
||||
end loop;
|
||||
end procedure drive_data;
|
||||
|
||||
-- Procedure to drive a number of zero-data input samples
|
||||
-- samples is the number of zero-data input samples to drive
|
||||
procedure drive_zeros ( samples : natural := 1 ) is
|
||||
begin
|
||||
drive_data((others => '0'), samples);
|
||||
end procedure drive_zeros;
|
||||
|
||||
-- Procedure to drive an impulse and let the impulse response emerge on the data master channel
|
||||
-- samples is the number of input samples to drive; default is enough for impulse response output to emerge
|
||||
procedure drive_impulse ( samples : natural := 27 ) is
|
||||
variable impulse : std_logic_vector(7 downto 0);
|
||||
begin
|
||||
impulse := (others => '0'); -- initialize unused bits to zero
|
||||
impulse(1 downto 0) := "01";
|
||||
drive_data(impulse);
|
||||
if samples > 1 then
|
||||
drive_zeros(samples-1);
|
||||
end if;
|
||||
end procedure drive_impulse;
|
||||
|
||||
begin
|
||||
|
||||
-- Drive inputs T_HOLD time after rising edge of clock
|
||||
wait until rising_edge(aclk);
|
||||
wait for T_HOLD;
|
||||
|
||||
-- Drive a single impulse and let the impulse response emerge
|
||||
drive_impulse;
|
||||
|
||||
-- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
|
||||
drive_impulse(2); -- start of impulse; data is now zero
|
||||
s_axis_data_tvalid <= '0';
|
||||
wait for CLOCK_PERIOD * 20; -- provide no data for 5 input samples worth
|
||||
drive_zeros(2); -- 2 normal input samples
|
||||
s_axis_data_tvalid <= '1';
|
||||
wait for CLOCK_PERIOD * 20; -- provide data as fast as the core can accept it for 5 input samples worth
|
||||
drive_zeros(18); -- back to normal operation
|
||||
|
||||
-- End of test
|
||||
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
|
||||
wait;
|
||||
|
||||
end process stimuli;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Check outputs
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
check_outputs : process
|
||||
variable check_ok : boolean := true;
|
||||
begin
|
||||
|
||||
-- Check outputs T_STROBE time after rising edge of clock
|
||||
wait until rising_edge(aclk);
|
||||
wait for T_STROBE;
|
||||
|
||||
-- Do not check the output payload values, as this requires the behavioral model
|
||||
-- which would make this demonstration testbench unwieldy.
|
||||
-- Instead, check the protocol of the master DATA channel:
|
||||
-- check that the payload is valid (not X) when TVALID is high
|
||||
|
||||
if m_axis_data_tvalid = '1' then
|
||||
if is_x(m_axis_data_tdata) then
|
||||
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
|
||||
check_ok := false;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
assert check_ok
|
||||
report "ERROR: terminating test with failures." severity failure;
|
||||
|
||||
end process check_outputs;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- Data slave channel alias signals
|
||||
s_axis_data_tdata_data <= s_axis_data_tdata(1 downto 0);
|
||||
|
||||
-- Data master channel alias signals: update these only when they are valid
|
||||
m_axis_data_tdata_data <= m_axis_data_tdata(14 downto 0) when m_axis_data_tvalid = '1';
|
||||
|
||||
end tb;
|
||||
-281
@@ -1,281 +0,0 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
|
||||
-- IP Revision: 12
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY fir_compiler_v7_2_12;
|
||||
USE fir_compiler_v7_2_12.fir_compiler_v7_2_12;
|
||||
|
||||
ENTITY GaussFir_12m IS
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
s_axis_data_tvalid : IN STD_LOGIC;
|
||||
s_axis_data_tready : OUT STD_LOGIC;
|
||||
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
);
|
||||
END GaussFir_12m;
|
||||
|
||||
ARCHITECTURE GaussFir_12m_arch OF GaussFir_12m IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF GaussFir_12m_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT fir_compiler_v7_2_12 IS
|
||||
GENERIC (
|
||||
C_XDEVICEFAMILY : STRING;
|
||||
C_ELABORATION_DIR : STRING;
|
||||
C_COMPONENT_NAME : STRING;
|
||||
C_COEF_FILE : STRING;
|
||||
C_COEF_FILE_LINES : INTEGER;
|
||||
C_FILTER_TYPE : INTEGER;
|
||||
C_INTERP_RATE : INTEGER;
|
||||
C_DECIM_RATE : INTEGER;
|
||||
C_ZERO_PACKING_FACTOR : INTEGER;
|
||||
C_SYMMETRY : INTEGER;
|
||||
C_NUM_FILTS : INTEGER;
|
||||
C_NUM_TAPS : INTEGER;
|
||||
C_NUM_CHANNELS : INTEGER;
|
||||
C_CHANNEL_PATTERN : STRING;
|
||||
C_ROUND_MODE : INTEGER;
|
||||
C_COEF_RELOAD : INTEGER;
|
||||
C_NUM_RELOAD_SLOTS : INTEGER;
|
||||
C_COL_MODE : INTEGER;
|
||||
C_COL_PIPE_LEN : INTEGER;
|
||||
C_COL_CONFIG : STRING;
|
||||
C_OPTIMIZATION : INTEGER;
|
||||
C_DATA_PATH_WIDTHS : STRING;
|
||||
C_DATA_IP_PATH_WIDTHS : STRING;
|
||||
C_DATA_PX_PATH_WIDTHS : STRING;
|
||||
C_DATA_WIDTH : INTEGER;
|
||||
C_COEF_PATH_WIDTHS : STRING;
|
||||
C_COEF_WIDTH : INTEGER;
|
||||
C_DATA_PATH_SRC : STRING;
|
||||
C_COEF_PATH_SRC : STRING;
|
||||
C_PX_PATH_SRC : STRING;
|
||||
C_DATA_PATH_SIGN : STRING;
|
||||
C_COEF_PATH_SIGN : STRING;
|
||||
C_ACCUM_PATH_WIDTHS : STRING;
|
||||
C_OUTPUT_WIDTH : INTEGER;
|
||||
C_OUTPUT_PATH_WIDTHS : STRING;
|
||||
C_ACCUM_OP_PATH_WIDTHS : STRING;
|
||||
C_EXT_MULT_CNFG : STRING;
|
||||
C_DATA_PATH_PSAMP_SRC : STRING;
|
||||
C_OP_PATH_PSAMP_SRC : STRING;
|
||||
C_NUM_MADDS : INTEGER;
|
||||
C_OPT_MADDS : STRING;
|
||||
C_OVERSAMPLING_RATE : INTEGER;
|
||||
C_INPUT_RATE : INTEGER;
|
||||
C_OUTPUT_RATE : INTEGER;
|
||||
C_DATA_MEMTYPE : INTEGER;
|
||||
C_COEF_MEMTYPE : INTEGER;
|
||||
C_IPBUFF_MEMTYPE : INTEGER;
|
||||
C_OPBUFF_MEMTYPE : INTEGER;
|
||||
C_DATAPATH_MEMTYPE : INTEGER;
|
||||
C_MEM_ARRANGEMENT : INTEGER;
|
||||
C_DATA_MEM_PACKING : INTEGER;
|
||||
C_COEF_MEM_PACKING : INTEGER;
|
||||
C_FILTS_PACKED : INTEGER;
|
||||
C_LATENCY : INTEGER;
|
||||
C_HAS_ARESETn : INTEGER;
|
||||
C_HAS_ACLKEN : INTEGER;
|
||||
C_DATA_HAS_TLAST : INTEGER;
|
||||
C_S_DATA_HAS_FIFO : INTEGER;
|
||||
C_S_DATA_HAS_TUSER : INTEGER;
|
||||
C_S_DATA_TDATA_WIDTH : INTEGER;
|
||||
C_S_DATA_TUSER_WIDTH : INTEGER;
|
||||
C_M_DATA_HAS_TREADY : INTEGER;
|
||||
C_M_DATA_HAS_TUSER : INTEGER;
|
||||
C_M_DATA_TDATA_WIDTH : INTEGER;
|
||||
C_M_DATA_TUSER_WIDTH : INTEGER;
|
||||
C_HAS_CONFIG_CHANNEL : INTEGER;
|
||||
C_CONFIG_SYNC_MODE : INTEGER;
|
||||
C_CONFIG_PACKET_SIZE : INTEGER;
|
||||
C_CONFIG_TDATA_WIDTH : INTEGER;
|
||||
C_RELOAD_TDATA_WIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
aresetn : IN STD_LOGIC;
|
||||
aclk : IN STD_LOGIC;
|
||||
aclken : IN STD_LOGIC;
|
||||
s_axis_data_tvalid : IN STD_LOGIC;
|
||||
s_axis_data_tready : OUT STD_LOGIC;
|
||||
s_axis_data_tlast : IN STD_LOGIC;
|
||||
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axis_config_tvalid : IN STD_LOGIC;
|
||||
s_axis_config_tready : OUT STD_LOGIC;
|
||||
s_axis_config_tlast : IN STD_LOGIC;
|
||||
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_reload_tvalid : IN STD_LOGIC;
|
||||
s_axis_reload_tready : OUT STD_LOGIC;
|
||||
s_axis_reload_tlast : IN STD_LOGIC;
|
||||
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tready : IN STD_LOGIC;
|
||||
m_axis_data_tlast : OUT STD_LOGIC;
|
||||
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
event_s_data_tlast_missing : OUT STD_LOGIC;
|
||||
event_s_data_tlast_unexpected : OUT STD_LOGIC;
|
||||
event_s_data_chanid_incorrect : OUT STD_LOGIC;
|
||||
event_s_config_tlast_missing : OUT STD_LOGIC;
|
||||
event_s_config_tlast_unexpected : OUT STD_LOGIC;
|
||||
event_s_reload_tlast_missing : OUT STD_LOGIC;
|
||||
event_s_reload_tlast_unexpected : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT fir_compiler_v7_2_12;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
|
||||
BEGIN
|
||||
U0 : fir_compiler_v7_2_12
|
||||
GENERIC MAP (
|
||||
C_XDEVICEFAMILY => "kintex7",
|
||||
C_ELABORATION_DIR => "./",
|
||||
C_COMPONENT_NAME => "GaussFir_12m",
|
||||
C_COEF_FILE => "GaussFir_12m.mif",
|
||||
C_COEF_FILE_LINES => 20,
|
||||
C_FILTER_TYPE => 2,
|
||||
C_INTERP_RATE => 4,
|
||||
C_DECIM_RATE => 1,
|
||||
C_ZERO_PACKING_FACTOR => 1,
|
||||
C_SYMMETRY => 0,
|
||||
C_NUM_FILTS => 1,
|
||||
C_NUM_TAPS => 17,
|
||||
C_NUM_CHANNELS => 1,
|
||||
C_CHANNEL_PATTERN => "fixed",
|
||||
C_ROUND_MODE => 0,
|
||||
C_COEF_RELOAD => 0,
|
||||
C_NUM_RELOAD_SLOTS => 1,
|
||||
C_COL_MODE => 1,
|
||||
C_COL_PIPE_LEN => 4,
|
||||
C_COL_CONFIG => "5",
|
||||
C_OPTIMIZATION => 0,
|
||||
C_DATA_PATH_WIDTHS => "2",
|
||||
C_DATA_IP_PATH_WIDTHS => "2",
|
||||
C_DATA_PX_PATH_WIDTHS => "2",
|
||||
C_DATA_WIDTH => 2,
|
||||
C_COEF_PATH_WIDTHS => "14",
|
||||
C_COEF_WIDTH => 14,
|
||||
C_DATA_PATH_SRC => "0",
|
||||
C_COEF_PATH_SRC => "0",
|
||||
C_PX_PATH_SRC => "0",
|
||||
C_DATA_PATH_SIGN => "0",
|
||||
C_COEF_PATH_SIGN => "1",
|
||||
C_ACCUM_PATH_WIDTHS => "15",
|
||||
C_OUTPUT_WIDTH => 15,
|
||||
C_OUTPUT_PATH_WIDTHS => "15",
|
||||
C_ACCUM_OP_PATH_WIDTHS => "15",
|
||||
C_EXT_MULT_CNFG => "none",
|
||||
C_DATA_PATH_PSAMP_SRC => "0",
|
||||
C_OP_PATH_PSAMP_SRC => "0",
|
||||
C_NUM_MADDS => 5,
|
||||
C_OPT_MADDS => "none",
|
||||
C_OVERSAMPLING_RATE => 1,
|
||||
C_INPUT_RATE => 4,
|
||||
C_OUTPUT_RATE => 1,
|
||||
C_DATA_MEMTYPE => 0,
|
||||
C_COEF_MEMTYPE => 2,
|
||||
C_IPBUFF_MEMTYPE => 0,
|
||||
C_OPBUFF_MEMTYPE => 0,
|
||||
C_DATAPATH_MEMTYPE => 0,
|
||||
C_MEM_ARRANGEMENT => 2,
|
||||
C_DATA_MEM_PACKING => 0,
|
||||
C_COEF_MEM_PACKING => 0,
|
||||
C_FILTS_PACKED => 0,
|
||||
C_LATENCY => 11,
|
||||
C_HAS_ARESETn => 0,
|
||||
C_HAS_ACLKEN => 0,
|
||||
C_DATA_HAS_TLAST => 0,
|
||||
C_S_DATA_HAS_FIFO => 0,
|
||||
C_S_DATA_HAS_TUSER => 0,
|
||||
C_S_DATA_TDATA_WIDTH => 8,
|
||||
C_S_DATA_TUSER_WIDTH => 1,
|
||||
C_M_DATA_HAS_TREADY => 0,
|
||||
C_M_DATA_HAS_TUSER => 0,
|
||||
C_M_DATA_TDATA_WIDTH => 16,
|
||||
C_M_DATA_TUSER_WIDTH => 1,
|
||||
C_HAS_CONFIG_CHANNEL => 0,
|
||||
C_CONFIG_SYNC_MODE => 0,
|
||||
C_CONFIG_PACKET_SIZE => 0,
|
||||
C_CONFIG_TDATA_WIDTH => 1,
|
||||
C_RELOAD_TDATA_WIDTH => 1
|
||||
)
|
||||
PORT MAP (
|
||||
aresetn => '1',
|
||||
aclk => aclk,
|
||||
aclken => '1',
|
||||
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||
s_axis_data_tready => s_axis_data_tready,
|
||||
s_axis_data_tlast => '0',
|
||||
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_data_tdata => s_axis_data_tdata,
|
||||
s_axis_config_tvalid => '0',
|
||||
s_axis_config_tlast => '0',
|
||||
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_reload_tvalid => '0',
|
||||
s_axis_reload_tlast => '0',
|
||||
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||
m_axis_data_tready => '1',
|
||||
m_axis_data_tdata => m_axis_data_tdata
|
||||
);
|
||||
END GaussFir_12m_arch;
|
||||
-70
@@ -1,70 +0,0 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:fir_compiler:7.2
|
||||
// IP Revision: 12
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
GaussFir_1mp5 your_instance_name (
|
||||
.aclk(aclk), // input wire aclk
|
||||
.s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata(s_axis_data_tdata), // input wire [7 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata(m_axis_data_tdata) // output wire [15 : 0] m_axis_data_tdata
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file GaussFir_1mp5.v when simulating
|
||||
// the core, GaussFir_1mp5. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
-85
@@ -1,85 +0,0 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
|
||||
-- IP Revision: 12
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT GaussFir_1mp5
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
s_axis_data_tvalid : IN STD_LOGIC;
|
||||
s_axis_data_tready : OUT STD_LOGIC;
|
||||
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : GaussFir_1mp5
|
||||
PORT MAP (
|
||||
aclk => aclk,
|
||||
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||
s_axis_data_tready => s_axis_data_tready,
|
||||
s_axis_data_tdata => s_axis_data_tdata,
|
||||
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||
m_axis_data_tdata => m_axis_data_tdata
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file GaussFir_1mp5.vhd when simulating
|
||||
-- the core, GaussFir_1mp5. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
-2607
File diff suppressed because it is too large
Load Diff
-3562
File diff suppressed because it is too large
Load Diff
-26
@@ -1,26 +0,0 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:33:47 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_stub.v
|
||||
// Design : GaussFir_1mp5
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *)
|
||||
module GaussFir_1mp5(aclk, s_axis_data_tvalid, s_axis_data_tready,
|
||||
s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
|
||||
input aclk;
|
||||
input s_axis_data_tvalid;
|
||||
output s_axis_data_tready;
|
||||
input [7:0]s_axis_data_tdata;
|
||||
output m_axis_data_tvalid;
|
||||
output [15:0]m_axis_data_tdata;
|
||||
endmodule
|
||||
-35
@@ -1,35 +0,0 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:33:47 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_stub.vhdl
|
||||
-- Design : GaussFir_1mp5
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity GaussFir_1mp5 is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_data_tvalid : in STD_LOGIC;
|
||||
s_axis_data_tready : out STD_LOGIC;
|
||||
s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
m_axis_data_tvalid : out STD_LOGIC;
|
||||
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
);
|
||||
|
||||
end GaussFir_1mp5;
|
||||
|
||||
architecture stub of GaussFir_1mp5 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
-261
@@ -1,261 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
-- Description:
|
||||
-- This is an example testbench for the FIR Compiler IP core.
|
||||
-- The testbench has been generated by Vivado to accompany the IP core
|
||||
-- instance you have generated.
|
||||
--
|
||||
-- This testbench is for demonstration purposes only. See note below for
|
||||
-- instructions on how to use it with your core.
|
||||
--
|
||||
-- See the FIR Compiler product guide for further information
|
||||
-- about this core.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Using this testbench
|
||||
--
|
||||
-- This testbench instantiates your generated FIR Compiler core
|
||||
-- instance named "GaussFir_1mp5".
|
||||
--
|
||||
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
|
||||
-- documentation for details.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity tb_GaussFir_1mp5 is
|
||||
end tb_GaussFir_1mp5;
|
||||
|
||||
architecture tb of tb_GaussFir_1mp5 is
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Timing constants
|
||||
-----------------------------------------------------------------------
|
||||
constant CLOCK_PERIOD : time := 100 ns;
|
||||
constant T_HOLD : time := 10 ns;
|
||||
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- DUT signals
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- General signals
|
||||
signal aclk : std_logic := '0'; -- the master clock
|
||||
|
||||
-- Data slave channel signals
|
||||
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
|
||||
signal s_axis_data_tready : std_logic := '1'; -- slave is ready
|
||||
signal s_axis_data_tdata : std_logic_vector(7 downto 0) := (others => '0'); -- data payload
|
||||
|
||||
-- Data master channel signals
|
||||
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
|
||||
signal m_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Aliases for AXI channel TDATA and TUSER fields
|
||||
-- These are a convenience for viewing data in a simulator waveform viewer.
|
||||
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
|
||||
-- to prevent the simulator optimizing away these signals.
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- Data slave channel alias signals
|
||||
signal s_axis_data_tdata_data : std_logic_vector(1 downto 0) := (others => '0');
|
||||
|
||||
-- Data master channel alias signals
|
||||
signal m_axis_data_tdata_data : std_logic_vector(12 downto 0) := (others => '0');
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Instantiate the DUT
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
dut : entity work.GaussFir_1mp5
|
||||
port map (
|
||||
aclk => aclk,
|
||||
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||
s_axis_data_tready => s_axis_data_tready,
|
||||
s_axis_data_tdata => s_axis_data_tdata,
|
||||
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||
m_axis_data_tdata => m_axis_data_tdata
|
||||
);
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Generate clock
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
clock_gen : process
|
||||
begin
|
||||
aclk <= '0';
|
||||
wait for CLOCK_PERIOD;
|
||||
loop
|
||||
aclk <= '0';
|
||||
wait for CLOCK_PERIOD/2;
|
||||
aclk <= '1';
|
||||
wait for CLOCK_PERIOD/2;
|
||||
end loop;
|
||||
end process clock_gen;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Generate inputs
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
stimuli : process
|
||||
|
||||
-- Procedure to drive a number of input samples with specific data
|
||||
-- data is the data value to drive on the tdata signal
|
||||
-- samples is the number of zero-data input samples to drive
|
||||
procedure drive_data ( data : std_logic_vector(7 downto 0);
|
||||
samples : natural := 1 ) is
|
||||
variable ip_count : integer := 0;
|
||||
begin
|
||||
ip_count := 0;
|
||||
loop
|
||||
s_axis_data_tvalid <= '1';
|
||||
s_axis_data_tdata <= data;
|
||||
loop
|
||||
wait until rising_edge(aclk);
|
||||
exit when s_axis_data_tready = '1';
|
||||
end loop;
|
||||
ip_count := ip_count + 1;
|
||||
wait for T_HOLD;
|
||||
-- Input rate is 1 input each 32 clock cycles: drive valid inputs at this rate
|
||||
s_axis_data_tvalid <= '0';
|
||||
wait for CLOCK_PERIOD * 31;
|
||||
exit when ip_count >= samples;
|
||||
end loop;
|
||||
end procedure drive_data;
|
||||
|
||||
-- Procedure to drive a number of zero-data input samples
|
||||
-- samples is the number of zero-data input samples to drive
|
||||
procedure drive_zeros ( samples : natural := 1 ) is
|
||||
begin
|
||||
drive_data((others => '0'), samples);
|
||||
end procedure drive_zeros;
|
||||
|
||||
-- Procedure to drive an impulse and let the impulse response emerge on the data master channel
|
||||
-- samples is the number of input samples to drive; default is enough for impulse response output to emerge
|
||||
procedure drive_impulse ( samples : natural := 165 ) is
|
||||
variable impulse : std_logic_vector(7 downto 0);
|
||||
begin
|
||||
impulse := (others => '0'); -- initialize unused bits to zero
|
||||
impulse(1 downto 0) := "01";
|
||||
drive_data(impulse);
|
||||
if samples > 1 then
|
||||
drive_zeros(samples-1);
|
||||
end if;
|
||||
end procedure drive_impulse;
|
||||
|
||||
begin
|
||||
|
||||
-- Drive inputs T_HOLD time after rising edge of clock
|
||||
wait until rising_edge(aclk);
|
||||
wait for T_HOLD;
|
||||
|
||||
-- Drive a single impulse and let the impulse response emerge
|
||||
drive_impulse;
|
||||
|
||||
-- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
|
||||
drive_impulse(2); -- start of impulse; data is now zero
|
||||
s_axis_data_tvalid <= '0';
|
||||
wait for CLOCK_PERIOD * 160; -- provide no data for 5 input samples worth
|
||||
drive_zeros(2); -- 2 normal input samples
|
||||
s_axis_data_tvalid <= '1';
|
||||
wait for CLOCK_PERIOD * 160; -- provide data as fast as the core can accept it for 5 input samples worth
|
||||
drive_zeros(156); -- back to normal operation
|
||||
|
||||
-- End of test
|
||||
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
|
||||
wait;
|
||||
|
||||
end process stimuli;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Check outputs
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
check_outputs : process
|
||||
variable check_ok : boolean := true;
|
||||
begin
|
||||
|
||||
-- Check outputs T_STROBE time after rising edge of clock
|
||||
wait until rising_edge(aclk);
|
||||
wait for T_STROBE;
|
||||
|
||||
-- Do not check the output payload values, as this requires the behavioral model
|
||||
-- which would make this demonstration testbench unwieldy.
|
||||
-- Instead, check the protocol of the master DATA channel:
|
||||
-- check that the payload is valid (not X) when TVALID is high
|
||||
|
||||
if m_axis_data_tvalid = '1' then
|
||||
if is_x(m_axis_data_tdata) then
|
||||
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
|
||||
check_ok := false;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
assert check_ok
|
||||
report "ERROR: terminating test with failures." severity failure;
|
||||
|
||||
end process check_outputs;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- Data slave channel alias signals
|
||||
s_axis_data_tdata_data <= s_axis_data_tdata(1 downto 0);
|
||||
|
||||
-- Data master channel alias signals: update these only when they are valid
|
||||
m_axis_data_tdata_data <= m_axis_data_tdata(12 downto 0) when m_axis_data_tvalid = '1';
|
||||
|
||||
end tb;
|
||||
-281
@@ -1,281 +0,0 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
|
||||
-- IP Revision: 12
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY fir_compiler_v7_2_12;
|
||||
USE fir_compiler_v7_2_12.fir_compiler_v7_2_12;
|
||||
|
||||
ENTITY GaussFir_1mp5 IS
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
s_axis_data_tvalid : IN STD_LOGIC;
|
||||
s_axis_data_tready : OUT STD_LOGIC;
|
||||
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
);
|
||||
END GaussFir_1mp5;
|
||||
|
||||
ARCHITECTURE GaussFir_1mp5_arch OF GaussFir_1mp5 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF GaussFir_1mp5_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT fir_compiler_v7_2_12 IS
|
||||
GENERIC (
|
||||
C_XDEVICEFAMILY : STRING;
|
||||
C_ELABORATION_DIR : STRING;
|
||||
C_COMPONENT_NAME : STRING;
|
||||
C_COEF_FILE : STRING;
|
||||
C_COEF_FILE_LINES : INTEGER;
|
||||
C_FILTER_TYPE : INTEGER;
|
||||
C_INTERP_RATE : INTEGER;
|
||||
C_DECIM_RATE : INTEGER;
|
||||
C_ZERO_PACKING_FACTOR : INTEGER;
|
||||
C_SYMMETRY : INTEGER;
|
||||
C_NUM_FILTS : INTEGER;
|
||||
C_NUM_TAPS : INTEGER;
|
||||
C_NUM_CHANNELS : INTEGER;
|
||||
C_CHANNEL_PATTERN : STRING;
|
||||
C_ROUND_MODE : INTEGER;
|
||||
C_COEF_RELOAD : INTEGER;
|
||||
C_NUM_RELOAD_SLOTS : INTEGER;
|
||||
C_COL_MODE : INTEGER;
|
||||
C_COL_PIPE_LEN : INTEGER;
|
||||
C_COL_CONFIG : STRING;
|
||||
C_OPTIMIZATION : INTEGER;
|
||||
C_DATA_PATH_WIDTHS : STRING;
|
||||
C_DATA_IP_PATH_WIDTHS : STRING;
|
||||
C_DATA_PX_PATH_WIDTHS : STRING;
|
||||
C_DATA_WIDTH : INTEGER;
|
||||
C_COEF_PATH_WIDTHS : STRING;
|
||||
C_COEF_WIDTH : INTEGER;
|
||||
C_DATA_PATH_SRC : STRING;
|
||||
C_COEF_PATH_SRC : STRING;
|
||||
C_PX_PATH_SRC : STRING;
|
||||
C_DATA_PATH_SIGN : STRING;
|
||||
C_COEF_PATH_SIGN : STRING;
|
||||
C_ACCUM_PATH_WIDTHS : STRING;
|
||||
C_OUTPUT_WIDTH : INTEGER;
|
||||
C_OUTPUT_PATH_WIDTHS : STRING;
|
||||
C_ACCUM_OP_PATH_WIDTHS : STRING;
|
||||
C_EXT_MULT_CNFG : STRING;
|
||||
C_DATA_PATH_PSAMP_SRC : STRING;
|
||||
C_OP_PATH_PSAMP_SRC : STRING;
|
||||
C_NUM_MADDS : INTEGER;
|
||||
C_OPT_MADDS : STRING;
|
||||
C_OVERSAMPLING_RATE : INTEGER;
|
||||
C_INPUT_RATE : INTEGER;
|
||||
C_OUTPUT_RATE : INTEGER;
|
||||
C_DATA_MEMTYPE : INTEGER;
|
||||
C_COEF_MEMTYPE : INTEGER;
|
||||
C_IPBUFF_MEMTYPE : INTEGER;
|
||||
C_OPBUFF_MEMTYPE : INTEGER;
|
||||
C_DATAPATH_MEMTYPE : INTEGER;
|
||||
C_MEM_ARRANGEMENT : INTEGER;
|
||||
C_DATA_MEM_PACKING : INTEGER;
|
||||
C_COEF_MEM_PACKING : INTEGER;
|
||||
C_FILTS_PACKED : INTEGER;
|
||||
C_LATENCY : INTEGER;
|
||||
C_HAS_ARESETn : INTEGER;
|
||||
C_HAS_ACLKEN : INTEGER;
|
||||
C_DATA_HAS_TLAST : INTEGER;
|
||||
C_S_DATA_HAS_FIFO : INTEGER;
|
||||
C_S_DATA_HAS_TUSER : INTEGER;
|
||||
C_S_DATA_TDATA_WIDTH : INTEGER;
|
||||
C_S_DATA_TUSER_WIDTH : INTEGER;
|
||||
C_M_DATA_HAS_TREADY : INTEGER;
|
||||
C_M_DATA_HAS_TUSER : INTEGER;
|
||||
C_M_DATA_TDATA_WIDTH : INTEGER;
|
||||
C_M_DATA_TUSER_WIDTH : INTEGER;
|
||||
C_HAS_CONFIG_CHANNEL : INTEGER;
|
||||
C_CONFIG_SYNC_MODE : INTEGER;
|
||||
C_CONFIG_PACKET_SIZE : INTEGER;
|
||||
C_CONFIG_TDATA_WIDTH : INTEGER;
|
||||
C_RELOAD_TDATA_WIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
aresetn : IN STD_LOGIC;
|
||||
aclk : IN STD_LOGIC;
|
||||
aclken : IN STD_LOGIC;
|
||||
s_axis_data_tvalid : IN STD_LOGIC;
|
||||
s_axis_data_tready : OUT STD_LOGIC;
|
||||
s_axis_data_tlast : IN STD_LOGIC;
|
||||
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axis_config_tvalid : IN STD_LOGIC;
|
||||
s_axis_config_tready : OUT STD_LOGIC;
|
||||
s_axis_config_tlast : IN STD_LOGIC;
|
||||
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_reload_tvalid : IN STD_LOGIC;
|
||||
s_axis_reload_tready : OUT STD_LOGIC;
|
||||
s_axis_reload_tlast : IN STD_LOGIC;
|
||||
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tready : IN STD_LOGIC;
|
||||
m_axis_data_tlast : OUT STD_LOGIC;
|
||||
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
event_s_data_tlast_missing : OUT STD_LOGIC;
|
||||
event_s_data_tlast_unexpected : OUT STD_LOGIC;
|
||||
event_s_data_chanid_incorrect : OUT STD_LOGIC;
|
||||
event_s_config_tlast_missing : OUT STD_LOGIC;
|
||||
event_s_config_tlast_unexpected : OUT STD_LOGIC;
|
||||
event_s_reload_tlast_missing : OUT STD_LOGIC;
|
||||
event_s_reload_tlast_unexpected : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT fir_compiler_v7_2_12;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
|
||||
BEGIN
|
||||
U0 : fir_compiler_v7_2_12
|
||||
GENERIC MAP (
|
||||
C_XDEVICEFAMILY => "kintex7",
|
||||
C_ELABORATION_DIR => "./",
|
||||
C_COMPONENT_NAME => "GaussFir_1mp5",
|
||||
C_COEF_FILE => "GaussFir_1mp5.mif",
|
||||
C_COEF_FILE_LINES => 160,
|
||||
C_FILTER_TYPE => 2,
|
||||
C_INTERP_RATE => 32,
|
||||
C_DECIM_RATE => 1,
|
||||
C_ZERO_PACKING_FACTOR => 1,
|
||||
C_SYMMETRY => 0,
|
||||
C_NUM_FILTS => 1,
|
||||
C_NUM_TAPS => 129,
|
||||
C_NUM_CHANNELS => 1,
|
||||
C_CHANNEL_PATTERN => "fixed",
|
||||
C_ROUND_MODE => 0,
|
||||
C_COEF_RELOAD => 0,
|
||||
C_NUM_RELOAD_SLOTS => 1,
|
||||
C_COL_MODE => 1,
|
||||
C_COL_PIPE_LEN => 4,
|
||||
C_COL_CONFIG => "5",
|
||||
C_OPTIMIZATION => 0,
|
||||
C_DATA_PATH_WIDTHS => "2",
|
||||
C_DATA_IP_PATH_WIDTHS => "2",
|
||||
C_DATA_PX_PATH_WIDTHS => "2",
|
||||
C_DATA_WIDTH => 2,
|
||||
C_COEF_PATH_WIDTHS => "14",
|
||||
C_COEF_WIDTH => 14,
|
||||
C_DATA_PATH_SRC => "0",
|
||||
C_COEF_PATH_SRC => "0",
|
||||
C_PX_PATH_SRC => "0",
|
||||
C_DATA_PATH_SIGN => "0",
|
||||
C_COEF_PATH_SIGN => "1",
|
||||
C_ACCUM_PATH_WIDTHS => "13",
|
||||
C_OUTPUT_WIDTH => 13,
|
||||
C_OUTPUT_PATH_WIDTHS => "13",
|
||||
C_ACCUM_OP_PATH_WIDTHS => "13",
|
||||
C_EXT_MULT_CNFG => "none",
|
||||
C_DATA_PATH_PSAMP_SRC => "0",
|
||||
C_OP_PATH_PSAMP_SRC => "0",
|
||||
C_NUM_MADDS => 5,
|
||||
C_OPT_MADDS => "none",
|
||||
C_OVERSAMPLING_RATE => 1,
|
||||
C_INPUT_RATE => 32,
|
||||
C_OUTPUT_RATE => 1,
|
||||
C_DATA_MEMTYPE => 0,
|
||||
C_COEF_MEMTYPE => 2,
|
||||
C_IPBUFF_MEMTYPE => 0,
|
||||
C_OPBUFF_MEMTYPE => 0,
|
||||
C_DATAPATH_MEMTYPE => 0,
|
||||
C_MEM_ARRANGEMENT => 2,
|
||||
C_DATA_MEM_PACKING => 0,
|
||||
C_COEF_MEM_PACKING => 0,
|
||||
C_FILTS_PACKED => 0,
|
||||
C_LATENCY => 11,
|
||||
C_HAS_ARESETn => 0,
|
||||
C_HAS_ACLKEN => 0,
|
||||
C_DATA_HAS_TLAST => 0,
|
||||
C_S_DATA_HAS_FIFO => 0,
|
||||
C_S_DATA_HAS_TUSER => 0,
|
||||
C_S_DATA_TDATA_WIDTH => 8,
|
||||
C_S_DATA_TUSER_WIDTH => 1,
|
||||
C_M_DATA_HAS_TREADY => 0,
|
||||
C_M_DATA_HAS_TUSER => 0,
|
||||
C_M_DATA_TDATA_WIDTH => 16,
|
||||
C_M_DATA_TUSER_WIDTH => 1,
|
||||
C_HAS_CONFIG_CHANNEL => 0,
|
||||
C_CONFIG_SYNC_MODE => 0,
|
||||
C_CONFIG_PACKET_SIZE => 0,
|
||||
C_CONFIG_TDATA_WIDTH => 1,
|
||||
C_RELOAD_TDATA_WIDTH => 1
|
||||
)
|
||||
PORT MAP (
|
||||
aresetn => '1',
|
||||
aclk => aclk,
|
||||
aclken => '1',
|
||||
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||
s_axis_data_tready => s_axis_data_tready,
|
||||
s_axis_data_tlast => '0',
|
||||
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_data_tdata => s_axis_data_tdata,
|
||||
s_axis_config_tvalid => '0',
|
||||
s_axis_config_tlast => '0',
|
||||
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_reload_tvalid => '0',
|
||||
s_axis_reload_tlast => '0',
|
||||
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||
m_axis_data_tready => '1',
|
||||
m_axis_data_tdata => m_axis_data_tdata
|
||||
);
|
||||
END GaussFir_1mp5_arch;
|
||||
@@ -1,68 +0,0 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||
// IP Revision: 3
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
data_1p5m your_instance_name (
|
||||
.clka(clka), // input wire clka
|
||||
.ena(ena), // input wire ena
|
||||
.addra(addra), // input wire [10 : 0] addra
|
||||
.douta(douta) // output wire [0 : 0] douta
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file data_1p5m.v when simulating
|
||||
// the core, data_1p5m. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
@@ -1,81 +0,0 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||
-- IP Revision: 3
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT data_1p5m
|
||||
PORT (
|
||||
clka : IN STD_LOGIC;
|
||||
ena : IN STD_LOGIC;
|
||||
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
douta : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : data_1p5m
|
||||
PORT MAP (
|
||||
clka => clka,
|
||||
ena => ena,
|
||||
addra => addra,
|
||||
douta => douta
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file data_1p5m.vhd when simulating
|
||||
-- the core, data_1p5m. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
-734
@@ -1,734 +0,0 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:34:17 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_sim_netlist.v
|
||||
// Design : data_1p5m
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "data_1p5m,blk_mem_gen_v8_4_3,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
|
||||
(* NotValidForBitStream *)
|
||||
module data_1p5m
|
||||
(clka,
|
||||
ena,
|
||||
addra,
|
||||
douta);
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) input clka;
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [10:0]addra;
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [0:0]douta;
|
||||
|
||||
wire [10:0]addra;
|
||||
wire clka;
|
||||
wire [0:0]douta;
|
||||
wire ena;
|
||||
wire NLW_U0_dbiterr_UNCONNECTED;
|
||||
wire NLW_U0_rsta_busy_UNCONNECTED;
|
||||
wire NLW_U0_rstb_busy_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_arready_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_awready_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_rlast_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_wready_UNCONNECTED;
|
||||
wire NLW_U0_sbiterr_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_doutb_UNCONNECTED;
|
||||
wire [10:0]NLW_U0_rdaddrecc_UNCONNECTED;
|
||||
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
|
||||
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
|
||||
wire [10:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_s_axi_rdata_UNCONNECTED;
|
||||
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
|
||||
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
|
||||
|
||||
(* C_ADDRA_WIDTH = "11" *)
|
||||
(* C_ADDRB_WIDTH = "11" *)
|
||||
(* C_ALGORITHM = "1" *)
|
||||
(* C_AXI_ID_WIDTH = "4" *)
|
||||
(* C_AXI_SLAVE_TYPE = "0" *)
|
||||
(* C_AXI_TYPE = "1" *)
|
||||
(* C_BYTE_SIZE = "9" *)
|
||||
(* C_COMMON_CLK = "0" *)
|
||||
(* C_COUNT_18K_BRAM = "1" *)
|
||||
(* C_COUNT_36K_BRAM = "0" *)
|
||||
(* C_CTRL_ECC_ALGO = "NONE" *)
|
||||
(* C_DEFAULT_DATA = "0" *)
|
||||
(* C_DISABLE_WARN_BHV_COLL = "0" *)
|
||||
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
|
||||
(* C_ELABORATION_DIR = "./" *)
|
||||
(* C_ENABLE_32BIT_ADDRESS = "0" *)
|
||||
(* C_EN_DEEPSLEEP_PIN = "0" *)
|
||||
(* C_EN_ECC_PIPE = "0" *)
|
||||
(* C_EN_RDADDRA_CHG = "0" *)
|
||||
(* C_EN_RDADDRB_CHG = "0" *)
|
||||
(* C_EN_SAFETY_CKT = "0" *)
|
||||
(* C_EN_SHUTDOWN_PIN = "0" *)
|
||||
(* C_EN_SLEEP_PIN = "0" *)
|
||||
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 0.990811 mW" *)
|
||||
(* C_FAMILY = "kintex7" *)
|
||||
(* C_HAS_AXI_ID = "0" *)
|
||||
(* C_HAS_ENA = "1" *)
|
||||
(* C_HAS_ENB = "0" *)
|
||||
(* C_HAS_INJECTERR = "0" *)
|
||||
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
|
||||
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
|
||||
(* C_HAS_MUX_OUTPUT_REGS_A = "1" *)
|
||||
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
|
||||
(* C_HAS_REGCEA = "0" *)
|
||||
(* C_HAS_REGCEB = "0" *)
|
||||
(* C_HAS_RSTA = "0" *)
|
||||
(* C_HAS_RSTB = "0" *)
|
||||
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
|
||||
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
|
||||
(* C_INITA_VAL = "0" *)
|
||||
(* C_INITB_VAL = "0" *)
|
||||
(* C_INIT_FILE = "data_1p5m.mem" *)
|
||||
(* C_INIT_FILE_NAME = "data_1p5m.mif" *)
|
||||
(* C_INTERFACE_TYPE = "0" *)
|
||||
(* C_LOAD_INIT_FILE = "1" *)
|
||||
(* C_MEM_TYPE = "3" *)
|
||||
(* C_MUX_PIPELINE_STAGES = "0" *)
|
||||
(* C_PRIM_TYPE = "1" *)
|
||||
(* C_READ_DEPTH_A = "2048" *)
|
||||
(* C_READ_DEPTH_B = "2048" *)
|
||||
(* C_READ_LATENCY_A = "1" *)
|
||||
(* C_READ_LATENCY_B = "1" *)
|
||||
(* C_READ_WIDTH_A = "1" *)
|
||||
(* C_READ_WIDTH_B = "1" *)
|
||||
(* C_RSTRAM_A = "0" *)
|
||||
(* C_RSTRAM_B = "0" *)
|
||||
(* C_RST_PRIORITY_A = "CE" *)
|
||||
(* C_RST_PRIORITY_B = "CE" *)
|
||||
(* C_SIM_COLLISION_CHECK = "ALL" *)
|
||||
(* C_USE_BRAM_BLOCK = "0" *)
|
||||
(* C_USE_BYTE_WEA = "0" *)
|
||||
(* C_USE_BYTE_WEB = "0" *)
|
||||
(* C_USE_DEFAULT_DATA = "0" *)
|
||||
(* C_USE_ECC = "0" *)
|
||||
(* C_USE_SOFTECC = "0" *)
|
||||
(* C_USE_URAM = "0" *)
|
||||
(* C_WEA_WIDTH = "1" *)
|
||||
(* C_WEB_WIDTH = "1" *)
|
||||
(* C_WRITE_DEPTH_A = "2048" *)
|
||||
(* C_WRITE_DEPTH_B = "2048" *)
|
||||
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
|
||||
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
||||
(* C_WRITE_WIDTH_A = "1" *)
|
||||
(* C_WRITE_WIDTH_B = "1" *)
|
||||
(* C_XDEVICEFAMILY = "kintex7" *)
|
||||
(* downgradeipidentifiedwarnings = "yes" *)
|
||||
data_1p5m_blk_mem_gen_v8_4_3 U0
|
||||
(.addra(addra),
|
||||
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.clka(clka),
|
||||
.clkb(1'b0),
|
||||
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
|
||||
.deepsleep(1'b0),
|
||||
.dina(1'b0),
|
||||
.dinb(1'b0),
|
||||
.douta(douta),
|
||||
.doutb(NLW_U0_doutb_UNCONNECTED[0]),
|
||||
.eccpipece(1'b0),
|
||||
.ena(ena),
|
||||
.enb(1'b0),
|
||||
.injectdbiterr(1'b0),
|
||||
.injectsbiterr(1'b0),
|
||||
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[10:0]),
|
||||
.regcea(1'b0),
|
||||
.regceb(1'b0),
|
||||
.rsta(1'b0),
|
||||
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
|
||||
.rstb(1'b0),
|
||||
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
|
||||
.s_aclk(1'b0),
|
||||
.s_aresetn(1'b0),
|
||||
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_arburst({1'b0,1'b0}),
|
||||
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
|
||||
.s_axi_arsize({1'b0,1'b0,1'b0}),
|
||||
.s_axi_arvalid(1'b0),
|
||||
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_awburst({1'b0,1'b0}),
|
||||
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
|
||||
.s_axi_awsize({1'b0,1'b0,1'b0}),
|
||||
.s_axi_awvalid(1'b0),
|
||||
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
|
||||
.s_axi_bready(1'b0),
|
||||
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
|
||||
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
|
||||
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
|
||||
.s_axi_injectdbiterr(1'b0),
|
||||
.s_axi_injectsbiterr(1'b0),
|
||||
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[10:0]),
|
||||
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[0]),
|
||||
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
|
||||
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
|
||||
.s_axi_rready(1'b0),
|
||||
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
|
||||
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
|
||||
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
|
||||
.s_axi_wdata(1'b0),
|
||||
.s_axi_wlast(1'b0),
|
||||
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
|
||||
.s_axi_wstrb(1'b0),
|
||||
.s_axi_wvalid(1'b0),
|
||||
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
|
||||
.shutdown(1'b0),
|
||||
.sleep(1'b0),
|
||||
.wea(1'b0),
|
||||
.web(1'b0));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
|
||||
module data_1p5m_blk_mem_gen_generic_cstr
|
||||
(douta,
|
||||
clka,
|
||||
ena,
|
||||
addra);
|
||||
output [0:0]douta;
|
||||
input clka;
|
||||
input ena;
|
||||
input [10:0]addra;
|
||||
|
||||
wire [10:0]addra;
|
||||
wire clka;
|
||||
wire [0:0]douta;
|
||||
wire ena;
|
||||
wire ram_douta;
|
||||
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[0]
|
||||
(.C(clka),
|
||||
.CE(ena),
|
||||
.D(ram_douta),
|
||||
.Q(douta),
|
||||
.R(1'b0));
|
||||
data_1p5m_blk_mem_gen_prim_width \ramloop[0].ram.r
|
||||
(.DOADO(ram_douta),
|
||||
.addra(addra),
|
||||
.clka(clka),
|
||||
.ena(ena));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
|
||||
module data_1p5m_blk_mem_gen_prim_width
|
||||
(DOADO,
|
||||
clka,
|
||||
ena,
|
||||
addra);
|
||||
output [0:0]DOADO;
|
||||
input clka;
|
||||
input ena;
|
||||
input [10:0]addra;
|
||||
|
||||
wire [0:0]DOADO;
|
||||
wire [10:0]addra;
|
||||
wire clka;
|
||||
wire ena;
|
||||
|
||||
data_1p5m_blk_mem_gen_prim_wrapper_init \prim_init.ram
|
||||
(.DOADO(DOADO),
|
||||
.addra(addra),
|
||||
.clka(clka),
|
||||
.ena(ena));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
|
||||
module data_1p5m_blk_mem_gen_prim_wrapper_init
|
||||
(DOADO,
|
||||
clka,
|
||||
ena,
|
||||
addra);
|
||||
output [0:0]DOADO;
|
||||
input clka;
|
||||
input ena;
|
||||
input [10:0]addra;
|
||||
|
||||
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_10 ;
|
||||
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_11 ;
|
||||
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_12 ;
|
||||
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_13 ;
|
||||
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_14 ;
|
||||
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_33 ;
|
||||
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_8 ;
|
||||
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_9 ;
|
||||
wire [0:0]DOADO;
|
||||
wire [10:0]addra;
|
||||
wire clka;
|
||||
wire ena;
|
||||
wire [15:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
|
||||
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
|
||||
wire [1:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
|
||||
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
|
||||
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
RAMB18E1 #(
|
||||
.DOA_REG(1),
|
||||
.DOB_REG(0),
|
||||
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_00(256'h0101000001010101000101000001010100010100010101000101000100010001),
|
||||
.INIT_01(256'h0000010001000000010100000100010100000100010101000100000100000101),
|
||||
.INIT_02(256'h0001000000010001010000010101000100010100000000010100000001010001),
|
||||
.INIT_03(256'h0100000101000100010000010000000101010000000001000000000101000001),
|
||||
.INIT_04(256'h0001010101010000000001000100010100000001010000010001000101010000),
|
||||
.INIT_05(256'h0101010100010000000101000101010101000100010000010001010000000101),
|
||||
.INIT_06(256'h0101010100010100010001010001010000000001000001010100000000010101),
|
||||
.INIT_07(256'h0000010100010000000101010001000000000100010000000100010001000001),
|
||||
.INIT_08(256'h0101000101010101010000000000000001000000010001000001000100000100),
|
||||
.INIT_09(256'h0000010000000101000100010001000000000101000001010001010100010001),
|
||||
.INIT_0A(256'h0000000101000100000001000001000100000100000101010100010100000101),
|
||||
.INIT_0B(256'h0100010001000000010101000101010001010000010101010101000001010100),
|
||||
.INIT_0C(256'h0100010101010001000101010101000000010100010100000000000101010100),
|
||||
.INIT_0D(256'h0001010001010000000000010000010100000000010100010001000001010101),
|
||||
.INIT_0E(256'h0000010000010001000000000001000100000000010000000101000100000100),
|
||||
.INIT_0F(256'h0000010101010100000000000000010101010001000001000100010101010101),
|
||||
.INIT_10(256'h0101000100010001010100010101000101010000010101010000000001000000),
|
||||
.INIT_11(256'h0101010100000000000001000000010000000100000001000001000001000001),
|
||||
.INIT_12(256'h0000000101010101000001000100010100010000010000010100010101000101),
|
||||
.INIT_13(256'h0100000000000000000100000100010000010000000101010101000101000100),
|
||||
.INIT_14(256'h0101010101010100010001000100010001010100000100000101010101010001),
|
||||
.INIT_15(256'h0100010000010101000000010001000001000100000001010001010000010000),
|
||||
.INIT_16(256'h0100000001000101000101010100000100000101000101000101010000010001),
|
||||
.INIT_17(256'h0100010001000100000101000000010000000000000000010000010001010000),
|
||||
.INIT_18(256'h0000010100000100000101010101000000000101010101010001010100010100),
|
||||
.INIT_19(256'h0100000100010001000100010000010000000100000000010001010001010100),
|
||||
.INIT_1A(256'h0001010100010001000100000100000000010100010001010100010100010001),
|
||||
.INIT_1B(256'h0100010000000101010000010101010100000000010001000000010000000001),
|
||||
.INIT_1C(256'h0101000000010100000000010100010100000001000000000100000100010100),
|
||||
.INIT_1D(256'h0101010101000101000100000100000000000001010001000101010100000001),
|
||||
.INIT_1E(256'h0101010100010001010000010101000100000100000100000000000101000000),
|
||||
.INIT_1F(256'h0101010000000100000001010001010001010001000001000001000001000101),
|
||||
.INIT_20(256'h0101000100010000010001000101010100010000010001010101000100010001),
|
||||
.INIT_21(256'h0001000001000100010000010101000001000100010101010100010100000101),
|
||||
.INIT_22(256'h0101000100010101010101010001000100000100000001000000010101000100),
|
||||
.INIT_23(256'h0000000000010101010100010001010100010101010001000001010100000000),
|
||||
.INIT_24(256'h0100000000010000000100000100000101000100000100010001010000000001),
|
||||
.INIT_25(256'h0001010100000001010000010000000001010000000100000100000101010100),
|
||||
.INIT_26(256'h0001010101010000010101000001000000010001010101000000010000010100),
|
||||
.INIT_27(256'h0001000000010100010101010001000100000000000000000001010000010101),
|
||||
.INIT_28(256'h0101010101010001010101010100000100000100000000000001000100000000),
|
||||
.INIT_29(256'h0100000100010101000001000101010001000001000000010001010001000100),
|
||||
.INIT_2A(256'h0001000000010000010001000101000101000101010000000100000000000101),
|
||||
.INIT_2B(256'h0100010101000000000101000101000001000101010101010100000001000101),
|
||||
.INIT_2C(256'h0101010000000001000001000100010100000000000100010001000101010001),
|
||||
.INIT_2D(256'h0001010000000101000100000101000000000001000100000100000000010001),
|
||||
.INIT_2E(256'h0001010101010000010101010000010000000000010001000100000000000001),
|
||||
.INIT_2F(256'h0000010101000100010000010000000000010101010100000001000001000000),
|
||||
.INIT_30(256'h0101000100000100010000000000000101010001000100000100000101000101),
|
||||
.INIT_31(256'h0000000000000001010001000100010001000000010101010001000100000001),
|
||||
.INIT_32(256'h0101000100010001010101010101000100000101010100000101000101000101),
|
||||
.INIT_33(256'h0000010101000101000101010001010001010101010000010101010001010101),
|
||||
.INIT_34(256'h0101000000010001010100010000010100000001000000000101000001010100),
|
||||
.INIT_35(256'h0001000001000100000101000001000101010001000100010101010100000000),
|
||||
.INIT_36(256'h0000010100010000010101010001010101000001010101000001000001000101),
|
||||
.INIT_37(256'h0001000101000101000000010101000101010100000100010101000000010001),
|
||||
.INIT_38(256'h0000000001010101000000000100000101000001010001000100010100010001),
|
||||
.INIT_39(256'h0000010101000001000000010000000100010001010100010001010101000101),
|
||||
.INIT_3A(256'h0101010100000100000000000001000000010100010000010001000101010001),
|
||||
.INIT_3B(256'h0001010100010101010100000001010101010101010000010001000100010001),
|
||||
.INIT_3C(256'h0000000001010000000100000101000101000101010100000000010100010101),
|
||||
.INIT_3D(256'h0001000101000000010000000100010100010101010001000000000000010001),
|
||||
.INIT_3E(256'h0000000101000100000000010000010000010100010001000000010100000100),
|
||||
.INIT_3F(256'h0100000000010001000100010100000101000000010100000101010100010000),
|
||||
.INIT_A(18'h00000),
|
||||
.INIT_B(18'h00000),
|
||||
.INIT_FILE("NONE"),
|
||||
.IS_CLKARDCLK_INVERTED(1'b0),
|
||||
.IS_CLKBWRCLK_INVERTED(1'b0),
|
||||
.IS_ENARDEN_INVERTED(1'b0),
|
||||
.IS_ENBWREN_INVERTED(1'b0),
|
||||
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
|
||||
.IS_RSTRAMB_INVERTED(1'b0),
|
||||
.IS_RSTREGARSTREG_INVERTED(1'b0),
|
||||
.IS_RSTREGB_INVERTED(1'b0),
|
||||
.RAM_MODE("TDP"),
|
||||
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
|
||||
.READ_WIDTH_A(9),
|
||||
.READ_WIDTH_B(9),
|
||||
.RSTREG_PRIORITY_A("REGCE"),
|
||||
.RSTREG_PRIORITY_B("REGCE"),
|
||||
.SIM_COLLISION_CHECK("ALL"),
|
||||
.SIM_DEVICE("7SERIES"),
|
||||
.SRVAL_A(18'h00000),
|
||||
.SRVAL_B(18'h00000),
|
||||
.WRITE_MODE_A("WRITE_FIRST"),
|
||||
.WRITE_MODE_B("WRITE_FIRST"),
|
||||
.WRITE_WIDTH_A(9),
|
||||
.WRITE_WIDTH_B(9))
|
||||
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram
|
||||
(.ADDRARDADDR({addra,1'b0,1'b0,1'b0}),
|
||||
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.CLKARDCLK(clka),
|
||||
.CLKBWRCLK(clka),
|
||||
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DIPADIP({1'b0,1'b0}),
|
||||
.DIPBDIP({1'b0,1'b0}),
|
||||
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:8],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_8 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_9 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_10 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_11 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_12 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_13 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_14 ,DOADO}),
|
||||
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:0]),
|
||||
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_33 }),
|
||||
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
|
||||
.ENARDEN(ena),
|
||||
.ENBWREN(1'b0),
|
||||
.REGCEAREGCE(ena),
|
||||
.REGCEB(1'b0),
|
||||
.RSTRAMARSTRAM(1'b0),
|
||||
.RSTRAMB(1'b0),
|
||||
.RSTREGARSTREG(1'b0),
|
||||
.RSTREGB(1'b0),
|
||||
.WEA({1'b0,1'b0}),
|
||||
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
|
||||
module data_1p5m_blk_mem_gen_top
|
||||
(douta,
|
||||
clka,
|
||||
ena,
|
||||
addra);
|
||||
output [0:0]douta;
|
||||
input clka;
|
||||
input ena;
|
||||
input [10:0]addra;
|
||||
|
||||
wire [10:0]addra;
|
||||
wire clka;
|
||||
wire [0:0]douta;
|
||||
wire ena;
|
||||
|
||||
data_1p5m_blk_mem_gen_generic_cstr \valid.cstr
|
||||
(.addra(addra),
|
||||
.clka(clka),
|
||||
.douta(douta),
|
||||
.ena(ena));
|
||||
endmodule
|
||||
|
||||
(* C_ADDRA_WIDTH = "11" *) (* C_ADDRB_WIDTH = "11" *) (* C_ALGORITHM = "1" *)
|
||||
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
|
||||
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
|
||||
(* C_COUNT_36K_BRAM = "0" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
|
||||
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
|
||||
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
|
||||
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
|
||||
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 0.990811 mW" *)
|
||||
(* C_FAMILY = "kintex7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *)
|
||||
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
|
||||
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "1" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
|
||||
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
|
||||
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
|
||||
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "data_1p5m.mem" *)
|
||||
(* C_INIT_FILE_NAME = "data_1p5m.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
|
||||
(* C_MEM_TYPE = "3" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
|
||||
(* C_READ_DEPTH_A = "2048" *) (* C_READ_DEPTH_B = "2048" *) (* C_READ_LATENCY_A = "1" *)
|
||||
(* C_READ_LATENCY_B = "1" *) (* C_READ_WIDTH_A = "1" *) (* C_READ_WIDTH_B = "1" *)
|
||||
(* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *)
|
||||
(* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *)
|
||||
(* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *)
|
||||
(* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *)
|
||||
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "2048" *)
|
||||
(* C_WRITE_DEPTH_B = "2048" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
||||
(* C_WRITE_WIDTH_A = "1" *) (* C_WRITE_WIDTH_B = "1" *) (* C_XDEVICEFAMILY = "kintex7" *)
|
||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_3" *) (* downgradeipidentifiedwarnings = "yes" *)
|
||||
module data_1p5m_blk_mem_gen_v8_4_3
|
||||
(clka,
|
||||
rsta,
|
||||
ena,
|
||||
regcea,
|
||||
wea,
|
||||
addra,
|
||||
dina,
|
||||
douta,
|
||||
clkb,
|
||||
rstb,
|
||||
enb,
|
||||
regceb,
|
||||
web,
|
||||
addrb,
|
||||
dinb,
|
||||
doutb,
|
||||
injectsbiterr,
|
||||
injectdbiterr,
|
||||
eccpipece,
|
||||
sbiterr,
|
||||
dbiterr,
|
||||
rdaddrecc,
|
||||
sleep,
|
||||
deepsleep,
|
||||
shutdown,
|
||||
rsta_busy,
|
||||
rstb_busy,
|
||||
s_aclk,
|
||||
s_aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
s_axi_injectsbiterr,
|
||||
s_axi_injectdbiterr,
|
||||
s_axi_sbiterr,
|
||||
s_axi_dbiterr,
|
||||
s_axi_rdaddrecc);
|
||||
input clka;
|
||||
input rsta;
|
||||
input ena;
|
||||
input regcea;
|
||||
input [0:0]wea;
|
||||
input [10:0]addra;
|
||||
input [0:0]dina;
|
||||
output [0:0]douta;
|
||||
input clkb;
|
||||
input rstb;
|
||||
input enb;
|
||||
input regceb;
|
||||
input [0:0]web;
|
||||
input [10:0]addrb;
|
||||
input [0:0]dinb;
|
||||
output [0:0]doutb;
|
||||
input injectsbiterr;
|
||||
input injectdbiterr;
|
||||
input eccpipece;
|
||||
output sbiterr;
|
||||
output dbiterr;
|
||||
output [10:0]rdaddrecc;
|
||||
input sleep;
|
||||
input deepsleep;
|
||||
input shutdown;
|
||||
output rsta_busy;
|
||||
output rstb_busy;
|
||||
input s_aclk;
|
||||
input s_aresetn;
|
||||
input [3:0]s_axi_awid;
|
||||
input [31:0]s_axi_awaddr;
|
||||
input [7:0]s_axi_awlen;
|
||||
input [2:0]s_axi_awsize;
|
||||
input [1:0]s_axi_awburst;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [0:0]s_axi_wdata;
|
||||
input [0:0]s_axi_wstrb;
|
||||
input s_axi_wlast;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [3:0]s_axi_bid;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [3:0]s_axi_arid;
|
||||
input [31:0]s_axi_araddr;
|
||||
input [7:0]s_axi_arlen;
|
||||
input [2:0]s_axi_arsize;
|
||||
input [1:0]s_axi_arburst;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [3:0]s_axi_rid;
|
||||
output [0:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rlast;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
input s_axi_injectsbiterr;
|
||||
input s_axi_injectdbiterr;
|
||||
output s_axi_sbiterr;
|
||||
output s_axi_dbiterr;
|
||||
output [10:0]s_axi_rdaddrecc;
|
||||
|
||||
wire \<const0> ;
|
||||
wire [10:0]addra;
|
||||
wire clka;
|
||||
wire [0:0]douta;
|
||||
wire ena;
|
||||
|
||||
assign dbiterr = \<const0> ;
|
||||
assign doutb[0] = \<const0> ;
|
||||
assign rdaddrecc[10] = \<const0> ;
|
||||
assign rdaddrecc[9] = \<const0> ;
|
||||
assign rdaddrecc[8] = \<const0> ;
|
||||
assign rdaddrecc[7] = \<const0> ;
|
||||
assign rdaddrecc[6] = \<const0> ;
|
||||
assign rdaddrecc[5] = \<const0> ;
|
||||
assign rdaddrecc[4] = \<const0> ;
|
||||
assign rdaddrecc[3] = \<const0> ;
|
||||
assign rdaddrecc[2] = \<const0> ;
|
||||
assign rdaddrecc[1] = \<const0> ;
|
||||
assign rdaddrecc[0] = \<const0> ;
|
||||
assign rsta_busy = \<const0> ;
|
||||
assign rstb_busy = \<const0> ;
|
||||
assign s_axi_arready = \<const0> ;
|
||||
assign s_axi_awready = \<const0> ;
|
||||
assign s_axi_bid[3] = \<const0> ;
|
||||
assign s_axi_bid[2] = \<const0> ;
|
||||
assign s_axi_bid[1] = \<const0> ;
|
||||
assign s_axi_bid[0] = \<const0> ;
|
||||
assign s_axi_bresp[1] = \<const0> ;
|
||||
assign s_axi_bresp[0] = \<const0> ;
|
||||
assign s_axi_bvalid = \<const0> ;
|
||||
assign s_axi_dbiterr = \<const0> ;
|
||||
assign s_axi_rdaddrecc[10] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[9] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[8] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[7] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[6] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[5] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[4] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[3] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[2] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[1] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[0] = \<const0> ;
|
||||
assign s_axi_rdata[0] = \<const0> ;
|
||||
assign s_axi_rid[3] = \<const0> ;
|
||||
assign s_axi_rid[2] = \<const0> ;
|
||||
assign s_axi_rid[1] = \<const0> ;
|
||||
assign s_axi_rid[0] = \<const0> ;
|
||||
assign s_axi_rlast = \<const0> ;
|
||||
assign s_axi_rresp[1] = \<const0> ;
|
||||
assign s_axi_rresp[0] = \<const0> ;
|
||||
assign s_axi_rvalid = \<const0> ;
|
||||
assign s_axi_sbiterr = \<const0> ;
|
||||
assign s_axi_wready = \<const0> ;
|
||||
assign sbiterr = \<const0> ;
|
||||
GND GND
|
||||
(.G(\<const0> ));
|
||||
data_1p5m_blk_mem_gen_v8_4_3_synth inst_blk_mem_gen
|
||||
(.addra(addra),
|
||||
.clka(clka),
|
||||
.douta(douta),
|
||||
.ena(ena));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_3_synth" *)
|
||||
module data_1p5m_blk_mem_gen_v8_4_3_synth
|
||||
(douta,
|
||||
clka,
|
||||
ena,
|
||||
addra);
|
||||
output [0:0]douta;
|
||||
input clka;
|
||||
input ena;
|
||||
input [10:0]addra;
|
||||
|
||||
wire [10:0]addra;
|
||||
wire clka;
|
||||
wire [0:0]douta;
|
||||
wire ena;
|
||||
|
||||
data_1p5m_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
|
||||
(.addra(addra),
|
||||
.clka(clka),
|
||||
.douta(douta),
|
||||
.ena(ena));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
-849
@@ -1,849 +0,0 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:34:17 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim
|
||||
-- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_sim_netlist.vhdl
|
||||
-- Design : data_1p5m
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity data_1p5m_blk_mem_gen_prim_wrapper_init is
|
||||
port (
|
||||
DOADO : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
clka : in STD_LOGIC;
|
||||
ena : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 10 downto 0 )
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of data_1p5m_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
|
||||
end data_1p5m_blk_mem_gen_prim_wrapper_init;
|
||||
|
||||
architecture STRUCTURE of data_1p5m_blk_mem_gen_prim_wrapper_init is
|
||||
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_10\ : STD_LOGIC;
|
||||
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_11\ : STD_LOGIC;
|
||||
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_12\ : STD_LOGIC;
|
||||
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_13\ : STD_LOGIC;
|
||||
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_14\ : STD_LOGIC;
|
||||
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_33\ : STD_LOGIC;
|
||||
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_8\ : STD_LOGIC;
|
||||
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_9\ : STD_LOGIC;
|
||||
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 );
|
||||
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
|
||||
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
attribute box_type : string;
|
||||
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
|
||||
begin
|
||||
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
|
||||
generic map(
|
||||
DOA_REG => 1,
|
||||
DOB_REG => 0,
|
||||
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_00 => X"0101000001010101000101000001010100010100010101000101000100010001",
|
||||
INIT_01 => X"0000010001000000010100000100010100000100010101000100000100000101",
|
||||
INIT_02 => X"0001000000010001010000010101000100010100000000010100000001010001",
|
||||
INIT_03 => X"0100000101000100010000010000000101010000000001000000000101000001",
|
||||
INIT_04 => X"0001010101010000000001000100010100000001010000010001000101010000",
|
||||
INIT_05 => X"0101010100010000000101000101010101000100010000010001010000000101",
|
||||
INIT_06 => X"0101010100010100010001010001010000000001000001010100000000010101",
|
||||
INIT_07 => X"0000010100010000000101010001000000000100010000000100010001000001",
|
||||
INIT_08 => X"0101000101010101010000000000000001000000010001000001000100000100",
|
||||
INIT_09 => X"0000010000000101000100010001000000000101000001010001010100010001",
|
||||
INIT_0A => X"0000000101000100000001000001000100000100000101010100010100000101",
|
||||
INIT_0B => X"0100010001000000010101000101010001010000010101010101000001010100",
|
||||
INIT_0C => X"0100010101010001000101010101000000010100010100000000000101010100",
|
||||
INIT_0D => X"0001010001010000000000010000010100000000010100010001000001010101",
|
||||
INIT_0E => X"0000010000010001000000000001000100000000010000000101000100000100",
|
||||
INIT_0F => X"0000010101010100000000000000010101010001000001000100010101010101",
|
||||
INIT_10 => X"0101000100010001010100010101000101010000010101010000000001000000",
|
||||
INIT_11 => X"0101010100000000000001000000010000000100000001000001000001000001",
|
||||
INIT_12 => X"0000000101010101000001000100010100010000010000010100010101000101",
|
||||
INIT_13 => X"0100000000000000000100000100010000010000000101010101000101000100",
|
||||
INIT_14 => X"0101010101010100010001000100010001010100000100000101010101010001",
|
||||
INIT_15 => X"0100010000010101000000010001000001000100000001010001010000010000",
|
||||
INIT_16 => X"0100000001000101000101010100000100000101000101000101010000010001",
|
||||
INIT_17 => X"0100010001000100000101000000010000000000000000010000010001010000",
|
||||
INIT_18 => X"0000010100000100000101010101000000000101010101010001010100010100",
|
||||
INIT_19 => X"0100000100010001000100010000010000000100000000010001010001010100",
|
||||
INIT_1A => X"0001010100010001000100000100000000010100010001010100010100010001",
|
||||
INIT_1B => X"0100010000000101010000010101010100000000010001000000010000000001",
|
||||
INIT_1C => X"0101000000010100000000010100010100000001000000000100000100010100",
|
||||
INIT_1D => X"0101010101000101000100000100000000000001010001000101010100000001",
|
||||
INIT_1E => X"0101010100010001010000010101000100000100000100000000000101000000",
|
||||
INIT_1F => X"0101010000000100000001010001010001010001000001000001000001000101",
|
||||
INIT_20 => X"0101000100010000010001000101010100010000010001010101000100010001",
|
||||
INIT_21 => X"0001000001000100010000010101000001000100010101010100010100000101",
|
||||
INIT_22 => X"0101000100010101010101010001000100000100000001000000010101000100",
|
||||
INIT_23 => X"0000000000010101010100010001010100010101010001000001010100000000",
|
||||
INIT_24 => X"0100000000010000000100000100000101000100000100010001010000000001",
|
||||
INIT_25 => X"0001010100000001010000010000000001010000000100000100000101010100",
|
||||
INIT_26 => X"0001010101010000010101000001000000010001010101000000010000010100",
|
||||
INIT_27 => X"0001000000010100010101010001000100000000000000000001010000010101",
|
||||
INIT_28 => X"0101010101010001010101010100000100000100000000000001000100000000",
|
||||
INIT_29 => X"0100000100010101000001000101010001000001000000010001010001000100",
|
||||
INIT_2A => X"0001000000010000010001000101000101000101010000000100000000000101",
|
||||
INIT_2B => X"0100010101000000000101000101000001000101010101010100000001000101",
|
||||
INIT_2C => X"0101010000000001000001000100010100000000000100010001000101010001",
|
||||
INIT_2D => X"0001010000000101000100000101000000000001000100000100000000010001",
|
||||
INIT_2E => X"0001010101010000010101010000010000000000010001000100000000000001",
|
||||
INIT_2F => X"0000010101000100010000010000000000010101010100000001000001000000",
|
||||
INIT_30 => X"0101000100000100010000000000000101010001000100000100000101000101",
|
||||
INIT_31 => X"0000000000000001010001000100010001000000010101010001000100000001",
|
||||
INIT_32 => X"0101000100010001010101010101000100000101010100000101000101000101",
|
||||
INIT_33 => X"0000010101000101000101010001010001010101010000010101010001010101",
|
||||
INIT_34 => X"0101000000010001010100010000010100000001000000000101000001010100",
|
||||
INIT_35 => X"0001000001000100000101000001000101010001000100010101010100000000",
|
||||
INIT_36 => X"0000010100010000010101010001010101000001010101000001000001000101",
|
||||
INIT_37 => X"0001000101000101000000010101000101010100000100010101000000010001",
|
||||
INIT_38 => X"0000000001010101000000000100000101000001010001000100010100010001",
|
||||
INIT_39 => X"0000010101000001000000010000000100010001010100010001010101000101",
|
||||
INIT_3A => X"0101010100000100000000000001000000010100010000010001000101010001",
|
||||
INIT_3B => X"0001010100010101010100000001010101010101010000010001000100010001",
|
||||
INIT_3C => X"0000000001010000000100000101000101000101010100000000010100010101",
|
||||
INIT_3D => X"0001000101000000010000000100010100010101010001000000000000010001",
|
||||
INIT_3E => X"0000000101000100000000010000010000010100010001000000010100000100",
|
||||
INIT_3F => X"0100000000010001000100010100000101000000010100000101010100010000",
|
||||
INIT_A => X"00000",
|
||||
INIT_B => X"00000",
|
||||
INIT_FILE => "NONE",
|
||||
IS_CLKARDCLK_INVERTED => '0',
|
||||
IS_CLKBWRCLK_INVERTED => '0',
|
||||
IS_ENARDEN_INVERTED => '0',
|
||||
IS_ENBWREN_INVERTED => '0',
|
||||
IS_RSTRAMARSTRAM_INVERTED => '0',
|
||||
IS_RSTRAMB_INVERTED => '0',
|
||||
IS_RSTREGARSTREG_INVERTED => '0',
|
||||
IS_RSTREGB_INVERTED => '0',
|
||||
RAM_MODE => "TDP",
|
||||
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
|
||||
READ_WIDTH_A => 9,
|
||||
READ_WIDTH_B => 9,
|
||||
RSTREG_PRIORITY_A => "REGCE",
|
||||
RSTREG_PRIORITY_B => "REGCE",
|
||||
SIM_COLLISION_CHECK => "ALL",
|
||||
SIM_DEVICE => "7SERIES",
|
||||
SRVAL_A => X"00000",
|
||||
SRVAL_B => X"00000",
|
||||
WRITE_MODE_A => "WRITE_FIRST",
|
||||
WRITE_MODE_B => "WRITE_FIRST",
|
||||
WRITE_WIDTH_A => 9,
|
||||
WRITE_WIDTH_B => 9
|
||||
)
|
||||
port map (
|
||||
ADDRARDADDR(13 downto 3) => addra(10 downto 0),
|
||||
ADDRARDADDR(2 downto 0) => B"000",
|
||||
ADDRBWRADDR(13 downto 0) => B"00000000000000",
|
||||
CLKARDCLK => clka,
|
||||
CLKBWRCLK => clka,
|
||||
DIADI(15 downto 0) => B"0000000000000000",
|
||||
DIBDI(15 downto 0) => B"0000000000000000",
|
||||
DIPADIP(1 downto 0) => B"00",
|
||||
DIPBDIP(1 downto 0) => B"00",
|
||||
DOADO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 8),
|
||||
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_8\,
|
||||
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_9\,
|
||||
DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_10\,
|
||||
DOADO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_11\,
|
||||
DOADO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_12\,
|
||||
DOADO(2) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_13\,
|
||||
DOADO(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_14\,
|
||||
DOADO(0) => DOADO(0),
|
||||
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
|
||||
DOPADOP(1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1),
|
||||
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_33\,
|
||||
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
|
||||
ENARDEN => ena,
|
||||
ENBWREN => '0',
|
||||
REGCEAREGCE => ena,
|
||||
REGCEB => '0',
|
||||
RSTRAMARSTRAM => '0',
|
||||
RSTRAMB => '0',
|
||||
RSTREGARSTREG => '0',
|
||||
RSTREGB => '0',
|
||||
WEA(1 downto 0) => B"00",
|
||||
WEBWE(3 downto 0) => B"0000"
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity data_1p5m_blk_mem_gen_prim_width is
|
||||
port (
|
||||
DOADO : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
clka : in STD_LOGIC;
|
||||
ena : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 10 downto 0 )
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of data_1p5m_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
|
||||
end data_1p5m_blk_mem_gen_prim_width;
|
||||
|
||||
architecture STRUCTURE of data_1p5m_blk_mem_gen_prim_width is
|
||||
begin
|
||||
\prim_init.ram\: entity work.data_1p5m_blk_mem_gen_prim_wrapper_init
|
||||
port map (
|
||||
DOADO(0) => DOADO(0),
|
||||
addra(10 downto 0) => addra(10 downto 0),
|
||||
clka => clka,
|
||||
ena => ena
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity data_1p5m_blk_mem_gen_generic_cstr is
|
||||
port (
|
||||
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
clka : in STD_LOGIC;
|
||||
ena : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 10 downto 0 )
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of data_1p5m_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
|
||||
end data_1p5m_blk_mem_gen_generic_cstr;
|
||||
|
||||
architecture STRUCTURE of data_1p5m_blk_mem_gen_generic_cstr is
|
||||
signal ram_douta : STD_LOGIC;
|
||||
begin
|
||||
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[0]\: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '0'
|
||||
)
|
||||
port map (
|
||||
C => clka,
|
||||
CE => ena,
|
||||
D => ram_douta,
|
||||
Q => douta(0),
|
||||
R => '0'
|
||||
);
|
||||
\ramloop[0].ram.r\: entity work.data_1p5m_blk_mem_gen_prim_width
|
||||
port map (
|
||||
DOADO(0) => ram_douta,
|
||||
addra(10 downto 0) => addra(10 downto 0),
|
||||
clka => clka,
|
||||
ena => ena
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity data_1p5m_blk_mem_gen_top is
|
||||
port (
|
||||
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
clka : in STD_LOGIC;
|
||||
ena : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 10 downto 0 )
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of data_1p5m_blk_mem_gen_top : entity is "blk_mem_gen_top";
|
||||
end data_1p5m_blk_mem_gen_top;
|
||||
|
||||
architecture STRUCTURE of data_1p5m_blk_mem_gen_top is
|
||||
begin
|
||||
\valid.cstr\: entity work.data_1p5m_blk_mem_gen_generic_cstr
|
||||
port map (
|
||||
addra(10 downto 0) => addra(10 downto 0),
|
||||
clka => clka,
|
||||
douta(0) => douta(0),
|
||||
ena => ena
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity data_1p5m_blk_mem_gen_v8_4_3_synth is
|
||||
port (
|
||||
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
clka : in STD_LOGIC;
|
||||
ena : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 10 downto 0 )
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of data_1p5m_blk_mem_gen_v8_4_3_synth : entity is "blk_mem_gen_v8_4_3_synth";
|
||||
end data_1p5m_blk_mem_gen_v8_4_3_synth;
|
||||
|
||||
architecture STRUCTURE of data_1p5m_blk_mem_gen_v8_4_3_synth is
|
||||
begin
|
||||
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.data_1p5m_blk_mem_gen_top
|
||||
port map (
|
||||
addra(10 downto 0) => addra(10 downto 0),
|
||||
clka => clka,
|
||||
douta(0) => douta(0),
|
||||
ena => ena
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity data_1p5m_blk_mem_gen_v8_4_3 is
|
||||
port (
|
||||
clka : in STD_LOGIC;
|
||||
rsta : in STD_LOGIC;
|
||||
ena : in STD_LOGIC;
|
||||
regcea : in STD_LOGIC;
|
||||
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
|
||||
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
clkb : in STD_LOGIC;
|
||||
rstb : in STD_LOGIC;
|
||||
enb : in STD_LOGIC;
|
||||
regceb : in STD_LOGIC;
|
||||
web : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
|
||||
dinb : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
doutb : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
injectsbiterr : in STD_LOGIC;
|
||||
injectdbiterr : in STD_LOGIC;
|
||||
eccpipece : in STD_LOGIC;
|
||||
sbiterr : out STD_LOGIC;
|
||||
dbiterr : out STD_LOGIC;
|
||||
rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 );
|
||||
sleep : in STD_LOGIC;
|
||||
deepsleep : in STD_LOGIC;
|
||||
shutdown : in STD_LOGIC;
|
||||
rsta_busy : out STD_LOGIC;
|
||||
rstb_busy : out STD_LOGIC;
|
||||
s_aclk : in STD_LOGIC;
|
||||
s_aresetn : in STD_LOGIC;
|
||||
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_wlast : in STD_LOGIC;
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rlast : out STD_LOGIC;
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
s_axi_injectsbiterr : in STD_LOGIC;
|
||||
s_axi_injectdbiterr : in STD_LOGIC;
|
||||
s_axi_sbiterr : out STD_LOGIC;
|
||||
s_axi_dbiterr : out STD_LOGIC;
|
||||
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 )
|
||||
);
|
||||
attribute C_ADDRA_WIDTH : integer;
|
||||
attribute C_ADDRA_WIDTH of data_1p5m_blk_mem_gen_v8_4_3 : entity is 11;
|
||||
attribute C_ADDRB_WIDTH : integer;
|
||||
attribute C_ADDRB_WIDTH of data_1p5m_blk_mem_gen_v8_4_3 : entity is 11;
|
||||
attribute C_ALGORITHM : integer;
|
||||
attribute C_ALGORITHM of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_AXI_ID_WIDTH : integer;
|
||||
attribute C_AXI_ID_WIDTH of data_1p5m_blk_mem_gen_v8_4_3 : entity is 4;
|
||||
attribute C_AXI_SLAVE_TYPE : integer;
|
||||
attribute C_AXI_SLAVE_TYPE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_AXI_TYPE : integer;
|
||||
attribute C_AXI_TYPE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_BYTE_SIZE : integer;
|
||||
attribute C_BYTE_SIZE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 9;
|
||||
attribute C_COMMON_CLK : integer;
|
||||
attribute C_COMMON_CLK of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_COUNT_18K_BRAM : string;
|
||||
attribute C_COUNT_18K_BRAM of data_1p5m_blk_mem_gen_v8_4_3 : entity is "1";
|
||||
attribute C_COUNT_36K_BRAM : string;
|
||||
attribute C_COUNT_36K_BRAM of data_1p5m_blk_mem_gen_v8_4_3 : entity is "0";
|
||||
attribute C_CTRL_ECC_ALGO : string;
|
||||
attribute C_CTRL_ECC_ALGO of data_1p5m_blk_mem_gen_v8_4_3 : entity is "NONE";
|
||||
attribute C_DEFAULT_DATA : string;
|
||||
attribute C_DEFAULT_DATA of data_1p5m_blk_mem_gen_v8_4_3 : entity is "0";
|
||||
attribute C_DISABLE_WARN_BHV_COLL : integer;
|
||||
attribute C_DISABLE_WARN_BHV_COLL of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_DISABLE_WARN_BHV_RANGE : integer;
|
||||
attribute C_DISABLE_WARN_BHV_RANGE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_ELABORATION_DIR : string;
|
||||
attribute C_ELABORATION_DIR of data_1p5m_blk_mem_gen_v8_4_3 : entity is "./";
|
||||
attribute C_ENABLE_32BIT_ADDRESS : integer;
|
||||
attribute C_ENABLE_32BIT_ADDRESS of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EN_DEEPSLEEP_PIN : integer;
|
||||
attribute C_EN_DEEPSLEEP_PIN of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EN_ECC_PIPE : integer;
|
||||
attribute C_EN_ECC_PIPE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EN_RDADDRA_CHG : integer;
|
||||
attribute C_EN_RDADDRA_CHG of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EN_RDADDRB_CHG : integer;
|
||||
attribute C_EN_RDADDRB_CHG of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EN_SAFETY_CKT : integer;
|
||||
attribute C_EN_SAFETY_CKT of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EN_SHUTDOWN_PIN : integer;
|
||||
attribute C_EN_SHUTDOWN_PIN of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EN_SLEEP_PIN : integer;
|
||||
attribute C_EN_SLEEP_PIN of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_EST_POWER_SUMMARY : string;
|
||||
attribute C_EST_POWER_SUMMARY of data_1p5m_blk_mem_gen_v8_4_3 : entity is "Estimated Power for IP : 0.990811 mW";
|
||||
attribute C_FAMILY : string;
|
||||
attribute C_FAMILY of data_1p5m_blk_mem_gen_v8_4_3 : entity is "kintex7";
|
||||
attribute C_HAS_AXI_ID : integer;
|
||||
attribute C_HAS_AXI_ID of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_ENA : integer;
|
||||
attribute C_HAS_ENA of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_HAS_ENB : integer;
|
||||
attribute C_HAS_ENB of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_INJECTERR : integer;
|
||||
attribute C_HAS_INJECTERR of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_REGCEA : integer;
|
||||
attribute C_HAS_REGCEA of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_REGCEB : integer;
|
||||
attribute C_HAS_REGCEB of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_RSTA : integer;
|
||||
attribute C_HAS_RSTA of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_RSTB : integer;
|
||||
attribute C_HAS_RSTB of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
|
||||
attribute C_HAS_SOFTECC_INPUT_REGS_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_INITA_VAL : string;
|
||||
attribute C_INITA_VAL of data_1p5m_blk_mem_gen_v8_4_3 : entity is "0";
|
||||
attribute C_INITB_VAL : string;
|
||||
attribute C_INITB_VAL of data_1p5m_blk_mem_gen_v8_4_3 : entity is "0";
|
||||
attribute C_INIT_FILE : string;
|
||||
attribute C_INIT_FILE of data_1p5m_blk_mem_gen_v8_4_3 : entity is "data_1p5m.mem";
|
||||
attribute C_INIT_FILE_NAME : string;
|
||||
attribute C_INIT_FILE_NAME of data_1p5m_blk_mem_gen_v8_4_3 : entity is "data_1p5m.mif";
|
||||
attribute C_INTERFACE_TYPE : integer;
|
||||
attribute C_INTERFACE_TYPE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_LOAD_INIT_FILE : integer;
|
||||
attribute C_LOAD_INIT_FILE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_MEM_TYPE : integer;
|
||||
attribute C_MEM_TYPE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 3;
|
||||
attribute C_MUX_PIPELINE_STAGES : integer;
|
||||
attribute C_MUX_PIPELINE_STAGES of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_PRIM_TYPE : integer;
|
||||
attribute C_PRIM_TYPE of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_READ_DEPTH_A : integer;
|
||||
attribute C_READ_DEPTH_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 2048;
|
||||
attribute C_READ_DEPTH_B : integer;
|
||||
attribute C_READ_DEPTH_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 2048;
|
||||
attribute C_READ_LATENCY_A : integer;
|
||||
attribute C_READ_LATENCY_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_READ_LATENCY_B : integer;
|
||||
attribute C_READ_LATENCY_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_READ_WIDTH_A : integer;
|
||||
attribute C_READ_WIDTH_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_READ_WIDTH_B : integer;
|
||||
attribute C_READ_WIDTH_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_RSTRAM_A : integer;
|
||||
attribute C_RSTRAM_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_RSTRAM_B : integer;
|
||||
attribute C_RSTRAM_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_RST_PRIORITY_A : string;
|
||||
attribute C_RST_PRIORITY_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is "CE";
|
||||
attribute C_RST_PRIORITY_B : string;
|
||||
attribute C_RST_PRIORITY_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is "CE";
|
||||
attribute C_SIM_COLLISION_CHECK : string;
|
||||
attribute C_SIM_COLLISION_CHECK of data_1p5m_blk_mem_gen_v8_4_3 : entity is "ALL";
|
||||
attribute C_USE_BRAM_BLOCK : integer;
|
||||
attribute C_USE_BRAM_BLOCK of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_USE_BYTE_WEA : integer;
|
||||
attribute C_USE_BYTE_WEA of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_USE_BYTE_WEB : integer;
|
||||
attribute C_USE_BYTE_WEB of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_USE_DEFAULT_DATA : integer;
|
||||
attribute C_USE_DEFAULT_DATA of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_USE_ECC : integer;
|
||||
attribute C_USE_ECC of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_USE_SOFTECC : integer;
|
||||
attribute C_USE_SOFTECC of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_USE_URAM : integer;
|
||||
attribute C_USE_URAM of data_1p5m_blk_mem_gen_v8_4_3 : entity is 0;
|
||||
attribute C_WEA_WIDTH : integer;
|
||||
attribute C_WEA_WIDTH of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_WEB_WIDTH : integer;
|
||||
attribute C_WEB_WIDTH of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_WRITE_DEPTH_A : integer;
|
||||
attribute C_WRITE_DEPTH_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 2048;
|
||||
attribute C_WRITE_DEPTH_B : integer;
|
||||
attribute C_WRITE_DEPTH_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 2048;
|
||||
attribute C_WRITE_MODE_A : string;
|
||||
attribute C_WRITE_MODE_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is "WRITE_FIRST";
|
||||
attribute C_WRITE_MODE_B : string;
|
||||
attribute C_WRITE_MODE_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is "WRITE_FIRST";
|
||||
attribute C_WRITE_WIDTH_A : integer;
|
||||
attribute C_WRITE_WIDTH_A of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_WRITE_WIDTH_B : integer;
|
||||
attribute C_WRITE_WIDTH_B of data_1p5m_blk_mem_gen_v8_4_3 : entity is 1;
|
||||
attribute C_XDEVICEFAMILY : string;
|
||||
attribute C_XDEVICEFAMILY of data_1p5m_blk_mem_gen_v8_4_3 : entity is "kintex7";
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of data_1p5m_blk_mem_gen_v8_4_3 : entity is "blk_mem_gen_v8_4_3";
|
||||
attribute downgradeipidentifiedwarnings : string;
|
||||
attribute downgradeipidentifiedwarnings of data_1p5m_blk_mem_gen_v8_4_3 : entity is "yes";
|
||||
end data_1p5m_blk_mem_gen_v8_4_3;
|
||||
|
||||
architecture STRUCTURE of data_1p5m_blk_mem_gen_v8_4_3 is
|
||||
signal \<const0>\ : STD_LOGIC;
|
||||
begin
|
||||
dbiterr <= \<const0>\;
|
||||
doutb(0) <= \<const0>\;
|
||||
rdaddrecc(10) <= \<const0>\;
|
||||
rdaddrecc(9) <= \<const0>\;
|
||||
rdaddrecc(8) <= \<const0>\;
|
||||
rdaddrecc(7) <= \<const0>\;
|
||||
rdaddrecc(6) <= \<const0>\;
|
||||
rdaddrecc(5) <= \<const0>\;
|
||||
rdaddrecc(4) <= \<const0>\;
|
||||
rdaddrecc(3) <= \<const0>\;
|
||||
rdaddrecc(2) <= \<const0>\;
|
||||
rdaddrecc(1) <= \<const0>\;
|
||||
rdaddrecc(0) <= \<const0>\;
|
||||
rsta_busy <= \<const0>\;
|
||||
rstb_busy <= \<const0>\;
|
||||
s_axi_arready <= \<const0>\;
|
||||
s_axi_awready <= \<const0>\;
|
||||
s_axi_bid(3) <= \<const0>\;
|
||||
s_axi_bid(2) <= \<const0>\;
|
||||
s_axi_bid(1) <= \<const0>\;
|
||||
s_axi_bid(0) <= \<const0>\;
|
||||
s_axi_bresp(1) <= \<const0>\;
|
||||
s_axi_bresp(0) <= \<const0>\;
|
||||
s_axi_bvalid <= \<const0>\;
|
||||
s_axi_dbiterr <= \<const0>\;
|
||||
s_axi_rdaddrecc(10) <= \<const0>\;
|
||||
s_axi_rdaddrecc(9) <= \<const0>\;
|
||||
s_axi_rdaddrecc(8) <= \<const0>\;
|
||||
s_axi_rdaddrecc(7) <= \<const0>\;
|
||||
s_axi_rdaddrecc(6) <= \<const0>\;
|
||||
s_axi_rdaddrecc(5) <= \<const0>\;
|
||||
s_axi_rdaddrecc(4) <= \<const0>\;
|
||||
s_axi_rdaddrecc(3) <= \<const0>\;
|
||||
s_axi_rdaddrecc(2) <= \<const0>\;
|
||||
s_axi_rdaddrecc(1) <= \<const0>\;
|
||||
s_axi_rdaddrecc(0) <= \<const0>\;
|
||||
s_axi_rdata(0) <= \<const0>\;
|
||||
s_axi_rid(3) <= \<const0>\;
|
||||
s_axi_rid(2) <= \<const0>\;
|
||||
s_axi_rid(1) <= \<const0>\;
|
||||
s_axi_rid(0) <= \<const0>\;
|
||||
s_axi_rlast <= \<const0>\;
|
||||
s_axi_rresp(1) <= \<const0>\;
|
||||
s_axi_rresp(0) <= \<const0>\;
|
||||
s_axi_rvalid <= \<const0>\;
|
||||
s_axi_sbiterr <= \<const0>\;
|
||||
s_axi_wready <= \<const0>\;
|
||||
sbiterr <= \<const0>\;
|
||||
GND: unisim.vcomponents.GND
|
||||
port map (
|
||||
G => \<const0>\
|
||||
);
|
||||
inst_blk_mem_gen: entity work.data_1p5m_blk_mem_gen_v8_4_3_synth
|
||||
port map (
|
||||
addra(10 downto 0) => addra(10 downto 0),
|
||||
clka => clka,
|
||||
douta(0) => douta(0),
|
||||
ena => ena
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity data_1p5m is
|
||||
port (
|
||||
clka : in STD_LOGIC;
|
||||
ena : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
|
||||
douta : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of data_1p5m : entity is true;
|
||||
attribute CHECK_LICENSE_TYPE : string;
|
||||
attribute CHECK_LICENSE_TYPE of data_1p5m : entity is "data_1p5m,blk_mem_gen_v8_4_3,{}";
|
||||
attribute downgradeipidentifiedwarnings : string;
|
||||
attribute downgradeipidentifiedwarnings of data_1p5m : entity is "yes";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of data_1p5m : entity is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
|
||||
end data_1p5m;
|
||||
|
||||
architecture STRUCTURE of data_1p5m is
|
||||
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
|
||||
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
|
||||
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
attribute C_ADDRA_WIDTH : integer;
|
||||
attribute C_ADDRA_WIDTH of U0 : label is 11;
|
||||
attribute C_ADDRB_WIDTH : integer;
|
||||
attribute C_ADDRB_WIDTH of U0 : label is 11;
|
||||
attribute C_ALGORITHM : integer;
|
||||
attribute C_ALGORITHM of U0 : label is 1;
|
||||
attribute C_AXI_ID_WIDTH : integer;
|
||||
attribute C_AXI_ID_WIDTH of U0 : label is 4;
|
||||
attribute C_AXI_SLAVE_TYPE : integer;
|
||||
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
|
||||
attribute C_AXI_TYPE : integer;
|
||||
attribute C_AXI_TYPE of U0 : label is 1;
|
||||
attribute C_BYTE_SIZE : integer;
|
||||
attribute C_BYTE_SIZE of U0 : label is 9;
|
||||
attribute C_COMMON_CLK : integer;
|
||||
attribute C_COMMON_CLK of U0 : label is 0;
|
||||
attribute C_COUNT_18K_BRAM : string;
|
||||
attribute C_COUNT_18K_BRAM of U0 : label is "1";
|
||||
attribute C_COUNT_36K_BRAM : string;
|
||||
attribute C_COUNT_36K_BRAM of U0 : label is "0";
|
||||
attribute C_CTRL_ECC_ALGO : string;
|
||||
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
|
||||
attribute C_DEFAULT_DATA : string;
|
||||
attribute C_DEFAULT_DATA of U0 : label is "0";
|
||||
attribute C_DISABLE_WARN_BHV_COLL : integer;
|
||||
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
|
||||
attribute C_DISABLE_WARN_BHV_RANGE : integer;
|
||||
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
|
||||
attribute C_ELABORATION_DIR : string;
|
||||
attribute C_ELABORATION_DIR of U0 : label is "./";
|
||||
attribute C_ENABLE_32BIT_ADDRESS : integer;
|
||||
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
|
||||
attribute C_EN_DEEPSLEEP_PIN : integer;
|
||||
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
|
||||
attribute C_EN_ECC_PIPE : integer;
|
||||
attribute C_EN_ECC_PIPE of U0 : label is 0;
|
||||
attribute C_EN_RDADDRA_CHG : integer;
|
||||
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
|
||||
attribute C_EN_RDADDRB_CHG : integer;
|
||||
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
|
||||
attribute C_EN_SAFETY_CKT : integer;
|
||||
attribute C_EN_SAFETY_CKT of U0 : label is 0;
|
||||
attribute C_EN_SHUTDOWN_PIN : integer;
|
||||
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
|
||||
attribute C_EN_SLEEP_PIN : integer;
|
||||
attribute C_EN_SLEEP_PIN of U0 : label is 0;
|
||||
attribute C_EST_POWER_SUMMARY : string;
|
||||
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 0.990811 mW";
|
||||
attribute C_FAMILY : string;
|
||||
attribute C_FAMILY of U0 : label is "kintex7";
|
||||
attribute C_HAS_AXI_ID : integer;
|
||||
attribute C_HAS_AXI_ID of U0 : label is 0;
|
||||
attribute C_HAS_ENA : integer;
|
||||
attribute C_HAS_ENA of U0 : label is 1;
|
||||
attribute C_HAS_ENB : integer;
|
||||
attribute C_HAS_ENB of U0 : label is 0;
|
||||
attribute C_HAS_INJECTERR : integer;
|
||||
attribute C_HAS_INJECTERR of U0 : label is 0;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 1;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
|
||||
attribute C_HAS_REGCEA : integer;
|
||||
attribute C_HAS_REGCEA of U0 : label is 0;
|
||||
attribute C_HAS_REGCEB : integer;
|
||||
attribute C_HAS_REGCEB of U0 : label is 0;
|
||||
attribute C_HAS_RSTA : integer;
|
||||
attribute C_HAS_RSTA of U0 : label is 0;
|
||||
attribute C_HAS_RSTB : integer;
|
||||
attribute C_HAS_RSTB of U0 : label is 0;
|
||||
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
|
||||
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
|
||||
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
|
||||
attribute C_INITA_VAL : string;
|
||||
attribute C_INITA_VAL of U0 : label is "0";
|
||||
attribute C_INITB_VAL : string;
|
||||
attribute C_INITB_VAL of U0 : label is "0";
|
||||
attribute C_INIT_FILE : string;
|
||||
attribute C_INIT_FILE of U0 : label is "data_1p5m.mem";
|
||||
attribute C_INIT_FILE_NAME : string;
|
||||
attribute C_INIT_FILE_NAME of U0 : label is "data_1p5m.mif";
|
||||
attribute C_INTERFACE_TYPE : integer;
|
||||
attribute C_INTERFACE_TYPE of U0 : label is 0;
|
||||
attribute C_LOAD_INIT_FILE : integer;
|
||||
attribute C_LOAD_INIT_FILE of U0 : label is 1;
|
||||
attribute C_MEM_TYPE : integer;
|
||||
attribute C_MEM_TYPE of U0 : label is 3;
|
||||
attribute C_MUX_PIPELINE_STAGES : integer;
|
||||
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
|
||||
attribute C_PRIM_TYPE : integer;
|
||||
attribute C_PRIM_TYPE of U0 : label is 1;
|
||||
attribute C_READ_DEPTH_A : integer;
|
||||
attribute C_READ_DEPTH_A of U0 : label is 2048;
|
||||
attribute C_READ_DEPTH_B : integer;
|
||||
attribute C_READ_DEPTH_B of U0 : label is 2048;
|
||||
attribute C_READ_LATENCY_A : integer;
|
||||
attribute C_READ_LATENCY_A of U0 : label is 1;
|
||||
attribute C_READ_LATENCY_B : integer;
|
||||
attribute C_READ_LATENCY_B of U0 : label is 1;
|
||||
attribute C_READ_WIDTH_A : integer;
|
||||
attribute C_READ_WIDTH_A of U0 : label is 1;
|
||||
attribute C_READ_WIDTH_B : integer;
|
||||
attribute C_READ_WIDTH_B of U0 : label is 1;
|
||||
attribute C_RSTRAM_A : integer;
|
||||
attribute C_RSTRAM_A of U0 : label is 0;
|
||||
attribute C_RSTRAM_B : integer;
|
||||
attribute C_RSTRAM_B of U0 : label is 0;
|
||||
attribute C_RST_PRIORITY_A : string;
|
||||
attribute C_RST_PRIORITY_A of U0 : label is "CE";
|
||||
attribute C_RST_PRIORITY_B : string;
|
||||
attribute C_RST_PRIORITY_B of U0 : label is "CE";
|
||||
attribute C_SIM_COLLISION_CHECK : string;
|
||||
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
|
||||
attribute C_USE_BRAM_BLOCK : integer;
|
||||
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
|
||||
attribute C_USE_BYTE_WEA : integer;
|
||||
attribute C_USE_BYTE_WEA of U0 : label is 0;
|
||||
attribute C_USE_BYTE_WEB : integer;
|
||||
attribute C_USE_BYTE_WEB of U0 : label is 0;
|
||||
attribute C_USE_DEFAULT_DATA : integer;
|
||||
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
|
||||
attribute C_USE_ECC : integer;
|
||||
attribute C_USE_ECC of U0 : label is 0;
|
||||
attribute C_USE_SOFTECC : integer;
|
||||
attribute C_USE_SOFTECC of U0 : label is 0;
|
||||
attribute C_USE_URAM : integer;
|
||||
attribute C_USE_URAM of U0 : label is 0;
|
||||
attribute C_WEA_WIDTH : integer;
|
||||
attribute C_WEA_WIDTH of U0 : label is 1;
|
||||
attribute C_WEB_WIDTH : integer;
|
||||
attribute C_WEB_WIDTH of U0 : label is 1;
|
||||
attribute C_WRITE_DEPTH_A : integer;
|
||||
attribute C_WRITE_DEPTH_A of U0 : label is 2048;
|
||||
attribute C_WRITE_DEPTH_B : integer;
|
||||
attribute C_WRITE_DEPTH_B of U0 : label is 2048;
|
||||
attribute C_WRITE_MODE_A : string;
|
||||
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
|
||||
attribute C_WRITE_MODE_B : string;
|
||||
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
|
||||
attribute C_WRITE_WIDTH_A : integer;
|
||||
attribute C_WRITE_WIDTH_A of U0 : label is 1;
|
||||
attribute C_WRITE_WIDTH_B : integer;
|
||||
attribute C_WRITE_WIDTH_B of U0 : label is 1;
|
||||
attribute C_XDEVICEFAMILY : string;
|
||||
attribute C_XDEVICEFAMILY of U0 : label is "kintex7";
|
||||
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
|
||||
attribute x_interface_info : string;
|
||||
attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
|
||||
attribute x_interface_parameter : string;
|
||||
attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
|
||||
attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
|
||||
attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
|
||||
attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
|
||||
begin
|
||||
U0: entity work.data_1p5m_blk_mem_gen_v8_4_3
|
||||
port map (
|
||||
addra(10 downto 0) => addra(10 downto 0),
|
||||
addrb(10 downto 0) => B"00000000000",
|
||||
clka => clka,
|
||||
clkb => '0',
|
||||
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
|
||||
deepsleep => '0',
|
||||
dina(0) => '0',
|
||||
dinb(0) => '0',
|
||||
douta(0) => douta(0),
|
||||
doutb(0) => NLW_U0_doutb_UNCONNECTED(0),
|
||||
eccpipece => '0',
|
||||
ena => ena,
|
||||
enb => '0',
|
||||
injectdbiterr => '0',
|
||||
injectsbiterr => '0',
|
||||
rdaddrecc(10 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(10 downto 0),
|
||||
regcea => '0',
|
||||
regceb => '0',
|
||||
rsta => '0',
|
||||
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
|
||||
rstb => '0',
|
||||
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
|
||||
s_aclk => '0',
|
||||
s_aresetn => '0',
|
||||
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
|
||||
s_axi_arburst(1 downto 0) => B"00",
|
||||
s_axi_arid(3 downto 0) => B"0000",
|
||||
s_axi_arlen(7 downto 0) => B"00000000",
|
||||
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
|
||||
s_axi_arsize(2 downto 0) => B"000",
|
||||
s_axi_arvalid => '0',
|
||||
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
|
||||
s_axi_awburst(1 downto 0) => B"00",
|
||||
s_axi_awid(3 downto 0) => B"0000",
|
||||
s_axi_awlen(7 downto 0) => B"00000000",
|
||||
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
|
||||
s_axi_awsize(2 downto 0) => B"000",
|
||||
s_axi_awvalid => '0',
|
||||
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
|
||||
s_axi_bready => '0',
|
||||
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
|
||||
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
|
||||
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
|
||||
s_axi_injectdbiterr => '0',
|
||||
s_axi_injectsbiterr => '0',
|
||||
s_axi_rdaddrecc(10 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(10 downto 0),
|
||||
s_axi_rdata(0) => NLW_U0_s_axi_rdata_UNCONNECTED(0),
|
||||
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
|
||||
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
|
||||
s_axi_rready => '0',
|
||||
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
|
||||
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
|
||||
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
|
||||
s_axi_wdata(0) => '0',
|
||||
s_axi_wlast => '0',
|
||||
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
|
||||
s_axi_wstrb(0) => '0',
|
||||
s_axi_wvalid => '0',
|
||||
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
|
||||
shutdown => '0',
|
||||
sleep => '0',
|
||||
wea(0) => '0',
|
||||
web(0) => '0'
|
||||
);
|
||||
end STRUCTURE;
|
||||
-23
@@ -1,23 +0,0 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:34:17 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_stub.v
|
||||
// Design : data_1p5m
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
|
||||
module data_1p5m(clka, ena, addra, douta)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clka,ena,addra[10:0],douta[0:0]" */;
|
||||
input clka;
|
||||
input ena;
|
||||
input [10:0]addra;
|
||||
output [0:0]douta;
|
||||
endmodule
|
||||
-33
@@ -1,33 +0,0 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:34:17 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_stub.vhdl
|
||||
-- Design : data_1p5m
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity data_1p5m is
|
||||
Port (
|
||||
clka : in STD_LOGIC;
|
||||
ena : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
|
||||
douta : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end data_1p5m;
|
||||
|
||||
architecture stub of data_1p5m is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clka,ena,addra[10:0],douta[0:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
-214
@@ -1,214 +0,0 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||
// IP Revision: 3
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module data_1p5m (
|
||||
clka,
|
||||
ena,
|
||||
addra,
|
||||
douta
|
||||
);
|
||||
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
|
||||
input wire clka;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
|
||||
input wire ena;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
|
||||
input wire [10 : 0] addra;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
|
||||
output wire [0 : 0] douta;
|
||||
|
||||
blk_mem_gen_v8_4_3 #(
|
||||
.C_FAMILY("kintex7"),
|
||||
.C_XDEVICEFAMILY("kintex7"),
|
||||
.C_ELABORATION_DIR("./"),
|
||||
.C_INTERFACE_TYPE(0),
|
||||
.C_AXI_TYPE(1),
|
||||
.C_AXI_SLAVE_TYPE(0),
|
||||
.C_USE_BRAM_BLOCK(0),
|
||||
.C_ENABLE_32BIT_ADDRESS(0),
|
||||
.C_CTRL_ECC_ALGO("NONE"),
|
||||
.C_HAS_AXI_ID(0),
|
||||
.C_AXI_ID_WIDTH(4),
|
||||
.C_MEM_TYPE(3),
|
||||
.C_BYTE_SIZE(9),
|
||||
.C_ALGORITHM(1),
|
||||
.C_PRIM_TYPE(1),
|
||||
.C_LOAD_INIT_FILE(1),
|
||||
.C_INIT_FILE_NAME("data_1p5m.mif"),
|
||||
.C_INIT_FILE("data_1p5m.mem"),
|
||||
.C_USE_DEFAULT_DATA(0),
|
||||
.C_DEFAULT_DATA("0"),
|
||||
.C_HAS_RSTA(0),
|
||||
.C_RST_PRIORITY_A("CE"),
|
||||
.C_RSTRAM_A(0),
|
||||
.C_INITA_VAL("0"),
|
||||
.C_HAS_ENA(1),
|
||||
.C_HAS_REGCEA(0),
|
||||
.C_USE_BYTE_WEA(0),
|
||||
.C_WEA_WIDTH(1),
|
||||
.C_WRITE_MODE_A("WRITE_FIRST"),
|
||||
.C_WRITE_WIDTH_A(1),
|
||||
.C_READ_WIDTH_A(1),
|
||||
.C_WRITE_DEPTH_A(2048),
|
||||
.C_READ_DEPTH_A(2048),
|
||||
.C_ADDRA_WIDTH(11),
|
||||
.C_HAS_RSTB(0),
|
||||
.C_RST_PRIORITY_B("CE"),
|
||||
.C_RSTRAM_B(0),
|
||||
.C_INITB_VAL("0"),
|
||||
.C_HAS_ENB(0),
|
||||
.C_HAS_REGCEB(0),
|
||||
.C_USE_BYTE_WEB(0),
|
||||
.C_WEB_WIDTH(1),
|
||||
.C_WRITE_MODE_B("WRITE_FIRST"),
|
||||
.C_WRITE_WIDTH_B(1),
|
||||
.C_READ_WIDTH_B(1),
|
||||
.C_WRITE_DEPTH_B(2048),
|
||||
.C_READ_DEPTH_B(2048),
|
||||
.C_ADDRB_WIDTH(11),
|
||||
.C_HAS_MEM_OUTPUT_REGS_A(1),
|
||||
.C_HAS_MEM_OUTPUT_REGS_B(0),
|
||||
.C_HAS_MUX_OUTPUT_REGS_A(1),
|
||||
.C_HAS_MUX_OUTPUT_REGS_B(0),
|
||||
.C_MUX_PIPELINE_STAGES(0),
|
||||
.C_HAS_SOFTECC_INPUT_REGS_A(0),
|
||||
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
|
||||
.C_USE_SOFTECC(0),
|
||||
.C_USE_ECC(0),
|
||||
.C_EN_ECC_PIPE(0),
|
||||
.C_READ_LATENCY_A(1),
|
||||
.C_READ_LATENCY_B(1),
|
||||
.C_HAS_INJECTERR(0),
|
||||
.C_SIM_COLLISION_CHECK("ALL"),
|
||||
.C_COMMON_CLK(0),
|
||||
.C_DISABLE_WARN_BHV_COLL(0),
|
||||
.C_EN_SLEEP_PIN(0),
|
||||
.C_USE_URAM(0),
|
||||
.C_EN_RDADDRA_CHG(0),
|
||||
.C_EN_RDADDRB_CHG(0),
|
||||
.C_EN_DEEPSLEEP_PIN(0),
|
||||
.C_EN_SHUTDOWN_PIN(0),
|
||||
.C_EN_SAFETY_CKT(0),
|
||||
.C_DISABLE_WARN_BHV_RANGE(0),
|
||||
.C_COUNT_36K_BRAM("0"),
|
||||
.C_COUNT_18K_BRAM("1"),
|
||||
.C_EST_POWER_SUMMARY("Estimated Power for IP : 0.990811 mW")
|
||||
) inst (
|
||||
.clka(clka),
|
||||
.rsta(1'D0),
|
||||
.ena(ena),
|
||||
.regcea(1'D0),
|
||||
.wea(1'B0),
|
||||
.addra(addra),
|
||||
.dina(1'B0),
|
||||
.douta(douta),
|
||||
.clkb(1'D0),
|
||||
.rstb(1'D0),
|
||||
.enb(1'D0),
|
||||
.regceb(1'D0),
|
||||
.web(1'B0),
|
||||
.addrb(11'B0),
|
||||
.dinb(1'B0),
|
||||
.doutb(),
|
||||
.injectsbiterr(1'D0),
|
||||
.injectdbiterr(1'D0),
|
||||
.eccpipece(1'D0),
|
||||
.sbiterr(),
|
||||
.dbiterr(),
|
||||
.rdaddrecc(),
|
||||
.sleep(1'D0),
|
||||
.deepsleep(1'D0),
|
||||
.shutdown(1'D0),
|
||||
.rsta_busy(),
|
||||
.rstb_busy(),
|
||||
.s_aclk(1'H0),
|
||||
.s_aresetn(1'D0),
|
||||
.s_axi_awid(4'B0),
|
||||
.s_axi_awaddr(32'B0),
|
||||
.s_axi_awlen(8'B0),
|
||||
.s_axi_awsize(3'B0),
|
||||
.s_axi_awburst(2'B0),
|
||||
.s_axi_awvalid(1'D0),
|
||||
.s_axi_awready(),
|
||||
.s_axi_wdata(1'B0),
|
||||
.s_axi_wstrb(1'B0),
|
||||
.s_axi_wlast(1'D0),
|
||||
.s_axi_wvalid(1'D0),
|
||||
.s_axi_wready(),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(),
|
||||
.s_axi_bvalid(),
|
||||
.s_axi_bready(1'D0),
|
||||
.s_axi_arid(4'B0),
|
||||
.s_axi_araddr(32'B0),
|
||||
.s_axi_arlen(8'B0),
|
||||
.s_axi_arsize(3'B0),
|
||||
.s_axi_arburst(2'B0),
|
||||
.s_axi_arvalid(1'D0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'D0),
|
||||
.s_axi_injectsbiterr(1'D0),
|
||||
.s_axi_injectdbiterr(1'D0),
|
||||
.s_axi_sbiterr(),
|
||||
.s_axi_dbiterr(),
|
||||
.s_axi_rdaddrecc()
|
||||
);
|
||||
endmodule
|
||||
+1
-1
@@ -58,7 +58,7 @@ probe_out4
|
||||
|
||||
input clk;
|
||||
|
||||
output reg [2 : 0] probe_out0 = 'h0 ;
|
||||
output reg [1 : 0] probe_out0 = 'h2 ;
|
||||
output reg [0 : 0] probe_out1 = 'h0 ;
|
||||
output reg [31 : 0] probe_out2 = 'h00000000 ;
|
||||
output reg [1 : 0] probe_out3 = 'h3 ;
|
||||
|
||||
+1
-1
@@ -56,7 +56,7 @@
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
vio_manual_ctrl your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
.probe_out0(probe_out0), // output wire [2 : 0] probe_out0
|
||||
.probe_out0(probe_out0), // output wire [1 : 0] probe_out0
|
||||
.probe_out1(probe_out1), // output wire [0 : 0] probe_out1
|
||||
.probe_out2(probe_out2), // output wire [31 : 0] probe_out2
|
||||
.probe_out3(probe_out3), // output wire [1 : 0] probe_out3
|
||||
|
||||
+1
-1
@@ -55,7 +55,7 @@
|
||||
COMPONENT vio_manual_ctrl
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
probe_out0 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe_out0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe_out3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
|
||||
+794
-820
File diff suppressed because one or more lines are too long
+1145
-1180
File diff suppressed because it is too large
Load Diff
+4
-4
@@ -1,10 +1,10 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:34:28 2023
|
||||
// Date : Tue Mar 21 22:54:43 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v
|
||||
// D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v
|
||||
// Design : vio_manual_ctrl
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
@@ -16,9 +16,9 @@
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module vio_manual_ctrl(clk, probe_out0, probe_out1, probe_out2,
|
||||
probe_out3, probe_out4)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */;
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */;
|
||||
input clk;
|
||||
output [2:0]probe_out0;
|
||||
output [1:0]probe_out0;
|
||||
output [0:0]probe_out1;
|
||||
output [31:0]probe_out2;
|
||||
output [1:0]probe_out3;
|
||||
|
||||
+4
-4
@@ -1,10 +1,10 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:34:28 2023
|
||||
-- Date : Tue Mar 21 22:54:43 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl
|
||||
-- D:/vivado-git/projects/datalink_814/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl
|
||||
-- Design : vio_manual_ctrl
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
@@ -15,7 +15,7 @@ use IEEE.STD_LOGIC_1164.ALL;
|
||||
entity vio_manual_ctrl is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
@@ -28,7 +28,7 @@ architecture stub of vio_manual_ctrl is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]";
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
|
||||
-83
@@ -1,83 +0,0 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required
|
||||
# to simulate the design for a simulator, the directory structure
|
||||
# and the generated exported files.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. Simulate Design
|
||||
|
||||
To simulate design, cd to the simulator directory and execute the script.
|
||||
|
||||
For example:-
|
||||
|
||||
% cd questa
|
||||
% ./top.sh
|
||||
|
||||
The export simulation flow requires the Xilinx pre-compiled simulation library
|
||||
components for the target simulator. These components are referred using the
|
||||
'-lib_map_path' switch. If this switch is specified, then the export simulation
|
||||
will automatically set this library path in the generated script and update,
|
||||
copy the simulator setup file(s) in the exported directory.
|
||||
|
||||
If '-lib_map_path' is not specified, then the pre-compiled simulation library
|
||||
information will not be included in the exported scripts and that may cause
|
||||
simulation errors when running this script. Alternatively, you can provide the
|
||||
library information using this switch while executing the generated script.
|
||||
|
||||
For example:-
|
||||
|
||||
% ./top.sh -lib_map_path /design/questa/clibs
|
||||
|
||||
Please refer to the generated script header 'Prerequisite' section for more details.
|
||||
|
||||
2. Directory Structure
|
||||
|
||||
By default, if the -directory switch is not specified, export_simulation will
|
||||
create the following directory structure:-
|
||||
|
||||
<current_working_directory>/export_sim/<simulator>
|
||||
|
||||
For example, if the current working directory is /tmp/test, export_simulation
|
||||
will create the following directory path:-
|
||||
|
||||
/tmp/test/export_sim/questa
|
||||
|
||||
If -directory switch is specified, export_simulation will create a simulator
|
||||
sub-directory under the specified directory path.
|
||||
|
||||
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
|
||||
command will create the following directory:-
|
||||
|
||||
/tmp/test/my_test_area/func_sim/questa
|
||||
|
||||
By default, if -simulator is not specified, export_simulation will create a
|
||||
simulator sub-directory for each simulator and export the files for each simulator
|
||||
in this sub-directory respectively.
|
||||
|
||||
IMPORTANT: Please note that the simulation library path must be specified manually
|
||||
in the generated script for the respective simulator. Please refer to the generated
|
||||
script header 'Prerequisite' section for more details.
|
||||
|
||||
3. Exported script and files
|
||||
|
||||
Export simulation will create the driver shell script, setup files and copy the
|
||||
design sources in the output directory path.
|
||||
|
||||
By default, when the -script_name switch is not specified, export_simulation will
|
||||
create the following script name:-
|
||||
|
||||
<simulation_top>.sh (Unix)
|
||||
When exporting the files for an IP using the -of_objects switch, export_simulation
|
||||
will create the following script name:-
|
||||
|
||||
<ip-name>.sh (Unix)
|
||||
Export simulation will create the setup files for the target simulator specified
|
||||
with the -simulator switch.
|
||||
|
||||
For example, if the target simulator is "ies", export_simulation will create the
|
||||
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
|
||||
file.
|
||||
|
||||
-8192
File diff suppressed because it is too large
Load Diff
-154
@@ -1,154 +0,0 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : COSLUT_10_16bit.sh
|
||||
# Simulator : Aldec Active-HDL Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Sat Mar 18 23:35:15 +0800 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: COSLUT_10_16bit.sh [-help]
|
||||
# usage: COSLUT_10_16bit.sh [-lib_map_path]
|
||||
# usage: COSLUT_10_16bit.sh [-noclean_files]
|
||||
# usage: COSLUT_10_16bit.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'COSLUT_10_16bit.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
|
||||
# Script info
|
||||
echo -e "COSLUT_10_16bit.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
source compile.do 2>&1 | tee -a compile.log
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
runvsimsa -l simulate.log -do "do {simulate.do}"
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./COSLUT_10_16bit.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
map_setup_file $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
map_setup_file $2
|
||||
esac
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Map library.cfg file
|
||||
map_setup_file()
|
||||
{
|
||||
file="library.cfg"
|
||||
lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
|
||||
if [[ ($1 != "" && -e $1) ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
if [[ -e $src_file ]]; then
|
||||
vmap -link $lib_map_path
|
||||
fi
|
||||
fi
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./COSLUT_10_16bit.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: COSLUT_10_16bit.sh [-help]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-lib_map_path]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-reset_run]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
-49
@@ -1,49 +0,0 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Sat Mar 18 23:35:15 +0800 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./COSLUT_10_16bit.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './COSLUT_10_16bit.sh' script.
|
||||
|
||||
./COSLUT_10_16bit.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./COSLUT_10_16bit.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './COSLUT_10_16bit.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
-27
@@ -1,27 +0,0 @@
|
||||
vlib work
|
||||
vlib activehdl
|
||||
|
||||
vlib activehdl/xil_defaultlib
|
||||
vlib activehdl/xpm
|
||||
vlib activehdl/blk_mem_gen_v8_4_3
|
||||
|
||||
vmap xil_defaultlib activehdl/xil_defaultlib
|
||||
vmap xpm activehdl/xpm
|
||||
vmap blk_mem_gen_v8_4_3 activehdl/blk_mem_gen_v8_4_3
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 \
|
||||
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work blk_mem_gen_v8_4_3 -v2k5 \
|
||||
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
||||
|
||||
vlog -work xil_defaultlib -v2k5 \
|
||||
"../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
-8194
File diff suppressed because it is too large
Load Diff
-6
@@ -1,6 +0,0 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
||||
COSLUT_10_16bit.v,verilog,xil_defaultlib,../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
-71
@@ -1,71 +0,0 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
-17
@@ -1,17 +0,0 @@
|
||||
onbreak {quit -force}
|
||||
onerror {quit -force}
|
||||
|
||||
asim -t 1ps +access +r +m+COSLUT_10_16bit -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.COSLUT_10_16bit xil_defaultlib.glbl
|
||||
|
||||
do {wave.do}
|
||||
|
||||
view wave
|
||||
view structure
|
||||
|
||||
do {COSLUT_10_16bit.udo}
|
||||
|
||||
run -all
|
||||
|
||||
endsim
|
||||
|
||||
quit -force
|
||||
-2
@@ -1,2 +0,0 @@
|
||||
add wave *
|
||||
add wave /glbl/GSR
|
||||
-8192
File diff suppressed because it is too large
Load Diff
-175
@@ -1,175 +0,0 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : COSLUT_10_16bit.sh
|
||||
# Simulator : Cadence Incisive Enterprise Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Sat Mar 18 23:35:15 +0800 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: COSLUT_10_16bit.sh [-help]
|
||||
# usage: COSLUT_10_16bit.sh [-lib_map_path]
|
||||
# usage: COSLUT_10_16bit.sh [-noclean_files]
|
||||
# usage: COSLUT_10_16bit.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'COSLUT_10_16bit.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
# Directory path for design sources and include directories (if any) wrt this path
|
||||
ref_dir="."
|
||||
|
||||
# Override directory with 'export_sim_ref_dir' env path value if set in the shell
|
||||
if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
|
||||
ref_dir="$export_sim_ref_dir"
|
||||
fi
|
||||
|
||||
# Set the compiled library directory
|
||||
ref_lib_dir="."
|
||||
|
||||
# Command line options
|
||||
irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
|
||||
|
||||
# Design libraries
|
||||
design_libs=(xil_defaultlib xpm blk_mem_gen_v8_4_3)
|
||||
|
||||
# Simulation root library directory
|
||||
sim_lib_dir="ies_lib"
|
||||
|
||||
# Script info
|
||||
echo -e "COSLUT_10_16bit.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
execute
|
||||
}
|
||||
|
||||
# RUN_STEP: <execute>
|
||||
execute()
|
||||
{
|
||||
irun $irun_opts \
|
||||
-reflib "$ref_lib_dir/unisim:unisim" \
|
||||
-reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
|
||||
-reflib "$ref_lib_dir/secureip:secureip" \
|
||||
-reflib "$ref_lib_dir/unimacro:unimacro" \
|
||||
-reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
|
||||
-top xil_defaultlib.COSLUT_10_16bit \
|
||||
-f run.f \
|
||||
-top glbl \
|
||||
glbl.v
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./COSLUT_10_16bit.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
else
|
||||
ref_lib_dir=$2
|
||||
fi
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
esac
|
||||
|
||||
create_lib_dir
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Create design library directory paths
|
||||
create_lib_dir()
|
||||
{
|
||||
if [[ -e $sim_lib_dir ]]; then
|
||||
rm -rf $sim_lib_dir
|
||||
fi
|
||||
|
||||
for (( i=0; i<${#design_libs[*]}; i++ )); do
|
||||
lib="${design_libs[i]}"
|
||||
lib_dir="$sim_lib_dir/$lib"
|
||||
if [[ ! -e $lib_dir ]]; then
|
||||
mkdir -p $lib_dir
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
|
||||
create_lib_dir
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./COSLUT_10_16bit.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: COSLUT_10_16bit.sh [-help]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-lib_map_path]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-reset_run]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
-48
@@ -1,48 +0,0 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Sat Mar 18 23:35:15 +0800 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./COSLUT_10_16bit.sh
|
||||
|
||||
This command will launch the 'execute' function for the single-step flow. This
|
||||
function is called from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './COSLUT_10_16bit.sh' script.
|
||||
|
||||
./COSLUT_10_16bit.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./COSLUT_10_16bit.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './COSLUT_10_16bit.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
-8194
File diff suppressed because it is too large
Load Diff
-6
@@ -1,6 +0,0 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
||||
COSLUT_10_16bit.v,verilog,xil_defaultlib,../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
-71
@@ -1,71 +0,0 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
-17
@@ -1,17 +0,0 @@
|
||||
-makelib ies_lib/xil_defaultlib -sv \
|
||||
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
-endlib
|
||||
-makelib ies_lib/xpm \
|
||||
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/blk_mem_gen_v8_4_3 \
|
||||
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
||||
-endlib
|
||||
-makelib ies_lib/xil_defaultlib \
|
||||
"../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v" \
|
||||
-endlib
|
||||
-makelib ies_lib/xil_defaultlib \
|
||||
glbl.v
|
||||
-endlib
|
||||
|
||||
-8192
File diff suppressed because it is too large
Load Diff
-167
@@ -1,167 +0,0 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : COSLUT_10_16bit.sh
|
||||
# Simulator : Mentor Graphics ModelSim Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Sat Mar 18 23:35:15 +0800 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: COSLUT_10_16bit.sh [-help]
|
||||
# usage: COSLUT_10_16bit.sh [-lib_map_path]
|
||||
# usage: COSLUT_10_16bit.sh [-noclean_files]
|
||||
# usage: COSLUT_10_16bit.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'COSLUT_10_16bit.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
|
||||
# Script info
|
||||
echo -e "COSLUT_10_16bit.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
source compile.do 2>&1 | tee -a compile.log
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
vsim -64 -c -do "do {simulate.do}" -l simulate.log
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./COSLUT_10_16bit.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
copy_setup_file $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
copy_setup_file $2
|
||||
esac
|
||||
|
||||
create_lib_dir
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Copy modelsim.ini file
|
||||
copy_setup_file()
|
||||
{
|
||||
file="modelsim.ini"
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
lib_map_path="C:/Mentor/CompLib/2019.1.3"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
cp $src_file .
|
||||
fi
|
||||
}
|
||||
|
||||
# Create design library directory
|
||||
create_lib_dir()
|
||||
{
|
||||
lib_dir="modelsim_lib"
|
||||
if [[ -e $lib_dir ]]; then
|
||||
rm -rf $lib_dir
|
||||
fi
|
||||
|
||||
mkdir $lib_dir
|
||||
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
|
||||
create_lib_dir
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./COSLUT_10_16bit.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: COSLUT_10_16bit.sh [-help]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-lib_map_path]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-reset_run]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
-49
@@ -1,49 +0,0 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Sat Mar 18 23:35:15 +0800 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./COSLUT_10_16bit.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './COSLUT_10_16bit.sh' script.
|
||||
|
||||
./COSLUT_10_16bit.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./COSLUT_10_16bit.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './COSLUT_10_16bit.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
-14
@@ -1,14 +0,0 @@
|
||||
vlib modelsim_lib/work
|
||||
vlib modelsim_lib/msim
|
||||
|
||||
vlib modelsim_lib/msim/xil_defaultlib
|
||||
|
||||
vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
|
||||
|
||||
vlog -work xil_defaultlib -64 -incr \
|
||||
"../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v" \
|
||||
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
-8194
File diff suppressed because it is too large
Load Diff
-2
@@ -1,2 +0,0 @@
|
||||
COSLUT_10_16bit.v,verilog,xil_defaultlib,../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
-71
@@ -1,71 +0,0 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
-2590
File diff suppressed because it is too large
Load Diff
-16
@@ -1,16 +0,0 @@
|
||||
onbreak {quit -f}
|
||||
onerror {quit -f}
|
||||
|
||||
vsim -voptargs="+acc" -t 1ps -L blk_mem_gen_v8_4_3 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.COSLUT_10_16bit xil_defaultlib.glbl
|
||||
|
||||
do {wave.do}
|
||||
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
|
||||
do {COSLUT_10_16bit.udo}
|
||||
|
||||
run -all
|
||||
|
||||
quit -force
|
||||
-2
@@ -1,2 +0,0 @@
|
||||
add wave *
|
||||
add wave /glbl/GSR
|
||||
-8192
File diff suppressed because it is too large
Load Diff
-175
@@ -1,175 +0,0 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : COSLUT_10_16bit.sh
|
||||
# Simulator : Mentor Graphics Questa Advanced Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Sat Mar 18 23:35:15 +0800 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: COSLUT_10_16bit.sh [-help]
|
||||
# usage: COSLUT_10_16bit.sh [-lib_map_path]
|
||||
# usage: COSLUT_10_16bit.sh [-noclean_files]
|
||||
# usage: COSLUT_10_16bit.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'COSLUT_10_16bit.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
|
||||
# Script info
|
||||
echo -e "COSLUT_10_16bit.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
elaborate
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
source compile.do 2>&1 | tee -a compile.log
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <elaborate>
|
||||
elaborate()
|
||||
{
|
||||
source elaborate.do 2>&1 | tee -a elaborate.log
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
vsim -64 -c -do "do {simulate.do}" -l simulate.log
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./COSLUT_10_16bit.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
copy_setup_file $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
copy_setup_file $2
|
||||
esac
|
||||
|
||||
create_lib_dir
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Copy modelsim.ini file
|
||||
copy_setup_file()
|
||||
{
|
||||
file="modelsim.ini"
|
||||
lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
|
||||
if [[ ($1 != "" && -e $1) ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
cp $src_file .
|
||||
fi
|
||||
}
|
||||
|
||||
# Create design library directory
|
||||
create_lib_dir()
|
||||
{
|
||||
lib_dir="questa_lib"
|
||||
if [[ -e $lib_dir ]]; then
|
||||
rm -rf $lib_dir
|
||||
fi
|
||||
|
||||
mkdir $lib_dir
|
||||
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
|
||||
create_lib_dir
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./COSLUT_10_16bit.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: COSLUT_10_16bit.sh [-help]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-lib_map_path]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-reset_run]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
-49
@@ -1,49 +0,0 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Sat Mar 18 23:35:15 +0800 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./COSLUT_10_16bit.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './COSLUT_10_16bit.sh' script.
|
||||
|
||||
./COSLUT_10_16bit.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./COSLUT_10_16bit.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './COSLUT_10_16bit.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
-27
@@ -1,27 +0,0 @@
|
||||
vlib questa_lib/work
|
||||
vlib questa_lib/msim
|
||||
|
||||
vlib questa_lib/msim/xil_defaultlib
|
||||
vlib questa_lib/msim/xpm
|
||||
vlib questa_lib/msim/blk_mem_gen_v8_4_3
|
||||
|
||||
vmap xil_defaultlib questa_lib/msim/xil_defaultlib
|
||||
vmap xpm questa_lib/msim/xpm
|
||||
vmap blk_mem_gen_v8_4_3 questa_lib/msim/blk_mem_gen_v8_4_3
|
||||
|
||||
vlog -work xil_defaultlib -64 -sv \
|
||||
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -64 -93 \
|
||||
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work blk_mem_gen_v8_4_3 -64 \
|
||||
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
||||
|
||||
vlog -work xil_defaultlib -64 \
|
||||
"../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
-8194
File diff suppressed because it is too large
Load Diff
-1
@@ -1 +0,0 @@
|
||||
vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.COSLUT_10_16bit xil_defaultlib.glbl -o COSLUT_10_16bit_opt
|
||||
-6
@@ -1,6 +0,0 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
||||
COSLUT_10_16bit.v,verilog,xil_defaultlib,../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
-71
@@ -1,71 +0,0 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
-16
@@ -1,16 +0,0 @@
|
||||
onbreak {quit -f}
|
||||
onerror {quit -f}
|
||||
|
||||
vsim -t 1ps -lib xil_defaultlib COSLUT_10_16bit_opt
|
||||
|
||||
do {wave.do}
|
||||
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
|
||||
do {COSLUT_10_16bit.udo}
|
||||
|
||||
run -all
|
||||
|
||||
quit -force
|
||||
-2
@@ -1,2 +0,0 @@
|
||||
add wave *
|
||||
add wave /glbl/GSR
|
||||
-8192
File diff suppressed because it is too large
Load Diff
-154
@@ -1,154 +0,0 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : COSLUT_10_16bit.sh
|
||||
# Simulator : Aldec Riviera-PRO Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Sat Mar 18 23:35:15 +0800 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: COSLUT_10_16bit.sh [-help]
|
||||
# usage: COSLUT_10_16bit.sh [-lib_map_path]
|
||||
# usage: COSLUT_10_16bit.sh [-noclean_files]
|
||||
# usage: COSLUT_10_16bit.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'COSLUT_10_16bit.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
|
||||
# Script info
|
||||
echo -e "COSLUT_10_16bit.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
source compile.do 2>&1 | tee -a compile.log
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
runvsimsa -l simulate.log -do "do {simulate.do}"
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./COSLUT_10_16bit.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
map_setup_file $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
map_setup_file $2
|
||||
esac
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Map library.cfg file
|
||||
map_setup_file()
|
||||
{
|
||||
file="library.cfg"
|
||||
lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
|
||||
if [[ ($1 != "" && -e $1) ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
if [[ -e $src_file ]]; then
|
||||
vmap -link $lib_map_path
|
||||
fi
|
||||
fi
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./COSLUT_10_16bit.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: COSLUT_10_16bit.sh [-help]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-lib_map_path]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-reset_run]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
-49
@@ -1,49 +0,0 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Sat Mar 18 23:35:15 +0800 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./COSLUT_10_16bit.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './COSLUT_10_16bit.sh' script.
|
||||
|
||||
./COSLUT_10_16bit.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./COSLUT_10_16bit.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './COSLUT_10_16bit.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
-27
@@ -1,27 +0,0 @@
|
||||
vlib work
|
||||
vlib riviera
|
||||
|
||||
vlib riviera/xil_defaultlib
|
||||
vlib riviera/xpm
|
||||
vlib riviera/blk_mem_gen_v8_4_3
|
||||
|
||||
vmap xil_defaultlib riviera/xil_defaultlib
|
||||
vmap xpm riviera/xpm
|
||||
vmap blk_mem_gen_v8_4_3 riviera/blk_mem_gen_v8_4_3
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 \
|
||||
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work blk_mem_gen_v8_4_3 -v2k5 \
|
||||
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
||||
|
||||
vlog -work xil_defaultlib -v2k5 \
|
||||
"../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
-8194
File diff suppressed because it is too large
Load Diff
-6
@@ -1,6 +0,0 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
||||
COSLUT_10_16bit.v,verilog,xil_defaultlib,../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
-71
@@ -1,71 +0,0 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
-17
@@ -1,17 +0,0 @@
|
||||
onbreak {quit -force}
|
||||
onerror {quit -force}
|
||||
|
||||
asim -t 1ps +access +r +m+COSLUT_10_16bit -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.COSLUT_10_16bit xil_defaultlib.glbl
|
||||
|
||||
do {wave.do}
|
||||
|
||||
view wave
|
||||
view structure
|
||||
|
||||
do {COSLUT_10_16bit.udo}
|
||||
|
||||
run -all
|
||||
|
||||
endsim
|
||||
|
||||
quit -force
|
||||
-2
@@ -1,2 +0,0 @@
|
||||
add wave *
|
||||
add wave /glbl/GSR
|
||||
-8192
File diff suppressed because it is too large
Load Diff
-233
@@ -1,233 +0,0 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : COSLUT_10_16bit.sh
|
||||
# Simulator : Synopsys Verilog Compiler Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Sat Mar 18 23:35:15 +0800 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: COSLUT_10_16bit.sh [-help]
|
||||
# usage: COSLUT_10_16bit.sh [-lib_map_path]
|
||||
# usage: COSLUT_10_16bit.sh [-noclean_files]
|
||||
# usage: COSLUT_10_16bit.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'COSLUT_10_16bit.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
# Directory path for design sources and include directories (if any) wrt this path
|
||||
ref_dir="."
|
||||
|
||||
# Override directory with 'export_sim_ref_dir' env path value if set in the shell
|
||||
if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
|
||||
ref_dir="$export_sim_ref_dir"
|
||||
fi
|
||||
|
||||
# Command line options
|
||||
vlogan_opts="-full64"
|
||||
vhdlan_opts="-full64"
|
||||
vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
|
||||
vcs_sim_opts="-ucli -licqueue -l simulate.log"
|
||||
|
||||
# Design libraries
|
||||
design_libs=(xil_defaultlib xpm blk_mem_gen_v8_4_3)
|
||||
|
||||
# Simulation root library directory
|
||||
sim_lib_dir="vcs_lib"
|
||||
|
||||
# Script info
|
||||
echo -e "COSLUT_10_16bit.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
elaborate
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
vlogan -work xil_defaultlib $vlogan_opts -sverilog \
|
||||
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
2>&1 | tee -a vlogan.log
|
||||
|
||||
vhdlan -work xpm $vhdlan_opts \
|
||||
"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
2>&1 | tee -a vhdlan.log
|
||||
|
||||
vlogan -work blk_mem_gen_v8_4_3 $vlogan_opts +v2k \
|
||||
"$ref_dir/../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
||||
2>&1 | tee -a vlogan.log
|
||||
|
||||
vlogan -work xil_defaultlib $vlogan_opts +v2k \
|
||||
"$ref_dir/../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v" \
|
||||
2>&1 | tee -a vlogan.log
|
||||
|
||||
|
||||
vlogan -work xil_defaultlib $vlogan_opts +v2k \
|
||||
glbl.v \
|
||||
2>&1 | tee -a vlogan.log
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <elaborate>
|
||||
elaborate()
|
||||
{
|
||||
vcs $vcs_elab_opts xil_defaultlib.COSLUT_10_16bit xil_defaultlib.glbl -o COSLUT_10_16bit_simv
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
./COSLUT_10_16bit_simv $vcs_sim_opts -do simulate.do
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./COSLUT_10_16bit.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
create_lib_mappings $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
create_lib_mappings $2
|
||||
esac
|
||||
|
||||
create_lib_dir
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Define design library mappings
|
||||
create_lib_mappings()
|
||||
{
|
||||
file="synopsys_sim.setup"
|
||||
if [[ -e $file ]]; then
|
||||
if [[ ($1 == "") ]]; then
|
||||
return
|
||||
else
|
||||
rm -rf $file
|
||||
fi
|
||||
fi
|
||||
|
||||
touch $file
|
||||
|
||||
lib_map_path=""
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
fi
|
||||
|
||||
for (( i=0; i<${#design_libs[*]}; i++ )); do
|
||||
lib="${design_libs[i]}"
|
||||
mapping="$lib:$sim_lib_dir/$lib"
|
||||
echo $mapping >> $file
|
||||
done
|
||||
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
|
||||
echo $incl_ref >> $file
|
||||
fi
|
||||
}
|
||||
|
||||
# Create design library directory paths
|
||||
create_lib_dir()
|
||||
{
|
||||
if [[ -e $sim_lib_dir ]]; then
|
||||
rm -rf $sim_lib_dir
|
||||
fi
|
||||
|
||||
for (( i=0; i<${#design_libs[*]}; i++ )); do
|
||||
lib="${design_libs[i]}"
|
||||
lib_dir="$sim_lib_dir/$lib"
|
||||
if [[ ! -e $lib_dir ]]; then
|
||||
mkdir -p $lib_dir
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(ucli.key COSLUT_10_16bit_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc COSLUT_10_16bit_simv.daidir)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
|
||||
create_lib_dir
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./COSLUT_10_16bit.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: COSLUT_10_16bit.sh [-help]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-lib_map_path]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-reset_run]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
-49
@@ -1,49 +0,0 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Sat Mar 18 23:35:15 +0800 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./COSLUT_10_16bit.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './COSLUT_10_16bit.sh' script.
|
||||
|
||||
./COSLUT_10_16bit.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./COSLUT_10_16bit.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './COSLUT_10_16bit.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
-8194
File diff suppressed because it is too large
Load Diff
-6
@@ -1,6 +0,0 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
||||
COSLUT_10_16bit.v,verilog,xil_defaultlib,../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
-71
@@ -1,71 +0,0 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
-2
@@ -1,2 +0,0 @@
|
||||
run
|
||||
quit
|
||||
-8192
File diff suppressed because it is too large
Load Diff
-175
@@ -1,175 +0,0 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : COSLUT_10_16bit.sh
|
||||
# Simulator : Cadence Xcelium Parallel Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Sat Mar 18 23:35:15 +0800 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: COSLUT_10_16bit.sh [-help]
|
||||
# usage: COSLUT_10_16bit.sh [-lib_map_path]
|
||||
# usage: COSLUT_10_16bit.sh [-noclean_files]
|
||||
# usage: COSLUT_10_16bit.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'COSLUT_10_16bit.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
# Directory path for design sources and include directories (if any) wrt this path
|
||||
ref_dir="."
|
||||
|
||||
# Override directory with 'export_sim_ref_dir' env path value if set in the shell
|
||||
if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
|
||||
ref_dir="$export_sim_ref_dir"
|
||||
fi
|
||||
|
||||
# Set the compiled library directory
|
||||
ref_lib_dir="."
|
||||
|
||||
# Command line options
|
||||
xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
|
||||
|
||||
# Design libraries
|
||||
design_libs=(xil_defaultlib xpm blk_mem_gen_v8_4_3)
|
||||
|
||||
# Simulation root library directory
|
||||
sim_lib_dir="xcelium_lib"
|
||||
|
||||
# Script info
|
||||
echo -e "COSLUT_10_16bit.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
execute
|
||||
}
|
||||
|
||||
# RUN_STEP: <execute>
|
||||
execute()
|
||||
{
|
||||
xrun $xrun_opts \
|
||||
-reflib "$ref_lib_dir/unisim:unisim" \
|
||||
-reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
|
||||
-reflib "$ref_lib_dir/secureip:secureip" \
|
||||
-reflib "$ref_lib_dir/unimacro:unimacro" \
|
||||
-reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
|
||||
-top xil_defaultlib.COSLUT_10_16bit \
|
||||
-f run.f \
|
||||
-top glbl \
|
||||
glbl.v
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./COSLUT_10_16bit.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
else
|
||||
ref_lib_dir=$2
|
||||
fi
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
esac
|
||||
|
||||
create_lib_dir
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Create design library directory paths
|
||||
create_lib_dir()
|
||||
{
|
||||
if [[ -e $sim_lib_dir ]]; then
|
||||
rm -rf $sim_lib_dir
|
||||
fi
|
||||
|
||||
for (( i=0; i<${#design_libs[*]}; i++ )); do
|
||||
lib="${design_libs[i]}"
|
||||
lib_dir="$sim_lib_dir/$lib"
|
||||
if [[ ! -e $lib_dir ]]; then
|
||||
mkdir -p $lib_dir
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
|
||||
create_lib_dir
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./COSLUT_10_16bit.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: COSLUT_10_16bit.sh [-help]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-lib_map_path]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-reset_run]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
-48
@@ -1,48 +0,0 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Sat Mar 18 23:35:15 +0800 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./COSLUT_10_16bit.sh
|
||||
|
||||
This command will launch the 'execute' function for the single-step flow. This
|
||||
function is called from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './COSLUT_10_16bit.sh' script.
|
||||
|
||||
./COSLUT_10_16bit.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./COSLUT_10_16bit.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './COSLUT_10_16bit.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
-8194
File diff suppressed because it is too large
Load Diff
-6
@@ -1,6 +0,0 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
||||
COSLUT_10_16bit.v,verilog,xil_defaultlib,../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
-71
@@ -1,71 +0,0 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user