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update dl814_k7_coarse

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josh
2023-03-21 23:24:37 +08:00
parent 715dfd374f
commit bbe2e84c78
538 changed files with 36234 additions and 250834 deletions
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projects/datalink_814/dl814_k7_cal_coarse/rtl/system_top.v
+13 -35
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@@ -495,7 +495,6 @@ wire [11:0] tx_ch1_i;
wire [11:0] tx_ch1_q;
wire [11:0] tx_ch2_i;
wire [11:0] tx_ch2_q;
wire [ 3:0] bb_rshift ;
ad9361_tx_map_cmos_dual u_ad9361_tx_map
(
@@ -518,50 +517,29 @@ assign ad9361_2_tx_fb_clk = ad9361_1_tx_fb_clk;
// assign ad9361_2_tx_frame = ad9361_1_tx_frame ;
// assign ad9361_2_tx_data = ad9361_1_tx_data ;
tx_pre_process u_tx_pre_process
(
// clock & reset
.clk (sys_clk ),
.rst (sys_rst ),
// input data
.tx_data_ch1_i (tx_data_i ),
.tx_data_ch1_q (tx_data_q ),
.tx_data_ch2_i (tx_data_i ),
.tx_data_ch2_q (tx_data_q ),
// ad9361 calibration interface
.ad9361_tx_switch (ad9361_tx_switch ),
//
.bb_rshift (bb_rshift ),
// output data
.tx_ch1_i (tx_ch1_i ),
.tx_ch1_q (tx_ch1_q ),
.tx_ch2_i (tx_ch2_i ),
.tx_ch2_q (tx_ch2_q )
);
// <--------------------------------------------------------------------------->
// <--------------------- insert transmitter logic below ---------------------->
// <--------------------------------------------------------------------------->
wire [ 2:0] waveform_sel;
wire [ 1:0] waveform_sel;
wire sweep_on ;
wire [31:0] freq_set ;
wire [ 1:0] iq_sel ;
wire [ 3:0] bb_rshift ;
tx_control u_tx_control
tx_qpsk u_tx_qpsk
(
.clk (sys_clk ), // input clk
.rst (sys_rst ), // input rst
.tx_data_i (tx_data_i ), // output [11:0] tx_data_i
.tx_data_q (tx_data_q ), // output [11:0] tx_data_q
.clk (sys_clk ), // input clk
.rst (sys_rst ), // input rst
.tx_data_i (tx_data_i ), // output [11:0] tx_data_i
.tx_data_q (tx_data_q ), // output [11:0] tx_data_q
// debug ports
.waveform_sel (waveform_sel ), // input [ 2:0] waveform_sel
.sweep_on (sweep_on ), // input sweep_on
.freq_set (freq_set ), // input [31:0] freq_set
.iq_sel (iq_sel ), // input [ 1:0] iq_sel
.bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift
.waveform_sel (waveform_sel[1:0] ), // input [ 1:0] waveform_sel
.sweep_on (sweep_on ), // input sweep_on
.freq_set (freq_set ), // input [31:0] freq_set
.iq_sel (iq_sel ), // input [ 1:0] iq_sel
.bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift
);
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// Rx Signals //////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
@@ -914,7 +892,7 @@ ila_rx u_ila_rx_2
vio_manual_ctrl u_vio_manual_ctrl
(
.clk (sys_clk ), // input wire clk
.probe_out0 (waveform_sel[2:0] ), // output wire [2 : 0] probe_out0
.probe_out0 (waveform_sel[1:0] ), // output wire [1 : 0] probe_out0
.probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1
.probe_out2 (freq_set[31:0] ), // output wire [31 : 0] probe_out2
.probe_out3 (iq_sel[1:0] ), // output wire [1 : 0] probe_out3
projects/datalink_814/dl814_k7_cal_coarse/rtl/transmitter/AddrtoWaveform.v
-173
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@@ -1,173 +0,0 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/07/11 15:53:41
// Design Name:
// Module Name: AddrtoWaveform
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module AddrtoWaveform(
input clk,
input rst,
input [14:0] Phase_addr,
output reg [17:0] Cos_Wave = 18'd0,
output reg [17:0] Sin_Wave = 18'd0
);
reg [14:0] Phase_addr_D1 = 13'd0;
always @(posedge clk)
if(rst)
begin
Phase_addr_D1 <= 13'd0;
end
else
begin
Phase_addr_D1[14:0] <= Phase_addr[14:0];
end
reg [1:0] PhaseChange = 2'd0;
always @(posedge clk)
if(rst)
begin
PhaseChange[1:0]<= 2'd0;
end
else
begin
PhaseChange[1:0]<= Phase_addr_D1[14:13];
end
reg [1:0] PhaseChange_D1 = 2'd0; reg [1:0] PhaseChange_D2 = 2'd0;
reg [1:0] PhaseChange_D3 = 2'd0; reg [1:0] PhaseChange_D4 = 2'd0;
always @(posedge clk)
if(rst)
begin
PhaseChange_D1[1:0] <= 2'd0;
PhaseChange_D2[1:0] <= 2'd0;
PhaseChange_D3[1:0] <= 2'd0;
PhaseChange_D4[1:0] <= 2'd0;
end
else
begin
PhaseChange_D1[1:0] <= PhaseChange[1:0];
PhaseChange_D2[1:0] <= PhaseChange_D1[1:0];
PhaseChange_D3[1:0] <= PhaseChange_D2[1:0];
PhaseChange_D4[1:0] <= PhaseChange_D3[1:0];
end
reg [12:0] Phase_addr_D2 = 13'd0;
always @(posedge clk)
if(rst)
begin
Phase_addr_D2[12:0]<= 13'd0;
end
else
begin
Phase_addr_D2[12:0]<= Phase_addr_D1[12:0];
end
reg [12:0]Cos_addr = 13'd0;
reg [12:0]Sin_addr = 13'd0;
always @(posedge clk)
if(rst)
begin
Cos_addr[12:0] <= 13'd0;
Sin_addr[12:0] <= 13'd0;
end
else
begin
case(PhaseChange[1:0])
2'd0:
begin
Cos_addr[12:0] <= Phase_addr_D2[12:0];
Sin_addr[12:0] <= 13'd8191 - Phase_addr_D2[12:0];
end
2'd1:
begin
Cos_addr[12:0] <= 13'd8191 - Phase_addr_D2[12:0];
Sin_addr[12:0] <= Phase_addr_D2[12:0];
end
2'd2:
begin
Cos_addr[12:0] <= Phase_addr_D2[12:0];
Sin_addr[12:0] <= 13'd8191 - Phase_addr_D2[12:0];
end
2'd3:
begin
Cos_addr[12:0] <= 13'd8191 - Phase_addr_D2[12:0];
Sin_addr[12:0] <= Phase_addr_D2[12:0];
end
default:
begin
Cos_addr[12:0] <= 13'd0;
Sin_addr[12:0] <= 13'd0;
end
endcase
end
wire [17:0] Cos_dout;
wire [17:0] Sin_dout;
COSLUT_10_16bit COSLUT_10_16bit (
.clka(clk), // input wire clka
.addra(Cos_addr[12:0]), // input wire [9 : 0] addra
.douta(Cos_dout[17:0]), // output wire [15 : 0] douta
.clkb(clk), // input wire clkb
.addrb(Sin_addr[12:0]), // input wire [9 : 0] addrb
.doutb(Sin_dout[17:0]) // output wire [15 : 0] doutb
);
always @(posedge clk)
if(rst)
begin
Cos_Wave[17:0] <= 16'd0;
Sin_Wave[17:0] <= 16'd0;
end
else
begin
case(PhaseChange_D4[1:0])
2'd0:
begin
Cos_Wave[17:0] <= Cos_dout[17:0];
Sin_Wave[17:0] <= Sin_dout[17:0];
end
2'd1:
begin
Cos_Wave[17:0] <= ~Cos_dout[17:0] + 18'd1;
Sin_Wave[17:0] <= Sin_dout[17:0];
end
2'd2:
begin
Cos_Wave[17:0] <= ~Cos_dout[17:0] + 18'd1;
Sin_Wave[17:0] <= ~Sin_dout[17:0] + 18'd1;
end
2'd3:
begin
Cos_Wave[17:0] <= Cos_dout[17:0];
Sin_Wave[17:0] <= ~Sin_dout[17:0] + 18'd1;
end
default:
begin
Cos_Wave[17:0] <= 18'd0;
Sin_Wave[17:0] <= 18'd0;
end
endcase
end
endmodule
projects/datalink_814/dl814_k7_cal_coarse/rtl/transmitter/GMSK_send.v
-213
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@@ -1,213 +0,0 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/07/11 15:13:23
// Design Name:
// Module Name: GMSK_send
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GMSK_send(
input clk_48M ,
input rst ,
output [11:0] gmsk_12M_i,
output [11:0] gmsk_12M_q,
output [11:0] gmsk_1p5m_i,
output [11:0] gmsk_1p5m_q
);
wire [17:0] gmsk_send1p5M_I ;
wire [17:0] gmsk_send1p5M_Q ;
wire [17:0] gmsk_send12M_I ;
wire [17:0] gmsk_send12M_Q ;
//ROM核输出数据 1.5M基带数据
reg [4:0] cnt_32_data = 5'd0 ;
reg [10:0] addra_1p5m = 11'd0 ;
wire data_bio_1p5M;
reg Rc_nd;
data_1p5m data_1p5m (
.clka(clk_48M), // input wire clka
.ena(1'b1), // input wire ena
.addra(addra_1p5m), // input wire [10 : 0] addra
.douta(data_bio_1p5M) // output wire [0 : 0] douta
);
always @(posedge clk_48M)begin
if(cnt_32_data == 5'd31)begin
cnt_32_data <= 5'd0;
addra_1p5m <= addra_1p5m + 11'd1;
Rc_nd <= 1'b1;
end
else begin
addra_1p5m <= addra_1p5m;
cnt_32_data <= cnt_32_data + 5'd1;
Rc_nd <= 1'b0;
end
end
//
reg Rc_data_buff = 0;
reg Minus_1_Npower = 0;
always @(posedge clk_48M)begin
if(Rc_nd)
Rc_data_buff <= data_bio_1p5M;
Minus_1_Npower <= !Minus_1_Npower;
end
//预编码
reg precode_nd = 1'b0 ;
reg [1:0] precode_data = 2'd0 ;
always @(posedge clk_48M)begin
if(Rc_nd)begin
precode_nd <= 1'b1;
precode_data <= {data_bio_1p5M ^ Rc_data_buff ^ Minus_1_Npower,1'b1} ;
end
else begin
precode_nd <= 1'b0;
precode_data <= precode_data;
end
end
//高斯滤波器基带数据成型
wire precode_tready_1mp5;
wire GaussFir_dout_valid_1mp5;
wire [15:0] GaussFir_dout_1mp5;
GaussFir_1mp5 GaussFir_1mp5 (
.aclk(clk_48M), // input wire aclk
.s_axis_data_tvalid(precode_nd), // input wire s_axis_data_tvalid
.s_axis_data_tready(precode_tready_1mp5), // output wire s_axis_data_tready
.s_axis_data_tdata({{6{precode_data[1]}},precode_data}), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid(GaussFir_dout_valid_1mp5), // output wire m_axis_data_tvalid
.m_axis_data_tdata(GaussFir_dout_1mp5[15:0]) // output wire [15 : 0] m_axis_data_tdata
);
//存储相位地址
reg signed [15:0] DDS_addra=16'd0;
always @ (posedge clk_48M) begin
if(rst)
DDS_addra[15:0] <= 15'd0;
else
DDS_addra[15:0] <= GaussFir_dout_1mp5[15:0];
end
reg [17:0] phase_addr = 18'd0;
always @ (posedge clk_48M)begin
phase_addr[17:0] <= phase_addr[17:0] + {{2{DDS_addra[15]}},DDS_addra[15:0]};
end
//相位累积进行基带调制1pm5
AddrtoWaveform AddrtoWaveform(
.clk ( clk_48M) ,
.rst ( rst ) ,
.Phase_addr (phase_addr[17:2]) ,
.Cos_Wave ( gmsk_send1p5M_I[17:0] ),
.Sin_Wave ( gmsk_send1p5M_Q[17:0] )
);
//ROM核输出数据 12M
reg [2:0] cnt_4_data = 3'd0;
reg [10:0] addra_12m = 11'd0;
wire data_bio_12M;
reg Rc_nd_12m = 1'b0;
data_1p5m data_12m (
.clka(clk_48M), // input wire clka
.ena(1'b1), // input wire ena
.addra(addra_12m), // input wire [10 : 0] addra
.douta(data_bio_12M) // output wire [0 : 0] douta
);
always @(posedge clk_48M)begin
if(cnt_4_data == 3'd3)begin
cnt_4_data <= 3'd0;
addra_12m <= addra_12m + 11'd1;
Rc_nd_12m <= 1'b1;
end
else begin
addra_12m <= addra_12m;
cnt_4_data <= cnt_4_data + 3'd1;
Rc_nd_12m <= 1'b0;
end
end
reg Rc_data_buff_12m = 0;
reg Minus_1_Npower_12m = 0;
always @(posedge clk_48M)begin
if(Rc_nd_12m)
Rc_data_buff_12m <= data_bio_12M;
Minus_1_Npower_12m <= !Minus_1_Npower_12m;
end
//预编码
reg precode_nd_12m = 1'b0 ;
reg [1:0] precode_data_12m = 2'd0 ;
always @(posedge clk_48M)begin
if(Rc_nd_12m)begin
precode_nd_12m <= 1'b1;
precode_data_12m <= {data_bio_12M ^ Rc_data_buff_12m ^ Minus_1_Npower_12m,1'b1};
end
else begin
precode_nd_12m <= 1'b0;
precode_data_12m <= precode_data_12m;
end
end
//经过高斯低通滤波器
wire precode_tready_12m;
wire GaussFir_dout_valid_12m;
wire [15:0] GaussFir_dout_12m;
GaussFir_12m GaussFir_12m(
.aclk(clk_48M), // input wire aclk
.s_axis_data_tvalid(precode_nd_12m), // input wire s_axis_data_tvalid
.s_axis_data_tready(precode_tready_12m), // output wire s_axis_data_tready
.s_axis_data_tdata({{6{precode_data_12m[1]}},precode_data_12m}), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid(GaussFir_dout_valid_12m), // output wire m_axis_data_tvalid
.m_axis_data_tdata(GaussFir_dout_12m[15:0]) // output wire [15 : 0] m_axis_data_tdata
);
//相位累积进行基带调制1pm5
reg signed [15:0] DDS_addra_12M=16'd0;
always @ (posedge clk_48M) begin
if(rst)
DDS_addra_12M[15:0] <= 15'd0;
else
DDS_addra_12M[15:0] <= {GaussFir_dout_12m[15:0]};
end
reg [17:0] phase_addr_12M = 18'd0;
always @ (posedge clk_48M)begin
phase_addr_12M[17:0] <= phase_addr_12M[17:0] + {{2{DDS_addra_12M[15]}},DDS_addra_12M[15:0]};
end
AddrtoWaveform AddrtoWaveform_12M(
.clk ( clk_48M) ,
.rst ( rst ) ,
.Phase_addr ( phase_addr_12M[17:3]) ,
.Cos_Wave ( gmsk_send12M_I[17:0] ),
.Sin_Wave ( gmsk_send12M_Q[17:0] )
);
//截位输出数据
assign gmsk_12M_i [11:0] = gmsk_send12M_I [17:6];
assign gmsk_12M_q [11:0] = gmsk_send12M_Q [17:6];
assign gmsk_1p5m_i [11:0] = gmsk_send1p5M_I [17:6];
assign gmsk_1p5m_q [11:0] = gmsk_send1p5M_Q [17:6];
endmodule
projects/datalink_814/dl814_k7_cal_coarse/rtl/transmitter/tx_control.v
-93
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@@ -1,93 +0,0 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/03/06 16:15:00
// Design Name:
// Module Name: tx_control
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tx_control
(
input clk ,
input rst ,
output [11:0] tx_data_i ,
output [11:0] tx_data_q ,
// debug ports
input [ 2:0] waveform_sel,
input sweep_on ,
input [31:0] freq_set ,
input [ 1:0] iq_sel ,
input [ 3:0] bb_rshift
);
wire [11:0] gmsk_12m_i, gmsk_12m_q;
wire [11:0] gmsk_1p5m_i, gmsk_1p5m_q;
wire [11:0] qpsk_i, qpsk_q;
GMSK_send u_GMSK_send
(
.clk_48M (clk ),
.rst (rst ),
.gmsk_12M_i (gmsk_12m_i ),
.gmsk_12M_q (gmsk_12m_q ),
.gmsk_1p5m_i (gmsk_1p5m_i ),
.gmsk_1p5m_q (gmsk_1p5m_q )
);
tx_qpsk u_tx_qpsk
(
.clk (clk ), // input clk
.rst (rst ), // input rst
.tx_data_i (qpsk_i ), // output [11:0] tx_data_i
.tx_data_q (qpsk_q ), // output [11:0] tx_data_q
// debug ports
.waveform_sel (waveform_sel[1:0] ), // input [ 1:0] waveform_sel
.sweep_on (sweep_on ), // input sweep_on
.freq_set (freq_set ), // input [31:0] freq_set
.iq_sel (iq_sel ), // input [ 1:0] iq_sel
.bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift
);
// tx buf
reg [11:0] tx_data_i_buf = 'b0;
reg [11:0] tx_data_q_buf = 'b0;
assign tx_data_i = tx_data_i_buf;
assign tx_data_q = tx_data_q_buf;
always @(posedge clk) begin
if (rst) begin
tx_data_i_buf <= 'b0;
tx_data_q_buf <= 'b0;
end
else casex (waveform_sel)
3'b10x: begin
tx_data_i_buf <= gmsk_12m_i;
tx_data_q_buf <= gmsk_12m_q;
end
3'b11x: begin
tx_data_i_buf <= gmsk_1p5m_i;
tx_data_q_buf <= gmsk_1p5m_q;
end
default: begin
tx_data_i_buf <= qpsk_i;
tx_data_q_buf <= qpsk_q;
end
endcase
end
endmodule