Update gitignore, add dl814_z7 project

gitignore structure is updated to work with single and multi project situation under a single project directory

projects/datalink_814/dl814_z7/rtl/glink_smartncnt_intf.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2022/08/26 14:27:08
+// Design Name: 
+// Module Name: glink_smartncnt_intf
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module glink_smartncnt_intf(
+   input          clk                        ,
+   input          rst_n                      ,
+
+   output [31:0]  glink_gpio_i_0             ,
+   output [31:0]  glink_gpio_i_1             ,
+   input  [31:0]  glink_gpio_o_0             ,
+   input  [31:0]  glink_gpio_o_1             ,
+
+   output  [11:0] i_node_id                  ,
+   output         i_node_id_par              ,
+   output  [15:0] i_smartnc_2nd_cfg          ,
+   output  [15:0] i_smartnc_3rd_cfg          ,
+   output  [15:0] i_smartnt_cfg              ,
+         
+   output         smartnc_trans_trig         ,//gpio control
+   output         smartnc_trans_reset        ,//gpio control
+   input          smartnc_trans_idle         ,
+   input          smartnc_trans_err          ,//gpio control
+   output  [15:0] smartnc_intf_tx_fifo_wdata ,
+   output         smartnc_intf_tx_fifo_wr_en ,
+   input          smartnc_intf_tx_fifo_afull ,
+   input          smartnc_intf_rx_fifo_empty ,//useless
+   input  [15:0]  smartnc_intf_rx_fifo_rdata ,//useless
+   output         smartnc_intf_rx_fifo_rd_en ,//useless
+
+   input          smartnt_intf_cmd_proc_req  ,
+   output         smartnt_intf_cmd_proc_ack  ,
+   input          smartnt_intf_rx_fifo_empty ,
+   input  [15:0]  smartnt_intf_rx_fifo_rdata ,
+   output         smartnt_intf_rx_fifo_rd_en ,
+   output [15:0]  smartnt_intf_tx_fifo_wdata ,//useless
+   output         smartnt_intf_tx_fifo_wr_en ,//useless
+
+   input [15:0]   glink_tx_fifo_tdata        ,
+   input          glink_tx_fifo_tlast        ,
+   output         glink_tx_fifo_tready       ,
+   input          glink_tx_fifo_tvalid       ,
+
+   output [15:0]  glink_rx_fifo_tdata        ,
+   output         glink_rx_fifo_tlast        ,
+   input          glink_rx_fifo_tready       ,
+   output         glink_rx_fifo_tvalid
+);
+
+wire  smartnc_trans_trig_d0;
+
+//control
+assign i_node_id[11:0] = glink_gpio_o_0[11:0];
+assign i_node_id_par = ~(^i_node_id);
+assign smartnc_trans_trig_d0 = glink_gpio_o_0[12];
+assign smartnc_trans_reset = glink_gpio_o_0[13];
+assign glink_gpio_i_0[14] = smartnc_trans_idle;
+assign glink_gpio_i_0[15] = smartnc_trans_err;
+assign i_smartnt_cfg = glink_gpio_o_0[31:16];
+assign i_smartnc_2nd_cfg = glink_gpio_o_1[15:0];
+assign i_smartnc_3rd_cfg = glink_gpio_o_1[31:16];
+
+reg   smartnc_trans_trig_d1;
+reg   smartnc_trans_trig_d2;
+reg   smartnc_trans_trig_d3;
+
+always @(posedge clk) begin
+   if(~rst_n) begin
+      smartnc_trans_trig_d1 <= 1'd0;
+      smartnc_trans_trig_d2 <= 1'd0;
+      smartnc_trans_trig_d3 <= 1'd0;
+   end
+   else begin
+      smartnc_trans_trig_d1 <= smartnc_trans_trig_d0;
+      smartnc_trans_trig_d2 <= smartnc_trans_trig_d1;
+      smartnc_trans_trig_d3 <= smartnc_trans_trig_d2;
+   end
+end
+
+assign smartnc_trans_trig = smartnc_trans_trig_d3^smartnc_trans_trig_d2;
+
+//useless interface
+assign smartnc_intf_rx_fifo_rd_en = 1'b0;
+assign smartnt_intf_tx_fifo_wdata = 16'b0;   
+assign smartnt_intf_tx_fifo_wr_en = 1'b0;   
+
+//stream_fifo_out   to  nc_tx_fifo
+assign smartnc_intf_tx_fifo_wdata = glink_tx_fifo_tdata;
+assign smartnc_intf_tx_fifo_wr_en = glink_tx_fifo_tvalid;
+assign glink_tx_fifo_tready = ~smartnc_intf_tx_fifo_afull;
+
+// nt_rx_fifo  to  stream_fifo_in
+wire glink_recv_active;
+reg glink_recv_active_d0;
+reg glink_recv_active_d1;
+reg glink_recv_active_d2;
+
+assign glink_recv_active = smartnt_intf_cmd_proc_req & ~smartnt_intf_rx_fifo_empty & glink_rx_fifo_tready;
+always @(posedge clk) begin
+   if(~rst_n) begin
+      glink_recv_active_d0 <= 1'b0;
+      glink_recv_active_d1 <= 1'b0;
+      glink_recv_active_d2 <= 1'b0;
+   end
+   else begin
+      glink_recv_active_d0 <= glink_recv_active    ;
+      glink_recv_active_d1 <= glink_recv_active_d0 ;
+      glink_recv_active_d2 <= glink_recv_active_d1 ;
+   end
+end
+
+assign smartnt_intf_cmd_proc_ack    = ~glink_recv_active_d1 & glink_recv_active_d2  ;
+assign glink_rx_fifo_tlast          = ~glink_recv_active_d0 & glink_recv_active_d1  ;     
+assign smartnt_intf_rx_fifo_rd_en   = glink_recv_active_d1                          ;
+assign glink_rx_fifo_tvalid         = glink_recv_active_d1                          ;
+assign glink_rx_fifo_tdata          = smartnt_intf_rx_fifo_rdata                    ;
+
+endmodule