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simulated dl814_k7_beam

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This commit is contained in:
Josh Gao
2023-03-23 11:36:28 +08:00
parent 5c679def58
commit d69ca67c60
217 changed files with 29610 additions and 8899 deletions
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projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/hdl/system_bd_wrapper.v
+3 -3
View File
@@ -1,8 +1,8 @@
//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
//Date : Sun Mar 19 00:32:52 2023
//Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
//Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
//Date : Wed Mar 22 22:51:50 2023
//Host : localhost.localdomain running 64-bit unknown
//Command : generate_target system_bd_wrapper.bd
//Design : system_bd_wrapper
//Purpose : IP block netlist
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/hw_handoff/system_bd.hwh
+11 -135
View File
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sun Mar 19 00:32:53 2023" VIVADOVERSION="2019.1.3">
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Wed Mar 22 22:51:55 2023" VIVADOVERSION="2019.1.3">
<SYSTEMINFO ARCH="kintex7" DEVICE="7k410t" NAME="system_bd" PACKAGE="ffg900" SPEEDGRADE="-2"/>
@@ -804,22 +804,26 @@
<CONNECTION INSTANCE="rst_clk_wiz_25M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M02_ACLK" SIGIS="clk" SIGNAME="clk_wiz_25M_clk_out1">
<CONNECTIONS>
<CONNECTION INSTANCE="clk_wiz_25M" PORT="clk_out1"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M02_ARESETN" SIGIS="rst" SIGNAME="rst_clk_wiz_25M_peripheral_aresetn">
<CONNECTIONS>
<CONNECTION INSTANCE="rst_clk_wiz_25M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_S00_AXI_awaddr">
<CONNECTIONS>
<CONNECTION INSTANCE="microblaze_ps" PORT="M_AXI_DP_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S00_AXI_awlen" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awsize" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awburst" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awcache" SIGIS="undef"/>
<PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_S00_AXI_awprot">
<CONNECTIONS>
<CONNECTION INSTANCE="microblaze_ps" PORT="M_AXI_DP_AWPROT"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_interconnect_S00_AXI_awvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="microblaze_ps" PORT="M_AXI_DP_AWVALID"/>
@@ -840,7 +844,6 @@
<CONNECTION INSTANCE="microblaze_ps" PORT="M_AXI_DP_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_interconnect_S00_AXI_wvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="microblaze_ps" PORT="M_AXI_DP_WVALID"/>
@@ -871,17 +874,11 @@
<CONNECTION INSTANCE="microblaze_ps" PORT="M_AXI_DP_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S00_AXI_arlen" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_arsize" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_arburst" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_arcache" SIGIS="undef"/>
<PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_S00_AXI_arprot">
<CONNECTIONS>
<CONNECTION INSTANCE="microblaze_ps" PORT="M_AXI_DP_ARPROT"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_interconnect_S00_AXI_arvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="microblaze_ps" PORT="M_AXI_DP_ARVALID"/>
@@ -902,7 +899,6 @@
<CONNECTION INSTANCE="microblaze_ps" PORT="M_AXI_DP_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef"/>
<PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_interconnect_S00_AXI_rvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="microblaze_ps" PORT="M_AXI_DP_RVALID"/>
@@ -918,18 +914,11 @@
<CONNECTION INSTANCE="axi_spi_engine_axi_spi_engine" PORT="s_axi_awaddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M00_AXI_awlen" SIGIS="undef"/>
<PORT DIR="O" NAME="M00_AXI_awsize" SIGIS="undef"/>
<PORT DIR="O" NAME="M00_AXI_awburst" SIGIS="undef"/>
<PORT DIR="O" NAME="M00_AXI_awlock" SIGIS="undef"/>
<PORT DIR="O" NAME="M00_AXI_awcache" SIGIS="undef"/>
<PORT DIR="O" LEFT="2" NAME="M00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_M00_AXI_awprot">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_spi_engine_axi_spi_engine" PORT="s_axi_awprot"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M00_AXI_awregion" SIGIS="undef"/>
<PORT DIR="O" NAME="M00_AXI_awqos" SIGIS="undef"/>
<PORT DIR="O" NAME="M00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_interconnect_M00_AXI_awvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_spi_engine_axi_spi_engine" PORT="s_axi_awvalid"/>
@@ -950,7 +939,6 @@
<CONNECTION INSTANCE="axi_spi_engine_axi_spi_engine" PORT="s_axi_wstrb"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef"/>
<PORT DIR="O" NAME="M00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_interconnect_M00_AXI_wvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_spi_engine_axi_spi_engine" PORT="s_axi_wvalid"/>
@@ -981,18 +969,11 @@
<CONNECTION INSTANCE="axi_spi_engine_axi_spi_engine" PORT="s_axi_araddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M00_AXI_arlen" SIGIS="undef"/>
<PORT DIR="O" NAME="M00_AXI_arsize" SIGIS="undef"/>
<PORT DIR="O" NAME="M00_AXI_arburst" SIGIS="undef"/>
<PORT DIR="O" NAME="M00_AXI_arlock" SIGIS="undef"/>
<PORT DIR="O" NAME="M00_AXI_arcache" SIGIS="undef"/>
<PORT DIR="O" LEFT="2" NAME="M00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_M00_AXI_arprot">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_spi_engine_axi_spi_engine" PORT="s_axi_arprot"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M00_AXI_arregion" SIGIS="undef"/>
<PORT DIR="O" NAME="M00_AXI_arqos" SIGIS="undef"/>
<PORT DIR="O" NAME="M00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_interconnect_M00_AXI_arvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_spi_engine_axi_spi_engine" PORT="s_axi_arvalid"/>
@@ -1013,7 +994,6 @@
<CONNECTION INSTANCE="axi_spi_engine_axi_spi_engine" PORT="s_axi_rresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef"/>
<PORT DIR="I" NAME="M00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_interconnect_M00_AXI_rvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_spi_engine_axi_spi_engine" PORT="s_axi_rvalid"/>
@@ -1025,63 +1005,30 @@
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M01_AXI_awaddr" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_awlen" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_awsize" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_awburst" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_awlock" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_awcache" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_awprot" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_awregion" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_awqos" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_awvalid" SIGIS="undef"/>
<PORT DIR="I" NAME="M01_AXI_awready" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_wdata" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_wstrb" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_wlast" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_wvalid" SIGIS="undef"/>
<PORT DIR="I" NAME="M01_AXI_wready" SIGIS="undef"/>
<PORT DIR="I" NAME="M01_AXI_bresp" SIGIS="undef"/>
<PORT DIR="I" NAME="M01_AXI_bvalid" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_bready" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_araddr" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_arlen" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_arsize" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_arburst" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_arlock" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_arcache" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_arprot" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_arregion" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_arqos" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_arvalid" SIGIS="undef"/>
<PORT DIR="I" NAME="M01_AXI_arready" SIGIS="undef"/>
<PORT DIR="I" NAME="M01_AXI_rdata" SIGIS="undef"/>
<PORT DIR="I" NAME="M01_AXI_rresp" SIGIS="undef"/>
<PORT DIR="I" NAME="M01_AXI_rlast" SIGIS="undef"/>
<PORT DIR="I" NAME="M01_AXI_rvalid" SIGIS="undef"/>
<PORT DIR="O" NAME="M01_AXI_rready" SIGIS="undef"/>
<PORT DIR="I" NAME="M02_ACLK" SIGIS="clk" SIGNAME="clk_wiz_25M_clk_out1">
<CONNECTIONS>
<CONNECTION INSTANCE="clk_wiz_25M" PORT="clk_out1"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M02_ARESETN" SIGIS="rst" SIGNAME="rst_clk_wiz_25M_peripheral_aresetn">
<CONNECTIONS>
<CONNECTION INSTANCE="rst_clk_wiz_25M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="31" NAME="M02_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_s_axi_awaddr">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_gpio" PORT="s_axi_awaddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M02_AXI_awlen" SIGIS="undef"/>
<PORT DIR="O" NAME="M02_AXI_awsize" SIGIS="undef"/>
<PORT DIR="O" NAME="M02_AXI_awburst" SIGIS="undef"/>
<PORT DIR="O" NAME="M02_AXI_awlock" SIGIS="undef"/>
<PORT DIR="O" NAME="M02_AXI_awcache" SIGIS="undef"/>
<PORT DIR="O" NAME="M02_AXI_awprot" SIGIS="undef"/>
<PORT DIR="O" NAME="M02_AXI_awregion" SIGIS="undef"/>
<PORT DIR="O" NAME="M02_AXI_awqos" SIGIS="undef"/>
<PORT DIR="O" LEFT="0" NAME="M02_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_s_axi_awvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_gpio" PORT="s_axi_awvalid"/>
@@ -1102,7 +1049,6 @@
<CONNECTION INSTANCE="axi_gpio" PORT="s_axi_wstrb"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M02_AXI_wlast" SIGIS="undef"/>
<PORT DIR="O" LEFT="0" NAME="M02_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_s_axi_wvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_gpio" PORT="s_axi_wvalid"/>
@@ -1133,14 +1079,7 @@
<CONNECTION INSTANCE="axi_gpio" PORT="s_axi_araddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M02_AXI_arlen" SIGIS="undef"/>
<PORT DIR="O" NAME="M02_AXI_arsize" SIGIS="undef"/>
<PORT DIR="O" NAME="M02_AXI_arburst" SIGIS="undef"/>
<PORT DIR="O" NAME="M02_AXI_arlock" SIGIS="undef"/>
<PORT DIR="O" NAME="M02_AXI_arcache" SIGIS="undef"/>
<PORT DIR="O" NAME="M02_AXI_arprot" SIGIS="undef"/>
<PORT DIR="O" NAME="M02_AXI_arregion" SIGIS="undef"/>
<PORT DIR="O" NAME="M02_AXI_arqos" SIGIS="undef"/>
<PORT DIR="O" LEFT="0" NAME="M02_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_s_axi_arvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_gpio" PORT="s_axi_arvalid"/>
@@ -1161,7 +1100,6 @@
<CONNECTION INSTANCE="axi_gpio" PORT="s_axi_rresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M02_AXI_rlast" SIGIS="undef"/>
<PORT DIR="I" LEFT="0" NAME="M02_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_s_axi_rvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_gpio" PORT="s_axi_rvalid"/>
@@ -1177,36 +1115,22 @@
<BUSINTERFACE BUSNAME="microblaze_ps_M_AXI_DP" DATAWIDTH="32" NAME="S00_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
<PORTMAPS>
<PORTMAP LOGICAL="AWADDR" PHYSICAL="S00_AXI_awaddr"/>
<PORTMAP LOGICAL="AWLEN" PHYSICAL="S00_AXI_awlen"/>
<PORTMAP LOGICAL="AWSIZE" PHYSICAL="S00_AXI_awsize"/>
<PORTMAP LOGICAL="AWBURST" PHYSICAL="S00_AXI_awburst"/>
<PORTMAP LOGICAL="AWLOCK" PHYSICAL="S00_AXI_awlock"/>
<PORTMAP LOGICAL="AWCACHE" PHYSICAL="S00_AXI_awcache"/>
<PORTMAP LOGICAL="AWPROT" PHYSICAL="S00_AXI_awprot"/>
<PORTMAP LOGICAL="AWQOS" PHYSICAL="S00_AXI_awqos"/>
<PORTMAP LOGICAL="AWVALID" PHYSICAL="S00_AXI_awvalid"/>
<PORTMAP LOGICAL="AWREADY" PHYSICAL="S00_AXI_awready"/>
<PORTMAP LOGICAL="WDATA" PHYSICAL="S00_AXI_wdata"/>
<PORTMAP LOGICAL="WSTRB" PHYSICAL="S00_AXI_wstrb"/>
<PORTMAP LOGICAL="WLAST" PHYSICAL="S00_AXI_wlast"/>
<PORTMAP LOGICAL="WVALID" PHYSICAL="S00_AXI_wvalid"/>
<PORTMAP LOGICAL="WREADY" PHYSICAL="S00_AXI_wready"/>
<PORTMAP LOGICAL="BRESP" PHYSICAL="S00_AXI_bresp"/>
<PORTMAP LOGICAL="BVALID" PHYSICAL="S00_AXI_bvalid"/>
<PORTMAP LOGICAL="BREADY" PHYSICAL="S00_AXI_bready"/>
<PORTMAP LOGICAL="ARADDR" PHYSICAL="S00_AXI_araddr"/>
<PORTMAP LOGICAL="ARLEN" PHYSICAL="S00_AXI_arlen"/>
<PORTMAP LOGICAL="ARSIZE" PHYSICAL="S00_AXI_arsize"/>
<PORTMAP LOGICAL="ARBURST" PHYSICAL="S00_AXI_arburst"/>
<PORTMAP LOGICAL="ARLOCK" PHYSICAL="S00_AXI_arlock"/>
<PORTMAP LOGICAL="ARCACHE" PHYSICAL="S00_AXI_arcache"/>
<PORTMAP LOGICAL="ARPROT" PHYSICAL="S00_AXI_arprot"/>
<PORTMAP LOGICAL="ARQOS" PHYSICAL="S00_AXI_arqos"/>
<PORTMAP LOGICAL="ARVALID" PHYSICAL="S00_AXI_arvalid"/>
<PORTMAP LOGICAL="ARREADY" PHYSICAL="S00_AXI_arready"/>
<PORTMAP LOGICAL="RDATA" PHYSICAL="S00_AXI_rdata"/>
<PORTMAP LOGICAL="RRESP" PHYSICAL="S00_AXI_rresp"/>
<PORTMAP LOGICAL="RLAST" PHYSICAL="S00_AXI_rlast"/>
<PORTMAP LOGICAL="RVALID" PHYSICAL="S00_AXI_rvalid"/>
<PORTMAP LOGICAL="RREADY" PHYSICAL="S00_AXI_rready"/>
</PORTMAPS>
@@ -1214,38 +1138,22 @@
<BUSINTERFACE BUSNAME="axi_interconnect_M00_AXI" DATAWIDTH="32" NAME="M00_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
<PORTMAPS>
<PORTMAP LOGICAL="AWADDR" PHYSICAL="M00_AXI_awaddr"/>
<PORTMAP LOGICAL="AWLEN" PHYSICAL="M00_AXI_awlen"/>
<PORTMAP LOGICAL="AWSIZE" PHYSICAL="M00_AXI_awsize"/>
<PORTMAP LOGICAL="AWBURST" PHYSICAL="M00_AXI_awburst"/>
<PORTMAP LOGICAL="AWLOCK" PHYSICAL="M00_AXI_awlock"/>
<PORTMAP LOGICAL="AWCACHE" PHYSICAL="M00_AXI_awcache"/>
<PORTMAP LOGICAL="AWPROT" PHYSICAL="M00_AXI_awprot"/>
<PORTMAP LOGICAL="AWREGION" PHYSICAL="M00_AXI_awregion"/>
<PORTMAP LOGICAL="AWQOS" PHYSICAL="M00_AXI_awqos"/>
<PORTMAP LOGICAL="AWVALID" PHYSICAL="M00_AXI_awvalid"/>
<PORTMAP LOGICAL="AWREADY" PHYSICAL="M00_AXI_awready"/>
<PORTMAP LOGICAL="WDATA" PHYSICAL="M00_AXI_wdata"/>
<PORTMAP LOGICAL="WSTRB" PHYSICAL="M00_AXI_wstrb"/>
<PORTMAP LOGICAL="WLAST" PHYSICAL="M00_AXI_wlast"/>
<PORTMAP LOGICAL="WVALID" PHYSICAL="M00_AXI_wvalid"/>
<PORTMAP LOGICAL="WREADY" PHYSICAL="M00_AXI_wready"/>
<PORTMAP LOGICAL="BRESP" PHYSICAL="M00_AXI_bresp"/>
<PORTMAP LOGICAL="BVALID" PHYSICAL="M00_AXI_bvalid"/>
<PORTMAP LOGICAL="BREADY" PHYSICAL="M00_AXI_bready"/>
<PORTMAP LOGICAL="ARADDR" PHYSICAL="M00_AXI_araddr"/>
<PORTMAP LOGICAL="ARLEN" PHYSICAL="M00_AXI_arlen"/>
<PORTMAP LOGICAL="ARSIZE" PHYSICAL="M00_AXI_arsize"/>
<PORTMAP LOGICAL="ARBURST" PHYSICAL="M00_AXI_arburst"/>
<PORTMAP LOGICAL="ARLOCK" PHYSICAL="M00_AXI_arlock"/>
<PORTMAP LOGICAL="ARCACHE" PHYSICAL="M00_AXI_arcache"/>
<PORTMAP LOGICAL="ARPROT" PHYSICAL="M00_AXI_arprot"/>
<PORTMAP LOGICAL="ARREGION" PHYSICAL="M00_AXI_arregion"/>
<PORTMAP LOGICAL="ARQOS" PHYSICAL="M00_AXI_arqos"/>
<PORTMAP LOGICAL="ARVALID" PHYSICAL="M00_AXI_arvalid"/>
<PORTMAP LOGICAL="ARREADY" PHYSICAL="M00_AXI_arready"/>
<PORTMAP LOGICAL="RDATA" PHYSICAL="M00_AXI_rdata"/>
<PORTMAP LOGICAL="RRESP" PHYSICAL="M00_AXI_rresp"/>
<PORTMAP LOGICAL="RLAST" PHYSICAL="M00_AXI_rlast"/>
<PORTMAP LOGICAL="RVALID" PHYSICAL="M00_AXI_rvalid"/>
<PORTMAP LOGICAL="RREADY" PHYSICAL="M00_AXI_rready"/>
</PORTMAPS>
@@ -1253,38 +1161,22 @@
<BUSINTERFACE BUSNAME="__NOC__" NAME="M01_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
<PORTMAPS>
<PORTMAP LOGICAL="AWADDR" PHYSICAL="M01_AXI_awaddr"/>
<PORTMAP LOGICAL="AWLEN" PHYSICAL="M01_AXI_awlen"/>
<PORTMAP LOGICAL="AWSIZE" PHYSICAL="M01_AXI_awsize"/>
<PORTMAP LOGICAL="AWBURST" PHYSICAL="M01_AXI_awburst"/>
<PORTMAP LOGICAL="AWLOCK" PHYSICAL="M01_AXI_awlock"/>
<PORTMAP LOGICAL="AWCACHE" PHYSICAL="M01_AXI_awcache"/>
<PORTMAP LOGICAL="AWPROT" PHYSICAL="M01_AXI_awprot"/>
<PORTMAP LOGICAL="AWREGION" PHYSICAL="M01_AXI_awregion"/>
<PORTMAP LOGICAL="AWQOS" PHYSICAL="M01_AXI_awqos"/>
<PORTMAP LOGICAL="AWVALID" PHYSICAL="M01_AXI_awvalid"/>
<PORTMAP LOGICAL="AWREADY" PHYSICAL="M01_AXI_awready"/>
<PORTMAP LOGICAL="WDATA" PHYSICAL="M01_AXI_wdata"/>
<PORTMAP LOGICAL="WSTRB" PHYSICAL="M01_AXI_wstrb"/>
<PORTMAP LOGICAL="WLAST" PHYSICAL="M01_AXI_wlast"/>
<PORTMAP LOGICAL="WVALID" PHYSICAL="M01_AXI_wvalid"/>
<PORTMAP LOGICAL="WREADY" PHYSICAL="M01_AXI_wready"/>
<PORTMAP LOGICAL="BRESP" PHYSICAL="M01_AXI_bresp"/>
<PORTMAP LOGICAL="BVALID" PHYSICAL="M01_AXI_bvalid"/>
<PORTMAP LOGICAL="BREADY" PHYSICAL="M01_AXI_bready"/>
<PORTMAP LOGICAL="ARADDR" PHYSICAL="M01_AXI_araddr"/>
<PORTMAP LOGICAL="ARLEN" PHYSICAL="M01_AXI_arlen"/>
<PORTMAP LOGICAL="ARSIZE" PHYSICAL="M01_AXI_arsize"/>
<PORTMAP LOGICAL="ARBURST" PHYSICAL="M01_AXI_arburst"/>
<PORTMAP LOGICAL="ARLOCK" PHYSICAL="M01_AXI_arlock"/>
<PORTMAP LOGICAL="ARCACHE" PHYSICAL="M01_AXI_arcache"/>
<PORTMAP LOGICAL="ARPROT" PHYSICAL="M01_AXI_arprot"/>
<PORTMAP LOGICAL="ARREGION" PHYSICAL="M01_AXI_arregion"/>
<PORTMAP LOGICAL="ARQOS" PHYSICAL="M01_AXI_arqos"/>
<PORTMAP LOGICAL="ARVALID" PHYSICAL="M01_AXI_arvalid"/>
<PORTMAP LOGICAL="ARREADY" PHYSICAL="M01_AXI_arready"/>
<PORTMAP LOGICAL="RDATA" PHYSICAL="M01_AXI_rdata"/>
<PORTMAP LOGICAL="RRESP" PHYSICAL="M01_AXI_rresp"/>
<PORTMAP LOGICAL="RLAST" PHYSICAL="M01_AXI_rlast"/>
<PORTMAP LOGICAL="RVALID" PHYSICAL="M01_AXI_rvalid"/>
<PORTMAP LOGICAL="RREADY" PHYSICAL="M01_AXI_rready"/>
</PORTMAPS>
@@ -1292,38 +1184,22 @@
<BUSINTERFACE BUSNAME="axi_interconnect_M02_AXI" DATAWIDTH="32" NAME="M02_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
<PORTMAPS>
<PORTMAP LOGICAL="AWADDR" PHYSICAL="M02_AXI_awaddr"/>
<PORTMAP LOGICAL="AWLEN" PHYSICAL="M02_AXI_awlen"/>
<PORTMAP LOGICAL="AWSIZE" PHYSICAL="M02_AXI_awsize"/>
<PORTMAP LOGICAL="AWBURST" PHYSICAL="M02_AXI_awburst"/>
<PORTMAP LOGICAL="AWLOCK" PHYSICAL="M02_AXI_awlock"/>
<PORTMAP LOGICAL="AWCACHE" PHYSICAL="M02_AXI_awcache"/>
<PORTMAP LOGICAL="AWPROT" PHYSICAL="M02_AXI_awprot"/>
<PORTMAP LOGICAL="AWREGION" PHYSICAL="M02_AXI_awregion"/>
<PORTMAP LOGICAL="AWQOS" PHYSICAL="M02_AXI_awqos"/>
<PORTMAP LOGICAL="AWVALID" PHYSICAL="M02_AXI_awvalid"/>
<PORTMAP LOGICAL="AWREADY" PHYSICAL="M02_AXI_awready"/>
<PORTMAP LOGICAL="WDATA" PHYSICAL="M02_AXI_wdata"/>
<PORTMAP LOGICAL="WSTRB" PHYSICAL="M02_AXI_wstrb"/>
<PORTMAP LOGICAL="WLAST" PHYSICAL="M02_AXI_wlast"/>
<PORTMAP LOGICAL="WVALID" PHYSICAL="M02_AXI_wvalid"/>
<PORTMAP LOGICAL="WREADY" PHYSICAL="M02_AXI_wready"/>
<PORTMAP LOGICAL="BRESP" PHYSICAL="M02_AXI_bresp"/>
<PORTMAP LOGICAL="BVALID" PHYSICAL="M02_AXI_bvalid"/>
<PORTMAP LOGICAL="BREADY" PHYSICAL="M02_AXI_bready"/>
<PORTMAP LOGICAL="ARADDR" PHYSICAL="M02_AXI_araddr"/>
<PORTMAP LOGICAL="ARLEN" PHYSICAL="M02_AXI_arlen"/>
<PORTMAP LOGICAL="ARSIZE" PHYSICAL="M02_AXI_arsize"/>
<PORTMAP LOGICAL="ARBURST" PHYSICAL="M02_AXI_arburst"/>
<PORTMAP LOGICAL="ARLOCK" PHYSICAL="M02_AXI_arlock"/>
<PORTMAP LOGICAL="ARCACHE" PHYSICAL="M02_AXI_arcache"/>
<PORTMAP LOGICAL="ARPROT" PHYSICAL="M02_AXI_arprot"/>
<PORTMAP LOGICAL="ARREGION" PHYSICAL="M02_AXI_arregion"/>
<PORTMAP LOGICAL="ARQOS" PHYSICAL="M02_AXI_arqos"/>
<PORTMAP LOGICAL="ARVALID" PHYSICAL="M02_AXI_arvalid"/>
<PORTMAP LOGICAL="ARREADY" PHYSICAL="M02_AXI_arready"/>
<PORTMAP LOGICAL="RDATA" PHYSICAL="M02_AXI_rdata"/>
<PORTMAP LOGICAL="RRESP" PHYSICAL="M02_AXI_rresp"/>
<PORTMAP LOGICAL="RLAST" PHYSICAL="M02_AXI_rlast"/>
<PORTMAP LOGICAL="RVALID" PHYSICAL="M02_AXI_rvalid"/>
<PORTMAP LOGICAL="RREADY" PHYSICAL="M02_AXI_rready"/>
</PORTMAPS>
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0.dcp
BIN
View File
Binary file not shown.
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0.xml
+18 -18
View File
@@ -961,7 +961,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:51 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -992,7 +992,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:51 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1021,7 +1021,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:51 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1041,7 +1041,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:51 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1059,7 +1059,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:51 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1077,7 +1077,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:55:53 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1811,6 +1811,18 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_axi_gpio_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_axi_gpio_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_axi_gpio_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
@@ -1825,18 +1837,6 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_axi_gpio_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_axi_gpio_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>Advanced eXtensible Interface General Purpose Input/Output (AXI GPIO) core provides a general purpose input/output interface to the AXI interface.</spirit:description>
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_sim_netlist.v
+130 -124
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:11 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_bd_axi_gpio_0 -prefix
// system_bd_axi_gpio_0_ system_bd_axi_gpio_0_sim_netlist.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:55:53 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode funcsim
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_sim_netlist.v
// Design : system_bd_axi_gpio_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -12,6 +12,125 @@
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_bd_axi_gpio_0,axi_gpio,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_gpio,Vivado 2019.1.3" *)
(* NotValidForBitStream *)
module system_bd_axi_gpio_0
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
gpio_io_o,
gpio2_io_i);
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_O" *) (* x_interface_parameter = "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE" *) output [31:0]gpio_io_o;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I" *) (* x_interface_parameter = "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE" *) input [31:0]gpio2_io_i;
wire [31:0]gpio2_io_i;
wire [31:0]gpio_io_o;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_U0_ip2intc_irpt_UNCONNECTED;
wire [31:0]NLW_U0_gpio2_io_o_UNCONNECTED;
wire [31:0]NLW_U0_gpio2_io_t_UNCONNECTED;
wire [31:0]NLW_U0_gpio_io_t_UNCONNECTED;
(* C_ALL_INPUTS = "0" *)
(* C_ALL_INPUTS_2 = "1" *)
(* C_ALL_OUTPUTS = "1" *)
(* C_ALL_OUTPUTS_2 = "0" *)
(* C_DOUT_DEFAULT = "-1" *)
(* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "kintex7" *)
(* C_GPIO2_WIDTH = "32" *)
(* C_GPIO_WIDTH = "32" *)
(* C_INTERRUPT_PRESENT = "0" *)
(* C_IS_DUAL = "1" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRI_DEFAULT = "-1" *)
(* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* ip_group = "LOGICORE" *)
system_bd_axi_gpio_0_axi_gpio U0
(.gpio2_io_i(gpio2_io_i),
.gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[31:0]),
.gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[31:0]),
.gpio_io_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.gpio_io_o(gpio_io_o),
.gpio_io_t(NLW_U0_gpio_io_t_UNCONNECTED[31:0]),
.ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "GPIO_Core" *)
module system_bd_axi_gpio_0_GPIO_Core
(\Dual.ALLOUT0_ND_G1.READ_REG_GEN[31].reg1_reg ,
gpio_io_o,
@@ -2198,6 +2317,7 @@ module system_bd_axi_gpio_0_GPIO_Core
.O(ip2bus_wrack_i));
endmodule
(* ORIG_REF_NAME = "address_decoder" *)
module system_bd_axi_gpio_0_address_decoder
(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
E,
@@ -2940,7 +3060,7 @@ endmodule
(* C_FAMILY = "kintex7" *) (* C_GPIO2_WIDTH = "32" *) (* C_GPIO_WIDTH = "32" *)
(* C_INTERRUPT_PRESENT = "0" *) (* C_IS_DUAL = "1" *) (* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *) (* C_TRI_DEFAULT = "-1" *) (* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *)
(* ORIG_REF_NAME = "axi_gpio" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *)
module system_bd_axi_gpio_0_axi_gpio
(s_axi_aclk,
s_axi_aresetn,
@@ -3491,6 +3611,7 @@ module system_bd_axi_gpio_0_axi_gpio
.R(bus2ip_reset));
endmodule
(* ORIG_REF_NAME = "axi_lite_ipif" *)
module system_bd_axi_gpio_0_axi_lite_ipif
(bus2ip_reset,
Q,
@@ -3869,6 +3990,7 @@ module system_bd_axi_gpio_0_axi_lite_ipif
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module system_bd_axi_gpio_0_cdc_sync
(scndry_vect_out,
gpio2_io_i,
@@ -5387,6 +5509,7 @@ module system_bd_axi_gpio_0_cdc_sync
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "pselect_f" *)
module system_bd_axi_gpio_0_pselect_f
(ce_expnd_i_3,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] );
@@ -5422,6 +5545,7 @@ module system_bd_axi_gpio_0_pselect_f__parameterized1
.O(ce_expnd_i_1));
endmodule
(* ORIG_REF_NAME = "slave_attachment" *)
module system_bd_axi_gpio_0_slave_attachment
(SR,
Q,
@@ -6412,124 +6536,6 @@ module system_bd_axi_gpio_0_slave_attachment
.Q(state[1]),
.R(SR));
endmodule
(* CHECK_LICENSE_TYPE = "system_bd_axi_gpio_0,axi_gpio,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_gpio,Vivado 2019.1.3" *)
(* NotValidForBitStream *)
module system_bd_axi_gpio_0
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
gpio_io_o,
gpio2_io_i);
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_O" *) (* x_interface_parameter = "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE" *) output [31:0]gpio_io_o;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I" *) (* x_interface_parameter = "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE" *) input [31:0]gpio2_io_i;
wire [31:0]gpio2_io_i;
wire [31:0]gpio_io_o;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_U0_ip2intc_irpt_UNCONNECTED;
wire [31:0]NLW_U0_gpio2_io_o_UNCONNECTED;
wire [31:0]NLW_U0_gpio2_io_t_UNCONNECTED;
wire [31:0]NLW_U0_gpio_io_t_UNCONNECTED;
(* C_ALL_INPUTS = "0" *)
(* C_ALL_INPUTS_2 = "1" *)
(* C_ALL_OUTPUTS = "1" *)
(* C_ALL_OUTPUTS_2 = "0" *)
(* C_DOUT_DEFAULT = "-1" *)
(* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "kintex7" *)
(* C_GPIO2_WIDTH = "32" *)
(* C_GPIO_WIDTH = "32" *)
(* C_INTERRUPT_PRESENT = "0" *)
(* C_IS_DUAL = "1" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRI_DEFAULT = "-1" *)
(* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* ip_group = "LOGICORE" *)
system_bd_axi_gpio_0_axi_gpio U0
(.gpio2_io_i(gpio2_io_i),
.gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[31:0]),
.gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[31:0]),
.gpio_io_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.gpio_io_o(gpio_io_o),
.gpio_io_t(NLW_U0_gpio_io_t_UNCONNECTED[31:0]),
.ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_sim_netlist.vhdl
+19 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:11 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_bd_axi_gpio_0 -prefix
-- system_bd_axi_gpio_0_ system_bd_axi_gpio_0_sim_netlist.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:55:53 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_sim_netlist.vhdl
-- Design : system_bd_axi_gpio_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -20,6 +20,8 @@ entity system_bd_axi_gpio_0_cdc_sync is
gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_axi_gpio_0_cdc_sync : entity is "cdc_sync";
end system_bd_axi_gpio_0_cdc_sync;
architecture STRUCTURE of system_bd_axi_gpio_0_cdc_sync is
@@ -1925,6 +1927,8 @@ entity system_bd_axi_gpio_0_pselect_f is
ce_expnd_i_3 : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_axi_gpio_0_pselect_f : entity is "pselect_f";
end system_bd_axi_gpio_0_pselect_f;
architecture STRUCTURE of system_bd_axi_gpio_0_pselect_f is
@@ -2055,6 +2059,8 @@ entity system_bd_axi_gpio_0_GPIO_Core is
\Dual.gpio2_Data_Out_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_axi_gpio_0_GPIO_Core : entity is "GPIO_Core";
end system_bd_axi_gpio_0_GPIO_Core;
architecture STRUCTURE of system_bd_axi_gpio_0_GPIO_Core is
@@ -4808,6 +4814,8 @@ entity system_bd_axi_gpio_0_address_decoder is
\Dual.ALLOUT0_ND_G1.READ_REG_GEN[0].reg1_reg\ : in STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_axi_gpio_0_address_decoder : entity is "address_decoder";
end system_bd_axi_gpio_0_address_decoder;
architecture STRUCTURE of system_bd_axi_gpio_0_address_decoder is
@@ -5554,6 +5562,8 @@ entity system_bd_axi_gpio_0_slave_attachment is
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_axi_gpio_0_slave_attachment : entity is "slave_attachment";
end system_bd_axi_gpio_0_slave_attachment;
architecture STRUCTURE of system_bd_axi_gpio_0_slave_attachment is
@@ -6598,6 +6608,8 @@ entity system_bd_axi_gpio_0_axi_lite_ipif is
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_axi_gpio_0_axi_lite_ipif : entity is "axi_lite_ipif";
end system_bd_axi_gpio_0_axi_lite_ipif;
architecture STRUCTURE of system_bd_axi_gpio_0_axi_lite_ipif is
@@ -6762,6 +6774,8 @@ entity system_bd_axi_gpio_0_axi_gpio is
attribute C_TRI_DEFAULT of system_bd_axi_gpio_0_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of system_bd_axi_gpio_0_axi_gpio : entity is -1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_axi_gpio_0_axi_gpio : entity is "axi_gpio";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_bd_axi_gpio_0_axi_gpio : entity is "yes";
attribute ip_group : string;
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_stub.v
+5 -5
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:11 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_bd_axi_gpio_0 -prefix
// system_bd_axi_gpio_0_ system_bd_axi_gpio_0_stub.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:55:53 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_stub.v
// Design : system_bd_axi_gpio_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_stub.vhdl
+5 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:11 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_axi_gpio_0 -prefix
-- system_bd_axi_gpio_0_ system_bd_axi_gpio_0_stub.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:55:53 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_stub.vhdl
-- Design : system_bd_axi_gpio_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0.dcp
BIN
View File
Binary file not shown.
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0.xml
+17 -17
View File
@@ -968,7 +968,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:51 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -999,7 +999,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:51 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1024,7 +1024,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:51 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1044,7 +1044,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:51 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1062,7 +1062,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:55:52 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -2531,6 +2531,18 @@
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_axi_spi_engine_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_axi_spi_engine_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_axi_spi_engine_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
@@ -2545,18 +2557,6 @@
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_axi_spi_engine_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_axi_spi_engine_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>axi_spi_engine_v1_0</spirit:description>
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_sim_netlist.v
+209 -205
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:11 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_bd_axi_spi_engine_0 -prefix
// system_bd_axi_spi_engine_0_ system_bd_axi_spi_engine_0_sim_netlist.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:55:52 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode funcsim
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_sim_netlist.v
// Design : system_bd_axi_spi_engine_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -12,11 +12,210 @@
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_bd_axi_spi_engine_0,axi_spi_engine,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* IP_DEFINITION_SOURCE = "package_project" *)
(* X_CORE_INFO = "axi_spi_engine,Vivado 2019.1.3" *)
(* NotValidForBitStream *)
module system_bd_axi_spi_engine_0
(s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_awprot,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_arprot,
s_axi_rvalid,
s_axi_rready,
s_axi_rresp,
s_axi_rdata,
irq,
spi_clk,
spi_resetn,
cmd_ready,
cmd_valid,
cmd_data,
sdo_data_ready,
sdo_data_valid,
sdo_data,
sdi_data_ready,
sdi_data_valid,
sdi_data,
sync_ready,
sync_valid,
sync_data);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK, xilinx.com:signal:clock:1.0 spi_engine_offload_ctrl0_s_axi_signal_clock CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_clock, ASSOCIATED_BUSIF spi_engine_offload_ctrl0:s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST, xilinx.com:signal:reset:1.0 spi_engine_offload_ctrl0_s_axi_signal_reset RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *) input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *) input [15:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *) output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *) input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *) output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *) output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *) input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *) input [15:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output [31:0]s_axi_rdata;
output irq;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 spi_engine_ctrl_signal_clock CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_clock, ASSOCIATED_BUSIF spi_engine_ctrl, ASSOCIATED_RESET spi_resetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input spi_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 spi_engine_ctrl_signal_reset RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) output spi_resetn;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_READY" *) input cmd_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_VALID" *) output cmd_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_DATA" *) output [15:0]cmd_data;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_READY" *) input sdo_data_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_VALID" *) output sdo_data_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_DATA" *) output [7:0]sdo_data;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_READY" *) output sdi_data_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_VALID" *) input sdi_data_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_DATA" *) input [7:0]sdi_data;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_READY" *) output sync_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_VALID" *) input sync_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_DATA" *) input [7:0]sync_data;
wire [15:0]cmd_data;
wire cmd_ready;
wire cmd_valid;
wire irq;
wire s_axi_aclk;
wire [15:0]s_axi_araddr;
wire s_axi_aresetn;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire s_axi_arvalid;
wire [15:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire [7:0]sdi_data;
wire sdi_data_ready;
wire sdi_data_valid;
wire [7:0]sdo_data;
wire sdo_data_ready;
wire sdo_data_valid;
wire spi_clk;
wire spi_resetn;
wire [7:0]sync_data;
wire sync_ready;
wire sync_valid;
wire NLW_inst_offload0_cmd_wr_en_UNCONNECTED;
wire NLW_inst_offload0_enable_UNCONNECTED;
wire NLW_inst_offload0_mem_reset_UNCONNECTED;
wire NLW_inst_offload0_sdo_wr_en_UNCONNECTED;
wire NLW_inst_offload_sync_ready_UNCONNECTED;
wire NLW_inst_up_rack_UNCONNECTED;
wire NLW_inst_up_wack_UNCONNECTED;
wire [15:0]NLW_inst_offload0_cmd_wr_data_UNCONNECTED;
wire [7:0]NLW_inst_offload0_sdo_wr_data_UNCONNECTED;
wire [31:0]NLW_inst_up_rdata_UNCONNECTED;
(* ASYNC_SPI_CLK = "1'b0" *)
(* CMD_FIFO_ADDRESS_WIDTH = "4" *)
(* DATA_WIDTH = "16'b0000000000001000" *)
(* ID = "0" *)
(* MM_IF_TYPE = "0" *)
(* NUM_OFFLOAD = "0" *)
(* NUM_OF_SDI = "8'b00000001" *)
(* OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = "4" *)
(* OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = "4" *)
(* PCORE_VERSION = "65649" *)
(* SDI_FIFO_ADDRESS_WIDTH = "5" *)
(* SDO_FIFO_ADDRESS_WIDTH = "5" *)
(* SYNC_FIFO_ADDRESS_WIDTH = "4" *)
(* S_AXI = "0" *)
(* UP_FIFO = "1" *)
system_bd_axi_spi_engine_0_axi_spi_engine inst
(.cmd_data(cmd_data),
.cmd_ready(cmd_ready),
.cmd_valid(cmd_valid),
.irq(irq),
.offload0_cmd_wr_data(NLW_inst_offload0_cmd_wr_data_UNCONNECTED[15:0]),
.offload0_cmd_wr_en(NLW_inst_offload0_cmd_wr_en_UNCONNECTED),
.offload0_enable(NLW_inst_offload0_enable_UNCONNECTED),
.offload0_enabled(1'b0),
.offload0_mem_reset(NLW_inst_offload0_mem_reset_UNCONNECTED),
.offload0_sdo_wr_data(NLW_inst_offload0_sdo_wr_data_UNCONNECTED[7:0]),
.offload0_sdo_wr_en(NLW_inst_offload0_sdo_wr_en_UNCONNECTED),
.offload_sync_data({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.offload_sync_ready(NLW_inst_offload_sync_ready_UNCONNECTED),
.offload_sync_valid(1'b0),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid),
.sdi_data(sdi_data),
.sdi_data_ready(sdi_data_ready),
.sdi_data_valid(sdi_data_valid),
.sdo_data(sdo_data),
.sdo_data_ready(sdo_data_ready),
.sdo_data_valid(sdo_data_valid),
.spi_clk(spi_clk),
.spi_resetn(spi_resetn),
.sync_data(sync_data),
.sync_ready(sync_ready),
.sync_valid(sync_valid),
.up_clk(1'b0),
.up_rack(NLW_inst_up_rack_UNCONNECTED),
.up_raddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.up_rdata(NLW_inst_up_rdata_UNCONNECTED[31:0]),
.up_rreq(1'b0),
.up_rstn(1'b0),
.up_wack(NLW_inst_up_wack_UNCONNECTED),
.up_waddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.up_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.up_wreq(1'b0));
endmodule
(* ASYNC_SPI_CLK = "1'b0" *) (* CMD_FIFO_ADDRESS_WIDTH = "4" *) (* DATA_WIDTH = "16'b0000000000001000" *)
(* ID = "0" *) (* MM_IF_TYPE = "0" *) (* NUM_OFFLOAD = "0" *)
(* NUM_OF_SDI = "8'b00000001" *) (* OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = "4" *) (* OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = "4" *)
(* PCORE_VERSION = "65649" *) (* SDI_FIFO_ADDRESS_WIDTH = "5" *) (* SDO_FIFO_ADDRESS_WIDTH = "5" *)
(* SYNC_FIFO_ADDRESS_WIDTH = "4" *) (* S_AXI = "0" *) (* UP_FIFO = "1" *)
(* ORIG_REF_NAME = "axi_spi_engine" *) (* PCORE_VERSION = "65649" *) (* SDI_FIFO_ADDRESS_WIDTH = "5" *)
(* SDO_FIFO_ADDRESS_WIDTH = "5" *) (* SYNC_FIFO_ADDRESS_WIDTH = "4" *) (* S_AXI = "0" *)
(* UP_FIFO = "1" *)
module system_bd_axi_spi_engine_0_axi_spi_engine
(s_axi_aclk,
s_axi_aresetn,
@@ -1210,6 +1409,7 @@ module system_bd_axi_spi_engine_0_axi_spi_engine
.R(i_up_axi_n_0));
endmodule
(* ORIG_REF_NAME = "fifo_address_sync" *)
module system_bd_axi_spi_engine_0_fifo_address_sync
(s_axis_ready_reg_0,
m_axis_valid_reg_0,
@@ -2686,204 +2886,7 @@ module system_bd_axi_spi_engine_0_fifo_address_sync__parameterized0_1
.O(\level_reg[4]_0 ));
endmodule
(* CHECK_LICENSE_TYPE = "system_bd_axi_spi_engine_0,axi_spi_engine,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* IP_DEFINITION_SOURCE = "package_project" *)
(* X_CORE_INFO = "axi_spi_engine,Vivado 2019.1.3" *)
(* NotValidForBitStream *)
module system_bd_axi_spi_engine_0
(s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_awprot,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_arprot,
s_axi_rvalid,
s_axi_rready,
s_axi_rresp,
s_axi_rdata,
irq,
spi_clk,
spi_resetn,
cmd_ready,
cmd_valid,
cmd_data,
sdo_data_ready,
sdo_data_valid,
sdo_data,
sdi_data_ready,
sdi_data_valid,
sdi_data,
sync_ready,
sync_valid,
sync_data);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK, xilinx.com:signal:clock:1.0 spi_engine_offload_ctrl0_s_axi_signal_clock CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_clock, ASSOCIATED_BUSIF spi_engine_offload_ctrl0:s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST, xilinx.com:signal:reset:1.0 spi_engine_offload_ctrl0_s_axi_signal_reset RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *) input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *) input [15:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *) output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *) input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *) output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *) output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *) input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *) input [15:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output [31:0]s_axi_rdata;
output irq;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 spi_engine_ctrl_signal_clock CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_clock, ASSOCIATED_BUSIF spi_engine_ctrl, ASSOCIATED_RESET spi_resetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input spi_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 spi_engine_ctrl_signal_reset RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) output spi_resetn;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_READY" *) input cmd_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_VALID" *) output cmd_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_DATA" *) output [15:0]cmd_data;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_READY" *) input sdo_data_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_VALID" *) output sdo_data_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_DATA" *) output [7:0]sdo_data;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_READY" *) output sdi_data_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_VALID" *) input sdi_data_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_DATA" *) input [7:0]sdi_data;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_READY" *) output sync_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_VALID" *) input sync_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_DATA" *) input [7:0]sync_data;
wire [15:0]cmd_data;
wire cmd_ready;
wire cmd_valid;
wire irq;
wire s_axi_aclk;
wire [15:0]s_axi_araddr;
wire s_axi_aresetn;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire s_axi_arvalid;
wire [15:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire [7:0]sdi_data;
wire sdi_data_ready;
wire sdi_data_valid;
wire [7:0]sdo_data;
wire sdo_data_ready;
wire sdo_data_valid;
wire spi_clk;
wire spi_resetn;
wire [7:0]sync_data;
wire sync_ready;
wire sync_valid;
wire NLW_inst_offload0_cmd_wr_en_UNCONNECTED;
wire NLW_inst_offload0_enable_UNCONNECTED;
wire NLW_inst_offload0_mem_reset_UNCONNECTED;
wire NLW_inst_offload0_sdo_wr_en_UNCONNECTED;
wire NLW_inst_offload_sync_ready_UNCONNECTED;
wire NLW_inst_up_rack_UNCONNECTED;
wire NLW_inst_up_wack_UNCONNECTED;
wire [15:0]NLW_inst_offload0_cmd_wr_data_UNCONNECTED;
wire [7:0]NLW_inst_offload0_sdo_wr_data_UNCONNECTED;
wire [31:0]NLW_inst_up_rdata_UNCONNECTED;
(* ASYNC_SPI_CLK = "1'b0" *)
(* CMD_FIFO_ADDRESS_WIDTH = "4" *)
(* DATA_WIDTH = "16'b0000000000001000" *)
(* ID = "0" *)
(* MM_IF_TYPE = "0" *)
(* NUM_OFFLOAD = "0" *)
(* NUM_OF_SDI = "8'b00000001" *)
(* OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = "4" *)
(* OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = "4" *)
(* PCORE_VERSION = "65649" *)
(* SDI_FIFO_ADDRESS_WIDTH = "5" *)
(* SDO_FIFO_ADDRESS_WIDTH = "5" *)
(* SYNC_FIFO_ADDRESS_WIDTH = "4" *)
(* S_AXI = "0" *)
(* UP_FIFO = "1" *)
system_bd_axi_spi_engine_0_axi_spi_engine inst
(.cmd_data(cmd_data),
.cmd_ready(cmd_ready),
.cmd_valid(cmd_valid),
.irq(irq),
.offload0_cmd_wr_data(NLW_inst_offload0_cmd_wr_data_UNCONNECTED[15:0]),
.offload0_cmd_wr_en(NLW_inst_offload0_cmd_wr_en_UNCONNECTED),
.offload0_enable(NLW_inst_offload0_enable_UNCONNECTED),
.offload0_enabled(1'b0),
.offload0_mem_reset(NLW_inst_offload0_mem_reset_UNCONNECTED),
.offload0_sdo_wr_data(NLW_inst_offload0_sdo_wr_data_UNCONNECTED[7:0]),
.offload0_sdo_wr_en(NLW_inst_offload0_sdo_wr_en_UNCONNECTED),
.offload_sync_data({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.offload_sync_ready(NLW_inst_offload_sync_ready_UNCONNECTED),
.offload_sync_valid(1'b0),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid),
.sdi_data(sdi_data),
.sdi_data_ready(sdi_data_ready),
.sdi_data_valid(sdi_data_valid),
.sdo_data(sdo_data),
.sdo_data_ready(sdo_data_ready),
.sdo_data_valid(sdo_data_valid),
.spi_clk(spi_clk),
.spi_resetn(spi_resetn),
.sync_data(sync_data),
.sync_ready(sync_ready),
.sync_valid(sync_valid),
.up_clk(1'b0),
.up_rack(NLW_inst_up_rack_UNCONNECTED),
.up_raddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.up_rdata(NLW_inst_up_rdata_UNCONNECTED[31:0]),
.up_rreq(1'b0),
.up_rstn(1'b0),
.up_wack(NLW_inst_up_wack_UNCONNECTED),
.up_waddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.up_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.up_wreq(1'b0));
endmodule
(* ORIG_REF_NAME = "up_axi" *)
module system_bd_axi_spi_engine_0_up_axi
(s_axi_aresetn_0,
up_wreq_s,
@@ -5924,6 +5927,7 @@ module system_bd_axi_spi_engine_0_up_axi
.R(s_axi_aresetn_0));
endmodule
(* ORIG_REF_NAME = "util_axis_fifo" *)
module system_bd_axi_spi_engine_0_util_axis_fifo
(s_axis_ready_reg,
m_axis_valid_reg,
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_sim_netlist.vhdl
+13 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:11 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_bd_axi_spi_engine_0 -prefix
-- system_bd_axi_spi_engine_0_ system_bd_axi_spi_engine_0_sim_netlist.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:55:52 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_sim_netlist.vhdl
-- Design : system_bd_axi_spi_engine_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -30,6 +30,8 @@ entity system_bd_axi_spi_engine_0_fifo_address_sync is
\level_reg[0]_1\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_axi_spi_engine_0_fifo_address_sync : entity is "fifo_address_sync";
end system_bd_axi_spi_engine_0_fifo_address_sync;
architecture STRUCTURE of system_bd_axi_spi_engine_0_fifo_address_sync is
@@ -2061,6 +2063,8 @@ entity system_bd_axi_spi_engine_0_up_axi is
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_axi_spi_engine_0_up_axi : entity is "up_axi";
end system_bd_axi_spi_engine_0_up_axi;
architecture STRUCTURE of system_bd_axi_spi_engine_0_up_axi is
@@ -5816,6 +5820,8 @@ entity system_bd_axi_spi_engine_0_util_axis_fifo is
s_mem_write : in STD_LOGIC;
offload0_cmd_wr_data : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_axi_spi_engine_0_util_axis_fifo : entity is "util_axis_fifo";
end system_bd_axi_spi_engine_0_util_axis_fifo;
architecture STRUCTURE of system_bd_axi_spi_engine_0_util_axis_fifo is
@@ -6346,6 +6352,8 @@ entity system_bd_axi_spi_engine_0_axi_spi_engine is
attribute OFFLOAD0_CMD_MEM_ADDRESS_WIDTH of system_bd_axi_spi_engine_0_axi_spi_engine : entity is 4;
attribute OFFLOAD0_SDO_MEM_ADDRESS_WIDTH : integer;
attribute OFFLOAD0_SDO_MEM_ADDRESS_WIDTH of system_bd_axi_spi_engine_0_axi_spi_engine : entity is 4;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_axi_spi_engine_0_axi_spi_engine : entity is "axi_spi_engine";
attribute PCORE_VERSION : integer;
attribute PCORE_VERSION of system_bd_axi_spi_engine_0_axi_spi_engine : entity is 65649;
attribute SDI_FIFO_ADDRESS_WIDTH : integer;
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_stub.v
+5 -5
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:11 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_bd_axi_spi_engine_0 -prefix
// system_bd_axi_spi_engine_0_ system_bd_axi_spi_engine_0_stub.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:55:52 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_stub.v
// Design : system_bd_axi_spi_engine_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_stub.vhdl
+5 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:11 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_axi_spi_engine_0 -prefix
-- system_bd_axi_spi_engine_0_ system_bd_axi_spi_engine_0_stub.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:55:52 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_stub.vhdl
-- Design : system_bd_axi_spi_engine_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0.dcp
BIN
View File
Binary file not shown.
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0.xml
+18 -18
View File
@@ -1168,7 +1168,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:52 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1198,7 +1198,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:52 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1217,7 +1217,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:52 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1236,7 +1236,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:52 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1254,7 +1254,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:52 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1272,7 +1272,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:55:50 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -3714,6 +3714,18 @@
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_clk_wiz_25M_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_clk_wiz_25M_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_clk_wiz_25M_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
@@ -3728,18 +3740,6 @@
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_clk_wiz_25M_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_clk_wiz_25M_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user&apos;s clocking requirements.</spirit:description>
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_sim_netlist.v
+6 -5
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:10 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_bd_clk_wiz_25M_0 -prefix
// system_bd_clk_wiz_25M_0_ system_bd_clk_wiz_25M_0_sim_netlist.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:55:50 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode funcsim
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_sim_netlist.v
// Design : system_bd_clk_wiz_25M_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -31,6 +31,7 @@ module system_bd_clk_wiz_25M_0
.locked(locked));
endmodule
(* ORIG_REF_NAME = "system_bd_clk_wiz_25M_0_clk_wiz" *)
module system_bd_clk_wiz_25M_0_system_bd_clk_wiz_25M_0_clk_wiz
(clk_out1,
locked,
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_sim_netlist.vhdl
+7 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:10 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_bd_clk_wiz_25M_0 -prefix
-- system_bd_clk_wiz_25M_0_ system_bd_clk_wiz_25M_0_sim_netlist.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:55:50 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_sim_netlist.vhdl
-- Design : system_bd_clk_wiz_25M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -20,6 +20,8 @@ entity system_bd_clk_wiz_25M_0_system_bd_clk_wiz_25M_0_clk_wiz is
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_clk_wiz_25M_0_system_bd_clk_wiz_25M_0_clk_wiz : entity is "system_bd_clk_wiz_25M_0_clk_wiz";
end system_bd_clk_wiz_25M_0_system_bd_clk_wiz_25M_0_clk_wiz;
architecture STRUCTURE of system_bd_clk_wiz_25M_0_system_bd_clk_wiz_25M_0_clk_wiz is
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_stub.v
+5 -5
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:10 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_bd_clk_wiz_25M_0 -prefix
// system_bd_clk_wiz_25M_0_ system_bd_clk_wiz_25M_0_stub.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:55:50 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_stub.v
// Design : system_bd_clk_wiz_25M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_stub.vhdl
+5 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:10 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_clk_wiz_25M_0 -prefix
-- system_bd_clk_wiz_25M_0_ system_bd_clk_wiz_25M_0_stub.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:55:50 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_stub.vhdl
-- Design : system_bd_clk_wiz_25M_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0.dcp
BIN
View File
Binary file not shown.
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0.xml
+18 -18
View File
@@ -1891,7 +1891,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:54 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1909,7 +1909,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:54 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1929,7 +1929,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:54 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1949,7 +1949,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:54 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1969,7 +1969,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:54 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1987,7 +1987,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:55:51 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -3858,6 +3858,18 @@
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_dlmb_bram_if_cntlr_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_dlmb_bram_if_cntlr_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_dlmb_bram_if_cntlr_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
@@ -3872,18 +3884,6 @@
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_dlmb_bram_if_cntlr_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_dlmb_bram_if_cntlr_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</spirit:description>
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_sim_netlist.v
+200 -200
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:09 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_bd_dlmb_bram_if_cntlr_0 -prefix
// system_bd_dlmb_bram_if_cntlr_0_ system_bd_dlmb_bram_if_cntlr_0_sim_netlist.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:55:51 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode funcsim
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_sim_netlist.v
// Design : system_bd_dlmb_bram_if_cntlr_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -12,6 +12,200 @@
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_bd_dlmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "lmb_bram_if_cntlr,Vivado 2019.1.3" *)
(* NotValidForBitStream *)
module system_bd_dlmb_bram_if_cntlr_0
(LMB_Clk,
LMB_Rst,
LMB_ABus,
LMB_WriteDBus,
LMB_AddrStrobe,
LMB_ReadStrobe,
LMB_WriteStrobe,
LMB_BE,
Sl_DBus,
Sl_Ready,
Sl_Wait,
Sl_UE,
Sl_CE,
BRAM_Rst_A,
BRAM_Clk_A,
BRAM_Addr_A,
BRAM_EN_A,
BRAM_WEN_A,
BRAM_Dout_A,
BRAM_Din_A);
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input LMB_Clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) input LMB_Rst;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ABUS" *) (* x_interface_parameter = "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE" *) input [0:31]LMB_ABus;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS" *) input [0:31]LMB_WriteDBus;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE" *) input LMB_AddrStrobe;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READSTROBE" *) input LMB_ReadStrobe;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE" *) input LMB_WriteStrobe;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB BE" *) input [0:3]LMB_BE;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READDBUS" *) output [0:31]Sl_DBus;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READY" *) output Sl_Ready;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WAIT" *) output Sl_Wait;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB UE" *) output Sl_UE;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB CE" *) output Sl_CE;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT RST" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 262144, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1" *) output BRAM_Rst_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT CLK" *) output BRAM_Clk_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR" *) output [0:31]BRAM_Addr_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT EN" *) output BRAM_EN_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT WE" *) output [0:3]BRAM_WEN_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DIN" *) output [0:31]BRAM_Dout_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT" *) input [0:31]BRAM_Din_A;
wire [0:31]BRAM_Addr_A;
wire BRAM_Clk_A;
wire [0:31]BRAM_Din_A;
wire [0:31]BRAM_Dout_A;
wire BRAM_EN_A;
wire BRAM_Rst_A;
wire [0:3]BRAM_WEN_A;
wire [0:31]LMB_ABus;
wire LMB_AddrStrobe;
wire [0:3]LMB_BE;
wire LMB_Clk;
wire LMB_ReadStrobe;
wire LMB_Rst;
wire [0:31]LMB_WriteDBus;
wire LMB_WriteStrobe;
wire Sl_CE;
wire [0:31]Sl_DBus;
wire Sl_Ready;
wire Sl_UE;
wire Sl_Wait;
wire NLW_U0_CE_UNCONNECTED;
wire NLW_U0_Interrupt_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED;
wire NLW_U0_Sl1_CE_UNCONNECTED;
wire NLW_U0_Sl1_Ready_UNCONNECTED;
wire NLW_U0_Sl1_UE_UNCONNECTED;
wire NLW_U0_Sl1_Wait_UNCONNECTED;
wire NLW_U0_Sl2_CE_UNCONNECTED;
wire NLW_U0_Sl2_Ready_UNCONNECTED;
wire NLW_U0_Sl2_UE_UNCONNECTED;
wire NLW_U0_Sl2_Wait_UNCONNECTED;
wire NLW_U0_Sl3_CE_UNCONNECTED;
wire NLW_U0_Sl3_Ready_UNCONNECTED;
wire NLW_U0_Sl3_UE_UNCONNECTED;
wire NLW_U0_Sl3_Wait_UNCONNECTED;
wire NLW_U0_UE_UNCONNECTED;
wire [1:0]NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED;
wire [31:0]NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED;
wire [1:0]NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED;
wire [0:31]NLW_U0_Sl1_DBus_UNCONNECTED;
wire [0:31]NLW_U0_Sl2_DBus_UNCONNECTED;
wire [0:31]NLW_U0_Sl3_DBus_UNCONNECTED;
(* C_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* C_BRAM_AWIDTH = "32" *)
(* C_CE_COUNTER_WIDTH = "0" *)
(* C_CE_FAILING_REGISTERS = "0" *)
(* C_ECC = "0" *)
(* C_ECC_ONOFF_REGISTER = "0" *)
(* C_ECC_ONOFF_RESET_VALUE = "1" *)
(* C_ECC_STATUS_REGISTERS = "0" *)
(* C_FAMILY = "kintex7" *)
(* C_FAULT_INJECT = "0" *)
(* C_HIGHADDR = "64'b0000000000000000000000000000000000000000000000111111111111111111" *)
(* C_INTERCONNECT = "0" *)
(* C_LMB_AWIDTH = "32" *)
(* C_LMB_DWIDTH = "32" *)
(* C_MASK = "64'b0000000000000000000000000000000001000000000000000000000000000000" *)
(* C_MASK1 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
(* C_MASK2 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
(* C_MASK3 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
(* C_NUM_LMB = "1" *)
(* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
(* C_S_AXI_CTRL_BASEADDR = "32'b11111111111111111111111111111111" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *)
(* C_S_AXI_CTRL_HIGHADDR = "32'b00000000000000000000000000000000" *)
(* C_UE_FAILING_REGISTERS = "0" *)
(* C_WRITE_ACCESS = "2" *)
system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr U0
(.BRAM_Addr_A(BRAM_Addr_A),
.BRAM_Clk_A(BRAM_Clk_A),
.BRAM_Din_A(BRAM_Din_A),
.BRAM_Dout_A(BRAM_Dout_A),
.BRAM_EN_A(BRAM_EN_A),
.BRAM_Rst_A(BRAM_Rst_A),
.BRAM_WEN_A(BRAM_WEN_A),
.CE(NLW_U0_CE_UNCONNECTED),
.Interrupt(NLW_U0_Interrupt_UNCONNECTED),
.LMB1_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB1_AddrStrobe(1'b0),
.LMB1_BE({1'b0,1'b0,1'b0,1'b0}),
.LMB1_ReadStrobe(1'b0),
.LMB1_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB1_WriteStrobe(1'b0),
.LMB2_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB2_AddrStrobe(1'b0),
.LMB2_BE({1'b0,1'b0,1'b0,1'b0}),
.LMB2_ReadStrobe(1'b0),
.LMB2_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB2_WriteStrobe(1'b0),
.LMB3_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB3_AddrStrobe(1'b0),
.LMB3_BE({1'b0,1'b0,1'b0,1'b0}),
.LMB3_ReadStrobe(1'b0),
.LMB3_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB3_WriteStrobe(1'b0),
.LMB_ABus(LMB_ABus),
.LMB_AddrStrobe(LMB_AddrStrobe),
.LMB_BE(LMB_BE),
.LMB_Clk(LMB_Clk),
.LMB_ReadStrobe(LMB_ReadStrobe),
.LMB_Rst(LMB_Rst),
.LMB_WriteDBus(LMB_WriteDBus),
.LMB_WriteStrobe(LMB_WriteStrobe),
.S_AXI_CTRL_ACLK(1'b0),
.S_AXI_CTRL_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_CTRL_ARESETN(1'b0),
.S_AXI_CTRL_ARREADY(NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED),
.S_AXI_CTRL_ARVALID(1'b0),
.S_AXI_CTRL_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_CTRL_AWREADY(NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED),
.S_AXI_CTRL_AWVALID(1'b0),
.S_AXI_CTRL_BREADY(1'b0),
.S_AXI_CTRL_BRESP(NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED[1:0]),
.S_AXI_CTRL_BVALID(NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED),
.S_AXI_CTRL_RDATA(NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED[31:0]),
.S_AXI_CTRL_RREADY(1'b0),
.S_AXI_CTRL_RRESP(NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED[1:0]),
.S_AXI_CTRL_RVALID(NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED),
.S_AXI_CTRL_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_CTRL_WREADY(NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED),
.S_AXI_CTRL_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_CTRL_WVALID(1'b0),
.Sl1_CE(NLW_U0_Sl1_CE_UNCONNECTED),
.Sl1_DBus(NLW_U0_Sl1_DBus_UNCONNECTED[0:31]),
.Sl1_Ready(NLW_U0_Sl1_Ready_UNCONNECTED),
.Sl1_UE(NLW_U0_Sl1_UE_UNCONNECTED),
.Sl1_Wait(NLW_U0_Sl1_Wait_UNCONNECTED),
.Sl2_CE(NLW_U0_Sl2_CE_UNCONNECTED),
.Sl2_DBus(NLW_U0_Sl2_DBus_UNCONNECTED[0:31]),
.Sl2_Ready(NLW_U0_Sl2_Ready_UNCONNECTED),
.Sl2_UE(NLW_U0_Sl2_UE_UNCONNECTED),
.Sl2_Wait(NLW_U0_Sl2_Wait_UNCONNECTED),
.Sl3_CE(NLW_U0_Sl3_CE_UNCONNECTED),
.Sl3_DBus(NLW_U0_Sl3_DBus_UNCONNECTED[0:31]),
.Sl3_Ready(NLW_U0_Sl3_Ready_UNCONNECTED),
.Sl3_UE(NLW_U0_Sl3_UE_UNCONNECTED),
.Sl3_Wait(NLW_U0_Sl3_Wait_UNCONNECTED),
.Sl_CE(Sl_CE),
.Sl_DBus(Sl_DBus),
.Sl_Ready(Sl_Ready),
.Sl_UE(Sl_UE),
.Sl_Wait(Sl_Wait),
.UE(NLW_U0_UE_UNCONNECTED));
endmodule
(* C_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_BRAM_AWIDTH = "32" *) (* C_CE_COUNTER_WIDTH = "0" *)
(* C_CE_FAILING_REGISTERS = "0" *) (* C_ECC = "0" *) (* C_ECC_ONOFF_REGISTER = "0" *)
(* C_ECC_ONOFF_RESET_VALUE = "1" *) (* C_ECC_STATUS_REGISTERS = "0" *) (* C_FAMILY = "kintex7" *)
@@ -20,7 +214,7 @@
(* C_MASK1 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) (* C_MASK2 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) (* C_MASK3 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
(* C_NUM_LMB = "1" *) (* C_S_AXI_CTRL_ADDR_WIDTH = "32" *) (* C_S_AXI_CTRL_BASEADDR = "32'b11111111111111111111111111111111" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *) (* C_S_AXI_CTRL_HIGHADDR = "32'b00000000000000000000000000000000" *) (* C_UE_FAILING_REGISTERS = "0" *)
(* C_WRITE_ACCESS = "2" *)
(* C_WRITE_ACCESS = "2" *) (* ORIG_REF_NAME = "lmb_bram_if_cntlr" *)
module system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr
(LMB_Clk,
LMB_Rst,
@@ -417,200 +611,6 @@ module system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr
.I1(lmb_as),
.O(Sl_Ready));
endmodule
(* CHECK_LICENSE_TYPE = "system_bd_dlmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "lmb_bram_if_cntlr,Vivado 2019.1.3" *)
(* NotValidForBitStream *)
module system_bd_dlmb_bram_if_cntlr_0
(LMB_Clk,
LMB_Rst,
LMB_ABus,
LMB_WriteDBus,
LMB_AddrStrobe,
LMB_ReadStrobe,
LMB_WriteStrobe,
LMB_BE,
Sl_DBus,
Sl_Ready,
Sl_Wait,
Sl_UE,
Sl_CE,
BRAM_Rst_A,
BRAM_Clk_A,
BRAM_Addr_A,
BRAM_EN_A,
BRAM_WEN_A,
BRAM_Dout_A,
BRAM_Din_A);
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input LMB_Clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) input LMB_Rst;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ABUS" *) (* x_interface_parameter = "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE" *) input [0:31]LMB_ABus;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS" *) input [0:31]LMB_WriteDBus;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE" *) input LMB_AddrStrobe;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READSTROBE" *) input LMB_ReadStrobe;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE" *) input LMB_WriteStrobe;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB BE" *) input [0:3]LMB_BE;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READDBUS" *) output [0:31]Sl_DBus;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READY" *) output Sl_Ready;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WAIT" *) output Sl_Wait;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB UE" *) output Sl_UE;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB CE" *) output Sl_CE;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT RST" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 262144, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1" *) output BRAM_Rst_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT CLK" *) output BRAM_Clk_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR" *) output [0:31]BRAM_Addr_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT EN" *) output BRAM_EN_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT WE" *) output [0:3]BRAM_WEN_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DIN" *) output [0:31]BRAM_Dout_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT" *) input [0:31]BRAM_Din_A;
wire [0:31]BRAM_Addr_A;
wire BRAM_Clk_A;
wire [0:31]BRAM_Din_A;
wire [0:31]BRAM_Dout_A;
wire BRAM_EN_A;
wire BRAM_Rst_A;
wire [0:3]BRAM_WEN_A;
wire [0:31]LMB_ABus;
wire LMB_AddrStrobe;
wire [0:3]LMB_BE;
wire LMB_Clk;
wire LMB_ReadStrobe;
wire LMB_Rst;
wire [0:31]LMB_WriteDBus;
wire LMB_WriteStrobe;
wire Sl_CE;
wire [0:31]Sl_DBus;
wire Sl_Ready;
wire Sl_UE;
wire Sl_Wait;
wire NLW_U0_CE_UNCONNECTED;
wire NLW_U0_Interrupt_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED;
wire NLW_U0_Sl1_CE_UNCONNECTED;
wire NLW_U0_Sl1_Ready_UNCONNECTED;
wire NLW_U0_Sl1_UE_UNCONNECTED;
wire NLW_U0_Sl1_Wait_UNCONNECTED;
wire NLW_U0_Sl2_CE_UNCONNECTED;
wire NLW_U0_Sl2_Ready_UNCONNECTED;
wire NLW_U0_Sl2_UE_UNCONNECTED;
wire NLW_U0_Sl2_Wait_UNCONNECTED;
wire NLW_U0_Sl3_CE_UNCONNECTED;
wire NLW_U0_Sl3_Ready_UNCONNECTED;
wire NLW_U0_Sl3_UE_UNCONNECTED;
wire NLW_U0_Sl3_Wait_UNCONNECTED;
wire NLW_U0_UE_UNCONNECTED;
wire [1:0]NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED;
wire [31:0]NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED;
wire [1:0]NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED;
wire [0:31]NLW_U0_Sl1_DBus_UNCONNECTED;
wire [0:31]NLW_U0_Sl2_DBus_UNCONNECTED;
wire [0:31]NLW_U0_Sl3_DBus_UNCONNECTED;
(* C_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* C_BRAM_AWIDTH = "32" *)
(* C_CE_COUNTER_WIDTH = "0" *)
(* C_CE_FAILING_REGISTERS = "0" *)
(* C_ECC = "0" *)
(* C_ECC_ONOFF_REGISTER = "0" *)
(* C_ECC_ONOFF_RESET_VALUE = "1" *)
(* C_ECC_STATUS_REGISTERS = "0" *)
(* C_FAMILY = "kintex7" *)
(* C_FAULT_INJECT = "0" *)
(* C_HIGHADDR = "64'b0000000000000000000000000000000000000000000000111111111111111111" *)
(* C_INTERCONNECT = "0" *)
(* C_LMB_AWIDTH = "32" *)
(* C_LMB_DWIDTH = "32" *)
(* C_MASK = "64'b0000000000000000000000000000000001000000000000000000000000000000" *)
(* C_MASK1 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
(* C_MASK2 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
(* C_MASK3 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
(* C_NUM_LMB = "1" *)
(* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
(* C_S_AXI_CTRL_BASEADDR = "32'b11111111111111111111111111111111" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *)
(* C_S_AXI_CTRL_HIGHADDR = "32'b00000000000000000000000000000000" *)
(* C_UE_FAILING_REGISTERS = "0" *)
(* C_WRITE_ACCESS = "2" *)
system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr U0
(.BRAM_Addr_A(BRAM_Addr_A),
.BRAM_Clk_A(BRAM_Clk_A),
.BRAM_Din_A(BRAM_Din_A),
.BRAM_Dout_A(BRAM_Dout_A),
.BRAM_EN_A(BRAM_EN_A),
.BRAM_Rst_A(BRAM_Rst_A),
.BRAM_WEN_A(BRAM_WEN_A),
.CE(NLW_U0_CE_UNCONNECTED),
.Interrupt(NLW_U0_Interrupt_UNCONNECTED),
.LMB1_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB1_AddrStrobe(1'b0),
.LMB1_BE({1'b0,1'b0,1'b0,1'b0}),
.LMB1_ReadStrobe(1'b0),
.LMB1_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB1_WriteStrobe(1'b0),
.LMB2_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB2_AddrStrobe(1'b0),
.LMB2_BE({1'b0,1'b0,1'b0,1'b0}),
.LMB2_ReadStrobe(1'b0),
.LMB2_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB2_WriteStrobe(1'b0),
.LMB3_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB3_AddrStrobe(1'b0),
.LMB3_BE({1'b0,1'b0,1'b0,1'b0}),
.LMB3_ReadStrobe(1'b0),
.LMB3_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB3_WriteStrobe(1'b0),
.LMB_ABus(LMB_ABus),
.LMB_AddrStrobe(LMB_AddrStrobe),
.LMB_BE(LMB_BE),
.LMB_Clk(LMB_Clk),
.LMB_ReadStrobe(LMB_ReadStrobe),
.LMB_Rst(LMB_Rst),
.LMB_WriteDBus(LMB_WriteDBus),
.LMB_WriteStrobe(LMB_WriteStrobe),
.S_AXI_CTRL_ACLK(1'b0),
.S_AXI_CTRL_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_CTRL_ARESETN(1'b0),
.S_AXI_CTRL_ARREADY(NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED),
.S_AXI_CTRL_ARVALID(1'b0),
.S_AXI_CTRL_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_CTRL_AWREADY(NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED),
.S_AXI_CTRL_AWVALID(1'b0),
.S_AXI_CTRL_BREADY(1'b0),
.S_AXI_CTRL_BRESP(NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED[1:0]),
.S_AXI_CTRL_BVALID(NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED),
.S_AXI_CTRL_RDATA(NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED[31:0]),
.S_AXI_CTRL_RREADY(1'b0),
.S_AXI_CTRL_RRESP(NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED[1:0]),
.S_AXI_CTRL_RVALID(NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED),
.S_AXI_CTRL_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_CTRL_WREADY(NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED),
.S_AXI_CTRL_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_CTRL_WVALID(1'b0),
.Sl1_CE(NLW_U0_Sl1_CE_UNCONNECTED),
.Sl1_DBus(NLW_U0_Sl1_DBus_UNCONNECTED[0:31]),
.Sl1_Ready(NLW_U0_Sl1_Ready_UNCONNECTED),
.Sl1_UE(NLW_U0_Sl1_UE_UNCONNECTED),
.Sl1_Wait(NLW_U0_Sl1_Wait_UNCONNECTED),
.Sl2_CE(NLW_U0_Sl2_CE_UNCONNECTED),
.Sl2_DBus(NLW_U0_Sl2_DBus_UNCONNECTED[0:31]),
.Sl2_Ready(NLW_U0_Sl2_Ready_UNCONNECTED),
.Sl2_UE(NLW_U0_Sl2_UE_UNCONNECTED),
.Sl2_Wait(NLW_U0_Sl2_Wait_UNCONNECTED),
.Sl3_CE(NLW_U0_Sl3_CE_UNCONNECTED),
.Sl3_DBus(NLW_U0_Sl3_DBus_UNCONNECTED[0:31]),
.Sl3_Ready(NLW_U0_Sl3_Ready_UNCONNECTED),
.Sl3_UE(NLW_U0_Sl3_UE_UNCONNECTED),
.Sl3_Wait(NLW_U0_Sl3_Wait_UNCONNECTED),
.Sl_CE(Sl_CE),
.Sl_DBus(Sl_DBus),
.Sl_Ready(Sl_Ready),
.Sl_UE(Sl_UE),
.Sl_Wait(Sl_Wait),
.UE(NLW_U0_UE_UNCONNECTED));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_sim_netlist.vhdl
+7 -5
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@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:09 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_bd_dlmb_bram_if_cntlr_0 -prefix
-- system_bd_dlmb_bram_if_cntlr_0_ system_bd_dlmb_bram_if_cntlr_0_sim_netlist.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:55:51 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_sim_netlist.vhdl
-- Design : system_bd_dlmb_bram_if_cntlr_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -142,6 +142,8 @@ entity system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr is
attribute C_UE_FAILING_REGISTERS of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_WRITE_ACCESS : integer;
attribute C_WRITE_ACCESS of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 2;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "lmb_bram_if_cntlr";
end system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr;
architecture STRUCTURE of system_bd_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr is
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_stub.v
+5 -5
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@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:09 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_bd_dlmb_bram_if_cntlr_0 -prefix
// system_bd_dlmb_bram_if_cntlr_0_ system_bd_dlmb_bram_if_cntlr_0_stub.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:55:51 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_stub.v
// Design : system_bd_dlmb_bram_if_cntlr_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_stub.vhdl
+5 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:09 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_dlmb_bram_if_cntlr_0 -prefix
-- system_bd_dlmb_bram_if_cntlr_0_ system_bd_dlmb_bram_if_cntlr_0_stub.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:55:51 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_stub.vhdl
-- Design : system_bd_dlmb_bram_if_cntlr_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0.dcp
BIN
View File
Binary file not shown.
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0.xml
+18 -18
View File
@@ -2867,7 +2867,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:55 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -2885,7 +2885,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:55 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -2905,7 +2905,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:55 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -2925,7 +2925,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:55 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -2945,7 +2945,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:55 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -2963,7 +2963,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:56:13 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -3456,6 +3456,18 @@
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_dlmb_v10_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_dlmb_v10_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_dlmb_v10_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
@@ -3470,18 +3482,6 @@
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_dlmb_v10_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_dlmb_v10_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM</spirit:description>
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_sim_netlist.v
+97 -97
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:10 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_bd_dlmb_v10_0 -prefix
// system_bd_dlmb_v10_0_ system_bd_dlmb_v10_0_sim_netlist.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:56:13 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode funcsim
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_sim_netlist.v
// Design : system_bd_dlmb_v10_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -12,98 +12,6 @@
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* C_EXT_RESET_HIGH = "1" *) (* C_LMB_AWIDTH = "32" *) (* C_LMB_DWIDTH = "32" *)
(* C_LMB_NUM_SLAVES = "1" *)
module system_bd_dlmb_v10_0_lmb_v10
(LMB_Clk,
SYS_Rst,
LMB_Rst,
M_ABus,
M_ReadStrobe,
M_WriteStrobe,
M_AddrStrobe,
M_DBus,
M_BE,
Sl_DBus,
Sl_Ready,
Sl_Wait,
Sl_UE,
Sl_CE,
LMB_ABus,
LMB_ReadStrobe,
LMB_WriteStrobe,
LMB_AddrStrobe,
LMB_ReadDBus,
LMB_WriteDBus,
LMB_Ready,
LMB_Wait,
LMB_UE,
LMB_CE,
LMB_BE);
input LMB_Clk;
input SYS_Rst;
output LMB_Rst;
input [0:31]M_ABus;
input M_ReadStrobe;
input M_WriteStrobe;
input M_AddrStrobe;
input [0:31]M_DBus;
input [0:3]M_BE;
input [0:31]Sl_DBus;
input [0:0]Sl_Ready;
input [0:0]Sl_Wait;
input [0:0]Sl_UE;
input [0:0]Sl_CE;
output [0:31]LMB_ABus;
output LMB_ReadStrobe;
output LMB_WriteStrobe;
output LMB_AddrStrobe;
output [0:31]LMB_ReadDBus;
output [0:31]LMB_WriteDBus;
output LMB_Ready;
output LMB_Wait;
output LMB_UE;
output LMB_CE;
output [0:3]LMB_BE;
wire LMB_Clk;
wire LMB_Rst;
wire [0:31]M_ABus;
wire M_AddrStrobe;
wire [0:3]M_BE;
wire [0:31]M_DBus;
wire M_ReadStrobe;
wire M_WriteStrobe;
wire SYS_Rst;
wire [0:0]Sl_CE;
wire [0:31]Sl_DBus;
wire [0:0]Sl_Ready;
wire [0:0]Sl_UE;
wire [0:0]Sl_Wait;
assign LMB_ABus[0:31] = M_ABus;
assign LMB_AddrStrobe = M_AddrStrobe;
assign LMB_BE[0:3] = M_BE;
assign LMB_CE = Sl_CE;
assign LMB_ReadDBus[0:31] = Sl_DBus;
assign LMB_ReadStrobe = M_ReadStrobe;
assign LMB_Ready = Sl_Ready;
assign LMB_UE = Sl_UE;
assign LMB_Wait = Sl_Wait;
assign LMB_WriteDBus[0:31] = M_DBus;
assign LMB_WriteStrobe = M_WriteStrobe;
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDS" *)
FDSE #(
.INIT(1'b1))
POR_FF_I
(.C(LMB_Clk),
.CE(1'b1),
.D(1'b0),
.Q(LMB_Rst),
.S(SYS_Rst));
endmodule
(* CHECK_LICENSE_TYPE = "system_bd_dlmb_v10_0,lmb_v10,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "lmb_v10,Vivado 2019.1.3" *)
(* NotValidForBitStream *)
module system_bd_dlmb_v10_0
@@ -215,6 +123,98 @@ module system_bd_dlmb_v10_0
.Sl_UE(Sl_UE),
.Sl_Wait(Sl_Wait));
endmodule
(* C_EXT_RESET_HIGH = "1" *) (* C_LMB_AWIDTH = "32" *) (* C_LMB_DWIDTH = "32" *)
(* C_LMB_NUM_SLAVES = "1" *) (* ORIG_REF_NAME = "lmb_v10" *)
module system_bd_dlmb_v10_0_lmb_v10
(LMB_Clk,
SYS_Rst,
LMB_Rst,
M_ABus,
M_ReadStrobe,
M_WriteStrobe,
M_AddrStrobe,
M_DBus,
M_BE,
Sl_DBus,
Sl_Ready,
Sl_Wait,
Sl_UE,
Sl_CE,
LMB_ABus,
LMB_ReadStrobe,
LMB_WriteStrobe,
LMB_AddrStrobe,
LMB_ReadDBus,
LMB_WriteDBus,
LMB_Ready,
LMB_Wait,
LMB_UE,
LMB_CE,
LMB_BE);
input LMB_Clk;
input SYS_Rst;
output LMB_Rst;
input [0:31]M_ABus;
input M_ReadStrobe;
input M_WriteStrobe;
input M_AddrStrobe;
input [0:31]M_DBus;
input [0:3]M_BE;
input [0:31]Sl_DBus;
input [0:0]Sl_Ready;
input [0:0]Sl_Wait;
input [0:0]Sl_UE;
input [0:0]Sl_CE;
output [0:31]LMB_ABus;
output LMB_ReadStrobe;
output LMB_WriteStrobe;
output LMB_AddrStrobe;
output [0:31]LMB_ReadDBus;
output [0:31]LMB_WriteDBus;
output LMB_Ready;
output LMB_Wait;
output LMB_UE;
output LMB_CE;
output [0:3]LMB_BE;
wire LMB_Clk;
wire LMB_Rst;
wire [0:31]M_ABus;
wire M_AddrStrobe;
wire [0:3]M_BE;
wire [0:31]M_DBus;
wire M_ReadStrobe;
wire M_WriteStrobe;
wire SYS_Rst;
wire [0:0]Sl_CE;
wire [0:31]Sl_DBus;
wire [0:0]Sl_Ready;
wire [0:0]Sl_UE;
wire [0:0]Sl_Wait;
assign LMB_ABus[0:31] = M_ABus;
assign LMB_AddrStrobe = M_AddrStrobe;
assign LMB_BE[0:3] = M_BE;
assign LMB_CE = Sl_CE;
assign LMB_ReadDBus[0:31] = Sl_DBus;
assign LMB_ReadStrobe = M_ReadStrobe;
assign LMB_Ready = Sl_Ready;
assign LMB_UE = Sl_UE;
assign LMB_Wait = Sl_Wait;
assign LMB_WriteDBus[0:31] = M_DBus;
assign LMB_WriteStrobe = M_WriteStrobe;
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDS" *)
FDSE #(
.INIT(1'b1))
POR_FF_I
(.C(LMB_Clk),
.CE(1'b1),
.D(1'b0),
.Q(LMB_Rst),
.S(SYS_Rst));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_sim_netlist.vhdl
+7 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:10 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_bd_dlmb_v10_0 -prefix
-- system_bd_dlmb_v10_0_ system_bd_dlmb_v10_0_sim_netlist.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:56:13 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_sim_netlist.vhdl
-- Design : system_bd_dlmb_v10_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -50,6 +50,8 @@ entity system_bd_dlmb_v10_0_lmb_v10 is
attribute C_LMB_DWIDTH of system_bd_dlmb_v10_0_lmb_v10 : entity is 32;
attribute C_LMB_NUM_SLAVES : integer;
attribute C_LMB_NUM_SLAVES of system_bd_dlmb_v10_0_lmb_v10 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_dlmb_v10_0_lmb_v10 : entity is "lmb_v10";
end system_bd_dlmb_v10_0_lmb_v10;
architecture STRUCTURE of system_bd_dlmb_v10_0_lmb_v10 is
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_stub.v
+5 -5
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:10 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_bd_dlmb_v10_0 -prefix
// system_bd_dlmb_v10_0_ system_bd_dlmb_v10_0_stub.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:56:13 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_stub.v
// Design : system_bd_dlmb_v10_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_stub.vhdl
+5 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:10 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_dlmb_v10_0 -prefix
-- system_bd_dlmb_v10_0_ system_bd_dlmb_v10_0_stub.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:56:13 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_stub.vhdl
-- Design : system_bd_dlmb_v10_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0.dcp
BIN
View File
Binary file not shown.
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0.xml
+18 -18
View File
@@ -1891,7 +1891,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:54 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1909,7 +1909,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:55 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1929,7 +1929,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:55 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1949,7 +1949,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:54 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1969,7 +1969,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:55 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1987,7 +1987,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:56:13 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -3858,6 +3858,18 @@
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_ilmb_bram_if_cntlr_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_ilmb_bram_if_cntlr_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_ilmb_bram_if_cntlr_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
@@ -3872,18 +3884,6 @@
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_ilmb_bram_if_cntlr_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_ilmb_bram_if_cntlr_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</spirit:description>
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_sim_netlist.v
+200 -200
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:10 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_bd_ilmb_bram_if_cntlr_0 -prefix
// system_bd_ilmb_bram_if_cntlr_0_ system_bd_ilmb_bram_if_cntlr_0_sim_netlist.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:56:13 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode funcsim
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_sim_netlist.v
// Design : system_bd_ilmb_bram_if_cntlr_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -12,6 +12,200 @@
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_bd_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "lmb_bram_if_cntlr,Vivado 2019.1.3" *)
(* NotValidForBitStream *)
module system_bd_ilmb_bram_if_cntlr_0
(LMB_Clk,
LMB_Rst,
LMB_ABus,
LMB_WriteDBus,
LMB_AddrStrobe,
LMB_ReadStrobe,
LMB_WriteStrobe,
LMB_BE,
Sl_DBus,
Sl_Ready,
Sl_Wait,
Sl_UE,
Sl_CE,
BRAM_Rst_A,
BRAM_Clk_A,
BRAM_Addr_A,
BRAM_EN_A,
BRAM_WEN_A,
BRAM_Dout_A,
BRAM_Din_A);
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input LMB_Clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) input LMB_Rst;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ABUS" *) (* x_interface_parameter = "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE" *) input [0:31]LMB_ABus;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS" *) input [0:31]LMB_WriteDBus;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE" *) input LMB_AddrStrobe;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READSTROBE" *) input LMB_ReadStrobe;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE" *) input LMB_WriteStrobe;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB BE" *) input [0:3]LMB_BE;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READDBUS" *) output [0:31]Sl_DBus;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READY" *) output Sl_Ready;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WAIT" *) output Sl_Wait;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB UE" *) output Sl_UE;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB CE" *) output Sl_CE;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT RST" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 262144, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1" *) output BRAM_Rst_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT CLK" *) output BRAM_Clk_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR" *) output [0:31]BRAM_Addr_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT EN" *) output BRAM_EN_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT WE" *) output [0:3]BRAM_WEN_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DIN" *) output [0:31]BRAM_Dout_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT" *) input [0:31]BRAM_Din_A;
wire [0:31]BRAM_Addr_A;
wire BRAM_Clk_A;
wire [0:31]BRAM_Din_A;
wire [0:31]BRAM_Dout_A;
wire BRAM_EN_A;
wire BRAM_Rst_A;
wire [0:3]BRAM_WEN_A;
wire [0:31]LMB_ABus;
wire LMB_AddrStrobe;
wire [0:3]LMB_BE;
wire LMB_Clk;
wire LMB_ReadStrobe;
wire LMB_Rst;
wire [0:31]LMB_WriteDBus;
wire LMB_WriteStrobe;
wire Sl_CE;
wire [0:31]Sl_DBus;
wire Sl_Ready;
wire Sl_UE;
wire Sl_Wait;
wire NLW_U0_CE_UNCONNECTED;
wire NLW_U0_Interrupt_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED;
wire NLW_U0_Sl1_CE_UNCONNECTED;
wire NLW_U0_Sl1_Ready_UNCONNECTED;
wire NLW_U0_Sl1_UE_UNCONNECTED;
wire NLW_U0_Sl1_Wait_UNCONNECTED;
wire NLW_U0_Sl2_CE_UNCONNECTED;
wire NLW_U0_Sl2_Ready_UNCONNECTED;
wire NLW_U0_Sl2_UE_UNCONNECTED;
wire NLW_U0_Sl2_Wait_UNCONNECTED;
wire NLW_U0_Sl3_CE_UNCONNECTED;
wire NLW_U0_Sl3_Ready_UNCONNECTED;
wire NLW_U0_Sl3_UE_UNCONNECTED;
wire NLW_U0_Sl3_Wait_UNCONNECTED;
wire NLW_U0_UE_UNCONNECTED;
wire [1:0]NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED;
wire [31:0]NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED;
wire [1:0]NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED;
wire [0:31]NLW_U0_Sl1_DBus_UNCONNECTED;
wire [0:31]NLW_U0_Sl2_DBus_UNCONNECTED;
wire [0:31]NLW_U0_Sl3_DBus_UNCONNECTED;
(* C_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* C_BRAM_AWIDTH = "32" *)
(* C_CE_COUNTER_WIDTH = "0" *)
(* C_CE_FAILING_REGISTERS = "0" *)
(* C_ECC = "0" *)
(* C_ECC_ONOFF_REGISTER = "0" *)
(* C_ECC_ONOFF_RESET_VALUE = "1" *)
(* C_ECC_STATUS_REGISTERS = "0" *)
(* C_FAMILY = "kintex7" *)
(* C_FAULT_INJECT = "0" *)
(* C_HIGHADDR = "64'b0000000000000000000000000000000000000000000000111111111111111111" *)
(* C_INTERCONNECT = "0" *)
(* C_LMB_AWIDTH = "32" *)
(* C_LMB_DWIDTH = "32" *)
(* C_MASK = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* C_MASK1 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
(* C_MASK2 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
(* C_MASK3 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
(* C_NUM_LMB = "1" *)
(* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
(* C_S_AXI_CTRL_BASEADDR = "32'b11111111111111111111111111111111" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *)
(* C_S_AXI_CTRL_HIGHADDR = "32'b00000000000000000000000000000000" *)
(* C_UE_FAILING_REGISTERS = "0" *)
(* C_WRITE_ACCESS = "2" *)
system_bd_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr U0
(.BRAM_Addr_A(BRAM_Addr_A),
.BRAM_Clk_A(BRAM_Clk_A),
.BRAM_Din_A(BRAM_Din_A),
.BRAM_Dout_A(BRAM_Dout_A),
.BRAM_EN_A(BRAM_EN_A),
.BRAM_Rst_A(BRAM_Rst_A),
.BRAM_WEN_A(BRAM_WEN_A),
.CE(NLW_U0_CE_UNCONNECTED),
.Interrupt(NLW_U0_Interrupt_UNCONNECTED),
.LMB1_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB1_AddrStrobe(1'b0),
.LMB1_BE({1'b0,1'b0,1'b0,1'b0}),
.LMB1_ReadStrobe(1'b0),
.LMB1_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB1_WriteStrobe(1'b0),
.LMB2_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB2_AddrStrobe(1'b0),
.LMB2_BE({1'b0,1'b0,1'b0,1'b0}),
.LMB2_ReadStrobe(1'b0),
.LMB2_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB2_WriteStrobe(1'b0),
.LMB3_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB3_AddrStrobe(1'b0),
.LMB3_BE({1'b0,1'b0,1'b0,1'b0}),
.LMB3_ReadStrobe(1'b0),
.LMB3_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB3_WriteStrobe(1'b0),
.LMB_ABus(LMB_ABus),
.LMB_AddrStrobe(LMB_AddrStrobe),
.LMB_BE(LMB_BE),
.LMB_Clk(LMB_Clk),
.LMB_ReadStrobe(LMB_ReadStrobe),
.LMB_Rst(LMB_Rst),
.LMB_WriteDBus(LMB_WriteDBus),
.LMB_WriteStrobe(LMB_WriteStrobe),
.S_AXI_CTRL_ACLK(1'b0),
.S_AXI_CTRL_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_CTRL_ARESETN(1'b0),
.S_AXI_CTRL_ARREADY(NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED),
.S_AXI_CTRL_ARVALID(1'b0),
.S_AXI_CTRL_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_CTRL_AWREADY(NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED),
.S_AXI_CTRL_AWVALID(1'b0),
.S_AXI_CTRL_BREADY(1'b0),
.S_AXI_CTRL_BRESP(NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED[1:0]),
.S_AXI_CTRL_BVALID(NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED),
.S_AXI_CTRL_RDATA(NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED[31:0]),
.S_AXI_CTRL_RREADY(1'b0),
.S_AXI_CTRL_RRESP(NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED[1:0]),
.S_AXI_CTRL_RVALID(NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED),
.S_AXI_CTRL_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_CTRL_WREADY(NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED),
.S_AXI_CTRL_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_CTRL_WVALID(1'b0),
.Sl1_CE(NLW_U0_Sl1_CE_UNCONNECTED),
.Sl1_DBus(NLW_U0_Sl1_DBus_UNCONNECTED[0:31]),
.Sl1_Ready(NLW_U0_Sl1_Ready_UNCONNECTED),
.Sl1_UE(NLW_U0_Sl1_UE_UNCONNECTED),
.Sl1_Wait(NLW_U0_Sl1_Wait_UNCONNECTED),
.Sl2_CE(NLW_U0_Sl2_CE_UNCONNECTED),
.Sl2_DBus(NLW_U0_Sl2_DBus_UNCONNECTED[0:31]),
.Sl2_Ready(NLW_U0_Sl2_Ready_UNCONNECTED),
.Sl2_UE(NLW_U0_Sl2_UE_UNCONNECTED),
.Sl2_Wait(NLW_U0_Sl2_Wait_UNCONNECTED),
.Sl3_CE(NLW_U0_Sl3_CE_UNCONNECTED),
.Sl3_DBus(NLW_U0_Sl3_DBus_UNCONNECTED[0:31]),
.Sl3_Ready(NLW_U0_Sl3_Ready_UNCONNECTED),
.Sl3_UE(NLW_U0_Sl3_UE_UNCONNECTED),
.Sl3_Wait(NLW_U0_Sl3_Wait_UNCONNECTED),
.Sl_CE(Sl_CE),
.Sl_DBus(Sl_DBus),
.Sl_Ready(Sl_Ready),
.Sl_UE(Sl_UE),
.Sl_Wait(Sl_Wait),
.UE(NLW_U0_UE_UNCONNECTED));
endmodule
(* C_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_BRAM_AWIDTH = "32" *) (* C_CE_COUNTER_WIDTH = "0" *)
(* C_CE_FAILING_REGISTERS = "0" *) (* C_ECC = "0" *) (* C_ECC_ONOFF_REGISTER = "0" *)
(* C_ECC_ONOFF_RESET_VALUE = "1" *) (* C_ECC_STATUS_REGISTERS = "0" *) (* C_FAMILY = "kintex7" *)
@@ -20,7 +214,7 @@
(* C_MASK1 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) (* C_MASK2 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) (* C_MASK3 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
(* C_NUM_LMB = "1" *) (* C_S_AXI_CTRL_ADDR_WIDTH = "32" *) (* C_S_AXI_CTRL_BASEADDR = "32'b11111111111111111111111111111111" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *) (* C_S_AXI_CTRL_HIGHADDR = "32'b00000000000000000000000000000000" *) (* C_UE_FAILING_REGISTERS = "0" *)
(* C_WRITE_ACCESS = "2" *)
(* C_WRITE_ACCESS = "2" *) (* ORIG_REF_NAME = "lmb_bram_if_cntlr" *)
module system_bd_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr
(LMB_Clk,
LMB_Rst,
@@ -412,200 +606,6 @@ module system_bd_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr
.I1(lmb_as),
.O(Sl_Ready));
endmodule
(* CHECK_LICENSE_TYPE = "system_bd_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "lmb_bram_if_cntlr,Vivado 2019.1.3" *)
(* NotValidForBitStream *)
module system_bd_ilmb_bram_if_cntlr_0
(LMB_Clk,
LMB_Rst,
LMB_ABus,
LMB_WriteDBus,
LMB_AddrStrobe,
LMB_ReadStrobe,
LMB_WriteStrobe,
LMB_BE,
Sl_DBus,
Sl_Ready,
Sl_Wait,
Sl_UE,
Sl_CE,
BRAM_Rst_A,
BRAM_Clk_A,
BRAM_Addr_A,
BRAM_EN_A,
BRAM_WEN_A,
BRAM_Dout_A,
BRAM_Din_A);
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input LMB_Clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) input LMB_Rst;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ABUS" *) (* x_interface_parameter = "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE" *) input [0:31]LMB_ABus;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS" *) input [0:31]LMB_WriteDBus;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE" *) input LMB_AddrStrobe;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READSTROBE" *) input LMB_ReadStrobe;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE" *) input LMB_WriteStrobe;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB BE" *) input [0:3]LMB_BE;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READDBUS" *) output [0:31]Sl_DBus;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READY" *) output Sl_Ready;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WAIT" *) output Sl_Wait;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB UE" *) output Sl_UE;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB CE" *) output Sl_CE;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT RST" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 262144, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1" *) output BRAM_Rst_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT CLK" *) output BRAM_Clk_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR" *) output [0:31]BRAM_Addr_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT EN" *) output BRAM_EN_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT WE" *) output [0:3]BRAM_WEN_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DIN" *) output [0:31]BRAM_Dout_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT" *) input [0:31]BRAM_Din_A;
wire [0:31]BRAM_Addr_A;
wire BRAM_Clk_A;
wire [0:31]BRAM_Din_A;
wire [0:31]BRAM_Dout_A;
wire BRAM_EN_A;
wire BRAM_Rst_A;
wire [0:3]BRAM_WEN_A;
wire [0:31]LMB_ABus;
wire LMB_AddrStrobe;
wire [0:3]LMB_BE;
wire LMB_Clk;
wire LMB_ReadStrobe;
wire LMB_Rst;
wire [0:31]LMB_WriteDBus;
wire LMB_WriteStrobe;
wire Sl_CE;
wire [0:31]Sl_DBus;
wire Sl_Ready;
wire Sl_UE;
wire Sl_Wait;
wire NLW_U0_CE_UNCONNECTED;
wire NLW_U0_Interrupt_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED;
wire NLW_U0_Sl1_CE_UNCONNECTED;
wire NLW_U0_Sl1_Ready_UNCONNECTED;
wire NLW_U0_Sl1_UE_UNCONNECTED;
wire NLW_U0_Sl1_Wait_UNCONNECTED;
wire NLW_U0_Sl2_CE_UNCONNECTED;
wire NLW_U0_Sl2_Ready_UNCONNECTED;
wire NLW_U0_Sl2_UE_UNCONNECTED;
wire NLW_U0_Sl2_Wait_UNCONNECTED;
wire NLW_U0_Sl3_CE_UNCONNECTED;
wire NLW_U0_Sl3_Ready_UNCONNECTED;
wire NLW_U0_Sl3_UE_UNCONNECTED;
wire NLW_U0_Sl3_Wait_UNCONNECTED;
wire NLW_U0_UE_UNCONNECTED;
wire [1:0]NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED;
wire [31:0]NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED;
wire [1:0]NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED;
wire [0:31]NLW_U0_Sl1_DBus_UNCONNECTED;
wire [0:31]NLW_U0_Sl2_DBus_UNCONNECTED;
wire [0:31]NLW_U0_Sl3_DBus_UNCONNECTED;
(* C_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* C_BRAM_AWIDTH = "32" *)
(* C_CE_COUNTER_WIDTH = "0" *)
(* C_CE_FAILING_REGISTERS = "0" *)
(* C_ECC = "0" *)
(* C_ECC_ONOFF_REGISTER = "0" *)
(* C_ECC_ONOFF_RESET_VALUE = "1" *)
(* C_ECC_STATUS_REGISTERS = "0" *)
(* C_FAMILY = "kintex7" *)
(* C_FAULT_INJECT = "0" *)
(* C_HIGHADDR = "64'b0000000000000000000000000000000000000000000000111111111111111111" *)
(* C_INTERCONNECT = "0" *)
(* C_LMB_AWIDTH = "32" *)
(* C_LMB_DWIDTH = "32" *)
(* C_MASK = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* C_MASK1 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
(* C_MASK2 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
(* C_MASK3 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
(* C_NUM_LMB = "1" *)
(* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
(* C_S_AXI_CTRL_BASEADDR = "32'b11111111111111111111111111111111" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *)
(* C_S_AXI_CTRL_HIGHADDR = "32'b00000000000000000000000000000000" *)
(* C_UE_FAILING_REGISTERS = "0" *)
(* C_WRITE_ACCESS = "2" *)
system_bd_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr U0
(.BRAM_Addr_A(BRAM_Addr_A),
.BRAM_Clk_A(BRAM_Clk_A),
.BRAM_Din_A(BRAM_Din_A),
.BRAM_Dout_A(BRAM_Dout_A),
.BRAM_EN_A(BRAM_EN_A),
.BRAM_Rst_A(BRAM_Rst_A),
.BRAM_WEN_A(BRAM_WEN_A),
.CE(NLW_U0_CE_UNCONNECTED),
.Interrupt(NLW_U0_Interrupt_UNCONNECTED),
.LMB1_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB1_AddrStrobe(1'b0),
.LMB1_BE({1'b0,1'b0,1'b0,1'b0}),
.LMB1_ReadStrobe(1'b0),
.LMB1_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB1_WriteStrobe(1'b0),
.LMB2_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB2_AddrStrobe(1'b0),
.LMB2_BE({1'b0,1'b0,1'b0,1'b0}),
.LMB2_ReadStrobe(1'b0),
.LMB2_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB2_WriteStrobe(1'b0),
.LMB3_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB3_AddrStrobe(1'b0),
.LMB3_BE({1'b0,1'b0,1'b0,1'b0}),
.LMB3_ReadStrobe(1'b0),
.LMB3_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB3_WriteStrobe(1'b0),
.LMB_ABus(LMB_ABus),
.LMB_AddrStrobe(LMB_AddrStrobe),
.LMB_BE(LMB_BE),
.LMB_Clk(LMB_Clk),
.LMB_ReadStrobe(LMB_ReadStrobe),
.LMB_Rst(LMB_Rst),
.LMB_WriteDBus(LMB_WriteDBus),
.LMB_WriteStrobe(LMB_WriteStrobe),
.S_AXI_CTRL_ACLK(1'b0),
.S_AXI_CTRL_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_CTRL_ARESETN(1'b0),
.S_AXI_CTRL_ARREADY(NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED),
.S_AXI_CTRL_ARVALID(1'b0),
.S_AXI_CTRL_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_CTRL_AWREADY(NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED),
.S_AXI_CTRL_AWVALID(1'b0),
.S_AXI_CTRL_BREADY(1'b0),
.S_AXI_CTRL_BRESP(NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED[1:0]),
.S_AXI_CTRL_BVALID(NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED),
.S_AXI_CTRL_RDATA(NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED[31:0]),
.S_AXI_CTRL_RREADY(1'b0),
.S_AXI_CTRL_RRESP(NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED[1:0]),
.S_AXI_CTRL_RVALID(NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED),
.S_AXI_CTRL_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_CTRL_WREADY(NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED),
.S_AXI_CTRL_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_CTRL_WVALID(1'b0),
.Sl1_CE(NLW_U0_Sl1_CE_UNCONNECTED),
.Sl1_DBus(NLW_U0_Sl1_DBus_UNCONNECTED[0:31]),
.Sl1_Ready(NLW_U0_Sl1_Ready_UNCONNECTED),
.Sl1_UE(NLW_U0_Sl1_UE_UNCONNECTED),
.Sl1_Wait(NLW_U0_Sl1_Wait_UNCONNECTED),
.Sl2_CE(NLW_U0_Sl2_CE_UNCONNECTED),
.Sl2_DBus(NLW_U0_Sl2_DBus_UNCONNECTED[0:31]),
.Sl2_Ready(NLW_U0_Sl2_Ready_UNCONNECTED),
.Sl2_UE(NLW_U0_Sl2_UE_UNCONNECTED),
.Sl2_Wait(NLW_U0_Sl2_Wait_UNCONNECTED),
.Sl3_CE(NLW_U0_Sl3_CE_UNCONNECTED),
.Sl3_DBus(NLW_U0_Sl3_DBus_UNCONNECTED[0:31]),
.Sl3_Ready(NLW_U0_Sl3_Ready_UNCONNECTED),
.Sl3_UE(NLW_U0_Sl3_UE_UNCONNECTED),
.Sl3_Wait(NLW_U0_Sl3_Wait_UNCONNECTED),
.Sl_CE(Sl_CE),
.Sl_DBus(Sl_DBus),
.Sl_Ready(Sl_Ready),
.Sl_UE(Sl_UE),
.Sl_Wait(Sl_Wait),
.UE(NLW_U0_UE_UNCONNECTED));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_sim_netlist.vhdl
+7 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:10 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_bd_ilmb_bram_if_cntlr_0 -prefix
-- system_bd_ilmb_bram_if_cntlr_0_ system_bd_ilmb_bram_if_cntlr_0_sim_netlist.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:56:13 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_sim_netlist.vhdl
-- Design : system_bd_ilmb_bram_if_cntlr_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -142,6 +142,8 @@ entity system_bd_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr is
attribute C_UE_FAILING_REGISTERS of system_bd_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_WRITE_ACCESS : integer;
attribute C_WRITE_ACCESS of system_bd_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 2;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "lmb_bram_if_cntlr";
end system_bd_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr;
architecture STRUCTURE of system_bd_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr is
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_stub.v
+5 -5
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:10 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_bd_ilmb_bram_if_cntlr_0 -prefix
// system_bd_ilmb_bram_if_cntlr_0_ system_bd_ilmb_bram_if_cntlr_0_stub.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:56:13 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_stub.v
// Design : system_bd_ilmb_bram_if_cntlr_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_stub.vhdl
+5 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:10 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_ilmb_bram_if_cntlr_0 -prefix
-- system_bd_ilmb_bram_if_cntlr_0_ system_bd_ilmb_bram_if_cntlr_0_stub.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:56:13 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_stub.vhdl
-- Design : system_bd_ilmb_bram_if_cntlr_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0.dcp
Regular → Executable
BIN
View File
Binary file not shown.
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0.xml
+18 -18
View File
@@ -2867,7 +2867,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:55 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -2885,7 +2885,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:55 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -2905,7 +2905,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:55 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -2925,7 +2925,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:55 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -2945,7 +2945,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:55 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -2963,7 +2963,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:56:19 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -3456,6 +3456,18 @@
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_ilmb_v10_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_ilmb_v10_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_ilmb_v10_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
@@ -3470,18 +3482,6 @@
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_ilmb_v10_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_ilmb_v10_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM</spirit:description>
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_sim_netlist.v
+3 -3
View File
@@ -1,8 +1,8 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:10 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:56:13 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode funcsim -rename_top system_bd_ilmb_v10_0 -prefix
// system_bd_ilmb_v10_0_ system_bd_dlmb_v10_0_sim_netlist.v
// Design : system_bd_dlmb_v10_0
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_sim_netlist.vhdl
+3 -3
View File
@@ -1,8 +1,8 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:10 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:56:13 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim -rename_top system_bd_ilmb_v10_0 -prefix
-- system_bd_ilmb_v10_0_ system_bd_dlmb_v10_0_sim_netlist.vhdl
-- Design : system_bd_dlmb_v10_0
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_stub.v
+3 -3
View File
@@ -1,8 +1,8 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:10 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:56:13 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode synth_stub -rename_top system_bd_ilmb_v10_0 -prefix
// system_bd_ilmb_v10_0_ system_bd_dlmb_v10_0_stub.v
// Design : system_bd_dlmb_v10_0
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_stub.vhdl
+3 -3
View File
@@ -1,8 +1,8 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:10 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:56:13 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_ilmb_v10_0 -prefix
-- system_bd_ilmb_v10_0_ system_bd_dlmb_v10_0_stub.vhdl
-- Design : system_bd_dlmb_v10_0
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0.dcp
BIN
View File
Binary file not shown.
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0.xml
+17 -17
View File
@@ -1458,7 +1458,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:51 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1489,7 +1489,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:55 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1508,7 +1508,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:55 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1528,7 +1528,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:55 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1546,7 +1546,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:57:03 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -3529,6 +3529,18 @@
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_lmb_bram_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_lmb_bram_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_lmb_bram_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
@@ -3543,18 +3555,6 @@
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_lmb_bram_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_lmb_bram_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet.</spirit:description>
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_sim_netlist.v
+11 -6
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:58:03 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_bd_lmb_bram_0 -prefix
// system_bd_lmb_bram_0_ system_bd_lmb_bram_0_sim_netlist.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:57:03 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode funcsim
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_sim_netlist.v
// Design : system_bd_lmb_bram_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -224,6 +224,7 @@ module system_bd_lmb_bram_0
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module system_bd_lmb_bram_0_blk_mem_gen_generic_cstr
(douta,
doutb,
@@ -783,6 +784,7 @@ module system_bd_lmb_bram_0_blk_mem_gen_generic_cstr
.web(web[1]));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module system_bd_lmb_bram_0_blk_mem_gen_prim_width
(douta,
doutb,
@@ -3018,6 +3020,7 @@ module system_bd_lmb_bram_0_blk_mem_gen_prim_width__parameterized9
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module system_bd_lmb_bram_0_blk_mem_gen_prim_wrapper
(douta,
doutb,
@@ -18817,6 +18820,7 @@ module system_bd_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized9
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module system_bd_lmb_bram_0_blk_mem_gen_top
(douta,
doutb,
@@ -18912,7 +18916,7 @@ endmodule
(* C_WEA_WIDTH = "4" *) (* C_WEB_WIDTH = "4" *) (* C_WRITE_DEPTH_A = "65536" *)
(* C_WRITE_DEPTH_B = "65536" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "32" *) (* C_WRITE_WIDTH_B = "32" *) (* C_XDEVICEFAMILY = "kintex7" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_3" *) (* downgradeipidentifiedwarnings = "yes" *)
module system_bd_lmb_bram_0_blk_mem_gen_v8_4_3
(clka,
rsta,
@@ -19198,6 +19202,7 @@ module system_bd_lmb_bram_0_blk_mem_gen_v8_4_3
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_3_synth" *)
module system_bd_lmb_bram_0_blk_mem_gen_v8_4_3_synth
(douta,
doutb,
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_sim_netlist.vhdl
+17 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:58:03 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_bd_lmb_bram_0 -prefix
-- system_bd_lmb_bram_0_ system_bd_lmb_bram_0_sim_netlist.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:57:03 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_sim_netlist.vhdl
-- Design : system_bd_lmb_bram_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -31,6 +31,8 @@ entity system_bd_lmb_bram_0_blk_mem_gen_prim_wrapper is
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_lmb_bram_0_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end system_bd_lmb_bram_0_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of system_bd_lmb_bram_0_blk_mem_gen_prim_wrapper is
@@ -16097,6 +16099,8 @@ entity system_bd_lmb_bram_0_blk_mem_gen_prim_width is
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_lmb_bram_0_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end system_bd_lmb_bram_0_blk_mem_gen_prim_width;
architecture STRUCTURE of system_bd_lmb_bram_0_blk_mem_gen_prim_width is
@@ -17787,6 +17791,8 @@ entity system_bd_lmb_bram_0_blk_mem_gen_generic_cstr is
rstb : in STD_LOGIC;
enb : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_lmb_bram_0_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end system_bd_lmb_bram_0_blk_mem_gen_generic_cstr;
architecture STRUCTURE of system_bd_lmb_bram_0_blk_mem_gen_generic_cstr is
@@ -18385,6 +18391,8 @@ entity system_bd_lmb_bram_0_blk_mem_gen_top is
rstb : in STD_LOGIC;
enb : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_lmb_bram_0_blk_mem_gen_top : entity is "blk_mem_gen_top";
end system_bd_lmb_bram_0_blk_mem_gen_top;
architecture STRUCTURE of system_bd_lmb_bram_0_blk_mem_gen_top is
@@ -18432,6 +18440,8 @@ entity system_bd_lmb_bram_0_blk_mem_gen_v8_4_3_synth is
rstb : in STD_LOGIC;
enb : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_lmb_bram_0_blk_mem_gen_v8_4_3_synth : entity is "blk_mem_gen_v8_4_3_synth";
end system_bd_lmb_bram_0_blk_mem_gen_v8_4_3_synth;
architecture STRUCTURE of system_bd_lmb_bram_0_blk_mem_gen_v8_4_3_synth is
@@ -18676,6 +18686,8 @@ entity system_bd_lmb_bram_0_blk_mem_gen_v8_4_3 is
attribute C_WRITE_WIDTH_B of system_bd_lmb_bram_0_blk_mem_gen_v8_4_3 : entity is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of system_bd_lmb_bram_0_blk_mem_gen_v8_4_3 : entity is "kintex7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_lmb_bram_0_blk_mem_gen_v8_4_3 : entity is "blk_mem_gen_v8_4_3";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_bd_lmb_bram_0_blk_mem_gen_v8_4_3 : entity is "yes";
end system_bd_lmb_bram_0_blk_mem_gen_v8_4_3;
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_stub.v
+5 -5
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:58:03 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_bd_lmb_bram_0 -prefix
// system_bd_lmb_bram_0_ system_bd_lmb_bram_0_stub.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:57:03 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_stub.v
// Design : system_bd_lmb_bram_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_stub.vhdl
+5 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:58:03 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_lmb_bram_0 -prefix
-- system_bd_lmb_bram_0_ system_bd_lmb_bram_0_stub.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:57:03 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_stub.vhdl
-- Design : system_bd_lmb_bram_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0.dcp
BIN
View File
Binary file not shown.
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0.xml
+17 -17
View File
@@ -30438,7 +30438,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:54 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -30469,7 +30469,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:54 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -30492,7 +30492,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:54 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -30512,7 +30512,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:54 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -30530,7 +30530,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:55:54 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -65390,6 +65390,18 @@
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_mdm_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_mdm_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_mdm_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
@@ -65404,18 +65416,6 @@
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_mdm_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_mdm_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>Debug module for MicroBlaze Soft Processor.</spirit:description>
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_sim_netlist.v
+2483 -2476
View File
File diff suppressed because it is too large Load Diff
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_sim_netlist.vhdl
+21 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:15 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_bd_mdm_0 -prefix
-- system_bd_mdm_0_ system_bd_mdm_0_sim_netlist.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:55:54 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_sim_netlist.vhdl
-- Design : system_bd_mdm_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -42,6 +42,8 @@ entity system_bd_mdm_0_MB_BSCANE2 is
Dbg_TDO_0 : in STD_LOGIC;
\Use_Serial_Unified_Completion.completion_status_reg[15]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_mdm_0_MB_BSCANE2 : entity is "MB_BSCANE2";
end system_bd_mdm_0_MB_BSCANE2;
architecture STRUCTURE of system_bd_mdm_0_MB_BSCANE2 is
@@ -170,6 +172,8 @@ entity system_bd_mdm_0_MB_BUFG is
Ext_JTAG_DRCK : out STD_LOGIC;
DRCK : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_mdm_0_MB_BUFG : entity is "MB_BUFG";
end system_bd_mdm_0_MB_BUFG;
architecture STRUCTURE of system_bd_mdm_0_MB_BUFG is
@@ -240,6 +244,8 @@ entity system_bd_mdm_0_MB_FDC_1 is
Debug_SYS_Rst : in STD_LOGIC;
Ext_NM_BRK : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_mdm_0_MB_FDC_1 : entity is "MB_FDC_1";
end system_bd_mdm_0_MB_FDC_1;
architecture STRUCTURE of system_bd_mdm_0_MB_FDC_1 is
@@ -854,6 +860,8 @@ entity system_bd_mdm_0_MB_FDRE_1 is
Dbg_Shift_0_3 : in STD_LOGIC;
Dbg_Shift_0_4 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_mdm_0_MB_FDRE_1 : entity is "MB_FDRE_1";
end system_bd_mdm_0_MB_FDRE_1;
architecture STRUCTURE of system_bd_mdm_0_MB_FDRE_1 is
@@ -910,6 +918,8 @@ entity system_bd_mdm_0_MB_SRL16E is
\Use_E2.BSCANE2_I_i_4_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
config_TDO_2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_mdm_0_MB_SRL16E : entity is "MB_SRL16E";
end system_bd_mdm_0_MB_SRL16E;
architecture STRUCTURE of system_bd_mdm_0_MB_SRL16E is
@@ -1149,6 +1159,8 @@ entity system_bd_mdm_0_JTAG_CONTROL is
\Use_Serial_Unified_Completion.count_reg[5]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\shift_Count_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_mdm_0_JTAG_CONTROL : entity is "JTAG_CONTROL";
end system_bd_mdm_0_JTAG_CONTROL;
architecture STRUCTURE of system_bd_mdm_0_JTAG_CONTROL is
@@ -2682,6 +2694,8 @@ entity system_bd_mdm_0_MDM_Core is
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\Use_Serial_Unified_Completion.count_reg[5]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_mdm_0_MDM_Core : entity is "MDM_Core";
end system_bd_mdm_0_MDM_Core;
architecture STRUCTURE of system_bd_mdm_0_MDM_Core is
@@ -4853,6 +4867,8 @@ entity system_bd_mdm_0_MDM is
attribute C_USE_CROSS_TRIGGER of system_bd_mdm_0_MDM : entity is 0;
attribute C_USE_UART : integer;
attribute C_USE_UART of system_bd_mdm_0_MDM : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_mdm_0_MDM : entity is "MDM";
end system_bd_mdm_0_MDM;
architecture STRUCTURE of system_bd_mdm_0_MDM is
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_stub.v
+5 -5
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:15 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_bd_mdm_0 -prefix
// system_bd_mdm_0_ system_bd_mdm_0_stub.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:55:53 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_stub.v
// Design : system_bd_mdm_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_stub.vhdl
+5 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:15 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_mdm_0 -prefix
-- system_bd_mdm_0_ system_bd_mdm_0_stub.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:55:53 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_mdm_0/system_bd_mdm_0_stub.vhdl
-- Design : system_bd_mdm_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/data/mb_bootloop_le.elf
Regular → Executable
View File
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0.dcp
BIN
View File
Binary file not shown.
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0.xml
+18 -18
View File
@@ -13931,7 +13931,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:54 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -13949,7 +13949,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:54 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -13969,7 +13969,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:54 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -13989,7 +13989,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:54 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -14009,7 +14009,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:54 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -14027,7 +14027,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:56:18 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -25472,6 +25472,18 @@
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_microblaze_ps_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_microblaze_ps_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_microblaze_ps_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
@@ -25486,18 +25498,6 @@
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_microblaze_ps_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_microblaze_ps_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:cpus>
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_sim_netlist.v
+47 -6
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:31 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_bd_microblaze_ps_0 -prefix
// system_bd_microblaze_ps_0_ system_bd_microblaze_ps_0_sim_netlist.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:56:17 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode funcsim
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_sim_netlist.v
// Design : system_bd_microblaze_ps_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -1028,6 +1028,7 @@ module system_bd_microblaze_ps_0
.Write_Strobe(Write_Strobe));
endmodule
(* ORIG_REF_NAME = "ALU" *)
module system_bd_microblaze_ps_0_ALU
(LO,
\EX_Op2_reg[0] ,
@@ -1708,6 +1709,7 @@ module system_bd_microblaze_ps_0_ALU
.lopt_3(lopt_74));
endmodule
(* ORIG_REF_NAME = "ALU_Bit" *)
module system_bd_microblaze_ps_0_ALU_Bit
(EX_CarryOut,
\EX_Op2_reg[10] ,
@@ -3951,6 +3953,7 @@ module system_bd_microblaze_ps_0_ALU_Bit__parameterized2
.lopt(lopt));
endmodule
(* ORIG_REF_NAME = "Byte_Doublet_Handle_gti" *)
module system_bd_microblaze_ps_0_Byte_Doublet_Handle_gti
(\No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel_reg[0]_0 ,
wb_read_msb_doublet_sel,
@@ -4289,6 +4292,7 @@ module system_bd_microblaze_ps_0_Byte_Doublet_Handle_gti
.R(sync_reset));
endmodule
(* ORIG_REF_NAME = "DAXI_interface" *)
module system_bd_microblaze_ps_0_DAXI_interface
(active_access_d1,
active_access,
@@ -5257,6 +5261,7 @@ module system_bd_microblaze_ps_0_DAXI_interface
.R(sync_reset));
endmodule
(* ORIG_REF_NAME = "Data_Flow_Logic" *)
module system_bd_microblaze_ps_0_Data_Flow_Logic
(\Using_FPGA.Native ,
MEM_Fwd,
@@ -5707,6 +5712,7 @@ module system_bd_microblaze_ps_0_Data_Flow_Logic
.R(SR));
endmodule
(* ORIG_REF_NAME = "Data_Flow_gti" *)
module system_bd_microblaze_ps_0_Data_Flow_gti
(\EX_Op1_reg[0] ,
out,
@@ -6544,6 +6550,7 @@ module system_bd_microblaze_ps_0_Data_Flow_gti
.wb_piperun(wb_piperun));
endmodule
(* ORIG_REF_NAME = "Debug" *)
module system_bd_microblaze_ps_0_Debug
(LOCKSTEP_Master_Out,
\Serial_Dbg_Intf.force_stop_cmd_i_reg_0 ,
@@ -9720,6 +9727,7 @@ module system_bd_microblaze_ps_0_Debug
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "Decode_gti" *)
module system_bd_microblaze_ps_0_Decode_gti
(of_pause_reg_0,
D,
@@ -14494,6 +14502,7 @@ module system_bd_microblaze_ps_0_Decode_gti
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "MB_AND2B1L" *)
module system_bd_microblaze_ps_0_MB_AND2B1L
(D,
E,
@@ -14515,6 +14524,7 @@ module system_bd_microblaze_ps_0_MB_AND2B1L
.SRI(SRI));
endmodule
(* ORIG_REF_NAME = "MB_FDE" *)
module system_bd_microblaze_ps_0_MB_FDE
(\Using_FPGA.Native_0 ,
\Using_FPGA.Native_1 ,
@@ -15410,6 +15420,7 @@ module system_bd_microblaze_ps_0_MB_FDE_401
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "MB_FDR" *)
module system_bd_microblaze_ps_0_MB_FDR
(\Performance_Debug_Control.ex_dbg_pc_hit_i_reg ,
sync_reset,
@@ -15496,6 +15507,7 @@ module system_bd_microblaze_ps_0_MB_FDR
.O(of_set_MSR_EE1));
endmodule
(* ORIG_REF_NAME = "MB_FDRE" *)
module system_bd_microblaze_ps_0_MB_FDRE
(D,
sync_reset,
@@ -25629,6 +25641,7 @@ module system_bd_microblaze_ps_0_MB_FDR_306
.O(\Using_FPGA.Native_0 ));
endmodule
(* ORIG_REF_NAME = "MB_FDS" *)
module system_bd_microblaze_ps_0_MB_FDS
(\Using_FPGA.Native_0 ,
I041_out,
@@ -26188,6 +26201,7 @@ module system_bd_microblaze_ps_0_MB_FDS
.O(I0_1));
endmodule
(* ORIG_REF_NAME = "MB_LUT4" *)
module system_bd_microblaze_ps_0_MB_LUT4
(S,
Q,
@@ -26217,6 +26231,7 @@ module system_bd_microblaze_ps_0_MB_LUT4
.O(S));
endmodule
(* ORIG_REF_NAME = "MB_LUT6" *)
module system_bd_microblaze_ps_0_MB_LUT6
(sel_input_iii_3,
if_sel_input,
@@ -26359,6 +26374,7 @@ module system_bd_microblaze_ps_0_MB_LUT6_118
.O(sel_input_iii_0));
endmodule
(* ORIG_REF_NAME = "MB_LUT6_2" *)
module system_bd_microblaze_ps_0_MB_LUT6_2
(DI,
S,
@@ -29827,6 +29843,7 @@ module system_bd_microblaze_ps_0_MB_LUT6__parameterized8_84
.O(of_read_mem_write_op3_conflict_part1));
endmodule
(* ORIG_REF_NAME = "MB_MULT_AND" *)
module system_bd_microblaze_ps_0_MB_MULT_AND
(DI,
I0,
@@ -29850,6 +29867,7 @@ module system_bd_microblaze_ps_0_MB_MULT_AND
.O(DI));
endmodule
(* ORIG_REF_NAME = "MB_MUXCY" *)
module system_bd_microblaze_ps_0_MB_MUXCY
(carry_7,
SRL16_Sel_7,
@@ -32283,6 +32301,7 @@ module system_bd_microblaze_ps_0_MB_MUXCY_99
.O(if_valid));
endmodule
(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *)
module system_bd_microblaze_ps_0_MB_MUXCY_XORCY
(O56_out,
Q,
@@ -36376,6 +36395,7 @@ module system_bd_microblaze_ps_0_MB_MUXCY_XORCY_580
assign \EX_Op2_reg[0]_0 = lopt_1;
endmodule
(* ORIG_REF_NAME = "MB_MUXF7" *)
module system_bd_microblaze_ps_0_MB_MUXF7
(sel_input_i_1,
I4_0,
@@ -39971,6 +39991,7 @@ module system_bd_microblaze_ps_0_MB_MUXF7_455
.O(swap_result));
endmodule
(* ORIG_REF_NAME = "MB_RAM32M" *)
module system_bd_microblaze_ps_0_MB_RAM32M
(GPR_Op1,
GPR_Op2,
@@ -40930,6 +40951,7 @@ module system_bd_microblaze_ps_0_MB_RAM32M_423
.WE(\EX_Branch_CMP_Op1_reg[18] ));
endmodule
(* ORIG_REF_NAME = "MB_SRL16E" *)
module system_bd_microblaze_ps_0_MB_SRL16E
(Q_0,
Q,
@@ -41480,6 +41502,7 @@ module system_bd_microblaze_ps_0_MB_SRL16E__parameterized9
.Q(Q1_in));
endmodule
(* ORIG_REF_NAME = "MB_SRLC16E" *)
module system_bd_microblaze_ps_0_MB_SRLC16E
(SRL16_Sel_7,
which_pc__0,
@@ -41863,7 +41886,7 @@ endmodule
(* C_USE_HW_MUL = "0" *) (* C_USE_ICACHE = "0" *) (* C_USE_INTERRUPT = "0" *)
(* C_USE_MMU = "0" *) (* C_USE_MSR_INSTR = "0" *) (* C_USE_NON_SECURE = "0" *)
(* C_USE_PCMP_INSTR = "0" *) (* C_USE_REORDER_INSTR = "1" *) (* C_USE_STACK_PROTECTION = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* ORIG_REF_NAME = "MicroBlaze" *) (* downgradeipidentifiedwarnings = "yes" *)
module system_bd_microblaze_ps_0_MicroBlaze
(RAM_To,
RAM_From,
@@ -54508,6 +54531,7 @@ module system_bd_microblaze_ps_0_MicroBlaze
(.P(\<const1> ));
endmodule
(* ORIG_REF_NAME = "MicroBlaze_Core" *)
module system_bd_microblaze_ps_0_MicroBlaze_Core
(of_pause_reg,
\Using_FPGA.Native ,
@@ -54730,6 +54754,7 @@ module system_bd_microblaze_ps_0_MicroBlaze_Core
.O(reset_temp__0));
endmodule
(* ORIG_REF_NAME = "MicroBlaze_GTi" *)
module system_bd_microblaze_ps_0_MicroBlaze_GTi
(E,
\Using_FPGA.Native ,
@@ -56261,6 +56286,7 @@ module system_bd_microblaze_ps_0_MicroBlaze_GTi
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "Operand_Select_gti" *)
module system_bd_microblaze_ps_0_Operand_Select_gti
(ex_load_alu_carry_reg,
Q,
@@ -57894,6 +57920,7 @@ module system_bd_microblaze_ps_0_Operand_Select_gti
.O(in0));
endmodule
(* ORIG_REF_NAME = "PC_Module_gti" *)
module system_bd_microblaze_ps_0_PC_Module_gti
(D,
O56_out,
@@ -60194,6 +60221,7 @@ module system_bd_microblaze_ps_0_PC_Module_gti
.R(sync_reset));
endmodule
(* ORIG_REF_NAME = "PreFetch_Buffer_gti" *)
module system_bd_microblaze_ps_0_PreFetch_Buffer_gti
(\Using_FPGA.Native ,
\Using_FPGA.Native_0 ,
@@ -62878,6 +62906,7 @@ module system_bd_microblaze_ps_0_PreFetch_Buffer_gti
.Q(p_1_in164_in));
endmodule
(* ORIG_REF_NAME = "Register_File_gti" *)
module system_bd_microblaze_ps_0_Register_File_gti
(GPR_Op1,
GPR_Op2,
@@ -63134,6 +63163,7 @@ module system_bd_microblaze_ps_0_Register_File_gti
.of_imm_data(of_imm_data));
endmodule
(* ORIG_REF_NAME = "Shift_Logic_Module_gti" *)
module system_bd_microblaze_ps_0_Shift_Logic_Module_gti
(out,
\EX_Op1_reg[24] ,
@@ -63153,6 +63183,7 @@ module system_bd_microblaze_ps_0_Shift_Logic_Module_gti
assign sign_doublet = \Using_FPGA.Native ;
endmodule
(* ORIG_REF_NAME = "Zero_Detect_gti" *)
module system_bd_microblaze_ps_0_Zero_Detect_gti
(ex_op1_zero,
ex_op1_cmp_equal,
@@ -63303,6 +63334,7 @@ module system_bd_microblaze_ps_0_Zero_Detect_gti
.zero_CI_6(zero_CI_6));
endmodule
(* ORIG_REF_NAME = "address_hit" *)
module system_bd_microblaze_ps_0_address_hit
(Hit,
single_Step_N_reg,
@@ -63540,6 +63572,7 @@ module system_bd_microblaze_ps_0_address_hit
.single_Step_N_reg(single_Step_N_reg));
endmodule
(* ORIG_REF_NAME = "carry_and" *)
module system_bd_microblaze_ps_0_carry_and
(of_PipeRun_carry_1,
use_Reg_Neg_S_reg,
@@ -64216,6 +64249,7 @@ module system_bd_microblaze_ps_0_carry_and_89
.wb_valid_reg_0(wb_valid_reg_0));
endmodule
(* ORIG_REF_NAME = "carry_or" *)
module system_bd_microblaze_ps_0_carry_or
(mem_wait_on_ready_N,
MEM_DataBus_Ready,
@@ -64278,6 +64312,7 @@ module system_bd_microblaze_ps_0_carry_or
.mem_wait_on_ready_N(mem_wait_on_ready_N));
endmodule
(* ORIG_REF_NAME = "exception_registers_gti" *)
module system_bd_microblaze_ps_0_exception_registers_gti
(DI,
\Using_FPGA.Native ,
@@ -65375,6 +65410,7 @@ module system_bd_microblaze_ps_0_exception_registers_gti
.\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[9].I_RET_ADDR_WB_n_0 ));
endmodule
(* ORIG_REF_NAME = "instr_mux" *)
module system_bd_microblaze_ps_0_instr_mux
(I139_out,
Y,
@@ -65409,6 +65445,7 @@ module system_bd_microblaze_ps_0_instr_mux
.in(in));
endmodule
(* ORIG_REF_NAME = "jump_logic" *)
module system_bd_microblaze_ps_0_jump_logic
(ex_jump,
ex_op1_cmp_equal,
@@ -65882,6 +65919,7 @@ module system_bd_microblaze_ps_0_jump_logic
.R(reset_bool_for_rst));
endmodule
(* ORIG_REF_NAME = "mb_sync_bit" *)
module system_bd_microblaze_ps_0_mb_sync_bit
(out,
reset_temp,
@@ -66867,6 +66905,7 @@ module system_bd_microblaze_ps_0_mb_sync_bit__parameterized4_30
.R(sync_reset));
endmodule
(* ORIG_REF_NAME = "mb_sync_vec" *)
module system_bd_microblaze_ps_0_mb_sync_vec
(D,
dbg_hit,
@@ -67037,6 +67076,7 @@ module system_bd_microblaze_ps_0_mb_sync_vec__parameterized1
.sync_reset(sync_reset));
endmodule
(* ORIG_REF_NAME = "msr_reg_gti" *)
module system_bd_microblaze_ps_0_msr_reg_gti
(ex_MSR,
MEM_Fwd,
@@ -67174,6 +67214,7 @@ module system_bd_microblaze_ps_0_msr_reg_gti
.R(sync_reset));
endmodule
(* ORIG_REF_NAME = "mux_bus" *)
module system_bd_microblaze_ps_0_mux_bus
(I139_out,
Y,
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_sim_netlist.vhdl
+89 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:31 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_bd_microblaze_ps_0 -prefix
-- system_bd_microblaze_ps_0_ system_bd_microblaze_ps_0_sim_netlist.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:56:18 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_sim_netlist.vhdl
-- Design : system_bd_microblaze_ps_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -32,6 +32,8 @@ entity system_bd_microblaze_ps_0_Byte_Doublet_Handle_gti is
mem_byte_access : in STD_LOGIC;
mem_doublet_access : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_Byte_Doublet_Handle_gti : entity is "Byte_Doublet_Handle_gti";
end system_bd_microblaze_ps_0_Byte_Doublet_Handle_gti;
architecture STRUCTURE of system_bd_microblaze_ps_0_Byte_Doublet_Handle_gti is
@@ -471,6 +473,8 @@ entity system_bd_microblaze_ps_0_DAXI_interface is
M_AXI_DP_BVALID : in STD_LOGIC;
M_AXI_DP_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_DAXI_interface : entity is "DAXI_interface";
end system_bd_microblaze_ps_0_DAXI_interface;
architecture STRUCTURE of system_bd_microblaze_ps_0_DAXI_interface is
@@ -1602,6 +1606,8 @@ entity system_bd_microblaze_ps_0_MB_AND2B1L is
E : in STD_LOGIC_VECTOR ( 0 to 0 );
SRI : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_AND2B1L : entity is "MB_AND2B1L";
end system_bd_microblaze_ps_0_MB_AND2B1L;
architecture STRUCTURE of system_bd_microblaze_ps_0_MB_AND2B1L is
@@ -1629,6 +1635,8 @@ entity system_bd_microblaze_ps_0_MB_FDE is
\Using_FPGA.Native_2\ : in STD_LOGIC;
Clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_FDE : entity is "MB_FDE";
end system_bd_microblaze_ps_0_MB_FDE;
architecture STRUCTURE of system_bd_microblaze_ps_0_MB_FDE is
@@ -2689,6 +2697,8 @@ entity system_bd_microblaze_ps_0_MB_FDR is
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\Using_FPGA.Native_3\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_FDR : entity is "MB_FDR";
end system_bd_microblaze_ps_0_MB_FDR;
architecture STRUCTURE of system_bd_microblaze_ps_0_MB_FDR is
@@ -2775,6 +2785,8 @@ entity system_bd_microblaze_ps_0_MB_FDRE is
Clk : in STD_LOGIC;
mem_exception_from_ex : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_FDRE : entity is "MB_FDRE";
end system_bd_microblaze_ps_0_MB_FDRE;
architecture STRUCTURE of system_bd_microblaze_ps_0_MB_FDRE is
@@ -13137,6 +13149,8 @@ entity system_bd_microblaze_ps_0_MB_FDS is
\Using_FPGA.Native_16\ : in STD_LOGIC;
\Using_FPGA.Native_17\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_FDS : entity is "MB_FDS";
end system_bd_microblaze_ps_0_MB_FDS;
architecture STRUCTURE of system_bd_microblaze_ps_0_MB_FDS is
@@ -13646,6 +13660,8 @@ entity system_bd_microblaze_ps_0_MB_LUT4 is
I2 : in STD_LOGIC;
alu_AddSub_1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_LUT4 : entity is "MB_LUT4";
end system_bd_microblaze_ps_0_MB_LUT4;
architecture STRUCTURE of system_bd_microblaze_ps_0_MB_LUT4 is
@@ -13677,6 +13693,8 @@ entity system_bd_microblaze_ps_0_MB_LUT6 is
\Using_FPGA.Native_1\ : in STD_LOGIC;
I5 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_LUT6 : entity is "MB_LUT6";
end system_bd_microblaze_ps_0_MB_LUT6;
architecture STRUCTURE of system_bd_microblaze_ps_0_MB_LUT6 is
@@ -13817,6 +13835,8 @@ entity system_bd_microblaze_ps_0_MB_LUT6_2 is
EX_ALU_Sel_Logic : in STD_LOGIC;
EX_Enable_ALU : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_LUT6_2 : entity is "MB_LUT6_2";
end system_bd_microblaze_ps_0_MB_LUT6_2;
architecture STRUCTURE of system_bd_microblaze_ps_0_MB_LUT6_2 is
@@ -17332,6 +17352,8 @@ entity system_bd_microblaze_ps_0_MB_MULT_AND is
I0 : in STD_LOGIC;
\Using_FPGA.Native_I1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_MULT_AND : entity is "MB_MULT_AND";
end system_bd_microblaze_ps_0_MB_MULT_AND;
architecture STRUCTURE of system_bd_microblaze_ps_0_MB_MULT_AND is
@@ -17371,6 +17393,8 @@ entity system_bd_microblaze_ps_0_MB_MUXCY is
lopt_7 : in STD_LOGIC;
lopt_8 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_MUXCY : entity is "MB_MUXCY";
end system_bd_microblaze_ps_0_MB_MUXCY;
architecture STRUCTURE of system_bd_microblaze_ps_0_MB_MUXCY is
@@ -19960,6 +19984,8 @@ entity system_bd_microblaze_ps_0_MB_MUXCY_XORCY is
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
LO : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_MUXCY_XORCY : entity is "MB_MUXCY_XORCY";
end system_bd_microblaze_ps_0_MB_MUXCY_XORCY;
architecture STRUCTURE of system_bd_microblaze_ps_0_MB_MUXCY_XORCY is
@@ -24167,6 +24193,8 @@ entity system_bd_microblaze_ps_0_MB_MUXF7 is
wb_exception : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_MUXF7 : entity is "MB_MUXF7";
end system_bd_microblaze_ps_0_MB_MUXF7;
architecture STRUCTURE of system_bd_microblaze_ps_0_MB_MUXF7 is
@@ -27950,6 +27978,8 @@ entity system_bd_microblaze_ps_0_MB_RAM32M is
of_gpr_op3_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
\EX_Branch_CMP_Op1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_RAM32M : entity is "MB_RAM32M";
end system_bd_microblaze_ps_0_MB_RAM32M;
architecture STRUCTURE of system_bd_microblaze_ps_0_MB_RAM32M is
@@ -28917,6 +28947,8 @@ entity system_bd_microblaze_ps_0_MB_SRL16E is
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
Dbg_Clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_SRL16E : entity is "MB_SRL16E";
end system_bd_microblaze_ps_0_MB_SRL16E;
architecture STRUCTURE of system_bd_microblaze_ps_0_MB_SRL16E is
@@ -29559,6 +29591,8 @@ entity system_bd_microblaze_ps_0_MB_SRLC16E is
Dbg_Clk : in STD_LOGIC;
Dbg_Reg_En : in STD_LOGIC_VECTOR ( 0 to 7 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MB_SRLC16E : entity is "MB_SRLC16E";
end system_bd_microblaze_ps_0_MB_SRLC16E;
architecture STRUCTURE of system_bd_microblaze_ps_0_MB_SRLC16E is
@@ -29895,6 +29929,8 @@ entity system_bd_microblaze_ps_0_Shift_Logic_Module_gti is
in0 : in STD_LOGIC;
\Using_FPGA.Native\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_Shift_Logic_Module_gti : entity is "Shift_Logic_Module_gti";
end system_bd_microblaze_ps_0_Shift_Logic_Module_gti;
architecture STRUCTURE of system_bd_microblaze_ps_0_Shift_Logic_Module_gti is
@@ -29919,6 +29955,8 @@ entity system_bd_microblaze_ps_0_mb_sync_bit is
reset_temp : in STD_LOGIC;
Clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_mb_sync_bit : entity is "mb_sync_bit";
end system_bd_microblaze_ps_0_mb_sync_bit;
architecture STRUCTURE of system_bd_microblaze_ps_0_mb_sync_bit is
@@ -31065,6 +31103,8 @@ entity system_bd_microblaze_ps_0_ALU_Bit is
lopt_10 : out STD_LOGIC;
lopt_11 : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_ALU_Bit : entity is "ALU_Bit";
end system_bd_microblaze_ps_0_ALU_Bit;
architecture STRUCTURE of system_bd_microblaze_ps_0_ALU_Bit is
@@ -32856,6 +32896,8 @@ entity system_bd_microblaze_ps_0_Data_Flow_Logic is
\WB_MEM_Result_reg[0]_0\ : in STD_LOGIC;
\WB_MEM_Result_reg[0]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_Data_Flow_Logic : entity is "Data_Flow_Logic";
end system_bd_microblaze_ps_0_Data_Flow_Logic;
architecture STRUCTURE of system_bd_microblaze_ps_0_Data_Flow_Logic is
@@ -33490,6 +33532,8 @@ entity system_bd_microblaze_ps_0_Operand_Select_gti is
\EX_Op2_reg[0]_1\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\EX_Op3_reg[0]_1\ : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_Operand_Select_gti : entity is "Operand_Select_gti";
end system_bd_microblaze_ps_0_Operand_Select_gti;
architecture STRUCTURE of system_bd_microblaze_ps_0_Operand_Select_gti is
@@ -35415,6 +35459,8 @@ entity system_bd_microblaze_ps_0_PC_Module_gti is
lopt_2 : out STD_LOGIC;
lopt_3 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_PC_Module_gti : entity is "PC_Module_gti";
end system_bd_microblaze_ps_0_PC_Module_gti;
architecture STRUCTURE of system_bd_microblaze_ps_0_PC_Module_gti is
@@ -38318,6 +38364,8 @@ entity system_bd_microblaze_ps_0_PreFetch_Buffer_gti is
\EX_Op1_reg[0]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
ex_MSR : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_PreFetch_Buffer_gti : entity is "PreFetch_Buffer_gti";
end system_bd_microblaze_ps_0_PreFetch_Buffer_gti;
architecture STRUCTURE of system_bd_microblaze_ps_0_PreFetch_Buffer_gti is
@@ -40839,6 +40887,8 @@ entity system_bd_microblaze_ps_0_Register_File_gti is
\EX_Branch_CMP_Op1_reg[28]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\EX_Branch_CMP_Op1_reg[30]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_Register_File_gti : entity is "Register_File_gti";
end system_bd_microblaze_ps_0_Register_File_gti;
architecture STRUCTURE of system_bd_microblaze_ps_0_Register_File_gti is
@@ -41115,6 +41165,8 @@ entity system_bd_microblaze_ps_0_Zero_Detect_gti is
lopt_1 : in STD_LOGIC;
lopt_2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_Zero_Detect_gti : entity is "Zero_Detect_gti";
end system_bd_microblaze_ps_0_Zero_Detect_gti;
architecture STRUCTURE of system_bd_microblaze_ps_0_Zero_Detect_gti is
@@ -41300,6 +41352,8 @@ entity system_bd_microblaze_ps_0_address_hit is
Address : in STD_LOGIC_VECTOR ( 0 to 31 );
Dbg_Clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_address_hit : entity is "address_hit";
end system_bd_microblaze_ps_0_address_hit;
architecture STRUCTURE of system_bd_microblaze_ps_0_address_hit is
@@ -41547,6 +41601,8 @@ entity system_bd_microblaze_ps_0_carry_and is
lopt : in STD_LOGIC;
lopt_1 : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_carry_and : entity is "carry_and";
end system_bd_microblaze_ps_0_carry_and;
architecture STRUCTURE of system_bd_microblaze_ps_0_carry_and is
@@ -42095,6 +42151,8 @@ entity system_bd_microblaze_ps_0_carry_or is
lopt_7 : in STD_LOGIC;
lopt_8 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_carry_or : entity is "carry_or";
end system_bd_microblaze_ps_0_carry_or;
architecture STRUCTURE of system_bd_microblaze_ps_0_carry_or is
@@ -42178,6 +42236,8 @@ entity system_bd_microblaze_ps_0_exception_registers_gti is
\LOCKSTEP_Out_reg[3025]\ : in STD_LOGIC;
\LOCKSTEP_Out_reg[3023]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_exception_registers_gti : entity is "exception_registers_gti";
end system_bd_microblaze_ps_0_exception_registers_gti;
architecture STRUCTURE of system_bd_microblaze_ps_0_exception_registers_gti is
@@ -43466,6 +43526,8 @@ entity system_bd_microblaze_ps_0_jump_logic is
lopt_1 : out STD_LOGIC;
lopt_2 : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_jump_logic : entity is "jump_logic";
end system_bd_microblaze_ps_0_jump_logic;
architecture STRUCTURE of system_bd_microblaze_ps_0_jump_logic is
@@ -43732,6 +43794,8 @@ entity system_bd_microblaze_ps_0_mb_sync_vec is
Dbg_Clk : in STD_LOGIC;
\Single_Synchronize.use_async_reset.sync_reg\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_mb_sync_vec : entity is "mb_sync_vec";
end system_bd_microblaze_ps_0_mb_sync_vec;
architecture STRUCTURE of system_bd_microblaze_ps_0_mb_sync_vec is
@@ -43897,6 +43961,8 @@ entity system_bd_microblaze_ps_0_msr_reg_gti is
\Using_FPGA.Native_2\ : in STD_LOGIC;
wb_piperun : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_msr_reg_gti : entity is "msr_reg_gti";
end system_bd_microblaze_ps_0_msr_reg_gti;
architecture STRUCTURE of system_bd_microblaze_ps_0_msr_reg_gti is
@@ -44044,6 +44110,8 @@ entity system_bd_microblaze_ps_0_mux_bus is
Instr : in STD_LOGIC_VECTOR ( 0 to 31 );
LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 32 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_mux_bus : entity is "mux_bus";
end system_bd_microblaze_ps_0_mux_bus;
architecture STRUCTURE of system_bd_microblaze_ps_0_mux_bus is
@@ -44243,6 +44311,8 @@ entity system_bd_microblaze_ps_0_ALU is
lopt_3 : out STD_LOGIC;
lopt_4 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_ALU : entity is "ALU";
end system_bd_microblaze_ps_0_ALU;
architecture STRUCTURE of system_bd_microblaze_ps_0_ALU is
@@ -45008,6 +45078,8 @@ entity system_bd_microblaze_ps_0_Debug is
\Serial_Dbg_Intf.status_reg_reg[22]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
dbg_stop_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_Debug : entity is "Debug";
end system_bd_microblaze_ps_0_Debug;
architecture STRUCTURE of system_bd_microblaze_ps_0_Debug is
@@ -49197,6 +49269,8 @@ entity system_bd_microblaze_ps_0_Decode_gti is
lopt_1 : out STD_LOGIC;
lopt_2 : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_Decode_gti : entity is "Decode_gti";
end system_bd_microblaze_ps_0_Decode_gti;
architecture STRUCTURE of system_bd_microblaze_ps_0_Decode_gti is
@@ -54781,6 +54855,8 @@ entity system_bd_microblaze_ps_0_instr_mux is
Instr : in STD_LOGIC_VECTOR ( 0 to 31 );
LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 32 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_instr_mux : entity is "instr_mux";
end system_bd_microblaze_ps_0_instr_mux;
architecture STRUCTURE of system_bd_microblaze_ps_0_instr_mux is
@@ -54982,6 +55058,8 @@ entity system_bd_microblaze_ps_0_Data_Flow_gti is
lopt_1 : in STD_LOGIC;
lopt_2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_Data_Flow_gti : entity is "Data_Flow_gti";
end system_bd_microblaze_ps_0_Data_Flow_gti;
architecture STRUCTURE of system_bd_microblaze_ps_0_Data_Flow_gti is
@@ -55565,6 +55643,8 @@ entity system_bd_microblaze_ps_0_MicroBlaze_GTi is
Dbg_TDI : in STD_LOGIC;
Data_Read : in STD_LOGIC_VECTOR ( 0 to 31 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MicroBlaze_GTi : entity is "MicroBlaze_GTi";
end system_bd_microblaze_ps_0_MicroBlaze_GTi;
architecture STRUCTURE of system_bd_microblaze_ps_0_MicroBlaze_GTi is
@@ -57969,6 +58049,8 @@ entity system_bd_microblaze_ps_0_MicroBlaze_Core is
Data_Read : in STD_LOGIC_VECTOR ( 0 to 31 );
Wakeup : in STD_LOGIC_VECTOR ( 0 to 1 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MicroBlaze_Core : entity is "MicroBlaze_Core";
end system_bd_microblaze_ps_0_MicroBlaze_Core;
architecture STRUCTURE of system_bd_microblaze_ps_0_MicroBlaze_Core is
@@ -58846,6 +58928,8 @@ entity system_bd_microblaze_ps_0_MicroBlaze is
attribute C_USE_REORDER_INSTR of system_bd_microblaze_ps_0_MicroBlaze : entity is 1;
attribute C_USE_STACK_PROTECTION : integer;
attribute C_USE_STACK_PROTECTION of system_bd_microblaze_ps_0_MicroBlaze : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_microblaze_ps_0_MicroBlaze : entity is "MicroBlaze";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_bd_microblaze_ps_0_MicroBlaze : entity is "yes";
end system_bd_microblaze_ps_0_MicroBlaze;
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_stub.v
+5 -5
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:31 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_bd_microblaze_ps_0 -prefix
// system_bd_microblaze_ps_0_ system_bd_microblaze_ps_0_stub.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:56:17 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_stub.v
// Design : system_bd_microblaze_ps_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_stub.vhdl
+5 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:31 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_microblaze_ps_0 -prefix
-- system_bd_microblaze_ps_0_ system_bd_microblaze_ps_0_stub.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:56:17 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_microblaze_ps_0/system_bd_microblaze_ps_0_stub.vhdl
-- Design : system_bd_microblaze_ps_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0.dcp
BIN
View File
Binary file not shown.
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0.xml
+19 -19
View File
@@ -385,7 +385,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:55 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -403,7 +403,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:55 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -423,7 +423,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:55 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -446,7 +446,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:55 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -466,7 +466,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:55 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -484,7 +484,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:55 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -502,7 +502,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:56:15 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -834,6 +834,18 @@
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_rst_clk_wiz_25M_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_rst_clk_wiz_25M_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_rst_clk_wiz_25M_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
@@ -848,18 +860,6 @@
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_rst_clk_wiz_25M_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_rst_clk_wiz_25M_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>Processor Reset System</spirit:description>
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_sim_netlist.v
+67 -62
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:09 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_bd_rst_clk_wiz_25M_0 -prefix
// system_bd_rst_clk_wiz_25M_0_ system_bd_rst_clk_wiz_25M_0_sim_netlist.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:56:15 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode funcsim
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_sim_netlist.v
// Design : system_bd_rst_clk_wiz_25M_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -12,6 +12,64 @@
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_bd_rst_clk_wiz_25M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2019.1.3" *)
(* NotValidForBitStream *)
module system_bd_rst_clk_wiz_25M_0
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input slowest_sync_clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input ext_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aux_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input mb_debug_sys_rst;
input dcm_locked;
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0" *) output mb_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]bus_struct_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]interconnect_aresetn;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_aresetn;
wire aux_reset_in;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire slowest_sync_clk;
(* C_AUX_RESET_HIGH = "1'b0" *)
(* C_AUX_RST_WIDTH = "4" *)
(* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *)
(* C_FAMILY = "kintex7" *)
(* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
(* C_NUM_PERP_ARESETN = "1" *)
(* C_NUM_PERP_RST = "1" *)
system_bd_rst_clk_wiz_25M_0_proc_sys_reset U0
(.aux_reset_in(aux_reset_in),
.bus_struct_reset(bus_struct_reset),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.interconnect_aresetn(interconnect_aresetn),
.mb_debug_sys_rst(mb_debug_sys_rst),
.mb_reset(mb_reset),
.peripheral_aresetn(peripheral_aresetn),
.peripheral_reset(peripheral_reset),
.slowest_sync_clk(slowest_sync_clk));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module system_bd_rst_clk_wiz_25M_0_cdc_sync
(lpf_asr_reg,
scndry_out,
@@ -193,6 +251,7 @@ module system_bd_rst_clk_wiz_25M_0_cdc_sync_0
.O(lpf_exr_reg));
endmodule
(* ORIG_REF_NAME = "lpf" *)
module system_bd_rst_clk_wiz_25M_0_lpf
(lpf_int,
slowest_sync_clk,
@@ -341,6 +400,7 @@ endmodule
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "kintex7" *) (* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *)
(* ORIG_REF_NAME = "proc_sys_reset" *)
module system_bd_rst_clk_wiz_25M_0_proc_sys_reset
(slowest_sync_clk,
ext_reset_in,
@@ -457,6 +517,7 @@ module system_bd_rst_clk_wiz_25M_0_proc_sys_reset
.slowest_sync_clk(slowest_sync_clk));
endmodule
(* ORIG_REF_NAME = "sequence_psr" *)
module system_bd_rst_clk_wiz_25M_0_sequence_psr
(MB_out,
Bsr_out,
@@ -697,63 +758,7 @@ module system_bd_rst_clk_wiz_25M_0_sequence_psr
.R(lpf_int));
endmodule
(* CHECK_LICENSE_TYPE = "system_bd_rst_clk_wiz_25M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2019.1.3" *)
(* NotValidForBitStream *)
module system_bd_rst_clk_wiz_25M_0
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input slowest_sync_clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input ext_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aux_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input mb_debug_sys_rst;
input dcm_locked;
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0" *) output mb_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]bus_struct_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]interconnect_aresetn;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_aresetn;
wire aux_reset_in;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire slowest_sync_clk;
(* C_AUX_RESET_HIGH = "1'b0" *)
(* C_AUX_RST_WIDTH = "4" *)
(* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *)
(* C_FAMILY = "kintex7" *)
(* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
(* C_NUM_PERP_ARESETN = "1" *)
(* C_NUM_PERP_RST = "1" *)
system_bd_rst_clk_wiz_25M_0_proc_sys_reset U0
(.aux_reset_in(aux_reset_in),
.bus_struct_reset(bus_struct_reset),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.interconnect_aresetn(interconnect_aresetn),
.mb_debug_sys_rst(mb_debug_sys_rst),
.mb_reset(mb_reset),
.peripheral_aresetn(peripheral_aresetn),
.peripheral_reset(peripheral_reset),
.slowest_sync_clk(slowest_sync_clk));
endmodule
(* ORIG_REF_NAME = "upcnt_n" *)
module system_bd_rst_clk_wiz_25M_0_upcnt_n
(Q,
seq_clr,
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_sim_netlist.vhdl
+15 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:09 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_bd_rst_clk_wiz_25M_0 -prefix
-- system_bd_rst_clk_wiz_25M_0_ system_bd_rst_clk_wiz_25M_0_sim_netlist.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:56:15 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_sim_netlist.vhdl
-- Design : system_bd_rst_clk_wiz_25M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -25,6 +25,8 @@ entity system_bd_rst_clk_wiz_25M_0_cdc_sync is
aux_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_rst_clk_wiz_25M_0_cdc_sync : entity is "cdc_sync";
end system_bd_rst_clk_wiz_25M_0_cdc_sync;
architecture STRUCTURE of system_bd_rst_clk_wiz_25M_0_cdc_sync is
@@ -233,6 +235,8 @@ entity system_bd_rst_clk_wiz_25M_0_upcnt_n is
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_rst_clk_wiz_25M_0_upcnt_n : entity is "upcnt_n";
end system_bd_rst_clk_wiz_25M_0_upcnt_n;
architecture STRUCTURE of system_bd_rst_clk_wiz_25M_0_upcnt_n is
@@ -397,6 +401,8 @@ entity system_bd_rst_clk_wiz_25M_0_lpf is
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_rst_clk_wiz_25M_0_lpf : entity is "lpf";
end system_bd_rst_clk_wiz_25M_0_lpf;
architecture STRUCTURE of system_bd_rst_clk_wiz_25M_0_lpf is
@@ -578,6 +584,8 @@ entity system_bd_rst_clk_wiz_25M_0_sequence_psr is
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_rst_clk_wiz_25M_0_sequence_psr : entity is "sequence_psr";
end system_bd_rst_clk_wiz_25M_0_sequence_psr;
architecture STRUCTURE of system_bd_rst_clk_wiz_25M_0_sequence_psr is
@@ -916,6 +924,8 @@ entity system_bd_rst_clk_wiz_25M_0_proc_sys_reset is
attribute C_NUM_PERP_ARESETN of system_bd_rst_clk_wiz_25M_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of system_bd_rst_clk_wiz_25M_0_proc_sys_reset : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_rst_clk_wiz_25M_0_proc_sys_reset : entity is "proc_sys_reset";
end system_bd_rst_clk_wiz_25M_0_proc_sys_reset;
architecture STRUCTURE of system_bd_rst_clk_wiz_25M_0_proc_sys_reset is
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_stub.v
+5 -5
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:09 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_bd_rst_clk_wiz_25M_0 -prefix
// system_bd_rst_clk_wiz_25M_0_ system_bd_rst_clk_wiz_25M_0_stub.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:56:15 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_stub.v
// Design : system_bd_rst_clk_wiz_25M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_stub.vhdl
+5 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:09 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_rst_clk_wiz_25M_0 -prefix
-- system_bd_rst_clk_wiz_25M_0_ system_bd_rst_clk_wiz_25M_0_stub.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:56:15 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_rst_clk_wiz_25M_0/system_bd_rst_clk_wiz_25M_0_stub.vhdl
-- Design : system_bd_rst_clk_wiz_25M_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0.dcp
BIN
View File
Binary file not shown.
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0.xml
+17 -17
View File
@@ -369,7 +369,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:51 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -400,7 +400,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:51 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -419,7 +419,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:51 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -439,7 +439,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:51 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -457,7 +457,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:53 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:55:52 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -869,6 +869,18 @@
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_spi_engine_execution_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_spi_engine_execution_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_spi_engine_execution_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
@@ -883,18 +895,6 @@
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_spi_engine_execution_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_spi_engine_execution_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>spi_engine_execution_v1_0</spirit:description>
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_sim_netlist.v
+99 -98
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:10 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_bd_spi_engine_execution_0 -prefix
// system_bd_spi_engine_execution_0_ system_bd_spi_engine_execution_0_sim_netlist.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:55:52 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode funcsim
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_sim_netlist.v
// Design : system_bd_spi_engine_execution_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -12,6 +12,100 @@
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_bd_spi_engine_execution_0,spi_engine_execution,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* IP_DEFINITION_SOURCE = "package_project" *)
(* X_CORE_INFO = "spi_engine_execution,Vivado 2019.1.3" *)
(* NotValidForBitStream *)
module system_bd_spi_engine_execution_0
(clk,
resetn,
active,
cmd_ready,
cmd_valid,
cmd,
sdo_data_valid,
sdo_data_ready,
sdo_data,
sdi_data_ready,
sdi_data_valid,
sdi_data,
sync_ready,
sync_valid,
sync,
sclk,
sdo,
sdo_t,
sdi,
cs,
three_wire);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ctrl_signal_clock CLK, xilinx.com:signal:clock:1.0 spi_signal_clock CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ctrl_signal_clock, ASSOCIATED_BUSIF ctrl, ASSOCIATED_RESET resetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_signal_clock, ASSOCIATED_BUSIF spi, ASSOCIATED_RESET resetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ctrl_signal_reset RST, xilinx.com:signal:reset:1.0 spi_signal_reset RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input resetn;
output active;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_READY" *) output cmd_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_VALID" *) input cmd_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_DATA" *) input [15:0]cmd;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_VALID" *) input sdo_data_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_READY" *) output sdo_data_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_DATA" *) input [7:0]sdo_data;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_READY" *) input sdi_data_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_VALID" *) output sdi_data_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_DATA" *) output [7:0]sdi_data;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_READY" *) input sync_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_VALID" *) output sync_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_DATA" *) output [7:0]sync;
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SCLK" *) output sclk;
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDO" *) output sdo;
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDO_T" *) output sdo_t;
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDI" *) input [0:0]sdi;
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi CS" *) output [2:0]cs;
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi THREE_WIRE" *) output three_wire;
wire active;
wire clk;
wire [15:0]cmd;
wire cmd_ready;
wire cmd_valid;
wire [2:0]cs;
wire resetn;
wire sclk;
wire [0:0]sdi;
wire [7:0]sdi_data;
wire sdi_data_ready;
wire sdi_data_valid;
wire sdo;
wire [7:0]sdo_data;
wire sdo_data_ready;
wire sdo_data_valid;
wire sdo_t;
wire [7:0]sync;
wire sync_ready;
wire sync_valid;
wire three_wire;
system_bd_spi_engine_execution_0_spi_engine_execution inst
(.active(active),
.clk(clk),
.cmd({cmd[13:12],cmd[9:0]}),
.cmd_valid(cmd_valid),
.cs(cs),
.idle_reg_0(cmd_ready),
.resetn(resetn),
.sclk(sclk),
.sdi(sdi),
.sdi_data(sdi_data),
.sdi_data_ready(sdi_data_ready),
.sdi_data_valid(sdi_data_valid),
.sdo(sdo),
.sdo_data(sdo_data),
.sdo_data_ready(sdo_data_ready),
.sdo_data_valid(sdo_data_valid),
.sdo_t(sdo_t),
.sync(sync),
.sync_ready(sync_ready),
.sync_valid(sync_valid),
.three_wire(three_wire));
endmodule
(* ORIG_REF_NAME = "spi_engine_execution" *)
module system_bd_spi_engine_execution_0_spi_engine_execution
(idle_reg_0,
sync,
@@ -2351,99 +2445,6 @@ module system_bd_spi_engine_execution_0_spi_engine_execution
.Q(word_length[7]),
.R(active_i_1_n_0));
endmodule
(* CHECK_LICENSE_TYPE = "system_bd_spi_engine_execution_0,spi_engine_execution,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* IP_DEFINITION_SOURCE = "package_project" *)
(* X_CORE_INFO = "spi_engine_execution,Vivado 2019.1.3" *)
(* NotValidForBitStream *)
module system_bd_spi_engine_execution_0
(clk,
resetn,
active,
cmd_ready,
cmd_valid,
cmd,
sdo_data_valid,
sdo_data_ready,
sdo_data,
sdi_data_ready,
sdi_data_valid,
sdi_data,
sync_ready,
sync_valid,
sync,
sclk,
sdo,
sdo_t,
sdi,
cs,
three_wire);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ctrl_signal_clock CLK, xilinx.com:signal:clock:1.0 spi_signal_clock CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ctrl_signal_clock, ASSOCIATED_BUSIF ctrl, ASSOCIATED_RESET resetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_signal_clock, ASSOCIATED_BUSIF spi, ASSOCIATED_RESET resetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *) input clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ctrl_signal_reset RST, xilinx.com:signal:reset:1.0 spi_signal_reset RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input resetn;
output active;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_READY" *) output cmd_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_VALID" *) input cmd_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_DATA" *) input [15:0]cmd;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_VALID" *) input sdo_data_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_READY" *) output sdo_data_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_DATA" *) input [7:0]sdo_data;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_READY" *) input sdi_data_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_VALID" *) output sdi_data_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_DATA" *) output [7:0]sdi_data;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_READY" *) input sync_ready;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_VALID" *) output sync_valid;
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_DATA" *) output [7:0]sync;
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SCLK" *) output sclk;
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDO" *) output sdo;
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDO_T" *) output sdo_t;
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDI" *) input [0:0]sdi;
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi CS" *) output [2:0]cs;
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi THREE_WIRE" *) output three_wire;
wire active;
wire clk;
wire [15:0]cmd;
wire cmd_ready;
wire cmd_valid;
wire [2:0]cs;
wire resetn;
wire sclk;
wire [0:0]sdi;
wire [7:0]sdi_data;
wire sdi_data_ready;
wire sdi_data_valid;
wire sdo;
wire [7:0]sdo_data;
wire sdo_data_ready;
wire sdo_data_valid;
wire sdo_t;
wire [7:0]sync;
wire sync_ready;
wire sync_valid;
wire three_wire;
system_bd_spi_engine_execution_0_spi_engine_execution inst
(.active(active),
.clk(clk),
.cmd({cmd[13:12],cmd[9:0]}),
.cmd_valid(cmd_valid),
.cs(cs),
.idle_reg_0(cmd_ready),
.resetn(resetn),
.sclk(sclk),
.sdi(sdi),
.sdi_data(sdi_data),
.sdi_data_ready(sdi_data_ready),
.sdi_data_valid(sdi_data_valid),
.sdo(sdo),
.sdo_data(sdo_data),
.sdo_data_ready(sdo_data_ready),
.sdo_data_valid(sdo_data_valid),
.sdo_t(sdo_t),
.sync(sync),
.sync_ready(sync_ready),
.sync_valid(sync_valid),
.three_wire(three_wire));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_sim_netlist.vhdl
+7 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:10 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_bd_spi_engine_execution_0 -prefix
-- system_bd_spi_engine_execution_0_ system_bd_spi_engine_execution_0_sim_netlist.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:55:52 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_sim_netlist.vhdl
-- Design : system_bd_spi_engine_execution_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -38,6 +38,8 @@ entity system_bd_spi_engine_execution_0_spi_engine_execution is
sdi_data_ready : in STD_LOGIC;
sdo_data : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_spi_engine_execution_0_spi_engine_execution : entity is "spi_engine_execution";
end system_bd_spi_engine_execution_0_spi_engine_execution;
architecture STRUCTURE of system_bd_spi_engine_execution_0_spi_engine_execution is
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_stub.v
+5 -5
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:10 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_bd_spi_engine_execution_0 -prefix
// system_bd_spi_engine_execution_0_ system_bd_spi_engine_execution_0_stub.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:55:52 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_stub.v
// Design : system_bd_spi_engine_execution_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_stub.vhdl
+5 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:10 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_spi_engine_execution_0 -prefix
-- system_bd_spi_engine_execution_0_ system_bd_spi_engine_execution_0_stub.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:55:52 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_stub.vhdl
-- Design : system_bd_spi_engine_execution_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.dcp
BIN
View File
Binary file not shown.
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.xml
+18 -18
View File
@@ -26554,7 +26554,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:51 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -26572,7 +26572,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:51 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -26592,7 +26592,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:51 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -26627,7 +26627,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:51 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -26647,7 +26647,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:52 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:51:51 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -26665,7 +26665,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Mar 18 16:32:54 UTC 2023</spirit:value>
<spirit:value>Wed Mar 22 14:56:06 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -29180,6 +29180,18 @@
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_xbar_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_xbar_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_xbar_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
@@ -29194,18 +29206,6 @@
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_xbar_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>system_bd_xbar_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>The AXI Crossbar IP provides the infrastructure to connect multiple AXI4/AXI3/AXI4-Lite masters and slaves.</spirit:description>
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_sim_netlist.v
+310 -305
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:17 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_bd_xbar_0 -prefix
// system_bd_xbar_0_ system_bd_xbar_0_sim_netlist.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:56:06 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode funcsim
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_sim_netlist.v
// Design : system_bd_xbar_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -12,6 +12,300 @@
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_bd_xbar_0,axi_crossbar_v2_1_20_axi_crossbar,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_crossbar_v2_1_20_axi_crossbar,Vivado 2019.1.3" *)
(* NotValidForBitStream *)
module system_bd_xbar_0
(aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input [0:0]s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output [0:0]s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input [0:0]s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output [0:0]s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output [0:0]s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input [0:0]s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input [0:0]s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output [0:0]s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output [0:0]s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [0:0]s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]" *) output [95:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]" *) output [8:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]" *) output [2:0]m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]" *) input [2:0]m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]" *) output [95:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]" *) output [11:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]" *) output [2:0]m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]" *) input [2:0]m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]" *) input [5:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]" *) input [2:0]m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]" *) output [2:0]m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]" *) output [95:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]" *) output [8:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]" *) output [2:0]m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]" *) input [2:0]m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]" *) input [95:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]" *) input [5:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]" *) input [2:0]m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output [2:0]m_axi_rready;
wire aclk;
wire aresetn;
wire [95:0]m_axi_araddr;
wire [8:0]m_axi_arprot;
wire [2:0]m_axi_arready;
wire [2:0]m_axi_arvalid;
wire [95:0]m_axi_awaddr;
wire [8:0]m_axi_awprot;
wire [2:0]m_axi_awready;
wire [2:0]m_axi_awvalid;
wire [2:0]m_axi_bready;
wire [5:0]m_axi_bresp;
wire [2:0]m_axi_bvalid;
wire [95:0]m_axi_rdata;
wire [2:0]m_axi_rready;
wire [5:0]m_axi_rresp;
wire [2:0]m_axi_rvalid;
wire [95:0]m_axi_wdata;
wire [2:0]m_axi_wready;
wire [11:0]m_axi_wstrb;
wire [2:0]m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [2:0]s_axi_arprot;
wire [0:0]s_axi_arready;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [0:0]s_axi_wready;
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wvalid;
wire [5:0]NLW_inst_m_axi_arburst_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_arcache_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_arid_UNCONNECTED;
wire [23:0]NLW_inst_m_axi_arlen_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_arlock_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_arqos_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_arregion_UNCONNECTED;
wire [8:0]NLW_inst_m_axi_arsize_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [5:0]NLW_inst_m_axi_awburst_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awcache_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awid_UNCONNECTED;
wire [23:0]NLW_inst_m_axi_awlen_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awlock_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awqos_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awregion_UNCONNECTED;
wire [8:0]NLW_inst_m_axi_awsize_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_wlast_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_bid_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_rid_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_rlast_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_PROTOCOL = "2" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_CONNECTIVITY_MODE = "0" *)
(* C_DEBUG = "1" *)
(* C_FAMILY = "kintex7" *)
(* C_M_AXI_ADDR_WIDTH = "96'b000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000" *)
(* C_M_AXI_BASE_ADDR = "192'b000000000000000000000000000000000100000000000000000000000000000011111111111111111111111111111111111111111111111111111111111111110000000000000000000000000000000001000100101000000000000000000000" *)
(* C_M_AXI_READ_CONNECTIVITY = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_READ_ISSUING = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_SECURE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_M_AXI_WRITE_CONNECTIVITY = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_WRITE_ISSUING = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_NUM_ADDR_RANGES = "1" *)
(* C_NUM_MASTER_SLOTS = "3" *)
(* C_NUM_SLAVE_SLOTS = "1" *)
(* C_R_REGISTER = "1" *)
(* C_S_AXI_ARB_PRIORITY = "0" *)
(* C_S_AXI_BASE_ID = "0" *)
(* C_S_AXI_READ_ACCEPTANCE = "1" *)
(* C_S_AXI_SINGLE_THREAD = "1" *)
(* C_S_AXI_THREAD_ID_WIDTH = "0" *)
(* C_S_AXI_WRITE_ACCEPTANCE = "1" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_ADDR_DECODE = "1" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_FAMILY = "kintex7" *)
(* P_INCR = "2'b01" *)
(* P_LEN = "8" *)
(* P_LOCK = "1" *)
(* P_M_AXI_ERR_MODE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* P_M_AXI_SUPPORTS_READ = "3'b111" *)
(* P_M_AXI_SUPPORTS_WRITE = "3'b111" *)
(* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *)
(* P_RANGE_CHECK = "1" *)
(* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_S_AXI_SUPPORTS_READ = "1'b1" *)
(* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
system_bd_xbar_0_axi_crossbar_v2_1_20_axi_crossbar inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[5:0]),
.m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[11:0]),
.m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[2:0]),
.m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[23:0]),
.m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[2:0]),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[11:0]),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[11:0]),
.m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[8:0]),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[2:0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[5:0]),
.m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[11:0]),
.m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[2:0]),
.m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[23:0]),
.m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[2:0]),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[11:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[11:0]),
.m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[8:0]),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[2:0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid({1'b0,1'b0,1'b0}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser({1'b0,1'b0,1'b0}),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid({1'b0,1'b0,1'b0}),
.m_axi_rlast({1'b1,1'b1,1'b1}),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser({1'b0,1'b0,1'b0}),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[2:0]),
.m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED[2:0]),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[2:0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(s_axi_arready),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(s_axi_awready),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_inst_s_axi_rlast_UNCONNECTED[0]),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b1),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_20_addr_arbiter_sasd" *)
module system_bd_xbar_0_axi_crossbar_v2_1_20_addr_arbiter_sasd
(aa_grant_any,
m_valid_i,
@@ -1081,13 +1375,13 @@ endmodule
(* C_NUM_MASTER_SLOTS = "3" *) (* C_NUM_SLAVE_SLOTS = "1" *) (* C_R_REGISTER = "1" *)
(* C_S_AXI_ARB_PRIORITY = "0" *) (* C_S_AXI_BASE_ID = "0" *) (* C_S_AXI_READ_ACCEPTANCE = "1" *)
(* C_S_AXI_SINGLE_THREAD = "1" *) (* C_S_AXI_THREAD_ID_WIDTH = "0" *) (* C_S_AXI_WRITE_ACCEPTANCE = "1" *)
(* DowngradeIPIdentifiedWarnings = "yes" *) (* P_ADDR_DECODE = "1" *) (* P_AXI3 = "1" *)
(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b010" *)
(* P_FAMILY = "kintex7" *) (* P_INCR = "2'b01" *) (* P_LEN = "8" *)
(* P_LOCK = "1" *) (* P_M_AXI_ERR_MODE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* P_M_AXI_SUPPORTS_READ = "3'b111" *)
(* P_M_AXI_SUPPORTS_WRITE = "3'b111" *) (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *) (* P_RANGE_CHECK = "1" *)
(* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_SUPPORTS_READ = "1'b1" *)
(* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
(* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "axi_crossbar_v2_1_20_axi_crossbar" *) (* P_ADDR_DECODE = "1" *)
(* P_AXI3 = "1" *) (* P_AXI4 = "0" *) (* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *) (* P_FAMILY = "kintex7" *) (* P_INCR = "2'b01" *)
(* P_LEN = "8" *) (* P_LOCK = "1" *) (* P_M_AXI_ERR_MODE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* P_M_AXI_SUPPORTS_READ = "3'b111" *) (* P_M_AXI_SUPPORTS_WRITE = "3'b111" *) (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *)
(* P_RANGE_CHECK = "1" *) (* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_S_AXI_SUPPORTS_READ = "1'b1" *) (* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
module system_bd_xbar_0_axi_crossbar_v2_1_20_axi_crossbar
(aclk,
aresetn,
@@ -1567,6 +1861,7 @@ module system_bd_xbar_0_axi_crossbar_v2_1_20_axi_crossbar
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_20_crossbar_sasd" *)
module system_bd_xbar_0_axi_crossbar_v2_1_20_crossbar_sasd
(Q,
\m_payload_i_reg[34] ,
@@ -1886,6 +2181,7 @@ module system_bd_xbar_0_axi_crossbar_v2_1_20_crossbar_sasd
.s_axi_wvalid_0_sp_1(splitter_aw_n_0));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_20_decerr_slave" *)
module system_bd_xbar_0_axi_crossbar_v2_1_20_decerr_slave
(\m_ready_d_reg[2] ,
m_axi_awready_2_sp_1,
@@ -2105,6 +2401,7 @@ module system_bd_xbar_0_axi_crossbar_v2_1_20_decerr_slave
.O(m_axi_wready_1_sn_1));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_20_splitter" *)
module system_bd_xbar_0_axi_crossbar_v2_1_20_splitter
(s_axi_wvalid_0_sp_1,
m_ready_d,
@@ -2272,6 +2569,7 @@ module system_bd_xbar_0_axi_crossbar_v2_1_20_splitter__parameterized0
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_19_axic_register_slice" *)
module system_bd_xbar_0_axi_register_slice_v2_1_19_axic_register_slice
(sr_rvalid,
aa_rready,
@@ -3495,299 +3793,6 @@ module system_bd_xbar_0_axi_register_slice_v2_1_19_axic_register_slice
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "system_bd_xbar_0,axi_crossbar_v2_1_20_axi_crossbar,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_crossbar_v2_1_20_axi_crossbar,Vivado 2019.1.3" *)
(* NotValidForBitStream *)
module system_bd_xbar_0
(aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input [0:0]s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output [0:0]s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input [0:0]s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output [0:0]s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output [0:0]s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input [0:0]s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input [0:0]s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output [0:0]s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output [0:0]s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [0:0]s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]" *) output [95:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]" *) output [8:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]" *) output [2:0]m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]" *) input [2:0]m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]" *) output [95:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]" *) output [11:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]" *) output [2:0]m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]" *) input [2:0]m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]" *) input [5:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]" *) input [2:0]m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]" *) output [2:0]m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]" *) output [95:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]" *) output [8:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]" *) output [2:0]m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]" *) input [2:0]m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]" *) input [95:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]" *) input [5:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]" *) input [2:0]m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output [2:0]m_axi_rready;
wire aclk;
wire aresetn;
wire [95:0]m_axi_araddr;
wire [8:0]m_axi_arprot;
wire [2:0]m_axi_arready;
wire [2:0]m_axi_arvalid;
wire [95:0]m_axi_awaddr;
wire [8:0]m_axi_awprot;
wire [2:0]m_axi_awready;
wire [2:0]m_axi_awvalid;
wire [2:0]m_axi_bready;
wire [5:0]m_axi_bresp;
wire [2:0]m_axi_bvalid;
wire [95:0]m_axi_rdata;
wire [2:0]m_axi_rready;
wire [5:0]m_axi_rresp;
wire [2:0]m_axi_rvalid;
wire [95:0]m_axi_wdata;
wire [2:0]m_axi_wready;
wire [11:0]m_axi_wstrb;
wire [2:0]m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [2:0]s_axi_arprot;
wire [0:0]s_axi_arready;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [0:0]s_axi_wready;
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wvalid;
wire [5:0]NLW_inst_m_axi_arburst_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_arcache_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_arid_UNCONNECTED;
wire [23:0]NLW_inst_m_axi_arlen_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_arlock_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_arqos_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_arregion_UNCONNECTED;
wire [8:0]NLW_inst_m_axi_arsize_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [5:0]NLW_inst_m_axi_awburst_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awcache_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awid_UNCONNECTED;
wire [23:0]NLW_inst_m_axi_awlen_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awlock_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awqos_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awregion_UNCONNECTED;
wire [8:0]NLW_inst_m_axi_awsize_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_wlast_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_bid_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_rid_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_rlast_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_PROTOCOL = "2" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_CONNECTIVITY_MODE = "0" *)
(* C_DEBUG = "1" *)
(* C_FAMILY = "kintex7" *)
(* C_M_AXI_ADDR_WIDTH = "96'b000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000" *)
(* C_M_AXI_BASE_ADDR = "192'b000000000000000000000000000000000100000000000000000000000000000011111111111111111111111111111111111111111111111111111111111111110000000000000000000000000000000001000100101000000000000000000000" *)
(* C_M_AXI_READ_CONNECTIVITY = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_READ_ISSUING = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_SECURE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_M_AXI_WRITE_CONNECTIVITY = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_WRITE_ISSUING = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_NUM_ADDR_RANGES = "1" *)
(* C_NUM_MASTER_SLOTS = "3" *)
(* C_NUM_SLAVE_SLOTS = "1" *)
(* C_R_REGISTER = "1" *)
(* C_S_AXI_ARB_PRIORITY = "0" *)
(* C_S_AXI_BASE_ID = "0" *)
(* C_S_AXI_READ_ACCEPTANCE = "1" *)
(* C_S_AXI_SINGLE_THREAD = "1" *)
(* C_S_AXI_THREAD_ID_WIDTH = "0" *)
(* C_S_AXI_WRITE_ACCEPTANCE = "1" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_ADDR_DECODE = "1" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_FAMILY = "kintex7" *)
(* P_INCR = "2'b01" *)
(* P_LEN = "8" *)
(* P_LOCK = "1" *)
(* P_M_AXI_ERR_MODE = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* P_M_AXI_SUPPORTS_READ = "3'b111" *)
(* P_M_AXI_SUPPORTS_WRITE = "3'b111" *)
(* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *)
(* P_RANGE_CHECK = "1" *)
(* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_S_AXI_SUPPORTS_READ = "1'b1" *)
(* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
system_bd_xbar_0_axi_crossbar_v2_1_20_axi_crossbar inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[5:0]),
.m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[11:0]),
.m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[2:0]),
.m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[23:0]),
.m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[2:0]),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[11:0]),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[11:0]),
.m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[8:0]),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[2:0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[5:0]),
.m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[11:0]),
.m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[2:0]),
.m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[23:0]),
.m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[2:0]),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[11:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[11:0]),
.m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[8:0]),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[2:0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid({1'b0,1'b0,1'b0}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser({1'b0,1'b0,1'b0}),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid({1'b0,1'b0,1'b0}),
.m_axi_rlast({1'b1,1'b1,1'b1}),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser({1'b0,1'b0,1'b0}),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[2:0]),
.m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED[2:0]),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[2:0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(s_axi_arready),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(s_axi_awready),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_inst_s_axi_rlast_UNCONNECTED[0]),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b1),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_sim_netlist.vhdl
+17 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:17 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_bd_xbar_0 -prefix
-- system_bd_xbar_0_ system_bd_xbar_0_sim_netlist.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:56:06 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_sim_netlist.vhdl
-- Design : system_bd_xbar_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -66,6 +66,8 @@ entity system_bd_xbar_0_axi_crossbar_v2_1_20_addr_arbiter_sasd is
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_xbar_0_axi_crossbar_v2_1_20_addr_arbiter_sasd : entity is "axi_crossbar_v2_1_20_addr_arbiter_sasd";
end system_bd_xbar_0_axi_crossbar_v2_1_20_addr_arbiter_sasd;
architecture STRUCTURE of system_bd_xbar_0_axi_crossbar_v2_1_20_addr_arbiter_sasd is
@@ -1338,6 +1340,8 @@ entity system_bd_xbar_0_axi_crossbar_v2_1_20_decerr_slave is
\gen_axilite.s_axi_bvalid_i_reg_2\ : in STD_LOGIC;
aa_rready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_xbar_0_axi_crossbar_v2_1_20_decerr_slave : entity is "axi_crossbar_v2_1_20_decerr_slave";
end system_bd_xbar_0_axi_crossbar_v2_1_20_decerr_slave;
architecture STRUCTURE of system_bd_xbar_0_axi_crossbar_v2_1_20_decerr_slave is
@@ -1552,6 +1556,8 @@ entity system_bd_xbar_0_axi_crossbar_v2_1_20_splitter is
\m_ready_d_reg[2]_1\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_xbar_0_axi_crossbar_v2_1_20_splitter : entity is "axi_crossbar_v2_1_20_splitter";
end system_bd_xbar_0_axi_crossbar_v2_1_20_splitter;
architecture STRUCTURE of system_bd_xbar_0_axi_crossbar_v2_1_20_splitter is
@@ -1747,6 +1753,8 @@ entity system_bd_xbar_0_axi_register_slice_v2_1_19_axic_register_slice is
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_xbar_0_axi_register_slice_v2_1_19_axic_register_slice : entity is "axi_register_slice_v2_1_19_axic_register_slice";
end system_bd_xbar_0_axi_register_slice_v2_1_19_axic_register_slice;
architecture STRUCTURE of system_bd_xbar_0_axi_register_slice_v2_1_19_axic_register_slice is
@@ -3325,6 +3333,8 @@ entity system_bd_xbar_0_axi_crossbar_v2_1_20_crossbar_sasd is
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_xbar_0_axi_crossbar_v2_1_20_crossbar_sasd : entity is "axi_crossbar_v2_1_20_crossbar_sasd";
end system_bd_xbar_0_axi_crossbar_v2_1_20_crossbar_sasd;
architecture STRUCTURE of system_bd_xbar_0_axi_crossbar_v2_1_20_crossbar_sasd is
@@ -3748,6 +3758,8 @@ entity system_bd_xbar_0_axi_crossbar_v2_1_20_axi_crossbar is
attribute C_S_AXI_WRITE_ACCEPTANCE of system_bd_xbar_0_axi_crossbar_v2_1_20_axi_crossbar : entity is 1;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_bd_xbar_0_axi_crossbar_v2_1_20_axi_crossbar : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_bd_xbar_0_axi_crossbar_v2_1_20_axi_crossbar : entity is "axi_crossbar_v2_1_20_axi_crossbar";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of system_bd_xbar_0_axi_crossbar_v2_1_20_axi_crossbar : entity is 1;
attribute P_AXI3 : integer;
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_stub.v
+5 -5
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
// Date : Sat Mar 18 23:57:17 2023
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_bd_xbar_0 -prefix
// system_bd_xbar_0_ system_bd_xbar_0_stub.v
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed Mar 22 22:56:06 2023
// Host : localhost.localdomain running 64-bit unknown
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_stub.v
// Design : system_bd_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_stub.vhdl
+5 -5
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
-- Date : Sat Mar 18 23:57:17 2023
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_bd_xbar_0 -prefix
-- system_bd_xbar_0_ system_bd_xbar_0_stub.vhdl
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed Mar 22 22:56:06 2023
-- Host : localhost.localdomain running 64-bit unknown
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0_stub.vhdl
-- Design : system_bd_xbar_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/1cb1/axi_spi_engine.v
Regular → Executable
View File
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/1f5a/hdl/fifo_generator_v13_2_rfs.v
Regular → Executable
View File
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/1f5a/hdl/fifo_generator_v13_2_rfs.vhd
Regular → Executable
View File
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/1f5a/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd
Regular → Executable
View File
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/1f5a/simulation/fifo_generator_vlog_beh.v
Regular → Executable
View File
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/4d88/hdl/axi_register_slice_v2_1_vl_rfs.v
Regular → Executable
+297 -297
View File
@@ -102,303 +102,303 @@ endmodule // tdm_sample
`default_nettype wire
// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
(* autopipeline_module="yes" *)
module axi_register_slice_v2_1_19_auto_slr #
(
parameter integer C_DATA_WIDTH = 32
)
(
// System Signals
input wire ACLK,
input wire ARESETN,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
wire handshake_pipe;
wire ready_pipe;
wire [C_DATA_WIDTH-1:0] payload_pipe;
(* keep="true" *) reg s_aclear = 1'b0;
(* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg s_areset_fwd = 1'b0;
(* autopipeline_group="resp" *) reg s_areset_resp = 1'b0;
(* keep="true" *) reg s_areset_resp2 = 1'b0;
(* keep="true" *) reg m_aclear = 1'b0;
(* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg m_areset_fwd = 1'b0;
(* autopipeline_group="resp" *) reg m_areset_resp = 1'b0;
(* keep="true" *) reg m_areset_resp2 = 1'b0;
// Global Reset pipelining
always @(posedge ACLK) begin
s_aclear <= ~ARESETN;
s_areset_fwd <= ~ARESETN;
s_areset_resp <= s_areset_fwd; // Auto-pipeline
s_areset_resp2 <= s_areset_resp; // Auto-pipeline
end
always @(posedge ACLK) begin
m_aclear <= ~ARESETN;
m_areset_fwd <= ~ARESETN;
m_areset_resp <= m_areset_fwd; // Auto-pipeline
m_areset_resp2 <= m_areset_resp; // Auto-pipeline
end
// Source-side submodule
axi_register_slice_v2_1_19_auto_src #
(
.C_DATA_WIDTH (C_DATA_WIDTH)
)
slr_auto_src
(
.ACLK (ACLK),
.s_aclear (s_aclear),
.s_areset_resp2 (s_areset_resp2),
.S_VALID (S_VALID),
.S_READY (S_READY),
.S_PAYLOAD_DATA (S_PAYLOAD_DATA),
.ready_pipe (ready_pipe),
.handshake_pipe (handshake_pipe),
.payload_pipe (payload_pipe)
);
// Destination-side submodule
axi_register_slice_v2_1_19_auto_dest #
(
.C_DATA_WIDTH (C_DATA_WIDTH)
)
slr_auto_dest
(
.ACLK (ACLK),
.m_aclear (m_aclear),
.m_areset_resp2 (m_areset_resp2),
.M_READY (M_READY),
.M_VALID (M_VALID),
.M_PAYLOAD_DATA (M_PAYLOAD_DATA),
.handshake_pipe (handshake_pipe),
.ready_pipe (ready_pipe),
.payload_pipe (payload_pipe)
);
endmodule // auto_slr
module axi_register_slice_v2_1_19_auto_src #
(
parameter integer C_DATA_WIDTH = 32
)
(
input wire ACLK,
input wire s_aclear,
input wire s_areset_resp2,
input wire S_VALID,
input wire ready_pipe,
output wire S_READY,
output wire handshake_pipe,
output wire [C_DATA_WIDTH-1:0] payload_pipe,
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA
);
(* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg [C_DATA_WIDTH-1:0] payload_pipe_r;
(* keep="true" *) reg s_areset_resp3 = 1'b0;
wire s_aresetn_d;
wire s_aresetn_q;
wire s_handshake_d;
wire s_ready_i;
assign S_READY = s_ready_i & s_aresetn_q;
assign s_aresetn_d = (~s_areset_resp2 & s_areset_resp3) | s_aresetn_q;
assign s_handshake_d = S_VALID & s_ready_i & s_aresetn_q;
assign payload_pipe = payload_pipe_r;
always @(posedge ACLK) begin
s_areset_resp3 <= s_areset_resp2;
end
always @(posedge ACLK) begin
payload_pipe_r <= S_PAYLOAD_DATA;
end
// Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2.
FDCE #(
.INIT(1'b0)
) reset_asyncclear (
.Q (s_aresetn_q),
.C (ACLK),
.CE (1'b1),
.CLR (s_aclear),
.D (s_aresetn_d)
);
(* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *)
FDCE #(
.INIT(1'b0)
) handshake_asyncclear (
.Q (handshake_pipe),
.C (ACLK),
.CE (1'b1),
.CLR (s_aclear),
.D (s_handshake_d)
);
FDCE #(
.INIT(1'b0)
) ready_asyncclear (
.Q (s_ready_i),
.C (ACLK),
.CE (1'b1),
.CLR (s_aclear),
.D (ready_pipe)
);
endmodule // auto_src
module axi_register_slice_v2_1_19_auto_dest #
(
parameter integer C_DATA_WIDTH = 32
)
(
input wire ACLK,
input wire m_aclear,
input wire m_areset_resp2,
input wire M_READY,
input wire handshake_pipe,
output wire ready_pipe,
output wire M_VALID,
input wire [C_DATA_WIDTH-1:0] payload_pipe,
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
(* keep="true" *) reg m_areset_resp3 = 1'b0;
wire m_aresetn_d;
wire m_aresetn_q;
wire m_valid_i;
wire pop;
wire m_ready_d;
wire m_handshake_q;
reg [C_DATA_WIDTH-1:0] m_payload_q;
assign M_VALID = m_valid_i;
assign m_aresetn_d = (~m_areset_resp2 & m_areset_resp3) | m_aresetn_q;
assign m_ready_d = (M_READY | ~m_valid_i) & m_aresetn_q;
assign pop = M_READY & m_valid_i;
always @(posedge ACLK) begin
m_areset_resp3 <= m_areset_resp2;
end
always @(posedge ACLK) begin
m_payload_q <= payload_pipe;
end
// Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2.
FDCE #(
.INIT(1'b0)
) reset_asyncclear (
.Q (m_aresetn_q),
.C (ACLK),
.CE (1'b1),
.CLR (m_aclear),
.D (m_aresetn_d)
);
FDCE #(
.INIT(1'b0)
) handshake_asyncclear (
.Q (m_handshake_q),
.C (ACLK),
.CE (1'b1),
.CLR (m_aclear),
.D (handshake_pipe)
);
(* autopipeline_group="resp" *)
FDCE #(
.INIT(1'b0)
) ready_asyncclear (
.Q (ready_pipe),
.C (ACLK),
.CE (1'b1),
.CLR (m_aclear),
.D (m_ready_d)
);
axi_register_slice_v2_1_19_axic_reg_srl_fifo #
(
.C_FIFO_WIDTH (C_DATA_WIDTH),
.C_FIFO_SIZE (5)
)
srl_fifo
(
.aclk (ACLK),
.areset (~m_aresetn_q),
.aclear (m_aclear),
.s_mesg (m_payload_q),
.s_valid (m_handshake_q),
.m_mesg (M_PAYLOAD_DATA),
.m_valid (m_valid_i),
.m_ready (pop)
);
endmodule // auto_dest
// -- (c) Copyright 2017 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
(* autopipeline_module="yes" *)
module axi_register_slice_v2_1_19_auto_slr #
(
parameter integer C_DATA_WIDTH = 32
)
(
// System Signals
input wire ACLK,
input wire ARESETN,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
wire handshake_pipe;
wire ready_pipe;
wire [C_DATA_WIDTH-1:0] payload_pipe;
(* keep="true" *) reg s_aclear = 1'b0;
(* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg s_areset_fwd = 1'b0;
(* autopipeline_group="resp" *) reg s_areset_resp = 1'b0;
(* keep="true" *) reg s_areset_resp2 = 1'b0;
(* keep="true" *) reg m_aclear = 1'b0;
(* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg m_areset_fwd = 1'b0;
(* autopipeline_group="resp" *) reg m_areset_resp = 1'b0;
(* keep="true" *) reg m_areset_resp2 = 1'b0;
// Global Reset pipelining
always @(posedge ACLK) begin
s_aclear <= ~ARESETN;
s_areset_fwd <= ~ARESETN;
s_areset_resp <= s_areset_fwd; // Auto-pipeline
s_areset_resp2 <= s_areset_resp; // Auto-pipeline
end
always @(posedge ACLK) begin
m_aclear <= ~ARESETN;
m_areset_fwd <= ~ARESETN;
m_areset_resp <= m_areset_fwd; // Auto-pipeline
m_areset_resp2 <= m_areset_resp; // Auto-pipeline
end
// Source-side submodule
axi_register_slice_v2_1_19_auto_src #
(
.C_DATA_WIDTH (C_DATA_WIDTH)
)
slr_auto_src
(
.ACLK (ACLK),
.s_aclear (s_aclear),
.s_areset_resp2 (s_areset_resp2),
.S_VALID (S_VALID),
.S_READY (S_READY),
.S_PAYLOAD_DATA (S_PAYLOAD_DATA),
.ready_pipe (ready_pipe),
.handshake_pipe (handshake_pipe),
.payload_pipe (payload_pipe)
);
// Destination-side submodule
axi_register_slice_v2_1_19_auto_dest #
(
.C_DATA_WIDTH (C_DATA_WIDTH)
)
slr_auto_dest
(
.ACLK (ACLK),
.m_aclear (m_aclear),
.m_areset_resp2 (m_areset_resp2),
.M_READY (M_READY),
.M_VALID (M_VALID),
.M_PAYLOAD_DATA (M_PAYLOAD_DATA),
.handshake_pipe (handshake_pipe),
.ready_pipe (ready_pipe),
.payload_pipe (payload_pipe)
);
endmodule // auto_slr
module axi_register_slice_v2_1_19_auto_src #
(
parameter integer C_DATA_WIDTH = 32
)
(
input wire ACLK,
input wire s_aclear,
input wire s_areset_resp2,
input wire S_VALID,
input wire ready_pipe,
output wire S_READY,
output wire handshake_pipe,
output wire [C_DATA_WIDTH-1:0] payload_pipe,
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA
);
(* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg [C_DATA_WIDTH-1:0] payload_pipe_r;
(* keep="true" *) reg s_areset_resp3 = 1'b0;
wire s_aresetn_d;
wire s_aresetn_q;
wire s_handshake_d;
wire s_ready_i;
assign S_READY = s_ready_i & s_aresetn_q;
assign s_aresetn_d = (~s_areset_resp2 & s_areset_resp3) | s_aresetn_q;
assign s_handshake_d = S_VALID & s_ready_i & s_aresetn_q;
assign payload_pipe = payload_pipe_r;
always @(posedge ACLK) begin
s_areset_resp3 <= s_areset_resp2;
end
always @(posedge ACLK) begin
payload_pipe_r <= S_PAYLOAD_DATA;
end
// Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2.
FDCE #(
.INIT(1'b0)
) reset_asyncclear (
.Q (s_aresetn_q),
.C (ACLK),
.CE (1'b1),
.CLR (s_aclear),
.D (s_aresetn_d)
);
(* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *)
FDCE #(
.INIT(1'b0)
) handshake_asyncclear (
.Q (handshake_pipe),
.C (ACLK),
.CE (1'b1),
.CLR (s_aclear),
.D (s_handshake_d)
);
FDCE #(
.INIT(1'b0)
) ready_asyncclear (
.Q (s_ready_i),
.C (ACLK),
.CE (1'b1),
.CLR (s_aclear),
.D (ready_pipe)
);
endmodule // auto_src
module axi_register_slice_v2_1_19_auto_dest #
(
parameter integer C_DATA_WIDTH = 32
)
(
input wire ACLK,
input wire m_aclear,
input wire m_areset_resp2,
input wire M_READY,
input wire handshake_pipe,
output wire ready_pipe,
output wire M_VALID,
input wire [C_DATA_WIDTH-1:0] payload_pipe,
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
(* keep="true" *) reg m_areset_resp3 = 1'b0;
wire m_aresetn_d;
wire m_aresetn_q;
wire m_valid_i;
wire pop;
wire m_ready_d;
wire m_handshake_q;
reg [C_DATA_WIDTH-1:0] m_payload_q;
assign M_VALID = m_valid_i;
assign m_aresetn_d = (~m_areset_resp2 & m_areset_resp3) | m_aresetn_q;
assign m_ready_d = (M_READY | ~m_valid_i) & m_aresetn_q;
assign pop = M_READY & m_valid_i;
always @(posedge ACLK) begin
m_areset_resp3 <= m_areset_resp2;
end
always @(posedge ACLK) begin
m_payload_q <= payload_pipe;
end
// Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2.
FDCE #(
.INIT(1'b0)
) reset_asyncclear (
.Q (m_aresetn_q),
.C (ACLK),
.CE (1'b1),
.CLR (m_aclear),
.D (m_aresetn_d)
);
FDCE #(
.INIT(1'b0)
) handshake_asyncclear (
.Q (m_handshake_q),
.C (ACLK),
.CE (1'b1),
.CLR (m_aclear),
.D (handshake_pipe)
);
(* autopipeline_group="resp" *)
FDCE #(
.INIT(1'b0)
) ready_asyncclear (
.Q (ready_pipe),
.C (ACLK),
.CE (1'b1),
.CLR (m_aclear),
.D (m_ready_d)
);
axi_register_slice_v2_1_19_axic_reg_srl_fifo #
(
.C_FIFO_WIDTH (C_DATA_WIDTH),
.C_FIFO_SIZE (5)
)
srl_fifo
(
.aclk (ACLK),
.areset (~m_aresetn_q),
.aclear (m_aclear),
.s_mesg (m_payload_q),
.s_valid (m_handshake_q),
.m_mesg (M_PAYLOAD_DATA),
.m_valid (m_valid_i),
.m_ready (pop)
);
endmodule // auto_dest
// -- (c) Copyright 2010 - 2017 Xilinx, Inc. All rights reserved.
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/550e/hdl/mdm_v3_2_vh_rfs.vhd
Regular → Executable
View File
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/5b9c/hdl/axi_data_fifo_v2_1_vl_rfs.v
Regular → Executable
View File
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/6335/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd
Regular → Executable
View File
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd
Regular → Executable
View File
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/78eb/hdl/lmb_v10_v3_0_vh_rfs.vhd
Regular → Executable
View File
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/802c/spi_engine_execution.v
Regular → Executable
View File
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd
Regular → Executable
View File
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd
Regular → Executable
View File
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/a040/hdl/interrupt_control_v3_1_vh_rfs.vhd
Regular → Executable
View File
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/ace7/hdl/axi_crossbar_v2_1_vl_rfs.v
Regular → Executable
View File
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v
Regular → Executable
View File
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c001/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd
Regular → Executable
View File
projects/datalink_814/dl814_k7_beam/ipi-bds/system_bd/ipshared/c001/simulation/blk_mem_gen_v8_4.v
Regular → Executable
View File

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