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simulated dl814_k7_beam

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This commit is contained in:
Josh Gao
2023-03-23 11:36:28 +08:00
parent 5c679def58
commit d69ca67c60
217 changed files with 29610 additions and 8899 deletions
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projects/datalink_814/dl814_k7_beam/rtl/rx_pre_process/rx_pre_process.v
+9 -8
View File
@@ -51,8 +51,9 @@ module rx_pre_process
parameter SNAPSHOT_NUM = 256,
parameter PS_PL_WIDTH = 32 ,
parameter WEIGHT_TRUNC_WIDTH = 16 ,
parameter CMPLX_DIM = 2
)
parameter CMPLX_DIM = 2 ,
parameter OUTPUT_DATA_WIDTH = ADC_DATA_WIDTH
)
(
// clock & reset
input sys_clk , // sync to adc data
@@ -86,8 +87,8 @@ module rx_pre_process
output accor_stream_data , // sync to [clk_96m]
input weight_stream_data , // sync to [clk_96m]
output rx_data_valid , // sync to [sys_clk]
output [ADC_DATA_WIDTH-1:0] rx_data_i , // sync to [sys_clk]
output [ADC_DATA_WIDTH-1:0] rx_data_q // sync to [sys_clk]
output [OUTPUT_DATA_WIDTH-1:0] rx_data_i, // sync to [sys_clk]
output [OUTPUT_DATA_WIDTH-1:0] rx_data_q // sync to [sys_clk]
);
localparam ACORR_WIDTH = 2*ADC_DATA_WIDTH;
@@ -421,8 +422,8 @@ assign filter_adc_imag = {rx_cal_ch4_q, rx_cal_ch3_q, rx_cal_ch2_q, rx_cal_ch1_q
// output data
wire filter_dout_valid;
wire [ADC_DATA_WIDTH-1 : 0] filter_dout_real;
wire [ADC_DATA_WIDTH-1 : 0] filter_dout_imag;
wire [OUTPUT_DATA_WIDTH-1 : 0] filter_dout_real;
wire [OUTPUT_DATA_WIDTH-1 : 0] filter_dout_imag;
assign rx_data_valid = filter_dout_valid;
assign rx_data_i = filter_dout_real;
@@ -432,7 +433,7 @@ spatial_filter #(
.CHANNEL_NUM (CHANNEL_NUM ),
.WEIGHT_WIDTH (WEIGHT_TRUNC_WIDTH ),
.ADC_WIDTH (ADC_DATA_WIDTH ),
.FILTER_O_WIDTH (ADC_DATA_WIDTH )
.FILTER_O_WIDTH (OUTPUT_DATA_WIDTH )
) u_spatial_filter
(
// clock & reset
@@ -445,7 +446,7 @@ spatial_filter #(
.din_weight_imag (filter_weight_imag ),
// input adc data
.hop_start_flag (hop_start_flag_cdc ),
.hop_start_flag (1'b0 ),
.din_adc_valid (filter_adc_valid ),
.din_adc_real (filter_adc_real ),
.din_adc_imag (filter_adc_imag ),
projects/datalink_814/dl814_k7_beam/rtl/rx_pre_process/spatial_filter.v
+2 -2
View File
@@ -176,9 +176,9 @@ for(i = 0; i < CHANNEL_NUM; i = i + 1) begin: spatial_filter_cmpy
cmpy_16x12 u_cmpy_16x12
(
.aclk (clk ), // input wire aclk
.s_axis_a_tvalid (last_hop_valid ), // input wire s_axis_a_tvalid
.s_axis_a_tvalid (din_adc_valid ), // input wire s_axis_a_tvalid
.s_axis_a_tdata (cmpy_a ), // input wire [31 : 0] s_axis_a_tdata
.s_axis_b_tvalid (last_hop_valid ), // input wire s_axis_b_tvalid
.s_axis_b_tvalid (din_adc_valid ), // input wire s_axis_b_tvalid
.s_axis_b_tdata (cmpy_b ), // input wire [31 : 0] s_axis_b_tdata
.m_axis_dout_tvalid (cmpy_p_vld ), // output wire m_axis_dout_tvalid
.m_axis_dout_tdata (cmpy_p ) // output wire [63 : 0] m_axis_dout_tdata
projects/datalink_814/dl814_k7_beam/rtl/system_top.v
+87 -64
View File
@@ -518,26 +518,26 @@ assign ad9361_2_tx_fb_clk = ad9361_1_tx_fb_clk;
// assign ad9361_2_tx_frame = ad9361_1_tx_frame ;
// assign ad9361_2_tx_data = ad9361_1_tx_data ;
tx_pre_process u_tx_pre_process
(
// clock & reset
.clk (sys_clk ),
.rst (sys_rst ),
// input data
.tx_data_ch1_i (tx_data_i ),
.tx_data_ch1_q (tx_data_q ),
.tx_data_ch2_i (tx_data_i ),
.tx_data_ch2_q (tx_data_q ),
// ad9361 calibration interface
.ad9361_tx_switch (ad9361_tx_switch ),
//
.bb_rshift (bb_rshift ),
// output data
.tx_ch1_i (tx_ch1_i ),
.tx_ch1_q (tx_ch1_q ),
.tx_ch2_i (tx_ch2_i ),
.tx_ch2_q (tx_ch2_q )
);
// tx_pre_process u_tx_pre_process
// (
// // clock & reset
// .clk (sys_clk ),
// .rst (sys_rst ),
// // input data
// .tx_data_ch1_i (tx_data_i ),
// .tx_data_ch1_q (tx_data_q ),
// .tx_data_ch2_i (tx_data_i ),
// .tx_data_ch2_q (tx_data_q ),
// // ad9361 calibration interface
// .ad9361_tx_switch (ad9361_tx_switch ),
// //
// .bb_rshift (bb_rshift ),
// // output data
// .tx_ch1_i (tx_ch1_i ),
// .tx_ch1_q (tx_ch1_q ),
// .tx_ch2_i (tx_ch2_i ),
// .tx_ch2_q (tx_ch2_q )
// );
// <--------------------------------------------------------------------------->
// <--------------------- insert transmitter logic below ---------------------->
@@ -571,7 +571,7 @@ wire [11:0] rx_ch3_i, rx_ch3_q;
wire [11:0] rx_ch4_i, rx_ch4_q;
wire rx_data_valid;
wire [11:0] rx_data_i, rx_data_q;
wire [29:0] rx_data_i, rx_data_q;
wire hop_start_flag ;
wire accor_stream_valid ;
@@ -619,7 +619,9 @@ ad9361_rx_map_cmos_dual u_ad9361_2_rx_map
.rx_ch2_q (rx_ch4_q ) // output [11:0] rx_ch2_q
);
rx_pre_process u_rx_pre_process
rx_pre_process #(
.OUTPUT_DATA_WIDTH (30 )
) u_rx_pre_process
(
// clock & reset
.sys_clk (sys_clk ), // sync to adc data
@@ -645,7 +647,7 @@ rx_pre_process u_rx_pre_process
.ad9361_cal_valid (ad9361_cal_valid ),
.ad9361_recal (ad9361_recal ),
// nulling algotithm interface
.hop_start_flag (hop_start_flag ), // sync to [sys_clk_4x]
.hop_start_flag (1'b0 ), // sync to [sys_clk_4x]
.accor_stream_valid (accor_stream_valid ), // sync to [clk_96m]
.accor_stream_data (accor_stream_data ), // sync to [clk_96m]
.weight_stream_data (weight_stream_data ), // sync to [clk_96m]
@@ -793,56 +795,77 @@ vio_ant_rd u_vio_ant_rd (
.probe_in5 (u_ant_rf_ctrl.Ant_RecvWord_last ) // input wire [127 : 0] probe_in5
);
ila_tx_rx u_ila_tx_rx
ila_rx u_ila_rx
(
.clk (sys_clk ), // input wire clk
.probe0 (tx_ch1_i ), // input wire [11:0] probe0
.probe1 (tx_ch1_q ), // input wire [11:0] probe1
.probe2 (u_rx_pre_process.rx_cal_ch1_i ), // input wire [11:0] probe2
.probe3 (u_rx_pre_process.rx_cal_ch1_q ), // input wire [11:0] probe3
.probe4 (u_rx_pre_process.rx_cal_ch2_i ), // input wire [11:0] probe4
.probe5 (u_rx_pre_process.rx_cal_ch2_q ), // input wire [11:0] probe5
.probe6 (u_rx_pre_process.rx_cal_ch3_i ), // input wire [11:0] probe6
.probe7 (u_rx_pre_process.rx_cal_ch3_q ), // input wire [11:0] probe7
.probe8 (u_rx_pre_process.rx_cal_ch4_i ), // input wire [11:0] probe8
.probe9 (u_rx_pre_process.rx_cal_ch4_q ) // input wire [11:0] probe9
.probe0 (u_rx_pre_process.rx_cal_ch1_i ), // input wire [11:0] probe0
.probe1 (u_rx_pre_process.rx_cal_ch1_q ), // input wire [11:0] probe1
.probe2 (u_rx_pre_process.rx_cal_ch2_i ), // input wire [11:0] probe2
.probe3 (u_rx_pre_process.rx_cal_ch2_q ), // input wire [11:0] probe3
.probe4 (u_rx_pre_process.rx_cal_ch3_i ), // input wire [11:0] probe4
.probe5 (u_rx_pre_process.rx_cal_ch3_q ), // input wire [11:0] probe5
.probe6 (u_rx_pre_process.rx_cal_ch4_i ), // input wire [11:0] probe6
.probe7 (u_rx_pre_process.rx_cal_ch4_q ), // input wire [11:0] probe7
.probe8 (rx_data_i ), // input wire [29:0] probe8
.probe9 (rx_data_q ) // input wire [29:0] probe9
);
ila_cal u_ila_cal
ila_tx u_ila_tx
(
.clk (sys_clk ), // input wire clk
.probe0 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_1_cal_start_d2 ), // input wire [0:0] probe0
.probe1 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_1_cal_done ), // input wire [0:0] probe1
.probe2 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_2_cal_start_d2 ), // input wire [0:0] probe2
.probe3 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_2_cal_done ), // input wire [0:0] probe3
.probe4 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_cal_result ), // input wire [0:0] probe4
.probe5 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_recal_d2 ), // input wire [0:0] probe5
.probe6 (u_rx_pre_process.u_ad9361_phase_cal.curr_state ), // input wire [1:0] probe6
.probe7 (rx_ch2_i ), // input wire [11:0] probe7
.probe8 (rx_ch2_q ), // input wire [11:0] probe8
.probe9 (rx_ch4_i ), // input wire [11:0] probe9
.probe10(rx_ch4_q ), // input wire [11:0] probe10
.probe11(u_rx_pre_process.rx_cal_ch2_i ), // input wire [11:0] probe11
.probe12(u_rx_pre_process.rx_cal_ch2_q ), // input wire [11:0] probe12
.probe13(u_rx_pre_process.rx_cal_ch4_i ), // input wire [11:0] probe13
.probe14(u_rx_pre_process.rx_cal_ch4_q ) // input wire [11:0] probe14
.clk (sys_clk ), // input wire clk
.probe0 (tx_data_i ), // input wire [11:0] probe0
.probe1 (tx_data_q ) // input wire [11:0] probe1
);
vio_cal u_vio_cal
(
.clk (sys_clk ), // input wire clk
.probe_in0 (u_rx_pre_process.u_ad9361_phase_cal.relative_delay ), // input wire [4 : 0] probe_in0
.probe_in1 (u_rx_pre_process.u_ad9361_phase_cal.phase_diff_raw ), // input wire [15 : 0] probe_in1
.probe_in2 (u_rx_pre_process.u_ad9361_phase_cal.phase_diff ) // input wire [15 : 0] probe_in2
);
ila_rx_pre u_ila_rx_pre
// ila_cal u_ila_cal
// (
// .clk (sys_clk ), // input wire clk
// .probe0 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_1_cal_start_d2 ), // input wire [0:0] probe0
// .probe1 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_1_cal_done ), // input wire [0:0] probe1
// .probe2 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_2_cal_start_d2 ), // input wire [0:0] probe2
// .probe3 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_2_cal_done ), // input wire [0:0] probe3
// .probe4 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_cal_result ), // input wire [0:0] probe4
// .probe5 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_recal_d2 ), // input wire [0:0] probe5
// .probe6 (u_rx_pre_process.u_ad9361_phase_cal.curr_state ), // input wire [1:0] probe6
// .probe7 (rx_ch2_i ), // input wire [11:0] probe7
// .probe8 (rx_ch2_q ), // input wire [11:0] probe8
// .probe9 (rx_ch4_i ), // input wire [11:0] probe9
// .probe10(rx_ch4_q ), // input wire [11:0] probe10
// .probe11(u_rx_pre_process.rx_cal_ch2_i ), // input wire [11:0] probe11
// .probe12(u_rx_pre_process.rx_cal_ch2_q ), // input wire [11:0] probe12
// .probe13(u_rx_pre_process.rx_cal_ch4_i ), // input wire [11:0] probe13
// .probe14(u_rx_pre_process.rx_cal_ch4_q ) // input wire [11:0] probe14
// );
// vio_cal u_vio_cal
// (
// .clk (sys_clk ), // input wire clk
// .probe_in0 (u_rx_pre_process.u_ad9361_phase_cal.relative_delay ), // input wire [4 : 0] probe_in0
// .probe_in1 (u_rx_pre_process.u_ad9361_phase_cal.phase_diff_raw ), // input wire [15 : 0] probe_in1
// .probe_in2 (u_rx_pre_process.u_ad9361_phase_cal.phase_diff ) // input wire [15 : 0] probe_in2
// );
// ila_rx_pre u_ila_rx_pre
// (
// .clk (clk_96m ), // input wire clk
// .probe0 (u_rx_pre_process.hop_start_flag_cdc ), // input wire [0:0] probe0
// .probe1 (accor_stream_valid ), // input wire [0:0] probe1
// .probe2 (accor_stream_data ), // input wire [0:0] probe2
// .probe3 (weight_stream_data ) // input wire [0:0] probe3
// );
vio_weight u_vio_weight
(
.clk (clk_96m ), // input wire clk
.probe0 (u_rx_pre_process.hop_start_flag_cdc ), // input wire [0:0] probe0
.probe1 (accor_stream_valid ), // input wire [0:0] probe1
.probe2 (accor_stream_data ), // input wire [0:0] probe2
.probe3 (weight_stream_data ) // input wire [0:0] probe3
.clk (sys_clk ), // input wire clk
.probe_out0 (u_rx_pre_process.weight_ch1_i ), // output wire [15 : 0] probe_out0
.probe_out1 (u_rx_pre_process.weight_ch1_q ), // output wire [15 : 0] probe_out1
.probe_out2 (u_rx_pre_process.weight_ch2_i ), // output wire [15 : 0] probe_out2
.probe_out3 (u_rx_pre_process.weight_ch2_q ), // output wire [15 : 0] probe_out3
.probe_out4 (u_rx_pre_process.weight_ch3_i ), // output wire [15 : 0] probe_out4
.probe_out5 (u_rx_pre_process.weight_ch3_q ), // output wire [15 : 0] probe_out5
.probe_out6 (u_rx_pre_process.weight_ch4_i ), // output wire [15 : 0] probe_out6
.probe_out7 (u_rx_pre_process.weight_ch4_q ) // output wire [15 : 0] probe_out7
);
vio_manual_ctrl u_vio_manual_ctrl