rename project to better classify different ad9361 data interface, resynthesis after the chage of ad9361 rx mapping strategy, split tx & rx ila, map correct tx signal to tx ila
in duifei_basic_v1.0, ila of tx and rx signal is seperated into two ilas; in module ad9361_mapping, the DDR_CLK_MODE of rx mapping iddr is changed to SAME_EDGE, and the output iq of iddr is swappedto satisfy ad9361 data interface
in dl814_k7_cal_coarse, change ant_clk to clk_96m, add rx_pre_test to verify nulling algorithm, with the ability to switch rx data between ad9361 data and test data
delete redundant file in dl814_k7_basic; simply duifei_cmos to duifei_basic and archive the project; rename duifei_cmos to duifei_cal_coarse and add ad9361 multichip calibration function, but not tested
now rf control and lcmv autocorrelation data shares the same signal line by simply 'or' operation, so the two must be transmitted at different time, otherwise the data will collapse
dl814_k7_basic is the driver instance of board smq7k410t_b9361, along with basic clock, adc and dac configurations; include nulling algorithm into dl814_z7 project
josh
Josh Gao